summaryrefslogtreecommitdiffstats
path: root/compiler/optimizing/locations.h
Commit message (Collapse)AuthorAgeFilesLines
* Add a parent environment to HEnvironment.Nicolas Geoffray2015-05-111-9/+0
| | | | | | | This code has no functionality change. It adds a placeholder for chaining inlined frames. Change-Id: I5ec57335af76ee406052345b947aad98a6a4423a
* Opt compiler: Implement parallel move resolver without using swap.Zheng Xu2015-04-171-7/+16
| | | | | | | | | | | | | | | | | | The algorithm of ParallelMoveResolverNoSwap() is almost the same with ParallelMoveResolverWithSwap(), except the way we resolve the circular dependency. NoSwap() uses additional scratch register to resolve the circular dependency. For example, (0->1) (1->2) (2->0) will be performed as (2->scratch) (1->2) (0->1) (scratch->0). On architectures without swap register support, NoSwap() can reduce the number of moves from 3x(N-1) to (N+1) when there is circular dependency with N moves. And also, NoSwap() algorithm does not depend on architecture register layout information, which means it can support register pairs on arm32 and X/W, D/S registers on arm64 without additional modification. Change-Id: Idf56bd5469bb78c0e339e43ab16387428a082318
* Revert "Add a check in the location summary."Nicolas Geoffray2015-04-151-6/+0
| | | | | | | | My assumption was wrong. We actually can use same as first input with any, *only if* the generate code does not clobber the first input. We use this for, e.g. DivZeroCheck, NullCheck. This reverts commit 95bf7547986e68d4ac93b0a529aaa8eb3c998c1f. Change-Id: Ib72d73fe580f5bc707b41c651f2c8936bd4e2407
* Add a check in the location summary.Nicolas Geoffray2015-04-151-0/+6
| | | | | | | | | Having SameAsFirstInput for out, and first input Any does not make sense currently. If it's stack, we are going to overwrite it, potentially clobbering another local. And constant does not make sense. Change-Id: I0ce357137487ed3dcecf4efd9922a039a2a1a29d
* [optimizing] Improve x86, x86_64 codeMark Mendell2015-03-131-0/+1
| | | | | | | | | | | | | | Tweak the generated code to allow more use of constants and other small changes - Use test vs. compare to 0 - EmitMove of 0.0 should use xorps - VisitCompare kPrimLong can use constants - cmp/add/sub/mul on x86_64 can use constants if in int32_t range - long bit operations on x86 examine long constant high/low to optimize - Use 3 operand imulq if constant is in int32_t range Change-Id: I2dd4010fdffa129fe00905b0020590fe95f3f926 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Revert "Revert "[optimizing] Enable x86 long support.""Nicolas Geoffray2015-03-111-6/+16
| | | | | | This reverts commit 154552e666347d41d95d7619c6ee56249ff4feca. Change-Id: Idc726551c249a888b7ff5fde8508ae50e81b2e13
* Revert "[optimizing] Enable x86 long support."Nicolas Geoffray2015-03-061-16/+6
| | | | | | | | Few libcore failures. This reverts commit b4ba354cf8d22b261205494875cc014f18587b50. Change-Id: I4a28d853e730dff9b69aec9555505803cf2fcd63
* [optimizing] Enable x86 long support.Nicolas Geoffray2015-03-061-6/+16
| | | | Change-Id: I9006972a65a1f191c45691104a960366747f9d16
* Move arenas into runtimeMathieu Chartier2015-02-191-1/+1
| | | | | | | | | | Moved arena pool into the runtime. Motivation: Allow GC to use arena allocators, recycle arena pool for linear alloc. Bug: 19264997 Change-Id: I8ddbb6d55ee923a980b28fb656c758c5d7697c2f
* Support hints for register pairs.Nicolas Geoffray2015-02-131-0/+4
| | | | Change-Id: Ia49dc5bf3e9a2bd481425bfe7fbeea9feb66c8e6
* Improve ParallelMoveResolver to work with pairs.Nicolas Geoffray2015-02-101-0/+14
| | | | Change-Id: Ie2a540ffdb78f7f15d69c16a08ca2d3e794f65b9
* Merge "ART: Change x86 long param ABI (Quick/JNI/Opt)"Nicolas Geoffray2015-02-041-27/+1
|\
| * ART: Change x86 long param ABI (Quick/JNI/Opt)Mark Mendell2015-01-301-27/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure that we don't pass a long parameter across the last register and the stack: skip the register and allocate it only on the stack. This was requested to simplify the optimizing compiler code generation for x86. Optimizing (Baseline) compiler support for x86 longs: - Remove QuickParameter from Location, as there are no longer any uses of it. Bump oat.h version because we changed an ABI again. I changed IsParamALong() to return false for argument 0 (this argument). I am not sure why it differed from all other tests. I have not tested on ARM. I followed Nicolas's suggestions for setting the value of kSplitPairAcrossRegisterAndStack for different architectures. Change-Id: I2f16b33c1dac58dd4f4f503e9c2309d845f5fb7a Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | Finally implement Location::kNoOutputOverlap.Nicolas Geoffray2015-02-041-20/+15
|/ | | | | | | | | | The [i, i + 1) interval scheme we chose for representing lifetime positions is not optimal for doing this optimization. It however doesn't prevent recognizing a non-split interval during the TryAllocateFreeReg phase, and try to re-use its inputs' registers. Change-Id: I80a2823b0048d3310becfc5f5fb7b1230dfd8201
* ART: Arm64 optimizing compiler intrinsicsAndreas Gampe2015-01-281-0/+2
| | | | | | Implement most intrinsics for the optimizing compiler for Arm64. Change-Id: Idb459be09f0524cb9aeab7a5c7fccb1c6b65a707
* Enable core callee-save on x64.Nicolas Geoffray2015-01-211-1/+20
| | | | | | Will work on other architectures and FP support in other CLs. Change-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d
* Revert "Revert "Fully support pairs in the register allocator.""Nicolas Geoffray2015-01-211-4/+7
| | | | | | This reverts commit c399fdc442db82dfda66e6c25518872ab0f1d24f. Change-Id: I19f8215c4b98f2f0827e04bf7806c3ca439794e5
* Revert "Fully support pairs in the register allocator."Nicolas Geoffray2015-01-211-7/+4
| | | | | | | | Libcore tests fail. This reverts commit 41aedbb684ccef76ff8373f39aba606ce4cb3194. Change-Id: I2572f120d4bbaeb7a4d4cbfd47ab00c9ea39ac6c
* Fully support pairs in the register allocator.Nicolas Geoffray2015-01-211-4/+7
| | | | | | Enabled on ARM for longs and doubles. Change-Id: Id8792d08bd7ca9fb049c5db8a40ae694bafc2d8b
* Do not use register pair in a parallel move.Nicolas Geoffray2015-01-161-12/+0
| | | | | | | The ParallelMoveResolver does not work with pairs. Instead, decompose the pair into two individual moves. Change-Id: Ie9d3f0b078cef8dc20640c98b20bb20cc4971a7f
* ART: Optimizing compiler intrinsicsAndreas Gampe2015-01-151-1/+10
| | | | | | | | | Add intrinsics infrastructure to the optimizing compiler. Add almost all intrinsics supported by Quick to the x86-64 backend. Further intrinsics require more assembler support. Change-Id: I48de9b44c82886bb298d16e74e12a9506b8e8807
* Implement double and float support for arm in register allocator.Nicolas Geoffray2015-01-081-5/+44
| | | | | | | | | | | | The basic approach is: - An instruction that needs two registers gets two intervals. - When allocating the low part, we also allocate the high part. - When splitting a low (or high) interval, we also split the high (or low) equivalent. - Allocation follows the (S/D register) requirement that low registers are always even and the high equivalent is low + 1. Change-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797
* Ensure opt. compiler doesn't get core & FP registers mixed up.Roland Levillain2014-11-271-1/+8
| | | | | | | | Replace Location::As<T>() with two method methods (Location::AsRegister<T>() and Location::AsFpuRegister<T>()) checking the kind of the location (register). Change-Id: I22b4abee1a124b684becd2dc1caf33652b911070
* Fix safepoint bug when computing live registers.Nicolas Geoffray2014-11-191-0/+8
| | | | Change-Id: I8f28dd287c0e04223c49dea6a323058c1b210913
* Do not update Out after it has a valid location.Nicolas Geoffray2014-11-071-1/+14
| | | | | | | | | | Slow paths use LocationSummary to know where to move things around, and they are executed at the end of the code generation. This fix is needed for https://android-review.googlesource.com/#/c/113345/. Change-Id: Id336c6409479b1de6dc839b736a7234d08a7774a
* Implement CONST_CLASS in optimizing compiler.Nicolas Geoffray2014-11-041-3/+4
| | | | Change-Id: Ia8c8dfbef87cb2f7893bfb6e178466154eec9efd
* Merge "ART: Replace COMPILE_ASSERT with static_assert (compiler)"Andreas Gampe2014-11-041-10/+10
|\
| * ART: Replace COMPILE_ASSERT with static_assert (compiler)Andreas Gampe2014-11-031-10/+10
| | | | | | | | | | | | Replace all occurrences of COMPILE_ASSERT in the compiler tree. Change-Id: Icc40a38c8bdeaaf7305ab3352a838a2cd7e7d840
* | Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.Ian Rogers2014-11-031-1/+3
|/ | | | | | | | | | | Fix associated errors about unused paramenters and implict sign conversions. For sign conversion this was largely in the area of enums, so add ostream operators for the effected enums and fix tools/generate-operator-out.py. Tidy arena allocation code and arena allocated data types, rather than fixing new and delete operators. Remove dead code. Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
* Fix for long parameter passed both in stack and register.Nicolas Geoffray2014-10-301-4/+9
| | | | | | | | | Fix for long parameter passed both in stack and register on 32bits architectures. The move to hard float ABI makes it so that the register index does not necessarily match the stack index anymore. Change-Id: I26b483f68ac86d336b4a37d94c38b04917668659
* Add support for static fields in optimizing compiler.Nicolas Geoffray2014-10-291-0/+9
| | | | Change-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9
* Support hard float on arm in optimizing compiler.Nicolas Geoffray2014-10-271-7/+31
| | | | | | Also bump oat version, needed after latest hard float switch. Change-Id: Idf5acfb36c07e74acff00edab998419a3c6b2965
* Remove the notion of dies at entry.Nicolas Geoffray2014-10-211-9/+16
| | | | | | | | | | | - Instead, explicitly say that the output does not overlap. - Inputs that must be in a fixed register do die at entry, as we know they have a location that others can not take. - There is also no need to differentiate between an input move and a connecting sibling move - those can be put in the same parallel move instruction. Change-Id: I1b2b2827906601f822b59fb9d6a21d48e43bae27
* stdint types all the way!Ian Rogers2014-10-091-11/+11
| | | | Change-Id: I4e4ef3a2002fc59ebd9097087f150eaf3f2a7e08
* Merge "Tidy ELF builder."Ian Rogers2014-10-091-1/+2
|\
| * Tidy ELF builder.Ian Rogers2014-10-091-1/+2
| | | | | | | | | | | | | | | | | | Don't do "if (ptr)". Use const. Use DISALLOW_COPY_AND_ASSIGN. Avoid public member variables. Move ValueObject to base and use in ELF builder. Tidy VectorOutputStream to not use non-const reference arguments. Change-Id: I2c727c3fc61769c3726de7cfb68b2d6eb4477e53
* | Stop converting from Location to ManagedRegister.Nicolas Geoffray2014-10-091-20/+52
|/ | | | | | | Now the source of truth is the Location object that knows which register (core, pair, fpu) it needs to refer to. Change-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1
* Add support for floats and doubles.Nicolas Geoffray2014-10-071-16/+41
| | | | | | | - Follows Quick conventions. - Currently only works with baseline register allocator. Change-Id: Ie4b8e298f4f5e1cd82364da83e4344d4fc3621a3
* Add a prepare for register allocation pass.Nicolas Geoffray2014-10-061-0/+3
| | | | | | | | | | - Currently the pass just changes the uses of checks to the actual values. - Also optimize array access, now that inputs can be constants. - And fix another bug in the register allocator reveiled by this change. Change-Id: I43be0dbde9330ee5c8f9d678de11361292d8bd98
* Add support for inputs dying at entry of instructions.Nicolas Geoffray2014-10-061-2/+8
| | | | | | | - Start using it in places where it makes sense. - Also improve suspend check on arm to use subs directly. Change-Id: I09ac0589f5ccb9b850ee757c76dcbcf35ee8cd01
* Register allocator: refine instructions liveness.Nicolas Geoffray2014-09-271-0/+10
| | | | | | | | | Add support for instructions that die at the beginning of another instruction. Before, an instruction needed to stay alive during the instruction, so the register allocator was not able not reuse the register. Change-Id: I5f11a80b0a20778227229eb797816edcc6365297
* Merge "Optimize suspend checks in optimizing compiler."Nicolas Geoffray2014-09-251-0/+4
|\
| * Optimize suspend checks in optimizing compiler.Nicolas Geoffray2014-09-251-0/+4
| | | | | | | | | | | | | | | | | | | | - Remove the ones added during graph build (they were added for the baseline code generator). - Emit them at loop back edges after phi moves, so that the test can directly jump to the loop header. - Fix x86 and x86_64 suspend check by using cmpw instead of cmpl. Change-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a
* | Optimizing compiler: remove unnecessary `explicit' keywords.Roland Levillain2014-09-251-1/+1
|/ | | | Change-Id: I5927fd92d53308c81e14edbd6e7d1c943bfa085b
* Support for saving and restoring live registers in a slow path.Nicolas Geoffray2014-09-231-3/+41
| | | | | | And use it in suspend check slow paths. Change-Id: I79caf28f334c145a36180c79a6e2fceae3990c31
* Runtime support for the new stack maps for the opt compiler.Nicolas Geoffray2014-09-081-5/+50
| | | | | | | Now most of the methods supported by the compiler can be optimized, instead of using the baseline. Change-Id: I80ab36a34913fa4e7dd576c7bf55af63594dc1fa
* Add assembly operations with constants in optimizing compiler.Nicolas Geoffray2014-07-211-11/+35
| | | | Change-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f
* Add x86_64 support to the optimizing compiler.Nicolas Geoffray2014-06-131-0/+1
| | | | Change-Id: I4462d9ae15be56c4a3dc1bd4d1c0c6548c1b94be
* Forgot these files from last commit.Nicolas Geoffray2014-05-231-0/+299
Change-Id: I9ab7975daa5ed7aae6bff8730bb63fb48a798ea8
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 16:35:44 +0000