| Commit message (Collapse) | Author | Age | Files | Lines |
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The basic approach is:
- An instruction that needs two registers gets two intervals.
- When allocating the low part, we also allocate the high part.
- When splitting a low (or high) interval, we also split the high
(or low) equivalent.
- Allocation follows the (S/D register) requirement that low
registers are always even and the high equivalent is low + 1.
Change-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797
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Replace Location::As<T>() with two method methods
(Location::AsRegister<T>() and Location::AsFpuRegister<T>())
checking the kind of the location (register).
Change-Id: I22b4abee1a124b684becd2dc1caf33652b911070
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Change-Id: I8f28dd287c0e04223c49dea6a323058c1b210913
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Slow paths use LocationSummary to know where to move
things around, and they are executed at the end of the
code generation.
This fix is needed for https://android-review.googlesource.com/#/c/113345/.
Change-Id: Id336c6409479b1de6dc839b736a7234d08a7774a
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Change-Id: Ia8c8dfbef87cb2f7893bfb6e178466154eec9efd
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Replace all occurrences of COMPILE_ASSERT in the compiler tree.
Change-Id: Icc40a38c8bdeaaf7305ab3352a838a2cd7e7d840
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Fix associated errors about unused paramenters and implict sign conversions.
For sign conversion this was largely in the area of enums, so add ostream
operators for the effected enums and fix tools/generate-operator-out.py.
Tidy arena allocation code and arena allocated data types, rather than fixing
new and delete operators.
Remove dead code.
Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
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Fix for long parameter passed both in stack and register
on 32bits architectures.
The move to hard float ABI makes it so that the
register index does not necessarily match the stack index anymore.
Change-Id: I26b483f68ac86d336b4a37d94c38b04917668659
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Change-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9
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Also bump oat version, needed after latest hard float switch.
Change-Id: Idf5acfb36c07e74acff00edab998419a3c6b2965
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- Instead, explicitly say that the output does not overlap.
- Inputs that must be in a fixed register do die at entry,
as we know they have a location that others can not take.
- There is also no need to differentiate between an input move
and a connecting sibling move - those can be put in the
same parallel move instruction.
Change-Id: I1b2b2827906601f822b59fb9d6a21d48e43bae27
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Change-Id: I4e4ef3a2002fc59ebd9097087f150eaf3f2a7e08
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Don't do "if (ptr)". Use const. Use DISALLOW_COPY_AND_ASSIGN. Avoid public
member variables.
Move ValueObject to base and use in ELF builder.
Tidy VectorOutputStream to not use non-const reference arguments.
Change-Id: I2c727c3fc61769c3726de7cfb68b2d6eb4477e53
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Now the source of truth is the Location object that knows
which register (core, pair, fpu) it needs to refer to.
Change-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1
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- Follows Quick conventions.
- Currently only works with baseline register allocator.
Change-Id: Ie4b8e298f4f5e1cd82364da83e4344d4fc3621a3
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- Currently the pass just changes the uses of checks to the
actual values.
- Also optimize array access, now that inputs can be constants.
- And fix another bug in the register allocator reveiled by
this change.
Change-Id: I43be0dbde9330ee5c8f9d678de11361292d8bd98
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- Start using it in places where it makes sense.
- Also improve suspend check on arm to use subs directly.
Change-Id: I09ac0589f5ccb9b850ee757c76dcbcf35ee8cd01
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Add support for instructions that die at the beginning
of another instruction. Before, an instruction needed
to stay alive during the instruction, so the register
allocator was not able not reuse the register.
Change-Id: I5f11a80b0a20778227229eb797816edcc6365297
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- Remove the ones added during graph build (they were added
for the baseline code generator).
- Emit them at loop back edges after phi moves, so that the test
can directly jump to the loop header.
- Fix x86 and x86_64 suspend check by using cmpw instead of cmpl.
Change-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a
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Change-Id: I5927fd92d53308c81e14edbd6e7d1c943bfa085b
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And use it in suspend check slow paths.
Change-Id: I79caf28f334c145a36180c79a6e2fceae3990c31
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Now most of the methods supported by the compiler can be optimized,
instead of using the baseline.
Change-Id: I80ab36a34913fa4e7dd576c7bf55af63594dc1fa
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Change-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f
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Change-Id: I4462d9ae15be56c4a3dc1bd4d1c0c6548c1b94be
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Change-Id: I9ab7975daa5ed7aae6bff8730bb63fb48a798ea8
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