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| author | Dmitry Petrochenko <dmitry.petrochenko@intel.com> | 2014-05-12 11:31:37 +0700 |
|---|---|---|
| committer | Dmitry Petrochenko <dmitry.petrochenko@intel.com> | 2014-05-14 00:40:57 +0700 |
| commit | 9ee801f5308aa3c62ae3bedae2658612762ffb91 (patch) | |
| tree | 86ed7ec36fe4a06bcc0b37df6661ac112888c0f6 /compiler/compilers.cc | |
| parent | cd6e04f738ee17b3e8ec51c1f14d636fa2a89a55 (diff) | |
| download | android_art-9ee801f5308aa3c62ae3bedae2658612762ffb91.tar.gz android_art-9ee801f5308aa3c62ae3bedae2658612762ffb91.tar.bz2 android_art-9ee801f5308aa3c62ae3bedae2658612762ffb91.zip | |
Add x86_64 code generation support
Utilizes r0..r7 in register allocator, implements spill/unsill
core regs as well as operations with stack pointer.
Change-Id: I973d5a1acb9aa735f6832df3d440185d9e896c67
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Diffstat (limited to 'compiler/compilers.cc')
| -rw-r--r-- | compiler/compilers.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/compiler/compilers.cc b/compiler/compilers.cc index 79a85db79a..76838d701b 100644 --- a/compiler/compilers.cc +++ b/compiler/compilers.cc @@ -111,7 +111,7 @@ Backend* QuickCompiler::GetCodeGenerator(CompilationUnit* cu, void* compilation_ mir_to_lir = X86CodeGenerator(cu, cu->mir_graph.get(), &cu->arena); break; case kX86_64: - mir_to_lir = X86CodeGenerator(cu, cu->mir_graph.get(), &cu->arena); + mir_to_lir = X86_64CodeGenerator(cu, cu->mir_graph.get(), &cu->arena); break; default: LOG(FATAL) << "Unexpected instruction set: " << cu->instruction_set; |