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* plat: pass -D option to BL*_CPPFLAGS instead of BL*_CFLAGSMasahiro Yamada2020-03-313-12/+12
| | | | | | | | | -D is a preprocessor flag that defines a macro. So, adding it to BL*_CPPFLAGS makes more sense. You can reference it not only from .c files but also from .S files. Change-Id: Ib4f2f27a3ed3eae476a6a32da7ab5225ad0649de Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge "plat/sgm775: Add support for dynamic config using fconf" into integrationManish Pandey2020-03-302-7/+18
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| * plat/sgm775: Add support for dynamic config using fconfMadhukar Pappireddy2020-03-302-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | 1. Necessary changes to platform makefile to include fw_config device tree and package it in fip.bin 2. Removed hw_config node from fw_config dts as there is no HW_CONFIG device tree source for sgm775 3. Added mbedtls_heap related properties for TBBR functionality Change-Id: I26b940c65b17ad2fb5537141f8649785bb0fd4ad Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | Merge "Flush dcache when storing timestamp" into integrationOlivier Deprez2020-03-301-5/+3
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| * | Flush dcache when storing timestampZelalem2020-03-271-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DynamIQ CPU FVPs, stats test cases are failing when hardware-assisted coherency is enabled due to a corrupt timestamp value. Investigation of the issue indicates that on these models the timestamp value is stored in cache instead of memory. This patch flushes the dcache when the timestamp is stored to make sure it is stored in memory. Change-Id: I05cd54ba5991a5a96dd07f1e08b5212273201411 Signed-off-by: Zelalem <zelalem.aweke@arm.com>
* | | Merge changes from topic "ddr_map" into integrationOlivier Deprez2020-03-309-47/+92
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: stm32mp1: use stm32mp_get_ddr_ns_size() function stm32mp1: set XN attribute for some areas in BL2 stm32mp1: dynamically map DDR later and non-cacheable during its test stm32mp1: add a function to get non-secure DDR size
| * | | stm32mp1: use stm32mp_get_ddr_ns_size() functionYann Gautier2020-03-262-21/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using dt_get_ddr_size() and withdrawing the secure and shared memory areas, use stm32mp_get_ddr_ns_size() function. Change-Id: I5608fd7873589ea0e1262ba7d2ee3e52b53d9a7d Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | stm32mp1: set XN attribute for some areas in BL2Yann Gautier2020-03-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DTB and BL32 area should not be set as executable in MMU during BL2 execution, hence set those areas as MT_RO_DATA. Change-Id: I87c47a1e7fda761e541ec98a5b294588384d31db Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | stm32mp1: dynamically map DDR later and non-cacheable during its testYann Gautier2020-03-265-21/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A speculative accesses to DDR could be done whereas it was not reachable and could lead to bus stall. To correct this the dynamic mapping in MMU is used. A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute, once DDR access is setup. It is then unmapped and a new mapping DDR is done with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE) load. The disabling of cache during DDR tests is also removed, as now useless. A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done instead. PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32. BL33 max size is also updated to take into account the secure and shared memory areas. Those are used in OP-TEE case. Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | stm32mp1: add a function to get non-secure DDR sizeYann Gautier2020-03-263-3/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function gets the DDR size from DT, and withdraws (if defined) the sizes of secure DDR and shared memory areas. This function also checks DT values fits the default DDR range. This non-secure memory is available for BL33 and non-secure OS. Change-Id: I162ae5e990a0f9b6b7d07e539de029f1d61a391b Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | | | plat/arm/sgi: fix the incorrect check for SCMI channel IDAditya Angadi2020-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use ARRAY_SIZE macro instead of sizeof operator to obtain the maximum number of SCMI channels supported on the platform. Change-Id: Id922bb548af98ac99b4ac0c34e38e589e5a80b2d Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
* | | | Merge changes from topic "os/bl31-fpga-port" into integrationManish Pandey2020-03-2711-0/+713
|\ \ \ \ | |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: plat/arm/board/arm_fpga: Compile with additional CPU libraries plat/arm/board/arm_fpga: Enable position-independent execution plat/arm/board/arm_fpga: Enable port for alternative cluster configurations plat/arm/board/arm_fpga: Initialize the Generic Interrupt Controller plat/arm/board/arm_fpga: Initialize the System Counter plat/arm/board/arm_fpga: Add PSCI implementation for FPGA images plat/arm/board/arm_fpga: Use preloaded BL33 alternative boot flow plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image
| * | | plat/arm/board/arm_fpga: Compile with additional CPU librariesOliver Swede2020-03-261-3/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is part of the goal of enabling the port to be compatible with multiple FPGA images. BL31 behaves differently depending on whether or not the CPUs in the system use cache coherency, and as a result any CPU libraries that are compiled together must serve processors that are consistent in this regard. This compiles a different set of CPU libraries depending on whether or not the HW_ASSISTED_COHERENCY is enabled at build-time to indicate the CPUs support hardware-level support for cache coherency. This build flag is used in the makefile in the same way as the Arm FVP port. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I18300b4443176b89767015e3688c0f315a91c27e
| * | | plat/arm/board/arm_fpga: Enable position-independent executionOliver Swede2020-03-261-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the BL31 port to run with position-independent execution enabled so that it can be ran from any address in the system. This increases the flexibility of the image, allowing it to be ran from other locations rather than only its hardcoded absolute address (currently set to the typical DRAM base of 2GB). This may be useful for future images that describe system configurations with other memory layouts (e.g. where SRAM is included). It does this by setting ENABLE_PIE=1 and changing the absolute address to 0. The load address of bl31.bin can then be specified by the -l [load address] argument in the fpga-run command (additionally, this address is required by any preceding payloads that specify the start address. For ELF payloads this is usually extracted automatically by reading the entrypoint address in the header, however bl31.bin is a different file format so has this additional dependency). Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: Idd74787796ab0cf605fe2701163d9c4b3223a143
| * | | plat/arm/board/arm_fpga: Enable port for alternative cluster configurationsOliver Swede2020-03-262-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is part of the goal of enabling the port to be compatible with multiple FPGA images. The BL31 port that is uploaded as a payload to the FPGA with an image should cater for a wide variety of system configurations. This patch makes the necessary changes to enable it to function with images whose cluster configurations may be larger (either by utilizing more clusters, more CPUs per cluster, more threads in each CPU, or a combination) than the initial image being used for testing. As part of this, the hard-coded values that configure the size of the array describing the topology of the power domain tree are increased to max. 8 clusters, max. 8 cores per cluster & max 4 threads per core. This ensures the port works with cluster configurations up to these sizes. When there are too many entries for the number of available PEs, e.g. if there is a variable number of CPUs between clusters, then there will be empty entries in the array. This is permitted and the PSCI library will still function as expected. While this increases its size, this shouldn't be an issue in the context of the size of BL31, and is worth the trade-off for the extra compatibility. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I7d4ae1e20b2e99fdbac428d122a2cf9445394363
| * | | plat/arm/board/arm_fpga: Initialize the Generic Interrupt ControllerOliver Swede2020-03-266-7/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This initializes the GIC using the Arm GIC drivers in TF-A. The initial FPGA image uses a GIC600 implementation, and so that its power controller is enabled, this platform port calls the corresponding implementation-specific routines. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I88d5a073eead4b653b1ca73273182cd98a95e4c5
| * | | plat/arm/board/arm_fpga: Initialize the System CounterOliver Swede2020-03-262-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sets the frequency of the system counter so that the Delay Timer driver programs the correct value to CNTCRL. This value depends on the FPGA image being used, and is 10MHz for the initial test image. Once configured, the BL31 platform setup sequence then enables the system counter. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: Ieb036a36fd990f350b5953357424a255b8ac5d5a
| * | | plat/arm/board/arm_fpga: Add PSCI implementation for FPGA imagesOliver Swede2020-03-264-11/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a basic PSCI implementation allow secondary CPUs to be released from an initial state and continue through to the warm boot entrypoint. Each secondary CPU is kept in a holding pen, whereby it polls the value representing its hold state, by reading this from an array that acts as a table for all the PEs. The hold states are initially set to 0 for all cores to indicate that the executing core should continue polling. To prevent the secondary CPUs from interfering with the platform's initialization, they are only updated by the primary CPU once the cold boot sequence has completed and fpga_pwr_domain_on(mpidr) is called. The polling target CPU will then read 1 (which indicates that it should branch to the warm reset entrypoint) and then jump to that address rather than continue polling. In addition to the initial polling behaviour of the secondary CPUs before their warm boot reset sequence, they are also placed in a low-power wfe() state at the end of each poll; accordingly, the PSCI fpga_pwr_domain_on(mpidr) function also signals an event to all cores (after updating the target CPU's hold entry) to wake them from this state, allowing any secondary CPUs that are still polling to check their hold state again. This method is in accordance with both the PSCI and Linux kernel recommendations, as the lessened overhead reduces the energy consumption associated with the busy-loop. The table of hold entries is implemented by a global array as shared SRAM (which is used by other platforms in similar implementations) is not available on the FPGA images. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I65cfd1892f8be1dfcb285f0e1e94e7a9870cdf5a
| * | | plat/arm/board/arm_fpga: Use preloaded BL33 alternative boot flowOliver Swede2020-03-261-9/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes use of the PRELOADED_BL33_BASE flag to indicate to BL31 that the BL33 payload (kernel) has already been loaded and resides in memory; BL31 will then jump to the non-secure address. For this port the BL33 payload is the Linux kernel, and in accordance with the pre-kernel setup requirements (as specified in the `Booting AArch64 Linux' documentation: https://www.kernel.org/doc/Documentation/arm64/booting.txt), this change also sets up the primary CPU's registers x0-x3 so they are the expected values, which includes the address of the DTB at x0. An external linker script is currently required to combine BL31, the BL33 payload, and any other software images to create an ELF file that can be uploaded to the FPGA board along with the bit file. It therefore has dependencies on the value of PRELOADED_BL33_BASE (kernel base) and the DTB base (plus any other relevant base addresses used to distinguish the different ELF sections), both of which are set in this patch. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: If7ae8ee82d1e09fb05f553f6077ae13680dbf66b
| * | | plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA imageOliver Swede2020-03-2610-0/+362
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
* | | Merge "FVP: Add BL2 hash calculation in BL1" into integrationMark Dykes2020-03-264-6/+158
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| * | FVP: Add BL2 hash calculation in BL1Alexei Fedorov2020-03-254-6/+158
| | | | | | | | | | | | | | | | | | | | | | | | This patch provides support for measured boot by adding calculation of BL2 image hash in BL1 and writing these data in TB_FW_CONFIG DTB. Change-Id: Ic074a7ed19b14956719c271c805b35d147b7cec1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | | Merge "Tegra194: se: increase max. operation timeout to 1 second" into ↵Sandrine Bailleux2020-03-261-5/+4
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| * | Tegra194: se: increase max. operation timeout to 1 secondVarun Wadekar2020-03-231-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch increases the maximum timeout value for SE operation completion to 1 second. This takes care of some corner cases where an operation might take more time than the previous timeout value of 100ms. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I0012448ba372a8bb0e156df7dfe49d7de6d21a68
* | | Merge "fconf: Clean Arm IO" into integrationMark Dykes2020-03-248-394/+142
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| * | | fconf: Clean Arm IOLouis Mayencourt2020-03-168-394/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This removes the duplicate io_policies and functions definition. This patch: - replace arm_io_storage.c with the content of arm_fconf_io_storage.c - rename the USE_FCONF_BASED_IO option into ARM_IO_IN_DTB. - use the ARM_IO_IN_DTB option to compile out io_policies moved in dtb. - propagate DEFINES when parsing dts. - use ARM_IO_IN_DTB to include or not uuid nodes in fw_config dtb. - set the ARM_IO_IN_DTB to 0 by default for fvp. This ensure that the behavior of fvp stays the same as it was before the introduction of fconf. Change-Id: Ia774a96d1d3a2bccad29f7ce2e2b4c21b26c080e Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | | Merge "plat/sgi: Bump bl1 RW limit" into integrationMark Dykes2020-03-241-1/+1
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| * | | plat/sgi: Bump bl1 RW limitLouis Mayencourt2020-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Increase bl1 RW limit to allow future development. Change-Id: I3159b36dbaca798b4c4374c1415cd033d6586388 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | | Merge "spmd: skip loading of secure partitions on pre-v8.4 platforms" into ↵Alexei Fedorov2020-03-243-5/+7
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| * | | spmd: skip loading of secure partitions on pre-v8.4 platformsOlivier Deprez2020-03-233-5/+7
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | When SPD=spmd and SPMD_SPM_AT_SEL2=0, that is SPMC sits at S-EL1 then there is no need for TF-A to load secure partitions individually. In this configuration, SPMC handles secure partition loading at S-EL1/EL0 levels. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I06a0d88a4811274a8c347ce57b56bb5f64e345df
* | | Merge changes from topic "static_analysis" into integrationManish Pandey2020-03-231-4/+6
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: io: io_stm32image: correct possible NULL pointer dereference plat/st: correctly check pwr-regulators node nand: stm32_fmc2_nand: correct xor_ecc.val assigned value plat/st: correct static analysis tool warning raw_nand: correct static analysis tool warning spi: stm32_qspi: correct static analysis issues
| * | | plat/st: correctly check pwr-regulators nodeYann Gautier2020-03-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This warning was issued by cppcheck in our downstream code: [plat/st/common/stm32mp_dt.c:629] -> [plat/st/common/stm32mp_dt.c:634]: (warning) Identical condition 'node<0', second condition is always false The second test has to check variable pwr_regulators_node. Change-Id: I4a20c4a3ac0ef0639c2df36309d90a61c02b511f Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | plat/st: correct static analysis tool warningYann Gautier2020-03-231-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct the following sparse warnings: plat/st/common/stm32mp_dt.c:103:5: warning: symbol 'fdt_get_node_parent_address_cells' was not declared. Should it be static? plat/st/common/stm32mp_dt.c:123:5: warning: symbol 'fdt_get_node_parent_size_cells' was not declared. Should it be static? As those 2 functions are only used by assert(), put them under ENABLE_ASSERTIONS flag. Change-Id: Iad721f12128df83a3de3f53e7920a9c1dce64c56 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | | | Merge "allwinner: H6: Fix GPIO and CCU memory map addresses" into integrationManish Pandey2020-03-231-2/+2
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| * | | allwinner: H6: Fix GPIO and CCU memory map addressesAndre Przywara2020-03-231-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The base address for both the GPIO and the clock unit of the H6 memory map have been typo-ed. Fix them to match the Linux DT and the manual. The H6 code use neither of them, so this doesn't change or fix anything in the real world, but should be corrected anyway. The issue was found and reported by Github user "armlabs". Change-Id: Ic6fdfb732ce1cfc54cbb927718035624a06a9e08 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge changes from topic "tegra-downstream-03192020" into integrationManish Pandey2020-03-2321-349/+101
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: Tegra194: move cluster and CPU counter to header file. Tegra: gicv2: initialize target masks spd: tlkd: support new TLK SMCs for RPMB service Tegra210: trigger CPU0 hotplug power on using FC Tegra: memctrl: cleanup streamid override registers Tegra: memctrl_v2: remove support to secure TZSRAM Tegra: include platform headers from individual makefiles Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro Tegra194: SiP function ID to read SMMU_PER registers Tegra: memctrl: map video memory as uncached Tegra: remove support for USE_COHERENT_MEM Tegra: remove circular dependency with common_def.h Tegra: include missing stdbool.h Tegra: remove support for SEPARATE_CODE_AND_RODATA=0
| * | | Tegra194: move cluster and CPU counter to header file.Anthony Zhou2020-03-213-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MISRA rules request that the cluster and CPU counter be unsigned values and have a suffix 'U'. If the define located in the makefile, this cannot be done. This patch moves the PLATFORM_CLUSTER_COUNT and PLATFORM_MAX_CPUS_PER_CLUSTER macros to tegra_def.h as a result. Change-Id: I9ef0beb29485729de204b4ffbb5241b039690e5a Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
| * | | Tegra: gicv2: initialize target masksVarun Wadekar2020-03-211-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch initializes the target masks in the GICv2 driver data, for all PEs. This will allow platforms to set the PE target for SPIs. Change-Id: I7bf2ad79c04c2555ab310acba17823fb157327a3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | Tegra210: trigger CPU0 hotplug power on using FCsumitg2020-03-211-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hotplug poweron is not working for boot CPU as it's being triggerred using PMC and not with Flow Controller. This is happening because "cpu_powergate_mask" is only getting set for non-boot CPU's as the boot CPU's first bootup follows different code path. The patch is marking a CPU as ON within "cpu_powergate_mask" when turning its power domain on during power on. This will ensure only first bootup on all CPU's is using PMC and subsequent hotplug poweron will be using Flow Controller. Change-Id: Ie9e86e6f9a777d41508a93d2ce286f31307932c2 Signed-off-by: sumitg <sumitg@nvidia.com>
| * | | Tegra: memctrl: cleanup streamid override registersPritesh Raithatha2020-03-212-210/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Streamid override registers are passed to memctrl to program bypass streamid for all the registers. There is no reason to bypass SMMU for any of the client so need to remove register list and do not set streamid_override_cfg. Some Tegra186 platforms don't boot due to SDMMC failure so keep SDMMC bypass as of now. Will revisit once these issues are fixed. Change-Id: I3f67e2a0e1b53160e2218f3acace7da45532f934 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
| * | | Tegra: memctrl_v2: remove support to secure TZSRAMVarun Wadekar2020-03-214-92/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes support to secure the on-chip TZSRAM memory for Tegra186 and Tegra194 platforms as the previous bootloader does that for them. Change-Id: I50c7b7f9694285fe31135ada09baed1cfedaaf07 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | Tegra: include platform headers from individual makefilesVarun Wadekar2020-03-215-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies PLAT_INCLUDES to include individual Tegra SoC headers from the platform's makefile. Change-Id: If5248667f4e58ac18727d37a18fbba8e53f2d7b5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macroVarun Wadekar2020-03-212-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch renames 'ENABLE_WDT_LEGACY_FIQ_HANDLING' macro to 'ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING', to indicate that this is a Tegra feature. Change-Id: I5c4431e662223ee80efbfd5ec2513f8b1cadfc50 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | Tegra194: SiP function ID to read SMMU_PER registersVarun Wadekar2020-03-211-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces SiP function ID, 0xC200FF00, to read SMMU_PER error records from all supported SMMU blocks. The register values are passed over to the client via CPU registers X1 - X3, where X1 = SMMU_PER[instance #1] | SMMU_PER[instance #0] X2 = SMMU_PER[instance #3] | SMMU_PER[instance #2] X3 = SMMU_PER[instance #5] | SMMU_PER[instance #4] Change-Id: Id56263f558838ad05f6021f8432e618e99e190fc Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | Tegra: memctrl: map video memory as uncachedKen Chang2020-03-212-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memmap video memory as uncached normal memory by adding flag 'MT_NON_CACHEABLE' in mmap_add_dynamic_region(). This improves the time taken for clearing the non-overlapping video memory: test conditions: 32MB memory size, EMC running at 1866MHz, t186 1) without MT_NON_CACHEABLE: 30ms ~ 40ms <3>[ 133.852885] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000 <3>[ 133.860471] _tegra_set_vpr_params[120]: begin <3>[ 133.896481] _tegra_set_vpr_params[123]: end <3>[ 133.908944] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000 <3>[ 133.916397] _tegra_set_vpr_params[120]: begin <3>[ 133.956369] _tegra_set_vpr_params[123]: end <3>[ 133.970394] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000 <3>[ 133.977934] _tegra_set_vpr_params[120]: begin <3>[ 134.013874] _tegra_set_vpr_params[123]: end <3>[ 134.025666] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000 <3>[ 134.033512] _tegra_set_vpr_params[120]: begin <3>[ 134.065996] _tegra_set_vpr_params[123]: end <3>[ 134.075465] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000 <3>[ 134.082923] _tegra_set_vpr_params[120]: begin <3>[ 134.113119] _tegra_set_vpr_params[123]: end <3>[ 134.123448] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000 <3>[ 134.130790] _tegra_set_vpr_params[120]: begin <3>[ 134.162523] _tegra_set_vpr_params[123]: end <3>[ 134.172413] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000 <3>[ 134.179772] _tegra_set_vpr_params[120]: begin <3>[ 134.209142] _tegra_set_vpr_params[123]: end 2) with MT_NON_CACHEABLE: 10ms ~ 18ms <3>[ 102.108702] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000 <3>[ 102.116296] _tegra_set_vpr_params[120]: begin <3>[ 102.134272] _tegra_set_vpr_params[123]: end <3>[ 102.145839] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000 <3>[ 102.153226] _tegra_set_vpr_params[120]: begin <3>[ 102.164201] _tegra_set_vpr_params[123]: end <3>[ 102.172275] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000 <3>[ 102.179638] _tegra_set_vpr_params[120]: begin <3>[ 102.190342] _tegra_set_vpr_params[123]: end <3>[ 102.197524] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000 <3>[ 102.205085] _tegra_set_vpr_params[120]: begin <3>[ 102.216112] _tegra_set_vpr_params[123]: end <3>[ 102.224080] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000 <3>[ 102.231387] _tegra_set_vpr_params[120]: begin <3>[ 102.241775] _tegra_set_vpr_params[123]: end <3>[ 102.248825] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000 <3>[ 102.256069] _tegra_set_vpr_params[120]: begin <3>[ 102.266368] _tegra_set_vpr_params[123]: end <3>[ 102.273400] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000 <3>[ 102.280672] _tegra_set_vpr_params[120]: begin <3>[ 102.290929] _tegra_set_vpr_params[123]: end Change-Id: I5f604064ce7b8b73ea9ad5860156ae5e2c6cc42a Signed-off-by: Ken Chang <kenc@nvidia.com>
| * | | Tegra: remove support for USE_COHERENT_MEMKalyani Chidambaram2020-03-211-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the support for 'USE_COHERENT_MEM' as Tegra platforms no longer support the feature. Change-Id: If1c80fc4e5974412572b3bc1fdf9e70b1ee5d4ec Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
| * | | Tegra: remove circular dependency with common_def.hVarun Wadekar2020-03-211-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch stops including common_def.h from platform_def.h to fix a circular depoendency between them. This means platform_def.h now has to define the linker macros: * PLATFORM_LINKER_FORMAT * PLATFORM_LINKER_ARCH Change-Id: Icd540b1bd32fb37e0e455e9146c8b7f4b314e012 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | Tegra: include missing stdbool.hVarun Wadekar2020-03-212-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes the missing stdbool.h header from flowctrl.h and bpmp_ivc.c files. Change-Id: If60d19142b1cb8ae663fbdbdf1ffe45cbbdbc1b2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
| * | | Tegra: remove support for SEPARATE_CODE_AND_RODATA=0Kalyani Chidambaram2020-03-212-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra platforms will not be supporting SEPARATE_CODE_AND_RODATA=0. This patch uses the common macros provided by bl_common.h as a result and adds a check to assert if SEPARATE_CODE_AND_RODATA set is not set to '1'. Change-Id: I376ea60c00ad69cb855d89418bdb80623f14800e Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
* | | | Merge "plat/arm/sgi: mark remote chip shared ram as non-cacheable" into ↵Manish Pandey2020-03-231-1/+1
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generated by cgit v1.2.3 (git 2.25.1) at 2025-06-14 21:13:21 +0000