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author | Varun Wadekar <vwadekar@nvidia.com> | 2018-10-05 11:24:54 -0700 |
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committer | Varun Wadekar <vwadekar@nvidia.com> | 2020-03-21 19:00:05 -0700 |
commit | 7644e2aa6ecd110e213bdb422c2df0ce6290c0a0 (patch) | |
tree | d666f03ff9929c18c7205e6a637e3859bbb513d5 /plat | |
parent | bd0c2f8d99533f2fa497444e7b8c52ac0a3d76cd (diff) | |
download | platform_external_arm-trusted-firmware-7644e2aa6ecd110e213bdb422c2df0ce6290c0a0.tar.gz platform_external_arm-trusted-firmware-7644e2aa6ecd110e213bdb422c2df0ce6290c0a0.tar.bz2 platform_external_arm-trusted-firmware-7644e2aa6ecd110e213bdb422c2df0ce6290c0a0.zip |
Tegra: gicv2: initialize target masks
This patch initializes the target masks in the GICv2 driver
data, for all PEs. This will allow platforms to set the PE
target for SPIs.
Change-Id: I7bf2ad79c04c2555ab310acba17823fb157327a3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat')
-rw-r--r-- | plat/nvidia/tegra/common/tegra_gicv2.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/plat/nvidia/tegra/common/tegra_gicv2.c b/plat/nvidia/tegra/common/tegra_gicv2.c index 293df8d4f..012107e3b 100644 --- a/plat/nvidia/tegra/common/tegra_gicv2.c +++ b/plat/nvidia/tegra/common/tegra_gicv2.c @@ -1,20 +1,23 @@ /* * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <assert.h> - #include <platform_def.h> #include <common/bl_common.h> #include <drivers/arm/gicv2.h> #include <lib/utils.h> +#include <plat/common/platform.h> #include <tegra_private.h> #include <tegra_def.h> +static unsigned int tegra_target_masks[PLATFORM_CORE_COUNT]; + /****************************************************************************** * Tegra common helper to setup the GICv2 driver data. *****************************************************************************/ @@ -33,6 +36,8 @@ void tegra_gic_setup(const interrupt_prop_t *interrupt_props, tegra_gic_data.gicc_base = TEGRA_GICC_BASE; tegra_gic_data.interrupt_props = interrupt_props; tegra_gic_data.interrupt_props_num = interrupt_props_num; + tegra_gic_data.target_masks = tegra_target_masks; + tegra_gic_data.target_masks_num = ARRAY_SIZE(tegra_target_masks); gicv2_driver_init(&tegra_gic_data); } @@ -43,6 +48,7 @@ void tegra_gic_init(void) { gicv2_distif_init(); gicv2_pcpu_distif_init(); + gicv2_set_pe_target_mask(plat_my_core_pos()); gicv2_cpuif_enable(); } @@ -61,5 +67,6 @@ void tegra_gic_cpuif_deactivate(void) void tegra_gic_pcpu_init(void) { gicv2_pcpu_distif_init(); + gicv2_set_pe_target_mask(plat_my_core_pos()); gicv2_cpuif_enable(); } |