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* types: use int-ll64 for both aarch32 and aarch64Masahiro Yamada2018-04-275-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 031dbb122472 ("AArch32: Add essential Arch helpers"), it is difficult to use consistent format strings for printf() family between aarch32 and aarch64. For example, uint64_t is defined as 'unsigned long long' for aarch32 and as 'unsigned long' for aarch64. Likewise, uintptr_t is defined as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64. A problem typically arises when you use printf() in common code. One solution could be, to cast the arguments to a type long enough for both architectures. For example, if 'val' is uint64_t type, like this: printf("val = %llx\n", (unsigned long long)val); Or, somebody may suggest to use a macro provided by <inttypes.h>, like this: printf("val = %" PRIx64 "\n", val); But, both would make the code ugly. The solution adopted in Linux kernel is to use the same typedefs for all architectures. The fixed integer types in the kernel-space have been unified into int-ll64, like follows: typedef signed char int8_t; typedef unsigned char uint8_t; typedef signed short int16_t; typedef unsigned short uint16_t; typedef signed int int32_t; typedef unsigned int uint32_t; typedef signed long long int64_t; typedef unsigned long long uint64_t; [ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ] This gets along with the codebase shared between 32 bit and 64 bit, with the data model called ILP32, LP64, respectively. The width for primitive types is defined as follows: ILP32 LP64 int 32 32 long 32 64 long long 64 64 pointer 32 64 'long long' is 64 bit for both, so it is used for defining uint64_t. 'long' has the same width as pointer, so for uintptr_t. We still need an ifdef conditional for (s)size_t. All 64 bit architectures use "unsigned long" size_t, and most 32 bit architectures use "unsigned int" size_t. H8/300, S/390 are known as exceptions; they use "unsigned long" size_t despite their architecture is 32 bit. One idea for simplification might be to define size_t as 'unsigned long' across architectures, then forbid the use of "%z" string format. However, this would cause a distortion between size_t and sizeof() operator. We have unknowledge about the native type of sizeof(), so we need a guess of it anyway. I want the following formula to always return 1: __builtin_types_compatible_p(size_t, typeof(sizeof(int))) Fortunately, ARM is probably a majority case. As far as I know, all 32 bit ARM compilers use "unsigned int" size_t. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Fix pointer type mismatch of handlersMasahiro Yamada2018-04-279-84/+84
| | | | | | | | Commit 4c0d03907652 ("Rework type usage in Trusted Firmware") changed the type usage in struct declarations, but did not touch the definition side. Fix the type mismatch. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* css/sgi575: enable ARM_PLAT_MT flagSudipto Paul2018-04-181-0/+1
| | | | | | | | SGI-575 platform is based on Cortex-A75 processor which has its MT bit in the MPIDR register set to '1'. So the Arm platform layer code has to be made aware of this. Signed-off-by: Sudipto Paul <sudipto.paul@arm.com>
* Merge pull request #1250 from jollysxilinx/zynqmp-new-eemi-apiDimitris Papastamos2018-04-1714-25/+8834
|\ | | | | plat/xilinx: Add support for new platform management APIs for ZynqMP
| * zynqmp: pm: Minor corrections for MISRA complianceJolly Shah2018-03-1510-393/+438
| | | | | | | | | | | | Various changes to comply with MISRA static analysis rules Signed-off-by: Jolly Shah <jollys@xilinx.com>
| * zynqmp: pm_service: Support multiple SDIO modesRajan Vaja2018-03-152-237/+481
| | | | | | | | | | | | | | | | | | | | | | | | | | Existing database allows to set only single mode for SDIO. SDIO can have different groups (8 bit, 4 bit and 1 bit). As there is only single SDIO group in each pin, it is not possible to use different mode groups for SDIO. Extend database in generic way to allow multiuple function groups in single pin. Add different SDIO groups to pins and create separate functions for each modes. Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
| * zynqmp: pm: Support ATF PM version checkRajan Vaja2018-03-152-0/+10
| | | | | | | | | | | | | | Add SMC call to query ATF PM version. This version can be used by Linux to match with expected version. Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
| * zynqmp: pm: Update API version to 1.0Jolly Shah2018-03-151-2/+2
| | | | | | | | | | | | With new EEMI APIs addition, version is updated to 1.0 Signed-off-by: Jolly Shah <jollys@xilinx.com>
| * zynqmp: Use DDR memory when DEBUG is enabledJolly Shah2018-03-151-0/+5
| | | | | | | | | | | | | | | | | | | | Define default DDR location to which ATF has to compiled if DEBUG option is enabled. This is required now, as the ATF cant fit in OCM with DEBUG option enabled. The default value is 0x1000 and can be used till 0x7ffff. User can still override as per wish/requirement using current commandline options. Signed-off-by: Jolly Shah <jollys@xilinx.com>
| * zynqmp: pm: Add APIs for pin control queriesRajan Vaja2018-03-154-274/+3269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pin control APIs which driver can use to query pin information from firmware. Using these APIs, driver do not need to maintain hard-coded pin database. Major changes in patch are: - Add pin database with pins, functions and function groups information - Implement APIs for pin information queries - Update pin control APIs for get/set functions to use new pin control database. Remove pin database which was added earlier. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
| * zynqmp: pm: Add IOCTLs for global storage accessRajan Vaja2018-03-153-0/+100
| | | | | | | | | | | | | | | | Add IOCTLs to read/write global general storage and persistent global general storage registers access. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
| * zynqmp: pm: Implement clock APIsRajan Vaja2018-03-153-18/+3171
| | | | | | | | | | | | | | | | | | | | - Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
| * zynqmp: pm: Add clock control EEMI API and ioctl functionsRajan Vaja2018-03-159-1/+885
| | | | | | | | | | | | | | | | These are empty functions with no logic right now. Code will be added in subsequent commits. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
| * zynqmp: pm: Implement IOCTL APIs for device controlRajan Vaja2018-03-153-0/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement ioctl APIs which uses MMIO operations to configure devices. Below IOCTLs are supported in this patch: * Set tap delay bypass * Set SGMII mode * SD reset * Set SD/MMC tap delay Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
| * zynqmp: pm: Implement IOCTL APIs for remoteprocRajan Vaja2018-03-158-0/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement ioctl APIs which uses MMIO operations to control RPU operations. Below IOCTLs are supported in this patch: * Get RPU operation mode * Set RPU operation mode * Configure RPU boot address (OCM/TCM) * Configure TCM combined mode Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
| * zynqmp: pm: Implement pin control APIs for configurationsRajan Vaja2018-03-153-2/+296
| | | | | | | | | | | | | | | | Implement pin control APIs which uses MMIO operations to set/get values of configuration parameters. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
| * zynqmp: pm: Implement pin control APIs for get/set functionsRajan Vaja2018-03-156-5/+389
| | | | | | | | | | | | | | | | Implement pin control APIs which uses MMIO operations to set/get functions for the given pin. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
| * zynqmp: pm: Add wrappers for Pin control APIsRajan Vaja2018-03-154-4/+144
| | | | | | | | | | | | | | | | Add wrappers for pin control APIs. Actual implementation of these APIs would be done in subsequent changes. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
| * zynqmp: Add new function and node IDsRajan Vaja2018-03-151-1/+12
| | | | | | | | | | | | | | | | Add new function and node IDs supported by PMUFW in function list and node list respectively. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
* | Merge pull request #1346 from samarthp/sp/support-multiple-mhu-genDimitris Papastamos2018-04-1612-24/+105
|\ \ | | | | | | plat/arm: Add MHUv2 support to SCMI driver
| * | plat/arm: Add MHUv2 support to SCMI driverSamarth Parikh2018-04-1612-24/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the SCMI driver supports MHUv1, but Arm platforms may have varied versions of MHU driver, with MHUv2 controllers being in the latest Arm platforms. This patch updates the SCMI driver to support MHUv2, specifically that the sender must send the wake-up to the receiver before initiating any data transfer. Also, the existing mhu driver files, css_mhu.c and css_mhu.h, have been moved from the scpi directory to a new directory, css/drivers/mhu. Change-Id: I9b46b492a3e1d9e26db12d83a9773958a8c8402f Signed-off-by: Samarth Parikh <samarth.parikh@arm.com>
* | | Merge pull request #1356 from robertovargas-arm/misra-changesDimitris Papastamos2018-04-165-7/+10
|\ \ \ | | | | | | | | Misra changes
| * | | Fix MISRA rule 8.4 Part 4Roberto Vargas2018-04-131-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=fvp SPD=tspd TRUSTED_BOARD_BOOT=1 \ GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_rsa \ ROT_KEY=arm_rotprivk_rsa.pem MBEDTLS_DIR=mbedtls all Change-Id: Ie4cd6011b3e4fdcdd94ccb97a7e941f3b5b7aeb8 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
| * | | Fix MISRA rule 8.4 Part 3Roberto Vargas2018-04-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=fvp SPD=tspd all Change-Id: I0a16cf68fef29cf00ec0a52e47786f61d02ca4ae Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
| * | | Fix MISRA rule 8.3 Part 2Roberto Vargas2018-04-132-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rule 8.3: All declarations of an object or function shall use the same names and type qualifiers. Fixed for: make DEBUG=1 PLAT=juno LOG_LEVEL=50 all Change-Id: I0e4a03a0d2170cb1c632e079112a972091994a39 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
| * | | Fix MISRA rule 8.4 Part 1Roberto Vargas2018-04-131-0/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all Change-Id: I32b223251b8bf5924149d89431a65d3405a73d3e Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | | Merge pull request #1352 from hzhuang1/hikey_ddrDimitris Papastamos2018-04-133-110/+602
|\ \ \ | | | | | | | | Hikey ddr
| * | | hikey: clean sram before mcu usedHaojian Zhuang2018-04-111-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | Clean cache to flush parameters into SRAM before MCU using them. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * | | hikey: save ddr parameters into SRAMHaojian Zhuang2018-04-111-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Store those DDR parameters into SRAM. They may be used by MCU firmware. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * | | hikey: update ddr initializationHaojian Zhuang2018-04-113-108/+511
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix that DDR can't work at 533MHz. Now step to set DDR frequency from 150MHz to 800MHz. DDR could work among these frequency, 150MHz, 266MHz, 400MHz, 533MHz and 800MHz. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* | | | Merge pull request #1347 from davidcunado-arm/dc/affinitiesDimitris Papastamos2018-04-121-8/+14
|\ \ \ \ | | | | | | | | | | FVP: Fix function for translating MPIDR to linear index
| * | | | FVP: Fix function for translating MPIDR to linear indexDavid Cunado2018-04-061-8/+14
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current AArch32 version of plat_arm_calc_core_pos uses an incorrect algorithm to calculate the linear position of a core / PE from its MPIDR. This patch corrects the algorithm to: (ClusterId * FVP_MAX_CPUS_PER_CLUSTER) * FVP_MAX_PE_PER_CPU + (CPUId * FVP_MAX_PE_PER_CPU) + ThreadId which supports cores where there are more than 1 PE per CPU. NOTE: the AArch64 version was fixed in 39b21d1 Change-Id: I72aea89d8f72f8b1fef54e2177a0fa6fef0f5513 Signed-off-by: David Cunado <david.cunado@arm.com>
* | | | layerscape: fix integer handling issuesJiafei Pan2018-04-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Assert before actually using. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
* | | | Merge pull request #1342 from Summer-ARM/sq/support-tzmp1Dimitris Papastamos2018-04-117-68/+222
|\ \ \ \ | |_|/ / |/| | | support tzmp1
| * | | Juno: Add support for TrustZone Media Protection 1 (TZMP1)Summer Qin2018-04-104-3/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TZMP1 support on Juno and increase the BL2 size accordingly due to the extra data structures to describe the TZC regions and the additional code. Signed-off-by: Summer Qin <summer.qin@arm.com>
| * | | plat/arm: Allow override of default TZC regionsSummer Qin2018-04-104-66/+51
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows the ARM Platforms to specify the TZC regions to be specified to the ARM TZC helpers in arm_tzc400.c and arm_tzc_dmc500.c. If the regions are not specified then the default TZC region will be configured by these helpers. This override mechanism allows specifying special regions for TZMP1 usecase. Signed-off-by: Summer Qin <summer.qin@arm.com>
* | | Merge pull request #1349 from amitdanielkachhap/juno_fix_bl2_sizesDimitris Papastamos2018-04-101-3/+5
|\ \ \ | | | | | | | | Juno: Increase bl2 max size to fix build when SPD=opteed
| * | | Juno: Increase bl2 max size to fix build when SPD=opteedAmit Daniel Kachhap2018-04-091-3/+5
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building TBBR(SPD=opteed) and non-TBBR TF-A images is breaking for Juno for different configurations listed below: * Overflow error of 4096 bytes for rsa algorithm. * Overflow error of 8192 bytes for ecdsa algorithm. * Overflow error of 4096 bytes for rsa+ecdsa algorithm. * Overflow error of 4096 bytes for non-TBBR case. So this patch increments macro PLAT_ARM_MAX_BL2_SIZE for all the above cases accordingly. Change-Id: I75ec6c0a718181d34553fe55437f0496f467683f Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
* / / layerscape: Initial TF-A support for LS1043ardbJiafei Pan2018-04-1040-0/+3260
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduce TF-A support for NXP's ls1043a platform. more details information of ls1043a chip and ls1043ardb board can be found at docs/plat/ls1043a.rst. Boot sequence on ls1043a is: bootrom loads bl1 firstly, then bl1 loads bl2, bl2 will load bl31, bl32 and bl33, bl31 will boot bl32(tee os) and bl33(u-boot or uefi), bl33 boot Linux kernel. Now TF-A on ls1043ardb platform has the following features in this patch: * Support boot from Nor flash. * TF-A can boot bl33 which runs in el2 of non-secure world. * TF-A boot OPTee OS. * Support PSCI Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: Chenyin.Ha <Chenyin.Ha@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com> Signed-off-by: Wen He <wen.he_1@nxp.com>
* | Merge pull request #1334 from ↵Dimitris Papastamos2018-04-033-20/+22
|\ \ | | | | | | | | | | | | michpappas/tf-issues#572_qemu_dont_use_C_for_crash_console qemu: don't use C functions for the crash console callbacks
| * | qemu: don't use C functions for the crash console callbacksMichalis Pappas2018-03-313-20/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the console_pl011_core_* functions directly in the crash console callbacks. This bypasses the MULTI_CONSOLE_API for the crash console (UART1), but allows using the crash console before the C runtime has been initialized (eg to call ASM_ASSERT). This retains backwards compatibility with respect to functionality when the old API is used. Use the MULTI_CONSOLE_API to register UART0 as the boot and runtime console. Fixes ARM-software/tf-issues#572 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
* | | Merge pull request #1327 from npoushin/npoushin/sgi575Dimitris Papastamos2018-03-2915-0/+649
|\ \ \ | | | | | | | | ARM platforms: Add support for SGI575
| * | | ARM platforms: Add support for SGI575Nariman Poushin2018-03-2815-0/+649
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for System Guidance for Infrastructure platform SGI575. Change-Id: I0125c2ed4469fbc8367dafcc8adce770b6b3147d Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
* | | | Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statementsDimitris Papastamos2018-03-2918-45/+62
|\ \ \ \ | | | | | | | | | | Fix switch statements to comply with MISRA rules
| * | | | plat: fix switch statements to comply with MISRA rulesJonathan Wright2018-03-2618-42/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure (where possible) that switch statements in plat comply with MISRA rules 16.1 - 16.7. Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
| * | | | plat/common: remove fall-through on release buildJonathan Wright2018-03-261-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removes fall-through in switch statement on unknown interrupt type in release builds. Previous behaviour was to assert(0) on default case in debug builds but fall through and interpret the unknown interrupt type as INTR_TYPE_EL3 in release builds. Change-Id: I05fb0299608efda0f9eda2288d3e56e5625e05c9 Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
* | | | | Merge pull request #1325 from ↵Dimitris Papastamos2018-03-293-2/+29
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | michpappas/tf-issues#568_qemu_add_ENABLE_STACK_PROTECTOR qemu: Add support for stack canary protection
| * | | | | qemu: Add support for stack canary protectionMichalis Pappas2018-03-203-2/+29
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow qemu users to enable stack protection. Since the virt platform does not provide an RNG, use a basic, timer-based, canary generation, similarly to FVP. Increase SRAM size and BL2 size to fit images when stack protection is enabled. Notice that stack protection is not enabled by default in qemu. Fixes ARM-software/tf-issues#568 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
* | | | | Merge pull request #1331 from hzhuang1/reboot_delayDimitris Papastamos2018-03-291-0/+4
|\ \ \ \ \ | | | | | | | | | | | | hikey960: add delay before reset
| * | | | | hikey960: add delay before resetHaojian Zhuang2018-03-281-0/+4
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If system is still accessing storage device, reboot operation may cause data broken. So add the flush and delay operation before system reset. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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