zynqmp: pm: Implement pin control APIs for get/set functions

Implement pin control APIs which uses MMIO operations
to set/get functions for the given pin.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

6 files changed, 389 insertions, 5 deletions

diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index bddf30562..cefb73a65 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 
@@ -77,6 +77,7 @@ BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
 				plat/xilinx/zynqmp/zynqmp_ipi.c		\
 				plat/xilinx/zynqmp/pm_service/pm_svc_main.c	\
 				plat/xilinx/zynqmp/pm_service/pm_api_sys.c	\
+				plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c	\
 				plat/xilinx/zynqmp/pm_service/pm_ipi.c		\
 				plat/xilinx/zynqmp/pm_service/pm_client.c	\
 				plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
new file mode 100644
index 000000000..01cc0c8a2
--- /dev/null
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * ZynqMP system level PM-API functions for pin control.
+ */
+
+#include <arch_helpers.h>
+#include <platform.h>
+#include "pm_api_pinctrl.h"
+#include "pm_api_sys.h"
+#include "pm_client.h"
+#include "pm_common.h"
+#include "pm_ipi.h"
+
+#define PINCTRL_FUNCTION_MASK			0xFE
+#define NFUNCS_PER_PIN				13
+
+#define PINMUX_MAP(pin, f0, f1, f2, f3, f4, f5, f6,	\
+		   f7, f8, f9, f10, f11, f12)		\
+	[pin] = {					\
+		.funcs =  {				\
+			f0,				\
+			f1,				\
+			f2,				\
+			f3,				\
+			f4,				\
+			f5,				\
+			f6,				\
+			f7,				\
+			f8,				\
+			f9,				\
+			f10,				\
+			f11,				\
+			f12,				\
+		},					\
+	}
+
+struct pm_pinctrl_pinmux_map {
+	uint8_t funcs[NFUNCS_PER_PIN];
+};
+
+static uint8_t pm_pinctrl_mux[NFUNCS_PER_PIN] = {
+	0x02, 0x04, 0x08, 0x10, 0x18,
+	0x00, 0x20, 0x40, 0x60, 0x80,
+	0xA0, 0xC0, 0xE0
+};
+
+struct pm_pinctrl_pinmux_map pinmux_maps[] = {
+	PINMUX_MAP(0, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(1, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(2, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(3, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(4, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(5, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(6, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(7, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(8, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(9, NODE_QSPI, NODE_NAND, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(10, NODE_QSPI, NODE_NAND, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(11, NODE_QSPI, NODE_NAND, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(12, NODE_QSPI, NODE_NAND, NODE_UNKNOWN, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(13, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(14, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(15, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(16, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(17, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(18, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_UNKNOWN),
+	PINMUX_MAP(19, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_CSU, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_UNKNOWN),
+	PINMUX_MAP(20, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_CSU, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_UNKNOWN),
+	PINMUX_MAP(21, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_CSU, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_UNKNOWN),
+	PINMUX_MAP(22, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_CSU, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_UNKNOWN),
+	PINMUX_MAP(23, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_CSU, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_UNKNOWN),
+	PINMUX_MAP(24, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_CSU, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_UNKNOWN, NODE_TTC_3, NODE_UART_1, NODE_UNKNOWN),
+	PINMUX_MAP(25, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN,
+		   NODE_CSU, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_UNKNOWN, NODE_TTC_3, NODE_UART_1, NODE_UNKNOWN),
+	PINMUX_MAP(26, NODE_ETH_0, NODE_NAND, NODE_PMU, NODE_TESTSCAN,
+		   NODE_CSU, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(27, NODE_ETH_0, NODE_NAND, NODE_PMU, NODE_TESTSCAN,
+		   NODE_DP, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(28, NODE_ETH_0, NODE_NAND, NODE_PMU, NODE_TESTSCAN,
+		   NODE_DP, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(29, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN,
+		   NODE_DP, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(30, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN,
+		   NODE_DP, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(31, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN,
+		   NODE_CSU, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(32, NODE_ETH_0, NODE_NAND, NODE_PMU, NODE_TESTSCAN,
+		   NODE_CSU, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(33, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN,
+		   NODE_CSU, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(34, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN,
+		   NODE_DP, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(35, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN,
+		   NODE_DP, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(36, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN,
+		   NODE_DP, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(37, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN,
+		   NODE_DP, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(38, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(39, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(40, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(41, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(42, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(43, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(44, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_UNKNOWN),
+	PINMUX_MAP(45, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_UNKNOWN),
+	PINMUX_MAP(46, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_UNKNOWN),
+	PINMUX_MAP(47, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_UNKNOWN),
+	PINMUX_MAP(48, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_TTC_3, NODE_UART_1, NODE_UNKNOWN),
+	PINMUX_MAP(49, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_TTC_3, NODE_UART_1, NODE_UNKNOWN),
+	PINMUX_MAP(50, NODE_GEM_TSU, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_ETH_1, NODE_TTC_2, NODE_UART_0, NODE_UNKNOWN),
+	PINMUX_MAP(51, NODE_GEM_TSU, NODE_UNKNOWN, NODE_UNKNOWN, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_ETH_1, NODE_TTC_2, NODE_UART_0, NODE_UNKNOWN),
+	PINMUX_MAP(52, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(53, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(54, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(55, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG,
+		   NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(56, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(57, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(58, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG,
+		   NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(59, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG,
+		   NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(60, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG,
+		   NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(61, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG,
+		   NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(62, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(63, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(64, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(65, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(66, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(67, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE),
+	PINMUX_MAP(68, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_UNKNOWN,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(69, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE),
+	PINMUX_MAP(70, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_UNKNOWN),
+	PINMUX_MAP(71, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_UNKNOWN),
+	PINMUX_MAP(72, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_UNKNOWN, NODE_UART_1, NODE_UNKNOWN),
+	PINMUX_MAP(73, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1,
+		   NODE_SPI_1, NODE_UNKNOWN, NODE_UART_1, NODE_UNKNOWN),
+	PINMUX_MAP(74, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_UNKNOWN, NODE_UART_0, NODE_UNKNOWN),
+	PINMUX_MAP(75, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0,
+		   NODE_SPI_1, NODE_UNKNOWN, NODE_UART_0, NODE_UNKNOWN),
+	PINMUX_MAP(76, NODE_UNKNOWN, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_ETH_0,
+		   NODE_ETH_1, NODE_ETH_2, NODE_ETH_3, NODE_UNKNOWN),
+	PINMUX_MAP(77, NODE_UNKNOWN, NODE_UNKNOWN, NODE_UNKNOWN, NODE_SD_1,
+		   NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_ETH_0,
+		   NODE_ETH_1, NODE_ETH_2, NODE_ETH_3, NODE_UNKNOWN),
+};
+
+/**
+ * pm_api_pinctrl_get_function() - Read function id set for the given pin
+ * @pin		Pin number
+ * @nid		Node ID of function currently set for given pin
+ *
+ * This function provides the function currently set for the given pin.
+ *
+ * @return	Returns status, either success or error+reason
+ */
+enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin,
+					       enum pm_node_id *nid)
+{
+	struct pm_pinctrl_pinmux_map *pinmux_map = &pinmux_maps[pin];
+	int i, ret = PM_RET_SUCCESS;
+	unsigned int reg, val;
+
+	reg = IOU_SLCR_BASEADDR + 4 * pin;
+	ret = pm_mmio_read(reg, &val);
+	if (ret)
+		return ret;
+
+	val &= PINCTRL_FUNCTION_MASK;
+
+	for (i = 0; i < NFUNCS_PER_PIN; i++)
+		if (val == pm_pinctrl_mux[i])
+			break;
+
+	if (i == NFUNCS_PER_PIN)
+		return PM_RET_ERROR_NOTSUPPORTED;
+
+	*nid = pinmux_map->funcs[i];
+
+	return ret;
+}
+
+/**
+ * pm_api_pinctrl_set_function() - Set function id set for the given pin
+ * @pin		Pin number
+ * @nid		Node ID of function to set for given pin
+ *
+ * This function provides the function currently set for the given pin.
+ *
+ * @return	Returns status, either success or error+reason
+ */
+enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin,
+					       enum pm_node_id nid)
+{
+	struct pm_pinctrl_pinmux_map *pinmux_map = &pinmux_maps[pin];
+	int i;
+	unsigned int reg, val;
+
+	for (i = 0; i < NFUNCS_PER_PIN; i++)
+		if (nid == pinmux_map->funcs[i])
+			break;
+
+	if (i == NFUNCS_PER_PIN)
+		return PM_RET_ERROR_NOTSUPPORTED;
+
+	reg = IOU_SLCR_BASEADDR + 4 * pin;
+	val = pm_pinctrl_mux[i];
+
+	return pm_mmio_write(reg, PINCTRL_FUNCTION_MASK, val);
+}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
new file mode 100644
index 000000000..a7e740b0f
--- /dev/null
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * ZynqMP system level PM-API functions for pin control.
+ */
+
+#ifndef _PM_API_PINCTRL_H_
+#define _PM_API_PINCTRL_H_
+
+#include "pm_common.h"
+
+enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin,
+					       enum pm_node_id nid);
+enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin,
+					       enum pm_node_id *nid);
+
+#endif /* _PM_API_PINCTRL_H_ */
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
index 5bc344227..027d1fe87 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
@@ -11,6 +11,7 @@
 
 #include <arch_helpers.h>
 #include <platform.h>
+#include "pm_api_pinctrl.h"
 #include "pm_api_sys.h"
 #include "pm_client.h"
 #include "pm_common.h"
@@ -584,7 +585,7 @@ enum pm_ret_status pm_pinctrl_release(unsigned int pin)
 enum pm_ret_status pm_pinctrl_get_function(unsigned int pin,
 					   enum pm_node_id *nid)
 {
-	return PM_RET_SUCCESS;
+	return pm_api_pinctrl_get_function(pin, nid);
 }
 
 /**
@@ -599,7 +600,7 @@ enum pm_ret_status pm_pinctrl_get_function(unsigned int pin,
 enum pm_ret_status pm_pinctrl_set_function(unsigned int pin,
 					   enum pm_node_id nid)
 {
-	return PM_RET_SUCCESS;
+	return pm_api_pinctrl_set_function(pin, nid);
 }
 
 /**
diff --git a/plat/xilinx/zynqmp/pm_service/pm_defs.h b/plat/xilinx/zynqmp/pm_service/pm_defs.h
index 7b26c1587..c9656e31f 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_defs.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_defs.h
@@ -149,7 +149,15 @@ enum pm_node_id {
 	NODE_IPI_PL_2,
 	NODE_IPI_PL_3,
 	NODE_PL,
-	NODE_MAX
+	NODE_GEM_TSU,
+	NODE_SWDT_0,
+	NODE_SWDT_1,
+	NODE_CSU,
+	NODE_PJTAG,
+	NODE_TRACE,
+	NODE_TESTSCAN,
+	NODE_PMU,
+	NODE_MAX,
 };
 
 enum pm_request_ack {
diff --git a/plat/xilinx/zynqmp/zynqmp_def.h b/plat/xilinx/zynqmp/zynqmp_def.h
index e90ad02c5..45fa387d6 100644
--- a/plat/xilinx/zynqmp/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/zynqmp_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -174,4 +174,6 @@
 #define ACTLR_EL3_L2ACTLR_BIT	(1 << 6)
 #define ACTLR_EL3_CPUACTLR_BIT	(1 << 0)
 
+#define IOU_SLCR_BASEADDR		0xFF180000
+
 #endif /* __ZYNQMP_DEF_H__ */