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* Neoverse N1: Forces cacheable atomic to nearLouis Mayencourt2019-04-181-0/+6
| | | | | | | | This patch forces all cacheable atomic instructions to be near, which improves performance in highly contended parallelized use-cases. Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* DSU: Implement workaround for errata 798953Louis Mayencourt2019-04-175-1/+78
| | | | | | | | | Under certain near idle conditions, DSU may miss response transfers on the ACE master or Peripheral port, leading to deadlock. This workaround disables high-level clock gating of the DSU to prevent this. Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* DSU: Small fix and reformat on errata frameworkLouis Mayencourt2019-04-171-22/+22
| | | | | Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* Cortex-A35: Implement workaround for errata 855472Louis Mayencourt2019-04-172-2/+57
| | | | | | | | | Under specific conditions, the processor might issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. Set the CPUACTLR.ENDCCASCI bit to 1 to avoid this. Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* Cortex A9:errata 794073 workaroundJoel Hutton2019-04-123-1/+22
| | | | | | | | | | | | | On Cortex A9 an errata can cause the processor to violate the rules for speculative fetches when the MMU is off but branch prediction has not been disabled. The workaround for this is to execute an Invalidate Entire Branch Prediction Array (BPIALL) followed by a DSB. see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf for more details. Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93 Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>
* cache_helpers.s:fix mixed tabs and spacesJoel Hutton2019-04-101-9/+9
| | | | | Change-Id: I8b7c7888d09200410e1a1c11a070c94dd8013ea7 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
* Add note about erratum 814220 for A7Joel Hutton2019-04-101-1/+3
| | | | | | | | | | On Cortex-A7 an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation. The mitigation for this is to use a `DSB` instruction before changing cache. The cache cleaning code happens to already be doing this, so only a comment was added. Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
* Add support for Cortex-A76AE CPUAlexei Fedorov2019-04-081-0/+56
| | | | | Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Remove deprecated interfacesAmbroise Vincent2019-04-031-30/+0
| | | | | Change-Id: I14fcabbdfd53153d1d5f187f6f8b23a045794408 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* SPM: Move shim layer to TTBR1_EL1Antonio Nino Diaz2019-04-032-4/+4
| | | | | | | | | | | | This gives each Secure Partition complete freedom on its address space. Previously, the memory used by the exception vectors was reserved and couldn't be used. Also, it always had to be mapped, forcing SPM to generate translation tables that included the exception vectors as well as the Partition memory regions. With this change, partitions can reduce their address space size easily. Change-Id: I67fb5e9bdf2870b73347f23bff702fab0a8f8711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Remove several warnings reported with W=2Ambroise Vincent2019-04-011-2/+2
| | | | | | | | | | | | | Improved support for W=2 compilation flag by solving some nested-extern and sign-compare warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed. Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Remove several warnings reported with W=1Ambroise Vincent2019-04-014-4/+8
| | | | | | | | | | | | | | Improved support for W=1 compilation flag by solving missing-prototypes and old-style-definition warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed without heavy structural changes. Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Merge pull request #1902 from jts-arm/romlibDimitris Papastamos2019-03-212-12/+9
|\ | | | | ROMLIB bug fixes
| * ROMLIB bug fixesJohn Tsichritzis2019-03-212-12/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed the below bugs: 1) Bug related to build flag V=1: if the flag was V=0, building with ROMLIB would fail. 2) Due to a syntax bug in genwrappers.sh, index file entries marked as "patch" or "reserved" were ignored. 3) Added a prepending hash to constants that genwrappers is generating. 4) Due to broken dependencies, currently the inclusion functionality is intentionally not utilised. This is why the contents of romlib/jmptbl.i have been copied to platform specific jmptbl.i files. As a result of the broken dependencies, when changing the index files, e.g. patching functions, a clean build is always required. This is a known issue that will be fixed in the future. Change-Id: I9d92aa9724e86d8f90fcd3e9f66a27aa3cab7aaa Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* | Merge pull request #1887 from ambroise-arm/av/a76-cveDimitris Papastamos2019-03-201-13/+16
|\ \ | |/ |/| Cortex-A76: Optimize CVE_2018_3639 workaround
| * Cortex-A76: Optimize CVE_2018_3639 workaroundAmbroise Vincent2019-03-141-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Switched from a static check to a runtime assert to make sure a workaround is implemented for CVE_2018_3639. This allows platforms that know they have the SSBS hardware workaround in the CPU to compile out code under DYNAMIC_WORKAROUND_CVE_2018_3639. The gain in memory size without the dynamic workaround is 4KB in bl31. Change-Id: I61bb7d87c59964b0c7faac5d6bc7fc5c4651cbf3 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * Cortex-A76: fix spellingAmbroise Vincent2019-03-141-6/+6
| | | | | | | | | | Change-Id: I6adf7c14e8a974a7d40d51615b5e69eab1a7436f Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | Merge pull request #1900 from soby-mathew/sm/revert_xlat_changesSoby Mathew2019-03-192-341/+153
|\ \ | | | | | | xlat_tables_v2: Revert recent changes to remove recursion
| * | xlat_tables_v2: Revert recent changes to remove recursionAntonio Nino Diaz2019-03-192-341/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit reverts the following commits: - c54c7fc35842 ("xlat_tables_v2: print xlat tables without recursion") - db8cac2d986a ("xlat_tables_v2: unmap region without recursion.") - 0ffe269215bd ("xlat_tables_v2: map region without recursion.") This was part of PR#1843. A problem has been detected in one of our test run configurations involving dynamic mapping of regions and it is blocking the next release. Until the problem can be solved, it is safer to revert the changes. Change-Id: I3d5456e4dbebf291c8b74939c6fb02a912e0903b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1892 from sandrine-bailleux-arm/sb/pauthSoby Mathew2019-03-181-1/+1
|\ \ \ | |/ / |/| | Pointer authentication fixes
| * | Fix restoring APIBKey registersSandrine Bailleux2019-03-141-1/+1
| |/ | | | | | | | | | | | | | | Instruction key A was incorrectly restored in the instruction key B registers. Change-Id: I4cb81ac72180442c077898509cb696c9d992eda3 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | Merge pull request #1888 from jts-arm/zeusDimitris Papastamos2019-03-151-0/+60
|\ \ | | | | | | Introduce preliminary support for Neoverse Zeus
| * | Introduce preliminary support for Neoverse ZeusJohn Tsichritzis2019-03-141-0/+60
| |/ | | | | | | | | Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* / Apply variant 4 mitigation for Neoverse N1John Tsichritzis2019-03-141-0/+4
|/ | | | | | | | | This patch applies the new MSR instruction to directly set the PSTATE.SSBS bit which controls speculative loads. This new instruction is available at Neoverse N1 core so it's utilised. Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Cortex-A17: Implement workaround for errata 852423Ambroise Vincent2019-03-132-0/+44
| | | | | Change-Id: I3a101e540f0b134ecf9a51fa3d7d8e3d0369b297 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Cortex-A17: Implement workaround for errata 852421Ambroise Vincent2019-03-132-1/+47
| | | | | Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Merge pull request #1882 from ambroise-arm/av/a15-errataSoby Mathew2019-03-132-1/+78
|\ | | | | Apply workarounds for errata of Cortex-A15
| * Cortex-A15: Implement workaround for errata 827671Ambroise Vincent2019-03-132-0/+47
| | | | | | | | | | | | | | | | | | | | This erratum can only be worked around on revisions >= r3p0 because the register that needs to be accessed only exists in those revisions[1]. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * Cortex-A15: Implement workaround for errata 816470Ambroise Vincent2019-03-132-1/+31
| | | | | | | | | | Change-Id: I9755252725be25bfd0147839d7df56888424ff84 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | Merge pull request #1880 from lmayencourt/lm/pieSoby Mathew2019-03-131-4/+4
|\ \ | | | | | | PIE: fix linking with pie and binutils > 2.27
| * | PIE: Correct minor typographical errorsLouis Mayencourt2019-03-121-4/+4
| |/ | | | | | | | | Change-Id: Ie7832b2ebffe15d53ffe3584e4d23a449d4f81ac Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Merge pull request #1843 from DavidPu/xlat_tables_v2_non_recursionSoby Mathew2019-03-132-153/+341
|\ \ | |/ |/| Remove recursion from xlat_tables_v2 library
| * xlat_tables_v2: print xlat tables without recursionDavid Pu2019-03-051-55/+111
| | | | | | | | | | | | | | | | | | | | This patch uses an array on stack to save parent xlat table information when traversing the xlat tables. It keeps exactly same xlat table traversal order compared to recursive version. fixes arm-software/tf-issues#664 Signed-off-by: David Pu <dpu@nvidia.com>
| * xlat_tables_v2: unmap region without recursion.David Pu2019-03-051-41/+109
| | | | | | | | | | | | | | | | | | | | This patch uses an array on stack to save parent xlat table information when traversing the xlat tables. It keeps exactly same xlat table traversal order compared to recursive version. fixes arm-software/tf-issues#664 Signed-off-by: David Pu <dpu@nvidia.com>
| * xlat_tables_v2: map region without recursion.David Pu2019-03-051-56/+120
| | | | | | | | | | | | | | | | | | | | This patch uses an array on stack to save parent xlat table information when traversing the xlat tables. It keeps exactly same xlat table traversal order compared to recursive version. fixes arm-software/tf-issues#664 Signed-off-by: David Pu <dpu@nvidia.com>
* | Fixup register handling in aarch32 reset_handlerHeiko Stuebner2019-03-081-3/+3
|/ | | | | | | | | | | | | | | | The BL handover interface stores the bootloader arguments in registers r9-r12, so when the reset_handler stores the lr pointer in r10 it clobers one of the arguments. Adapt to use r8 and adapt the comment about registers allowed to clober. I've checked aarch32 reset_handlers and none seem to use higher registers as far as I can tell. Fixes: a6f340fe58b9 ("Introduce the new BL handover interface") Cc: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* Merge pull request #1842 from DavidPu/reduce_cyclomatic_complexity_metricAntonio Niño Díaz2019-03-011-75/+99
|\ | | | | Reduce cyclomatic complexity metric
| * xlat_tables_v2: find VA/idx with helper functions.David Pu2019-02-281-26/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces 2 helper functions 'xlat_tables_find_start_va' and 'xlat_tables_va_to_index' to find the first VA and table index affected by the specified mmap region. it reduces code duplication and cyclomatic code complexity in xlat_tables_map/unmap_region functions. Cyclomatic complexity calculated using 'Coverity' fixes arm-software/tf-issues#673 Signed-off-by: David Pu <dpu@nvidia.com>
| * xlat_tables_v2: get unmap action type with helper function.David Pu2019-02-281-49/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces helper function 'xlat_tables_unmap_region_action' to get the required action type from given arguments when unmapping the specified region. it reduces cyclomatic code complexity in xlat_tables_unmap_region function. Cyclomatic complexity calculated using 'Coverity' fixes arm-software/tf-issues#673 Signed-off-by: David Pu <dpu@nvidia.com>
* | Merge pull request #1751 from vwadekar/tegra-scatter-file-supportAntonio Niño Díaz2019-03-012-2/+4
|\ \ | | | | | | Tegra scatter file support
| * | Tegra: Support for scatterfile for the BL31 imageVarun Wadekar2019-02-272-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support for using the scatterfile format as the linker script with the 'armlink' linker for Tegra platforms. In order to enable the scatterfile usage the following changes have been made: * provide mapping for ld.S symbols in bl_common.h * include bl_common.h from all the affected files * update the makefile rules to use the scatterfile and armlink to compile BL31 * update pubsub.h to add sections to the scatterfile NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY. Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | Merge pull request #1849 from loumay-arm/lm/a73_errataAntonio Niño Díaz2019-03-012-0/+44
|\ \ \ | | | | | | | | Cortex-A73: Implement workaround for errata 852427
| * | | Cortex-A73: Implement workaround for errata 852427Louis Mayencourt2019-02-282-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In AArch32, execution of 2 instructions with opposite condition code might lead to either a data corruption or a CPU deadlock. Set the bit 12 of the Diagnostic Register to prevent this. Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | | Merge pull request #1845 from ambroise-arm/av/errataAntonio Niño Díaz2019-03-016-5/+488
|\ \ \ \ | | | | | | | | | | Apply workarounds for errata of Cortex-A53, A55 and A57
| * | | | Cortex-A53: Workarounds for 819472, 824069 and 827319Ambroise Vincent2019-02-283-2/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The workarounds for these errata are so closely related that it is better to only have one patch to make it easier to understand. Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | | | Cortex-A57: Implement workaround for erratum 817169Ambroise Vincent2019-02-283-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | | | Cortex-A57: Implement workaround for erratum 814670Ambroise Vincent2019-02-283-2/+79
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | | | Cortex-A55: Implement workaround for erratum 903758Ambroise Vincent2019-02-282-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: I07e69061ba7a918cdfaaa83fa3a42dee910887d7 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | | | Cortex-A55: Implement workaround for erratum 846532Ambroise Vincent2019-02-282-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: Iacb6331c1f6b27340e71279f92f147ebbc71862f Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | | | Cortex-A55: Implement workaround for erratum 798797Ambroise Vincent2019-02-282-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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