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| author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2019-03-27 11:10:31 +0000 |
|---|---|---|
| committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2019-04-03 10:51:31 +0100 |
| commit | 6de6965b2fcaffec01b2679118d16eabfde4d9c9 (patch) | |
| tree | 96734032d5d6de50bfa2ba210618c8e88344f061 /lib | |
| parent | 5db5930bafe00db095c2aed150fdbc45059b692a (diff) | |
| download | platform_external_arm-trusted-firmware-6de6965b2fcaffec01b2679118d16eabfde4d9c9.tar.gz platform_external_arm-trusted-firmware-6de6965b2fcaffec01b2679118d16eabfde4d9c9.tar.bz2 platform_external_arm-trusted-firmware-6de6965b2fcaffec01b2679118d16eabfde4d9c9.zip | |
SPM: Move shim layer to TTBR1_EL1
This gives each Secure Partition complete freedom on its address space.
Previously, the memory used by the exception vectors was reserved and
couldn't be used. Also, it always had to be mapped, forcing SPM to
generate translation tables that included the exception vectors as well
as the Partition memory regions. With this change, partitions can reduce
their address space size easily.
Change-Id: I67fb5e9bdf2870b73347f23bff702fab0a8f8711
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/xlat_tables/aarch64/xlat_tables.c | 6 | ||||
| -rw-r--r-- | lib/xlat_tables_v2/aarch64/xlat_tables_arch.c | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c index e64fd3ef7..c86412c9b 100644 --- a/lib/xlat_tables/aarch64/xlat_tables.c +++ b/lib/xlat_tables/aarch64/xlat_tables.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -174,12 +174,12 @@ void init_xlat_tables(void) /* Inner & outer non-cacheable non-shareable. */\ tcr = TCR_SH_NON_SHAREABLE | \ TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC | \ - (uint64_t) t0sz; \ + ((uint64_t)t0sz << TCR_T0SZ_SHIFT); \ } else { \ /* Inner & outer WBWA & shareable. */ \ tcr = TCR_SH_INNER_SHAREABLE | \ TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \ - (uint64_t) t0sz; \ + ((uint64_t)t0sz << TCR_T0SZ_SHIFT); \ } \ tcr |= _tcr_extra; \ write_tcr_el##_el(tcr); \ diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c index e7593dde7..8eeeea1dd 100644 --- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c @@ -248,7 +248,7 @@ void setup_mmu_cfg(uint64_t *params, unsigned int flags, */ int t0sz = 64 - __builtin_ctzll(virtual_addr_space_size); - tcr = (uint64_t) t0sz; + tcr = (uint64_t)t0sz << TCR_T0SZ_SHIFT; /* * Set the cacheability and shareability attributes for memory |