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| author | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-03-05 09:54:21 +0000 |
|---|---|---|
| committer | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-03-13 14:05:47 +0000 |
| commit | 5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23 (patch) | |
| tree | d5918159a05a43b97db0777f4267c4248082a000 /lib | |
| parent | 75a1ada95efa78e4133bdd947c64944005a8e5c2 (diff) | |
| download | platform_external_arm-trusted-firmware-5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23.tar.gz platform_external_arm-trusted-firmware-5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23.tar.bz2 platform_external_arm-trusted-firmware-5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23.zip | |
Cortex-A15: Implement workaround for errata 827671
This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html
Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch32/cortex_a15.S | 39 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 8 |
2 files changed, 47 insertions, 0 deletions
diff --git a/lib/cpus/aarch32/cortex_a15.S b/lib/cpus/aarch32/cortex_a15.S index 8c3bbf41e..ab136adf4 100644 --- a/lib/cpus/aarch32/cortex_a15.S +++ b/lib/cpus/aarch32/cortex_a15.S @@ -62,6 +62,35 @@ func check_errata_816470 bx lr endfunc check_errata_816470 + /* ---------------------------------------------------- + * Errata Workaround for Cortex A15 Errata #827671. + * This applies only to revision >= r3p0 of Cortex A15. + * Inputs: + * r0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: r0-r3 + * ---------------------------------------------------- + */ +func errata_a15_827671_wa + /* + * Compare r0 against revision r3p0 + */ + mov r2, lr + bl check_errata_827671 + cmp r0, #ERRATA_NOT_APPLIES + beq 1f + ldcopr r0, CORTEX_A15_ACTLR2 + orr r0, #CORTEX_A15_ACTLR2_INV_DCC_BIT + stcopr r0, CORTEX_A15_ACTLR2 + isb +1: + bx r2 +endfunc errata_a15_827671_wa + +func check_errata_827671 + mov r1, #0x30 + b cpu_rev_var_hs +endfunc check_errata_827671 + func check_errata_cve_2017_5715 #if WORKAROUND_CVE_2017_5715 mov r0, #ERRATA_APPLIES @@ -86,6 +115,7 @@ func cortex_a15_errata_report * checking functions of each errata. */ report_errata ERRATA_A15_816470, cortex_a15, 816470 + report_errata ERRATA_A15_827671, cortex_a15, 827671 report_errata WORKAROUND_CVE_2017_5715, cortex_a15, cve_2017_5715 pop {r12, lr} @@ -94,6 +124,13 @@ endfunc cortex_a15_errata_report #endif func cortex_a15_reset_func + mov r5, lr + bl cpu_get_rev_var + +#if ERRATA_A15_827671 + bl errata_a15_827671_wa +#endif + #if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 ldcopr r0, ACTLR orr r0, #CORTEX_A15_ACTLR_INV_BTB_BIT @@ -103,6 +140,8 @@ func cortex_a15_reset_func stcopr r0, MVBAR /* isb will be applied in the course of the reset func */ #endif + + mov lr, r5 b cortex_a15_enable_smp endfunc cortex_a15_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index a82db106c..f178f1af2 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -57,6 +57,10 @@ endif # applies only to revision >= r3p0 of the Cortex A15 cpu. ERRATA_A15_816470 ?=0 +# Flag to apply erratum 827671 workaround during reset. This erratum applies +# only to revision >= r3p0 of the Cortex A15 cpu. +ERRATA_A15_827671 ?=0 + # Flag to apply erratum 819472 workaround during reset. This erratum applies # only to revision <= r0p1 of the Cortex A53 cpu. ERRATA_A53_819472 ?=0 @@ -204,6 +208,10 @@ ERRATA_DSU_936184 ?=0 $(eval $(call assert_boolean,ERRATA_A15_816470)) $(eval $(call add_define,ERRATA_A15_816470)) +# Process ERRATA_A15_827671 flag +$(eval $(call assert_boolean,ERRATA_A15_827671)) +$(eval $(call add_define,ERRATA_A15_827671)) + # Process ERRATA_A53_819472 flag $(eval $(call assert_boolean,ERRATA_A53_819472)) $(eval $(call add_define,ERRATA_A53_819472)) |