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* fconf: enhancements to firmware configuration frameworkMadhukar Pappireddy2020-03-113-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | A populate() function essentially captures the value of a property, defined by a platform, into a fconf related c structure. Such a callback is usually platform specific and is associated to a specific configuration source. For example, a populate() function which captures the hardware topology of the platform can only parse HW_CONFIG DTB. Hence each populator function must be registered with a specific 'config_type' identifier. It broadly represents a logical grouping of configuration properties which is usually a device tree source file. Example: > TB_FW: properties related to trusted firmware such as IO policies, base address of other DTBs, mbedtls heap info etc. > HW_CONFIG: properties related to hardware configuration of the SoC such as topology, GIC controller, PSCI hooks, CPU ID etc. This patch modifies FCONF_REGISTER_POPULATOR macro and fconf_populate() to register and invoke the appropriate callbacks selectively based on configuration type. Change-Id: I6f63b1fd7a8729c6c9137d5b63270af1857bb44a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* cpus: denver: fixup register used to store return addressKalyani Chidambaram2020-03-091-4/+4
| | | | | | | | | | | | The denver_enable_dco and denver_disable_dco use register X3 to store the return address. But X3 gets over-written by other functions, downstream. This patch stores the return address to X18 instead, to fix this anomaly. Change-Id: Ic40bfc1d9abaa7b90348843b9ecd09521bb4ee7b Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
* SPMD: Adds partially supported EL2 registers.Max Shvetsov2020-03-032-273/+268
| | | | | | | | | | | | | | | This patch adds EL2 registers that are supported up to ARMv8.6. ARM_ARCH_MINOR has to specified to enable save/restore routine. Note: Following registers are still not covered in save/restore. * AMEVCNTVOFF0<n>_EL2 * AMEVCNTVOFF1<n>_EL2 * ICH_AP0R<n>_EL2 * ICH_AP1R<n>_EL2 * ICH_LR<n>_EL2 Change-Id: I4813f3243e56e21cb297b31ef549a4b38d4876e1 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
* SPMD: save/restore EL2 system registers.Max Shvetsov2020-03-022-1/+436
| | | | | | | | | | | NOTE: Not all EL-2 system registers are saved/restored. This subset includes registers recognized by ARMv8.0 Change-Id: I9993c7d78d8f5f8e72d1c6c8d6fd871283aa3ce0 Signed-off-by: Jose Marinho <jose.marinho@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
* Merge changes from topic "console_t_cleanup" into integrationMark Dykes2020-02-251-1/+1
|\ | | | | | | | | | | | | * changes: coreboot: Use generic base address skeletton: Use generic console_t data structure cdns: Use generic console_t data structure
| * coreboot: Use generic base addressAndre Przywara2020-02-251-1/+1
| | | | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location for the coreboot memory console. This removes the base member from the coreboot specific data structure, but keeps the struct console_cbmc_t and its size member. Change-Id: I7f1dffd41392ba3fe5c07090aea761a42313fb5b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Read-only xlat tables for BL31 memoryPetre-Ionut Tudor2020-02-244-5/+122
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a build flag which allows the xlat tables to be mapped in a read-only region within BL31 memory. It makes it much harder for someone who has acquired the ability to write to arbitrary secure memory addresses to gain control of the translation tables. The memory attributes of the descriptors describing the tables themselves are changed to read-only secure data. This change happens at the end of BL31 runtime setup. Until this point, the tables have read-write permissions. This gives a window of opportunity for changes to be made to the tables with the MMU on (e.g. reclaiming init code). No changes can be made to the tables with the MMU turned on from this point onwards. This change is also enabled for sp_min and tspd. To make all this possible, the base table was moved to .rodata. The penalty we pay is that now .rodata must be aligned to the size of the base table (512B alignment). Still, this is better than putting the base table with the higher level tables in the xlat_table section, as that would cost us a full 4KB page. Changing the tables from read-write to read-only cannot be done with the MMU on, as the break-before-make sequence would invalidate the descriptor which resolves the level 3 page table where that very descriptor is located. This would make the translation required for writing the changes impossible, generating an MMU fault. The caches are also flushed. Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Change-Id: Ibe5de307e6dc94c67d6186139ac3973516430466
* Merge "Add Matterhorn CPU lib" into integrationjoanna.farley2020-02-211-0/+77
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| * Add Matterhorn CPU libJimmy Brisson2020-02-181-0/+77
| | | | | | | | | | | | | | Also update copyright statements Change-Id: Iba0305522ac0f2ddc4da99127fd773f340e67300 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* | Merge "Add CPULib for Klein Core" into integrationjoanna.farley2020-02-211-0/+77
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| * Add CPULib for Klein CoreJimmy Brisson2020-02-181-0/+77
| | | | | | | | | | Change-Id: I686fd623b8264c85434853a2a26ecd71e9eeac01 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* | cpus: higher performance non-cacheable load forwardingVarun Wadekar2020-02-202-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable non-cacheable streaming enhancement. Platforms can set this bit only if their memory system meets the requirement that cache line fill requests from the Cortex-A57 processor are atomic. This patch adds support to enable higher performance non-cacheable load forwarding for such platforms. Platforms must enable this support by setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their makefiles. This flag is disabled by default. Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | coverity: fix MISRA violationsZelalem2020-02-181-2/+2
|/ | | | | | | | | | | Fixes for the following MISRA violations: - Missing explicit parentheses on sub-expression - An identifier or macro name beginning with an underscore, shall not be declared - Type mismatch in BL1 SMC handlers and tspd_main.c Change-Id: I7a92abf260da95acb0846b27c2997b59b059efc4 Signed-off-by: Zelalem <zelalem.aweke@arm.com>
* Merge changes from topic "lm/fconf" into integrationSandrine Bailleux2020-02-114-0/+267
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: arm-io: Panic in case of io setup failure MISRA fix: Use boolean essential type fconf: Add documentation fconf: Move platform io policies into fconf fconf: Add mbedtls shared heap as property fconf: Add TBBR disable_authentication property fconf: Add dynamic config DTBs info as property fconf: Populate properties from dtb during bl2 setup fconf: Load config dtb from bl1 fconf: initial commit
| * fconf: Add mbedtls shared heap as propertyLouis Mayencourt2020-02-071-0/+19
| | | | | | | | | | | | | | | | | | | | | | Use the firmware configuration framework in arm dynamic configuration to retrieve mbedtls heap information between bl1 and bl2. For this, a new fconf getter is added to expose the device tree base address and size. Change-Id: Ifa5ac9366ae100e2cdd1f4c8e85fc591b170f4b6 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
| * fconf: Add TBBR disable_authentication propertyLouis Mayencourt2020-02-071-0/+56
| | | | | | | | | | | | | | | | Use fconf to retrieve the `disable_authentication` property. Move this access from arm dynamic configuration to bl common. Change-Id: Ibf184a5c6245d04839222f5457cf5e651f252b86 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
| * fconf: Add dynamic config DTBs info as propertyLouis Mayencourt2020-02-073-2/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a better separation between the trusted-boot related properties, and the dynamic configuration DTBs loading information. The dynamic configuration DTBs properties are moved to a new node: `dtb-registry`. All the sub-nodes present will be provided to the dynamic config framework to be loaded. The node currently only contains the already defined configuration DTBs, but can be extended for future features if necessary. The dynamic config framework is modified to use the abstraction provided by the fconf framework, instead of directly accessing the DTBs. The trusted-boot properties are kept under the "arm,tb_fw" compatible string, but in a separate `tb_fw-config` node. The `tb_fw-config` property of the `dtb-registry` node simply points to the load address of `fw_config`, as the `tb_fw-config` is currently part of the same DTB. Change-Id: Iceb6c4c2cb92b692b6e28dbdc9fb060f1c46de82 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
| * fconf: Populate properties from dtb during bl2 setupLouis Mayencourt2020-02-071-8/+14
| | | | | | | | | | | | | | Use the dtb provided by bl1 as configuration file for fconf. Change-Id: I3f466ad9b7047e1a361d94e71ac6d693e31496d9 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
| * fconf: Load config dtb from bl1Louis Mayencourt2020-02-071-0/+39
| | | | | | | | | | | | | | | | | | Move the loading of the dtb from arm_dym_cfg to fconf. The new loading function is not associated to arm platform anymore, and can be moved to bl_main if wanted. Change-Id: I847d07eaba36d31d9d3ed9eba8e58666ea1ba563 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
| * fconf: initial commitLouis Mayencourt2020-02-072-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the Firmware CONfiguration Framework (fconf). The fconf is an abstraction layer for platform specific data, allowing a "property" to be queried and a value retrieved without the requesting entity knowing what backing store is being used to hold the data. The default backing store used is C structure. If another backing store has to be used, the platform integrator needs to provide a "populate()" function to fill the corresponding C structure. The "populate()" function must be registered to the fconf framework with the "FCONF_REGISTER_POPULATOR()". This ensures that the function would be called inside the "fconf_populate()" function. A two level macro is used as getter: - the first macro takes 3 parameters and converts it to a function call: FCONF_GET_PROPERTY(a,b,c) -> a__b_getter(c). - the second level defines a__b_getter(c) to the matching C structure, variable, array, function, etc.. Ex: Get a Chain of trust property: 1) FCONF_GET_PROPERY(tbbr, cot, BL2_id) -> tbbr__cot_getter(BL2_id) 2) tbbr__cot_getter(BL2_id) -> cot_desc_ptr[BL2_id] Change-Id: Id394001353ed295bc680c3f543af0cf8da549469 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | coverity: Fix MISRA null pointer violationsZelalem2020-02-051-3/+3
|/ | | | | | | | | | | Fix code that violates the MISRA rule: MISRA C-2012 Rule 11.9: Literal "0" shall not be used as null pointer constant. The fix explicitly checks whether a pointer is NULL. Change-Id: Ibc318dc0f464982be9a34783f24ccd1d44800551 Signed-off-by: Zelalem <zelalem.aweke@arm.com>
* Merge "Coverity: remove unnecessary header file includes" into integrationMark Dykes2020-02-044-11/+3
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| * Coverity: remove unnecessary header file includesZelalem2020-02-044-11/+3
| | | | | | | | | | | | | | | | This patch removes unnecessary header file includes discovered by Coverity HFA option. Change-Id: I2827c37c1c24866c87db0e206e681900545925d4 Signed-off-by: Zelalem <zelalem.aweke@arm.com>
* | Merge changes from topic "mp/separate_nobits" into integrationSandrine Bailleux2020-02-041-2/+3
|\ \ | | | | | | | | | | | | | | | * changes: plat/arm: Add support for SEPARATE_NOBITS_REGION Changes necessary to support SEPARATE_NOBITS_REGION feature
| * | Changes necessary to support SEPARATE_NOBITS_REGION featureMadhukar Pappireddy2020-01-271-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since BL31 PROGBITS and BL31 NOBITS sections are going to be in non-adjacent memory regions, potentially far from each other, some fixes are needed to support it completely. 1. adr instruction only allows computing the effective address of a location only within 1MB range of the PC. However, adrp instruction together with an add permits position independent address of any location with 4GB range of PC. 2. Since BL31 _RW_END_ marks the end of BL31 image, care must be taken that it is aligned to page size since we map this memory region in BL31 using xlat_v2 lib utils which mandate alignment of image size to page granularity. Change-Id: I3451cc030d03cb2032db3cc088f0c0e2c84bffda Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | coverity: debugfs devfip remove comparisons to LONG_MAXOlivier Deprez2020-02-041-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CID 353228: Integer handling issues (CONSTANT_EXPRESSION_RESULT) The checks on size and offset_address in get_entry always resolve to false provided those fields are long long int and cannot be greater than LONG_MAX. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I0fac485a39ac4a40ae8c0d25a706ad74c795e130
* | | Merge "FDT wrappers: add functions for read/write bytes" into integrationManish Pandey2020-02-031-1/+2
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| * | FDT wrappers: add functions for read/write bytesAlexei Fedorov2020-02-031-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds 'fdtw_read_bytes' and 'fdtw_write_inplace_bytes' functions for read/write array of bytes from/to a given property. It also adds 'fdt_setprop_inplace_namelen_partial' to jmptbl.i files for builds with USE_ROMLIB=1 option. Change-Id: Ied7b5c8b38a0e21d508aa7bcf5893e656028b14d Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | | Merge "Use correct type when reading SCR register" into integrationAlexei Fedorov2020-01-301-11/+11
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| * | | Use correct type when reading SCR registerLouis Mayencourt2020-01-281-11/+11
| | |/ | |/| | | | | | | | | | | | | | | | | | | The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | Merge "qemu: Implement PSCI_CPU_OFF." into integrationSoby Mathew2020-01-291-1/+1
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| * | | qemu: Implement PSCI_CPU_OFF.Andrew Walbran2020-01-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is based on the rpi implementation from https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746. Signed-off-by: Andrew Walbran <qwandor@google.com> Change-Id: I5fe324fcd9d5e232091e01267ea12147c46bc9c1
* | | | Merge "T589: Fix insufficient ordering guarantees in bakery lock" into ↵Soby Mathew2020-01-292-12/+20
|\ \ \ \ | |/ / / |/| | | | | | | integration
| * | | T589: Fix insufficient ordering guarantees in bakery lockRaghu Krishnamurthy2020-01-272-12/+20
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bakery_lock_get() uses DMB LD after lock acquisition and bakery_lock_release() uses DMB ST before releasing the lock. This is insufficient in both cases. With just DMB LD, stores in the critical section can be reordered before the DMB LD which could mean writes in the critical section completing before the lock has been acquired successfully. Similarly, with just DMB ST, a load in the critical section could be reordered after the the DMB ST. DMB is the least expensive barrier that can provide the required ordering. Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@icloud.com> Change-Id: Ieb74cbf5b76b09e1789331b71f37f7c660221b0e
* | | Merge changes I0fb7cf79,Ia8eb4710 into integrationSoby Mathew2020-01-291-11/+23
|\ \ \ | |_|/ |/| | | | | | | | | | | * changes: qemu: Implement qemu_system_off via semihosting. qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.
| * | qemu: Implement qemu_system_off via semihosting.Andrew Walbran2020-01-231-11/+23
| | | | | | | | | | | | | | | | | | | | | | | | This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has semihosting enabled, but that is already assumed by the image loader. Signed-off-by: Andrew Walbran <qwandor@google.com> Change-Id: I0fb7cf7909262b675c3143efeac07f4d60730b03
* | | Neovers N1: added support to update presence of External LLCManish Pandey2020-01-272-1/+15
| |/ |/| | | | | | | | | | | | | | | | | | | | | CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external last level cache(LLC) in the system, the reset value is internal LLC. To cater for the platforms(like N1SDP) which has external LLC present introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be enabled by platform port. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
* | Merge "xlat_tables_v2: simplify end address checks in ↵Soby Mathew2020-01-241-3/+3
|\ \ | | | | | | | | | mmap_add_region_check()" into integration
| * | xlat_tables_v2: simplify end address checks in mmap_add_region_check()Masahiro Yamada2020-01-221-3/+3
| |/ | | | | | | | | | | | | Use end_va and end_pa defined at the beginning of this function. Change-Id: I0e8b3b35fceb87b5d35397eb892d4fe92ba90b4c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge "Prevent speculative execution past ERET" into integrationSoby Mathew2020-01-244-7/+7
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| * | Prevent speculative execution past ERETAnthony Steinhauser2020-01-224-7/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though ERET always causes a jump to another address, aarch64 CPUs speculatively execute following instructions as if the ERET instruction was not a jump instruction. The speculative execution does not cross privilege-levels (to the jump target as one would expect), but it continues on the kernel privilege level as if the ERET instruction did not change the control flow - thus execution anything that is accidentally linked after the ERET instruction. Later, the results of this speculative execution are always architecturally discarded, however they can leak data using microarchitectural side channels. This speculative execution is very reliable (seems to be unconditional) and it manages to complete even relatively performance-heavy operations (e.g. multiple dependent fetches from uncached memory). This was fixed in Linux, FreeBSD, OpenBSD and Optee OS: https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8 https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61 https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2 https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a It is demonstrated in a SafeSide example: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Anthony Steinhauser <asteinhauser@google.com> Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
* | Merge "Revert "Changes necessary to support SEPARATE_NOBITS_REGION feature"" ↵Mark Dykes2020-01-231-3/+2
|\ \ | | | | | | | | | into integration
| * | Revert "Changes necessary to support SEPARATE_NOBITS_REGION feature"Mark Dykes2020-01-221-3/+2
| | | | | | | | | | | | | | | | | | This reverts commit 76d84cbc60ab3ee7bf40d53487f85ed7417bdcc3. Change-Id: I867af7af3d9f5e568101f79b9ebea578e5cb2a4b
* | | Errata workarounds N1 1043202, 1315703 default offlaurenw-arm2020-01-231-2/+2
|/ / | | | | | | | | | | | | | | Setting errata workarounds for N1 1043202 and 1315703 to 0 since they should be turned off by default. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I116673a4ddcf64436e90d70133f035a133989ed9
* / Changes necessary to support SEPARATE_NOBITS_REGION featureMadhukar Pappireddy2020-01-211-2/+3
|/ | | | | | | | | | | | | | | | | | | Since BL31 PROGBITS and BL31 NOBITS sections are going to be in non-adjacent memory regions, potentially far from each other, some fixes are needed to support it completely. 1. adr instruction only allows computing the effective address of a location only within 1MB range of the PC. However, adrp instruction together with an add permits position independent address of any location with 4GB range of PC. 2. Since BL31 _RW_END_ marks the end of BL31 image, care must be taken that it is aligned to page size since we map this memory region in BL31 using xlat_v2 lib utils which mandate alignment of image size to page granularity. Change-Id: Ic745c5a130fe4239fa2742142d083b2bdc4e8b85 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* compiler_rt: Import popcountdi2.c and popcountsi2.c filesLionel Debieve2020-01-203-1/+73
| | | | | | | | | | | Imported from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). This is to get the __popcountsi2(si_int a) and __popcountdi2(di_int a) builtin which are required by a driver that uses a __builtin_popcount(). Change-Id: I8e0d97cebdd90d224690c8ce1b02e657acdddb25 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
* Merge changes from topic "ld/mtd_framework" into integrationSoby Mathew2020-01-174-4/+107
|\ | | | | | | | | | | * changes: io: change seek offset to signed long long compiler_rt: Import aeabi_ldivmode.S file and dependencies
| * compiler_rt: Import aeabi_ldivmode.S file and dependenciesLionel Debieve2020-01-024-4/+107
| | | | | | | | | | | | | | | | | | | | | | | | Import aeabi_ldivmod.S with divmoddi4.c and divdi3.c from the LLVM compiler_rt library on master branch as of 30 Oct 2018 (SVN revision: r345645). This is to get the __aeabi_ldivmod builtin, which is required by a patch using signed long long division. Change-Id: Iee4c421deb3175142655e19074cd3732edd82227 Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
* | Unify type of "cpu_idx" across PSCI module.Deepika Bhavnani2020-01-107-39/+44
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | NOTE for platform integrators: API `plat_psci_stat_get_residency()` third argument `last_cpu_idx` is changed from "signed int" to the "unsigned int" type. Issue / Trouble points 1. cpu_idx is used as mix of `unsigned int` and `signed int` in code with typecasting at some places leading to coverity issues. 2. Underlying platform API's return cpu_idx as `unsigned int` and comparison is performed with platform specific defines `PLAFORM_xxx` which is not consistent Misra Rule 10.4: The value of a complex expression of integer type may only be cast to a type that is narrower and of the same signedness as the underlying type of the expression. Based on above points, cpu_idx is kept as `unsigned int` to match the API's and low-level functions and platform defines are updated where ever required Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
* Workaround for Hercules erratum 1688305Madhukar Pappireddy2019-12-232-11/+62
| | | | | | | | | | Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions of Hercules core. The erratum can be avoided by setting bit 1 of the implementation defined register CPUACTLR2_EL1 to 1 to prevent store- release from being dispatched before it is the oldest. Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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