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| author | Manish Pandey <manish.pandey2@arm.com> | 2020-01-24 11:54:44 +0000 |
|---|---|---|
| committer | Manish Pandey <manish.pandey2@arm.com> | 2020-01-27 14:44:35 +0000 |
| commit | f2d6b4ee5740245a92fd511180f7eebc6736a80b (patch) | |
| tree | 472c08cbcc8f5d3ca0dbf7eaada2a859771f0e32 /lib | |
| parent | 9054018bd5c12b16ef55ea41fcf8cdb15a24ae18 (diff) | |
| download | platform_external_arm-trusted-firmware-f2d6b4ee5740245a92fd511180f7eebc6736a80b.tar.gz platform_external_arm-trusted-firmware-f2d6b4ee5740245a92fd511180f7eebc6736a80b.tar.bz2 platform_external_arm-trusted-firmware-f2d6b4ee5740245a92fd511180f7eebc6736a80b.zip | |
Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.
To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/neoverse_n1.S | 7 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 9 |
2 files changed, 15 insertions, 1 deletions
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index d058d98df..d537ed6a8 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -465,6 +465,13 @@ func neoverse_n1_reset_func msr CPUAMCNTENSET_EL0, x0 #endif +#if NEOVERSE_N1_EXTERNAL_LLC + /* Some system may have External LLC, core needs to be made aware */ + mrs x0, NEOVERSE_N1_CPUECTLR_EL1 + orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT + msr NEOVERSE_N1_CPUECTLR_EL1, x0 +#endif + #if ERRATA_DSU_936184 bl errata_dsu_936184_wa #endif diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 398edf9dc..e3bfc2f2e 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -20,6 +20,10 @@ WORKAROUND_CVE_2017_5715 ?=1 WORKAROUND_CVE_2018_3639 ?=1 DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0 +# Flag to indicate internal or external Last level cache +# By default internal +NEOVERSE_N1_EXTERNAL_LLC ?=0 + # Process SKIP_A57_L1_FLUSH_PWR_DWN flag $(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) $(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) @@ -43,6 +47,9 @@ $(eval $(call add_define,WORKAROUND_CVE_2018_3639)) $(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639)) $(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639)) +$(eval $(call assert_boolean,NEOVERSE_N1_EXTERNAL_LLC)) +$(eval $(call add_define,NEOVERSE_N1_EXTERNAL_LLC)) + ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0) ifeq (${WORKAROUND_CVE_2018_3639},0) $(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1") |