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* AMU: Implement support for aarch32Dimitris Papastamos2017-11-292-0/+37
| | | | | | | | | The `ENABLE_AMU` build option can be used to enable the architecturally defined AMU counters. At present, there is no support for the auxiliary counter group. Change-Id: Ifc7532ef836f83e629f2a146739ab61e75c4abc8 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* AMU: Implement support for aarch64Dimitris Papastamos2017-11-293-0/+49
| | | | | | | | | The `ENABLE_AMU` build option can be used to enable the architecturally defined AMU counters. At present, there is no support for the auxiliary counter group. Change-Id: I7ea0c0a00327f463199d1b0a481f01dadb09d312 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Implement support for the Activity Monitor Unit on Cortex A75Dimitris Papastamos2017-11-291-0/+34
| | | | | | | | | | | | The Cortex A75 has 5 AMU counters. The first three counters are fixed and the remaining two are programmable. A new build option is introduced, `ENABLE_AMU`. When set, the fixed counters will be enabled for use by lower ELs. The programmable counters are currently disabled. Change-Id: I4bd5208799bb9ed7d2596e8b0bfc87abbbe18740 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Merge pull request #1145 from etienne-lms/rfc-armv7-2davidcunado-arm2017-11-2312-3/+256
|\ | | | | Support ARMv7 architectures
| * ARMv7: GICv2 driver can manage GICv1 with security extensionEtienne Carriere2017-11-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SoCs integrate a GIC in version 1 that is currently not supported by the trusted firmware. This change hijacks GICv2 driver to handle the GICv1 as GICv1 is compatible enough with GICv2 as far as the platform does not attempt to play with virtualization support or some GICv2 specific power features. Note that current trusted firmware does not use these GICv2 features that are not available in GICv1 Security Extension. Change-Id: Ic2cb3055f1319a83455571d6d918661da583f179 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * aarch32: add missing dmb() macroEtienne Carriere2017-11-081-0/+1
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7 may not support Virtualization ExtensionsEtienne Carriere2017-11-082-1/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv7-A Virtualization extensions brings new instructions and resources that were supported by later architectures. Reference ARM ARM Issue C.c [DDI0406C_C]. ERET and extended MSR/MRS instructions, as specified in [DDI0406C_C] in ID_PFR1 description of bits[15:12] (Virtualization Extensions): A value of 0b0001 implies implementation of the HVC, ERET, MRS (Banked register), and MSR (Banked register) instructions. The ID_ISARs do not identify whether these instructions are implemented. UDIV/SDIV were introduced with the Virtualization extensions, even if not strictly related to the virtualization extensions. If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform shall define ARMV7_SUPPORTS_VIRTUALIZATION to enable virtualization extension related resources. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7: introduce Cortex-A12Etienne Carriere2017-11-081-0/+20
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7: introduce Cortex-A17Etienne Carriere2017-11-081-0/+20
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7: introduce Cortex-A7Etienne Carriere2017-11-081-0/+20
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7: introduce Cortex-A5Etienne Carriere2017-11-081-0/+20
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7: introduce Cortex-A9Etienne Carriere2017-11-081-0/+31
| | | | | | | | | | | | | | | | | | As Cortex-A9 needs to manually enable program flow prediction, do not reset SCTLR[Z] at entry. Platform should enable it only once MMU is enabled. Change-Id: I34e1ee2da73221903f7767f23bc6fc10ad01e3de Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7: introduce Cortex-A15Etienne Carriere2017-11-081-0/+20
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7 architecture have specific system registersEtienne Carriere2017-11-082-2/+22
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7 does not support SDCREtienne Carriere2017-11-081-0/+2
| | | | | | | | Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| * ARMv7 does not support STL instructionEtienne Carriere2017-11-081-0/+9
| | | | | | | | | | | | | | Also need to add a SEV instruction in ARMv7 spin_unlock which is implicit in ARMv8. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* | Merge pull request #1163 from antonio-nino-diaz-arm/an/parangedavidcunado-arm2017-11-231-0/+1
|\ \ | | | | | | Add ARMv8.2 ID_AA64MMFR0_EL1.PARange value
| * | Add ARMv8.2 ID_AA64MMFR0_EL1.PARange valueAntonio Nino Diaz2017-11-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an implementation of ARMv8.2 includes ARMv8.2-LPA, the value 0b0110 is permitted in ID_AA64MMFR0_EL1.PARange, which means that the Physical Address range supported is 52 bits (4 PiB). It is a reserved value otherwise. Change-Id: Ie0147218e9650aa09f0034a9ee03c1cca8db908a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1165 from geesun/qx/support-sha512davidcunado-arm2017-11-221-0/+10
|\ \ \ | | | | | | | | Add support sha512 for hash algorithm
| * | | tbbr: Add build flag HASH_ALG to let the user to select the SHAQixiang Xu2017-11-211-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flag support the following values: - sha256 (default) - sha384 - sha512 Change-Id: I7a49d858c361e993949cf6ada0a86575c3291066 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
* | | | Merge pull request #1161 from jeenu-arm/sdei-fixesdavidcunado-arm2017-11-221-1/+1
|\ \ \ \ | | | | | | | | | | SDEI fixes
| * | | | SDEI: Fix type of register countJeenu Viswambharan2017-11-201-1/+1
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Register count is currently declared as unsigned, where as there are asserts in place to check it being negative during unregister. These are flagged as never being true. Change-Id: I34f00f0ac5bf88205791e9c1298a175dababe7c8 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* / / / Refactor Statistical Profiling Extensions implementationDimitris Papastamos2017-11-206-21/+21
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out SPE operations in a separate file. Use the publish subscribe framework to drain the SPE buffers before entering secure world. Additionally, enable SPE before entering normal world. A side effect of this change is that the profiling buffers are now only drained when a transition from normal world to secure world happens. Previously they were drained also on return from secure world, which is unnecessary as SPE is not supported in S-EL1. Change-Id: I17582c689b4b525770dbb6db098b3a0b5777b70a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* / / Move FPEXC32_EL2 to FP ContextDavid Cunado2017-11-151-3/+7
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FPEXC32_EL2 register controls SIMD and FP functionality when the lower ELs are executing in AArch32 mode. It is architecturally mapped to AArch32 system register FPEXC. This patch removes FPEXC32_EL2 register from the System Register context and adds it to the floating-point context. EL3 only saves / restores the floating-point context if the build option CTX_INCLUDE_FPREGS is set to 1. The rationale for this change is that if the Secure world is using FP functionality and EL3 is not managing the FP context, then the Secure world will save / restore the appropriate FP registers. NOTE - this is a break in behaviour in the unlikely case that CTX_INCLUDE_FPREGS is set to 0 and the platform contains an AArch32 Secure Payload that modifies FPEXC, but does not save and restore this register Change-Id: Iab80abcbfe302752d52b323b4abcc334b585c184 Signed-off-by: David Cunado <david.cunado@arm.com>
* | SDEI: Add API for explicit dispatchJeenu Viswambharan2017-11-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | This allows for other EL3 components to schedule an SDEI event dispatch to Normal world upon the next ERET. The API usage constrains are set out in the SDEI dispatcher documentation. Documentation to follow. Change-Id: Id534bae0fd85afc94523490098c81f85c4e8f019 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | ARM platforms: Enable SDEIJeenu Viswambharan2017-11-131-1/+14
| | | | | | | | | | | | | | | | | | Support SDEI on ARM platforms using frameworks implemented in earlier patches by defining and exporting SDEI events: this patch defines the standard event 0, and a handful of shared and private dynamic events. Change-Id: I9d3d92a92cff646b8cc55eabda78e140deaa24e1 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | ARM platforms: Define exception macrosJeenu Viswambharan2017-11-131-0/+6
| | | | | | | | | | | | | | Define number of priority bits, and allocate priority levels for SDEI. Change-Id: Ib6bb6c5c09397f7caef950c4caed5a737b3d4112 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | ARM platforms: Provide SDEI entry point validationJeenu Viswambharan2017-11-132-0/+7
| | | | | | | | | | | | | | | | | | Provide a strong definition for plat_sdei_validate_sdei_entrypoint() which translates client address to Physical Address, and then validating the address to be present in DRAM. Change-Id: Ib93eb66b413d638aa5524d1b3de36aa16d38ea11 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | ARM platforms: Make arm_validate_ns_entrypoint() commonJeenu Viswambharan2017-11-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function arm_validate_ns_entrypoint() validates a given non-secure physical address. This function however specifically returns PSCI error codes. Non-secure physical address validation is potentially useful across ARM platforms, even for non-PSCI use cases. Therefore make this function common by returning 0 for success or -1 otherwise. Having made the function common, make arm_validate_psci_entrypoint() a wrapper around arm_validate_ns_entrypoint() which only translates return value into PSCI error codes. This wrapper is now used where arm_validate_ns_entrypoint() was currently used for PSCI entry point validation. Change-Id: Ic781fc3105d6d199fd8f53f01aba5baea0ebc310 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | BL31: Add SDEI dispatcherJeenu Viswambharan2017-11-132-0/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation currently supports only interrupt-based SDEI events, and supports all interfaces as defined by SDEI specification version 1.0 [1]. Introduce the build option SDEI_SUPPORT to include SDEI dispatcher in BL31. Update user guide and porting guide. SDEI documentation to follow. [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf Change-Id: I758b733084e4ea3b27ac77d0259705565842241a Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | BL31: Program Priority Mask for SMC handlingJeenu Viswambharan2017-11-132-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On GICv3 systems, as a side effect of adding provision to handle EL3 interrupts (unconditionally routing FIQs to EL3), pending Non-secure interrupts (signalled as FIQs) may preempt execution in lower Secure ELs [1]. This will inadvertently disrupt the semantics of Fast SMC (previously called Atomic SMC) calls. To retain semantics of Fast SMCs, the GIC PMR must be programmed to prevent Non-secure interrupts from preempting Secure execution. To that effect, two new functions in the Exception Handling Framework subscribe to events introduced in an earlier commit: - Upon 'cm_exited_normal_world', the Non-secure PMR is stashed, and the PMR is programmed to the highest Non-secure interrupt priority. - Upon 'cm_entering_normal_world', the previously stashed Non-secure PMR is restored. The above sequence however prevents Yielding SMCs from being preempted by Non-secure interrupts as intended. To facilitate this, the public API exc_allow_ns_preemption() is introduced that programs the PMR to the original Non-secure PMR value. Another API exc_is_ns_preemption_allowed() is also introduced to check if exc_allow_ns_preemption() had been called previously. API documentation to follow. [1] On GICv2 systems, this isn't a problem as, unlike GICv3, pending NS IRQs during Secure execution are signalled as IRQs, which aren't routed to EL3. Change-Id: Ief96b162b0067179b1012332cd991ee1b3051dd0 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | BL31: Introduce Exception Handling FrameworkJeenu Viswambharan2017-11-132-1/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EHF is a framework that allows dispatching of EL3 interrupts to their respective handlers in EL3. This framework facilitates the firmware-first error handling policy in which asynchronous exceptions may be routed to EL3. Such exceptions may be handed over to respective exception handlers. Individual handlers might further delegate exception handling to lower ELs. The framework associates the delegated execution to lower ELs with a priority value. For interrupts, this corresponds to the priorities programmed in GIC; for other types of exceptions, viz. SErrors or Synchronous External Aborts, individual dispatchers shall explicitly associate delegation to a secure priority. In order to prevent lower priority interrupts from preempting higher priority execution, the framework provides helpers to control preemption by virtue of programming Priority Mask register in the interrupt controller. This commit allows for handling interrupts targeted at EL3. Exception handlers own interrupts by assigning them a range of secure priorities, and registering handlers for each priority range it owns. Support for exception handling in BL31 image is enabled by setting the build option EL3_EXCEPTION_HANDLING=1. Documentation to follow. NOTE: The framework assumes the priority scheme supported by platform interrupt controller is compliant with that of ARM GIC architecture (v2 or later). Change-Id: I7224337e4cea47c6ca7d7a4ca22a3716939f7e42 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | GIC: Introduce API to get interrupt IDJeenu Viswambharan2017-11-132-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Acknowledging interrupt shall return a raw value from the interrupt controller in which the actual interrupt ID may be encoded. Add a platform API to extract the actual interrupt ID from the raw value obtained from interrupt controller. Document the new function. Also clarify the semantics of interrupt acknowledge. Change-Id: I818dad7be47661658b16f9807877d259eb127405 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | Merge pull request #1148 from antonio-nino-diaz-arm/an/spmdavidcunado-arm2017-11-0911-16/+355
|\ \ | |/ |/| Introduce Secure Partition Manager
| * SPM: FVP: Introduce port of SPMAntonio Nino Diaz2017-11-094-6/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This initial port of the Secure Partitions Manager to FVP supports BL31 in both SRAM and Trusted DRAM. A document with instructions to build the SPM has been added. Change-Id: I4ea83ff0a659be77f2cd72eaf2302cdf8ba98b32 Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Achin Gupta <achin.gupta@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * SPM: Introduce Secure Partition ManagerAntonio Nino Diaz2017-11-086-10/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A Secure Partition is a software execution environment instantiated in S-EL0 that can be used to implement simple management and security services. Since S-EL0 is an unprivileged exception level, a Secure Partition relies on privileged firmware e.g. ARM Trusted Firmware to be granted access to system and processor resources. Essentially, it is a software sandbox that runs under the control of privileged software in the Secure World and accesses the following system resources: - Memory and device regions in the system address map. - PE system registers. - A range of asynchronous exceptions e.g. interrupts. - A range of synchronous exceptions e.g. SMC function identifiers. A Secure Partition enables privileged firmware to implement only the absolutely essential secure services in EL3 and instantiate the rest in a partition. Since the partition executes in S-EL0, its implementation cannot be overly complex. The component in ARM Trusted Firmware responsible for managing a Secure Partition is called the Secure Partition Manager (SPM). The SPM is responsible for the following: - Validating and allocating resources requested by a Secure Partition. - Implementing a well defined interface that is used for initialising a Secure Partition. - Implementing a well defined interface that is used by the normal world and other secure services for accessing the services exported by a Secure Partition. - Implementing a well defined interface that is used by a Secure Partition to fulfil service requests. - Instantiating the software execution environment required by a Secure Partition to fulfil a service request. Change-Id: I6f7862d6bba8732db5b73f54e789d717a35e802f Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Achin Gupta <achin.gupta@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * xlat: Make function to calculate TCR PA bits publicAntonio Nino Diaz2017-11-081-0/+5
| | | | | | | | | | | | | | | | | | | | This function can be useful to setup TCR_ELx by callers that don't use the translation tables library to setup the system registers related to them. By making it common, it can be reused whenever it is needed without duplicating code. Change-Id: Ibfada9e846d2a6cd113b1925ac911bb27327d375 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1153 from robertovargas-arm/fix-macrosdavidcunado-arm2017-11-061-1/+1
|\ \ | |/ |/| Avoid use of undefined macros
| * Fix usage of IMAGE_BLx macrosRoberto Vargas2017-11-011-1/+1
| | | | | | | | | | | | | | | | | | These macros are only defined for corresponding image, and they are undefined for other images. It means that we have to use ifdef or defined() instead of relying on being 0 by default. Change-Id: Iad11efab9830ddf471599b46286e1c56581ef5a7 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | Merge pull request #1151 from JoelHutton/jh/MISRA-Mandatorydavidcunado-arm2017-11-031-6/+6
|\ \ | | | | | | Change sizeof to use type of struct not function
| * | Change sizeof to use type of struct not functionJoel Hutton2017-10-311-6/+6
| |/ | | | | | | | | | | | | | | Change sizeof call so it references a static type instead of return of a function in order to be MISRA compliant. Change-Id: I6f1adb206073d6cd200156e281b8d76249e3af0e Signed-off-by: Joel Hutton <joel.hutton@arm.com>
* | Merge pull request #1137 from soby-mathew/sm/arm_plat_en_gicv3_savedavidcunado-arm2017-11-034-2/+50
|\ \ | | | | | | Enable GICv3 save for ARM platforms
| * | ARM platforms: enable GICv3 state save/restoreSoby Mathew2017-10-112-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provides GICv3 save/restore feature to arm_system_pwr_domain_resume and arm_system_pwr_domain_save functions. Introduce FVP PSCI power level 3 (System level) support. This is solely done to provide example code on how to use the GICv3 save and restore helpers. Also make CSS GICv3 platforms power off the Redistributor on SYSTEM SUSPEND as its state is saved and restored. Change-Id: I0d852f3af8824edee1a17c085cf593ddd33a4e77 Signed-off-by: Soby Mathew <soby.mathew@arm.com> Co-Authored-by: Douglas Raillard <douglas.raillard@arm.com>
| * | ARM platforms: Add support for EL3 TZC memory regionSoby Mathew2017-10-112-1/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some recent enhancements to EL3 runtime firmware like support for save and restoring GICv3 register context during system_suspend necessitates additional data memory for the firmware. This patch introduces support for creating a TZC secured DDR carveout for use by ARM reference platforms. A new linker section `el3_tzc_dram` is created using platform supplied linker script and data marked with the attribute `arm_el3_tzc_dram` will be placed in this section. The FVP makefile now defines the `PLAT_EXTRA_LD_SCRIPT` variable to allow inclusion of the platform linker script by the top level BL31 linker script. Change-Id: I0e7f4a75a6ac51419c667875ff2677043df1585d Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | | Merge pull request #1150 from dp-arm/dp/eventsdavidcunado-arm2017-11-011-0/+18
|\ \ \ | | | | | | | | aarch64: Add PubSub events to capture security state transitions
| * | | aarch64: Add PubSub events to capture security state transitionsDimitris Papastamos2017-10-311-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add events that trigger before entry to normal/secure world. The events trigger after the normal/secure context has been restored. Similarly add events that trigger after leaving normal/secure world. The events trigger after the normal/secure context has been saved. Change-Id: I1b48a7ea005d56b1f25e2b5313d77e67d2f02bc5 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* | | | Merge pull request #1141 from robertovargas-arm/boot_redundancydavidcunado-arm2017-10-311-0/+2
|\ \ \ \ | |/ / / |/| | | Add platform hooks for boot redundancy support
| * | | Add platform hooks for boot redundancy supportRoberto Vargas2017-10-241-0/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | These hooks are intended to allow one platform to try load images from alternative places. There is a hook to initialize the sequence of boot locations and a hook to pass to the next sequence. Change-Id: Ia0f84c415208dc4fa4f9d060d58476db23efa5b2 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* / | plat/arm: enlarge the BL2 size on Arm platforms when TBB is enabledQixiang Xu2017-10-252-4/+5
|/ / | | | | | | | | | | | | | | For Trusted Board Boot, BL2 needs more space to support the ECDSA and ECDSA+RSA algorithms. Change-Id: Ie7eda9a1315ce836dbc6d18d6588f8d17891a92d Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
* | PSCI: Publish CPU ON eventJeenu Viswambharan2017-10-231-0/+6
| | | | | | | | | | | | | | | | | | | | This allows other EL3 components to subscribe to CPU on events. Update Firmware Design guide to list psci_cpu_on_finish as an available event. Change-Id: Ida774afe0f9cdce4021933fcc33a9527ba7aaae2 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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