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| author | Etienne Carriere <etienne.carriere@linaro.org> | 2017-11-05 22:56:26 +0100 |
|---|---|---|
| committer | Etienne Carriere <etienne.carriere@linaro.org> | 2017-11-08 13:49:45 +0100 |
| commit | d56a846121136ceacca1eeabfbf440059e99acba (patch) | |
| tree | f921cae05a341f120a328d251836082e04c4aec0 /include | |
| parent | e3148c2b5339da8201033bcc2e88e27cf46fd48b (diff) | |
| download | platform_external_arm-trusted-firmware-d56a846121136ceacca1eeabfbf440059e99acba.tar.gz platform_external_arm-trusted-firmware-d56a846121136ceacca1eeabfbf440059e99acba.tar.bz2 platform_external_arm-trusted-firmware-d56a846121136ceacca1eeabfbf440059e99acba.zip | |
ARMv7: introduce Cortex-A5
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a5.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch32/cortex_a5.h b/include/lib/cpus/aarch32/cortex_a5.h new file mode 100644 index 000000000..0a0b7ffa5 --- /dev/null +++ b/include/lib/cpus/aarch32/cortex_a5.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_A5_H__ +#define __CORTEX_A5_H__ + +/******************************************************************************* + * Cortex-A8 midr with version/revision set to 0 + ******************************************************************************/ +#define CORTEX_A5_MIDR 0x410FC050 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A5_ACTLR_SMP_BIT (1 << 6) + +#endif /* __CORTEX_A5_H__ */ |