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* Workaround for Cortex A78 erratum 1951500johpow012021-01-131-0/+3
| | | | | | | | | | | | | Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This workaround works on revisions r1p0 and r1p1, in r0p0 there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
* Workaround for Cortex A78 erratum 1941498johpow012021-01-121-9/+10
| | | | | | | | | | | | Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
* cadence: Change logic in uart driverMichal Simek2021-01-111-0/+1
| | | | | | | | | | | | | | | Write char if fifo is empty. If this is done like this all chars are printed. Because origin code just put that chars to fifo and in case of reset messages were missing. Before this change chars are put to fifo and only check before adding if fifo is full. The patch is changing this logic that it is adding char only when fifo is empty to make sure that in case of reset (by another SW for example) all chars are printed. Maybe one char can be missed but for IP itself it is much easier to send just one char compare to full fifo. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Change-Id: Ic24c2c1252bce24be2aed68ee29477ca4a549e5f
* Merge changes I0c5f32e8,Id49c124c,Idcfe933d into integrationAndré Przywara2020-12-221-0/+4
|\ | | | | | | | | | | | | * changes: allwinner: Use RSB for the PMIC connection on H6 allwinner: Return the PMIC to I2C mode after use allwinner: Always use a 3MHz RSB bus clock
| * allwinner: Return the PMIC to I2C mode after useSamuel Holland2020-12-131-0/+4
| | | | | | | | | | | | | | | | | | This gives the rich OS the flexibility to choose between I2C and RSB communication. Since a runtime address can only be assigned once after entering RSB mode, it also lets the rich OS choose any runtime address. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Id49c124c5e925985fc31c0ba38c7fb6c941aafa8
* | Merge changes from topic "tc0_optee_sp" into integrationMadhukar Pappireddy2020-12-211-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * changes: fdts: tc0: Add reserved-memory node for OP-TEE plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2 docs: arm: Add OPTEE_SP_FW_CONFIG plat: tc0: enable opteed support plat: arm: Increase SP max size
| * | plat: arm: Increase SP max sizeArunachalam Ganapathy2020-12-141-1/+1
| |/ | | | | | | | | | | | | | | Increase SP max size for latest OP-TEE build with debug and stats enabled. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I4593884e0deb39ada10009f6876d815136f8ee65
* / Add support for FEAT_MTPMU for Armv8.6Javier Almansa Sobrino2020-12-114-0/+26
|/ | | | | | | | | | | | | | | | | If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented as well, it is possible to control whether PMU counters take into account events happening on other threads. If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit leaving it to effective state of 0 regardless of any write to it. This patch introduces the DISABLE_MTPMU flag, which allows to diable multithread event count from EL3 (or EL2). The flag is disabled by default so the behavior is consistent with those architectures that do not implement FEAT_MTPMU. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
* Merge "Aarch64: Add support for FEAT_PANx extensions" into integrationManish Pandey2020-12-031-2/+57
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| * Aarch64: Add support for FEAT_PANx extensionsAlexei Fedorov2020-11-301-2/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides the changes listed below: - Adds new bit fields definitions for SCTLR_EL1/2 registers - Corrects the name of SCTLR_EL1/2.[20] bit field from SCTLR_UWXN_BIT to SCTLR_TSCXT_BIT - Adds FEAT_PANx bit field definitions and their possible values for ID_AA64MMFR1_EL1 register. - Adds setting of SCTLR_EL1.SPAN bit to preserve PSTATE.PAN on taking an exception to EL1 in spm_sp_setup() function (services\std_svc\spm_mm\spm_mm_setup.c) Change-Id: If51f20e7995c649126a7728a4d0867041fdade19 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | Aarch64: Add support for FEAT_MTE3Alexei Fedorov2020-12-021-3/+11
| | | | | | | | | | | | | | | | | | This patch provides the following changes: - Adds definition for FEAT_MTE3 value in ID_AA64PFR1_EL1 register - Enables Memory Tagging Extension for FEAT_MTE3. Change-Id: I735988575466fdc083892ec12c1aee89b5faa472 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | Add support for Neoverse-N2 CPUs.Javier Almansa Sobrino2020-11-303-8/+49
|/ | | | | | | Enable basic support for Neoverse-N2 CPUs. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
* Revert workaround for A77 erratum 1800714johpow012020-11-121-1/+0
| | | | | | | | | | | This errata workaround did not work as intended and was revised in subsequent SDEN releases so we are reverting this change. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe
* Revert workaround for A76 erratum 1800710johpow012020-11-121-1/+0
| | | | | | | | | | | This errata workaround did not work as intended and was revised in subsequent SDEN releases so we are reverting this change. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4684 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I560749a5b55e22fbe49d3f428a8b9545d6bdaaf0
* Merge "Use constant stack size with RECLAIM_INIT_CODE" into integrationAlexei Fedorov2020-10-291-39/+15
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| * Use constant stack size with RECLAIM_INIT_CODEDavid Horstmann2020-10-281-39/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when RECLAIM_INIT_CODE is set, the stacks are scaled to ensure that the entirety of the init section can be reclaimed as stack. This causes an issue in lib/psci/aarch64/psci_helpers.S, where the stack size is used for cache operations in psci_do_pwrdown_cache_maintenance(). If the stacks are scaled, then the PSCI code may fail to invalidate some of the stack memory before power down. Resizing stacks is also not good for stability in general, since code that works with a small number of cores may overflow the stack when the number of cores is increased. Change to make every stack be PLATFORM_STACK_SIZE big, and allow the total stack to be smaller than the init section. Any pages of the init section not reclaimed as stack will be set to read-only and execute-never, for security. Change-Id: I10b3884981006431f2fcbec3864c81d4a8c246e8 Signed-off-by: David Horstmann <david.horstmann@arm.com>
* | aarch64/arm: Add compiler barrier to barrier instructionsAndre Przywara2020-10-272-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When issuing barrier instructions like DSB or DMB, we must make sure that the compiler does not undermine out efforts to fence off instructions. Currently the compiler is free to move the barrier instruction around, in respect to former or later memory access statements, which is not what we want. Add a compiler barrier to the inline assembly statement in our DEFINE_SYSOP_TYPE_FUNC macro, to make sure memory accesses are not reordered by the compiler. This is in line with Linux' definition: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/include/asm/barrier.h Since those instructions share a definition, apart from DSB and DMB this now also covers some TLBI instructions. Having a compiler barrier there also is useful, although we probably have stronger barriers in place already. Change-Id: If6fe97b13a562643a643efc507cb4aad29daa5b6 Reported-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabledArunachalam Ganapathy2020-10-201-3/+3
| | | | | | | | | | | | | | | | | | To support platforms without Trusted DRAM this patch defines PLAT_ARM_SPMC_BASE and enables platform to use either Trusted DRAM or DRAM region behind TZC. Change-Id: Icaa5c7d33334258ff27e8e0bfd0812c304e68ae4 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
* | Merge "Increase type widths to satisfy width requirements" into integrationJoanna Farley2020-10-188-61/+64
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| * | Increase type widths to satisfy width requirementsJimmy Brisson2020-10-128-61/+64
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Usually, C has no problem up-converting types to larger bit sizes. MISRA rule 10.7 requires that you not do this, or be very explicit about this. This resolves the following required rule: bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None> The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U | 0x3c0U" (32 bits) is less that the right hand operand "18446744073709547519ULL" (64 bits). This also resolves MISRA defects such as: bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)] In the expression "3U << 20", shifting more than 7 bits, the number of bits in the essential type of the left expression, "3U", is not allowed. Further, MISRA requires that all shifts don't overflow. The definition of PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues. This fixes the violation by changing the definition to 1UL << 12. Since this uses 32bits, it should not create any issues for aarch32. This patch also contains a fix for a build failure in the sun50i_a64 platform. Specifically, these misra fixes removed a single and instruction, 92407e73 and x19, x19, #0xffffffff from the cm_setup_context function caused a relocation in psci_cpus_on_start to require a linker-generated stub. This increased the size of the .text section and caused an alignment later on to go over a page boundary and round up to the end of RAM before placing the .data section. This sectionn is of non-zero size and therefore causes a link error. The fix included in this reorders the functions during link time without changing their ording with respect to alignment. Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* | Merge changes Iba51bff1,I3f563cff into integrationMadhukar Pappireddy2020-10-161-1/+1
|\ \ | | | | | | | | | | | | | | | * changes: plat:qti Mandate SMC implementaion and bug fix Update in coreboot_get_memory_type API to include size as well
| * | Update in coreboot_get_memory_type API to include size as wellSaurabh Gorecha2020-10-161-1/+1
| |/ | | | | | | | | Change-Id: I3f563cffd58b0591b433c85c0ff6b71e486eb2c8 Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
* | Merge "Don't return error information from console_flush" into integrationMark Dykes2020-10-143-5/+5
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| * | Don't return error information from console_flushJimmy Brisson2020-10-093-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* | | stm32mp1: get peripheral base address from a defineYann Gautier2020-10-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Retrieve peripheral base address from a define instead of parsing the device tree. The goal is to improve execution time. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I2588c53ad3d4abcc3d7fe156458434a7940dd72b
* | | Remove deprecated macro from TF-A codeManish V Badarkhe2020-10-121-2/+2
| |/ |/| | | | | | | | | | | Removed '__ASSEMBLY__' deprecated macro from TF-A code Change-Id: I9082a568b695acb5b903f509db11c8672b62d9d0 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
* | Merge "Workaround for Cortex A77 erratum 1925769" into integrationLauren Wehrmeister2020-10-091-0/+1
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| * | Workaround for Cortex A77 erratum 1925769johpow012020-10-071-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Cortex A77 erratum 1925769 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9
* / lib/cpus: update MIDR value for rainier cpuJagadeesh Ujja2020-10-091-1/+1
|/ | | | | | | This patch updates the MIDR value for rainier cpu. Change-Id: I99a5d96f757239cf65b2688095c4ec66cd991cf9 Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
* Rename Neoverse Zeus to Neoverse V1Jimmy Brisson2020-10-051-8/+8
| | | | | Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* Rename Cortex Hercules AE to Cortex 78 AEJimmy Brisson2020-10-051-4/+4
| | | | | Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* Merge "libfdt: Upgrade libfdt source files" into integrationAlexei Fedorov2020-10-031-0/+8
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| * libfdt: Upgrade libfdt source filesAndre Przywara2020-10-021-0/+8
| | | | | | | | | | | | | | | | | | | | | | Update the libfdt source files, the upstream commit is 73e0f143b73d ("libfdt: fdt_strerror(): Fix comparison warning"). This brings us the fixes for the signed/unsigned comparison warnings, so platforms can enable -Wsign-compare now. Change-Id: I303d891c82ffea0acefdde27289339db5ac5a289 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Merge "fdts: stm32mp1: realign device tree with kernel" into integrationMadhukar Pappireddy2020-10-021-4/+5
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| * fdts: stm32mp1: realign device tree with kernelYann Gautier2020-09-241-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is one dtsi file per SoC version: - STM32MP151: common part for all version, Single Cortex-A7 - STM32MP153: Dual Cortex-A7 - STM32MP157: + GPU and DSI, but not needed for TF-A The STM32MP15xC include a cryptography peripheral, add it in a dedicated file. There are 4 packages available, for which the IOs number change. Have one file for each package. The 2 packages AB and AD are added. STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common dkx file is then created. Some reordering is done in other files, and realign with kernel DT files. The DDR files are generated with our internal tool, no changes in the registers values. Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | Crypto library: Migrate support to MbedTLS v2.24.0Alexei Fedorov2020-10-011-1/+8
| | | | | | | | | | | | | | | | | | | | This patch migrates the mbedcrypto dependency for TF-A to mbedTLS repo v2.24.0 which is the latest release tag. The relevant documentation is updated to reflect the use of new version. Change-Id: I116f44242e8c98e856416ea871d11abd3234dac1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | Merge changes from topic "fpga_generic" into integrationAndré Przywara2020-09-302-0/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: arm_fpga: Add platform documentation arm_fpga: Add post-build linker script arm_fpga: Add ROM trampoline arm_fpga: Add devicetree file arm_fpga: Remove SPE PMU DT node if SPE is not available arm_fpga: Adjust GICR size in DT to match number of cores fdt: Add function to adjust GICv3 redistributor size drivers: arm: gicv3: Allow detecting number of cores
| * | fdt: Add function to adjust GICv3 redistributor sizeAndre Przywara2020-09-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We now have code to detect the CPU topology at runtime, and can also populate the CPU nodes in a devicetree accordingly. This is used by the ARM FPGA port, for instance. But also a GICv3 compatible interrupt controller provides MMIO frames per core, so the size of this region needs to be adjusted in the DT, to match the number of cores as well. Provide a generic function to find the GICv3 interrupt controller in the DT, then adjust the "reg" entry to match the number of detected cores. Since the size of the GICR frame per cores differs between GICv4 and GICv3, this size is supplied as a parameter to the function. The caller should determine the applicable value by either hardcoding it or by observing GICR_TYPER.VLPIS. Change-Id: Ic2a6445c2c5381a36bf24263f52fcbefad378c05 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | drivers: arm: gicv3: Allow detecting number of coresAndre Przywara2020-09-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A GICv3 interrupt controller will be instantiated for a certain number of cores. This will result in the respective number of GICR frames. The last frame will have the "Last" bit set in its GICR_TYPER register. For platforms with a topology unknown at build time (the Arm FPGAs, for instance), we need to learn the number of used cores at runtime, to size the GICR region in the devicetree accordingly. Add a generic function that iterates over all GICR frames until it encounters one with the "Last" bit set. It returns the number of cores the GICv3 has been configured for. Change-Id: I79f033c50dfc1c275aba7122725868811abcc4f8 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge "Workaround for Cortex A77 erratum 1508412" into integrationMadhukar Pappireddy2020-09-291-0/+7
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| * | | Workaround for Cortex A77 erratum 1508412laurenw-arm2020-09-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0. The workaround is a write sequence to several implementation defined registers based on A77 revision. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
* | | | Merge changes I1ecbe5a1,Ib5945c37,Ic6b79648 into integrationManish Pandey2020-09-291-0/+66
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: plat/arm: Add platform support for Morello fdts: add device tree sources for morello platform lib/cpus: add support for Morello Rainier CPUs
| * | | | lib/cpus: add support for Morello Rainier CPUsManoj Kumar2020-09-281-0/+66
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds CPU support for the Rainier CPU which is derived from Neoverse N1 r4p0 CPU and implements the Morello capability architecture. Change-Id: Ic6b796481da5a66504ecb0648879446edf4c69fb Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
* | | | Merge "arm_fpga: Add support for unknown MPIDs" into integrationAndré Przywara2020-09-281-0/+18
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| * | | arm_fpga: Add support for unknown MPIDsJavier Almansa Sobrino2020-09-251-0/+18
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows the system to fallback to a default CPU library in case the MPID does not match with any of the supported ones. This feature can be enabled by setting SUPPORT_UNKNOWN_MPID build option to 1 (enabled by default only on arm_fpga platform). This feature can be very dangerous on a production image and therefore it MUST be disabled for Release images. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I0df7ef2b012d7d60a4fd5de44dea1fbbb46881ba
* | | Merge changes from topic "stm32_drivers_update" into integrationManish Pandey2020-09-252-1/+4
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: clk: stm32mp1: fix rcc mckprot status drivers: st: add missing includes in ETZPC header mmc: st: clear some flags before sending a command mmc: st: correct retries management nand: raw_nand: fix timeout issue in nand_wait_ready mtd: spi_nor: change message level on macronix detection gpio: stm32_gpio: check GPIO node status after checking DT crypto: stm32_hash: fix issue when restarting computation
| * | | drivers: st: add missing includes in ETZPC headerYann Gautier2020-09-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Depending on compiler, the issue about bool or uint*_t not defined can appear. Correct this by adding stdbool.h and stdint.h includes in etzpc.h. Change-Id: If1419dc511efbe682459fa4a776481fa52a38aa3 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | nand: raw_nand: fix timeout issue in nand_wait_readyLionel Debieve2020-09-241-1/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_wait_ready is called with a millisecond delay but the timeout used a micro second. Fixing the conversion in the timeout call. The prototype of the function is also changed to use an unsigned int parameter. Change-Id: Ia3281be7980477dfbfdb842308d35ecd8b926fb8 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | | Merge "Select the Log Level for the Event Log Dump on Measured Boot at build ↵Alexei Fedorov2020-09-241-2/+0
|\ \ \ | |/ / |/| | | | | time." into integration
| * | Select the Log Level for the Event Log Dump on Measured Boot at build time.Javier Almansa Sobrino2020-09-221-2/+0
| |/ | | | | | | | | | | | | | | | | | | Builds in Debug mode with Measured Boot enabled might run out of trusted SRAM. This patch allows to change the Log Level at which the Measured Boot driver will dump the event log, so the latter can be accessed even on Release builds if necessary, saving space on RAM. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I133689e313776cb3f231b774c26cbca4760fa120
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