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| author | Javier Almansa Sobrino <javier.almansasobrino@arm.com> | 2020-10-23 13:22:07 +0100 |
|---|---|---|
| committer | Javier Almansa Sobrino <javier.almansasobrino@arm.com> | 2020-11-30 19:12:56 +0000 |
| commit | 25bbbd2d632be40a4b9afd75a0dfb7eddd1e3081 (patch) | |
| tree | f333b741e2e34b05cd1409b0b073bf812962f791 /include | |
| parent | 20c378920e4deea3430a5eb50e407eff2c339e37 (diff) | |
| download | platform_external_arm-trusted-firmware-25bbbd2d632be40a4b9afd75a0dfb7eddd1e3081.tar.gz platform_external_arm-trusted-firmware-25bbbd2d632be40a4b9afd75a0dfb7eddd1e3081.tar.bz2 platform_external_arm-trusted-firmware-25bbbd2d632be40a4b9afd75a0dfb7eddd1e3081.zip | |
Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 8 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n2.h | 31 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n_common.h | 18 |
3 files changed, 49 insertions, 8 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 9998b93f2..b50befa8d 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -64,12 +64,4 @@ #define CPUPOR_EL3 S3_6_C15_C8_2 #define CPUPMR_EL3 S3_6_C15_C8_3 -/****************************************************************************** - * CPU Configuration register definitions. - *****************************************************************************/ -#define CPUCFR_EL1 S3_0_C15_C0_0 - -/* SCU bit of CPU Configuration Register, EL1 */ -#define SCU_SHIFT U(2) - #endif /* NEOVERSE_N1_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h new file mode 100644 index 000000000..7cbd8c17b --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_N2_H +#define NEOVERSE_N2_H + +/* Neoverse N2 ID register for revision r0p0 */ +#define NEOVERSE_N2_MIDR U(0x410FD490) + +/******************************************************************************* + * CPU Power control register + ******************************************************************************/ +#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) + +#endif /* NEOVERSE_N2_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n_common.h b/include/lib/cpus/aarch64/neoverse_n_common.h new file mode 100644 index 000000000..7cb91cd05 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_n_common.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_N_COMMON_H +#define NEOVERSE_N_COMMON_H + +/****************************************************************************** + * Neoverse Nx CPU Configuration register definitions + *****************************************************************************/ +#define CPUCFR_EL1 S3_0_C15_C0_0 + +/* SCU bit of CPU Configuration Register, EL1 */ +#define SCU_SHIFT U(2) + +#endif /* NEOVERSE_N_COMMON_H */ |