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| author | laurenw-arm <lauren.wehrmeister@arm.com> | 2020-07-14 14:18:34 -0500 |
|---|---|---|
| committer | laurenw-arm <lauren.wehrmeister@arm.com> | 2020-09-25 15:41:56 -0500 |
| commit | aa3efe3df81429ef696dfe7fcb9ad9ef7ce86f6c (patch) | |
| tree | 20b2a75b13cec23588e00af85c5f0a91cb67f3fb /include | |
| parent | 73740d98d99cb740ff67e188b6a7c1db816bf9f4 (diff) | |
| download | platform_external_arm-trusted-firmware-aa3efe3df81429ef696dfe7fcb9ad9ef7ce86f6c.tar.gz platform_external_arm-trusted-firmware-aa3efe3df81429ef696dfe7fcb9ad9ef7ce86f6c.tar.bz2 platform_external_arm-trusted-firmware-aa3efe3df81429ef696dfe7fcb9ad9ef7ce86f6c.zip | |
Workaround for Cortex A77 erratum 1508412
Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based on A77 revision.
This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a77.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h index bbd647c60..41aced8d2 100644 --- a/include/lib/cpus/aarch64/cortex_a77.h +++ b/include/lib/cpus/aarch64/cortex_a77.h @@ -24,4 +24,11 @@ #define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) +#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3 +#define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4 +#define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5 + #endif /* CORTEX_A77_H */ |