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* drivers: ti: uart: add a aarch32 variantHeiko Stuebner2019-04-251-0/+267
| | | | | | | | | | Rockchip re-uses the ti uart console driver and for aarch32 needs a specific variant, so add it. There are also aarch32 ti socs, so it may be useful for them as well at some point. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I31ede7cc7b10347b3691cff051db2b985fd59e17
* Console: Allow to register multiple timesAmbroise Vincent2019-04-241-2/+4
| | | | | | | It removes the need to unregister the console on system suspend. Change-Id: Ic9311a242a4a9a778651f7e6380bd2fc0964b2ce Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* drivers/sbsa: add sbsa watchdog driverAditya Angadi2019-04-171-0/+42
| | | | | | | | Add a driver for configuring the SBSA Generic Watchdog which aids in the detection of errant system behaviour. Change-Id: I5a1e7149c69fd8b85be7dfbcf511f431339946f4 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
* Merge changes from topic "av/tls-heap" into integrationAntonio Niño Díaz2019-04-121-5/+3
|\ | | | | | | | | | | * changes: Mbed TLS: Remove weak heap implementation sgm: Fix bl2 sources
| * Mbed TLS: Remove weak heap implementationAmbroise Vincent2019-04-121-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | The implementation of the heap function plat_get_mbedtls_heap() becomes mandatory for platforms supporting TRUSTED_BOARD_BOOT. The shared Mbed TLS heap default weak function implementation is converted to a helper function get_mbedtls_heap_helper() which can be used by the platforms for their own function implementation. Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | rcar_gen3: drivers: Change to restore timer counter value at resumeToshiyuki Ogasahara2019-04-115-58/+48
| | | | | | | | | | | | | | | | | | | | Changed to save and restore cntpct_el0 using memory mapped register for generic timer when System Suspend and Resume. Reported by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I40fd9f5434c4d52b320cd1d20322b9b8e4e67155
* | rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh modeYoshifumi Hosoya2019-04-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Very rarely, LPDDR4 power consumption may not decrease In self-refresh mode. This patch fixes the DBSC4 self-refresh mode sequence. Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Kenji Miyazawa <kenji.miyazawa.xt@renesas.com> Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Change-Id: I838fa0892b1caf1ecd3f04538b3427e7d971ef59
* | rcar_gen3: drivers: ddr: Update DDR setting rev.0.35Chiaki Fujii2019-04-116-48/+129
| | | | | | | | | | | | | | | | [IPL/DDR] - Update DDR setting rev.0.35. Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Change-Id: I2b936ca8621ca320cc97353f99240da5f24781f7
* | rcar_gen3: drivers: qos: change subslot cycleYoshifumi Hosoya2019-04-117-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Subslot cycle from 132 to 126 as default setting. Subslot cycle from 264 to 252. [IPL/QoS] - Update H3 Ver.2.0 QoS setting rev.0.21. - Update H3 Ver.3.0 QoS setting rev.0.11. - Update M3 Ver.1.1 QoS setting rev.0.19. - Update M3 Ver.3.0 QoS setting rev.0.02. - Update M3N Ver.1.1 QoS setting rev.0.09. Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I52b1bf880163ce03065dc8933d7f193e45cfd9a5
* | rcar_gen3: drivers: board: Add new board revision for H3ULCBYusuke Goda2019-04-111-1/+1
|/ | | | | | | | | | Board Revision[2:0] 3'b000 Rev1.0 OB 3'b001 Rev1.0 CE 3'b010 Rev2.0 [New] Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Change-Id: I0f109cddc95eca78aea34c7149e70f14e2f1620b
* Checkpatch: Style fixJoel Hutton2019-04-091-1/+1
| | | | | Change-Id: I0cb9f0db1ef3491f55c038a10db5a88d37e89697 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
* cot-desc: optimise memory furtherJoel Hutton2019-04-082-55/+62
| | | | | | | | | | | | | | | | | | | | | | | | | This changes the auth_img_desc_t struct to have pointers to struct arrays instead of struct arrays. This saves memory as many of these were never used, and can be NULL pointers. Note the memory savings are only when these arrays are not initialised, as it is assumed these arrays are fixed length. A possible future optimisation could allow for variable length. memory diff: bl1: bl2: text text -12 -12 bss bss -1463 0 data data -56 -48 rodata rodata -5688 -2592 total total -7419 -2652 Change-Id: I8f9bdedf75048b8867f40c56381e3a6dc6402bcc Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
* Reduce memory needed for CoT descriptionJoel Hutton2019-04-082-595/+650
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When Trusted Board Boot is enabled, we need to specify the Chain of Trust (CoT) of the BL1 and BL2 images. A CoT consists of an array of image descriptors. The authentication module assumes that each image descriptor in this array is indexed by its unique image identifier. For example, the Trusted Boot Firmware Certificate has to be at index [TRUSTED_BOOT_FW_CERT_ID]. Unique image identifiers may not necessarily be consecutive. Also, a given BL image might not use all image descriptors. For example, BL1 does not need any of the descriptors related to BL31. As a result, the CoT array might contain holes, which unnecessarily takes up space in the BL binary. Using pointers to auth_img_desc_t structs (rather than structs themselves) means these unused elements only use 1 pointer worth of space, rather than one struct worth of space. This patch also changes the code which accesses this array to reflect the change to pointers. Image descriptors not needed in BL1 or BL2 respectively are also ifdef'd out in this patch. For example, verifying the BL31 image is the responsibility of BL2 so BL1 does not need any of the data structures describing BL31. memory diff: bl1: bl2: text text -20 -20 bss bss -1463 0 data data -256 -48 rodata rodata -5240 -1952 total total -6979 -2020 Change-Id: I163668b174dc2b9bbb183acec817f2126864aaad Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
* Makefile: remove extra include paths in INCLUDESAmbroise Vincent2019-04-033-7/+7
| | | | | | | | | | Now it is needed to use the full path of the common header files. Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more information. Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* tzc: remove deprecated typesAmbroise Vincent2019-04-031-2/+2
| | | | | | | Types tzc_action_t and tzc_region_attributes_t are deprecated. Change-Id: Ieefeb8521a0e1130f39d09b5c0d2728f05084773 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Console: remove deprecated finish_console_registerAmbroise Vincent2019-04-039-9/+0
| | | | | | | | | | The old version of the macro is deprecated. Commit cc5859ca19ff ("Multi-console: Deprecate the `finish_console_register` macro") provides more details. Change-Id: I3d1cdf6496db7d8e6cfbb5804f508ff46ae7e67e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Merge pull request #1917 from marex/arm/master/v3meagle-v2.0.1Antonio Niño Díaz2019-04-0317-18/+2218
|\ | | | | rcar_gen3: plat: Add R-Car V3M support
| * rcar_gen3: plat: Add R-Car V3M supportValentine Barshak2019-04-0217-18/+2218
| | | | | | | | | | | | | | | | | | | | | | Add R-Car V3M support. This is based on the original V3M support patch for Yocto v2.23.1 by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> --- Marek: Update on top of mainline ATF/master
* | meson/gxl: Add support for SHA256 DMA engineRemi Pommarel2019-04-021-0/+185
|/ | | | | | | | | | In order to configure and boot SCP, BL31 has to compute and send the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC has a DMA facility that could be used to offload SHA-256 computations. This adds basic support of this hardware SHA-256 engine. Signed-off-by: Remi Pommarel <repk@triplefau.lt>
* rcar_gen3: drivers: qos: Add D3 QoS tablesMarek Vasut2019-04-024-3/+626
| | | | | | Add QoS tables for R-Car D3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* rcar_gen3: drivers: pfc: Add D3 PFC tablesMarek Vasut2019-04-024-0/+977
| | | | | | Add PFC tables for R-Car D3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* rcar_gen3: drivers: ddr_a: Add D3 DDR initMarek Vasut2019-04-024-2/+907
| | | | | | | Add R-Car D3 DDR initialization code. The code is in staging and needs cleanup, and possibly can even be merged with the E3 init code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* rcar_gen3: drivers: swdt: Add D3 supportMarek Vasut2019-04-021-0/+4
| | | | | | Add WTCNT register configuration for the D3 SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* rcar_gen3: drivers: scif: Add D3 supportMarek Vasut2019-04-021-3/+12
| | | | | | | Add SCIF configuration specifics for the D3 SoC, that is detection of the D3 SoC and SCBRR configuration. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* rcar_gen3: drivers: pwrc: Add D3 supportMarek Vasut2019-04-021-0/+7
| | | | | | The D3 SoC has one CPU core, just return 1 as a CPU number. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* rcar_gen3: drivers: rom: Mark NEW table as D3 compatibleMarek Vasut2019-04-021-3/+3
| | | | | | Add comment into the ROM driver that the new table is also D3 compatible. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* rcar_gen3: plat: Add initial D3 supportMarek Vasut2019-04-022-2/+8
| | | | | | | Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code will be added separately. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* Remove several warnings reported with W=2Ambroise Vincent2019-04-018-25/+32
| | | | | | | | | | | | | Improved support for W=2 compilation flag by solving some nested-extern and sign-compare warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed. Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Remove several warnings reported with W=1Ambroise Vincent2019-04-011-2/+2
| | | | | | | | | | | | | | Improved support for W=1 compilation flag by solving missing-prototypes and old-style-definition warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed without heavy structural changes. Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* driver: synosys: Fix SD MMC not initializing correctlyTien Hock, Loh2019-03-221-2/+1
| | | | | | | | dw_params.mmc_dev_type should be assigned before mmc_init, otherwise SDMMC initialization will fail as the initialization treats the device as EMMC instead of SD. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
* Merge pull request #1879 from pbeesley-arm/pb/todo-removalSoby Mathew2019-03-132-4/+0
|\ | | | | Pb/todo removal
| * drivers: Remove TODO from io_fip.cPaul Beesley2019-03-121-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The comment suggests checking version numbers and a checksum but there doesn't seem to be any usable data for either of these. For example, fip_toc_header_t doesn't contain any version information and neither does fip_toc_entry_t. As the function name "is_valid_header" suggests, this function is not concerned with checksumming any of the table of contents entries. Change-Id: I8673ae5dd37793771760169f26b2f55c15fbf587 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
| * drivers: Remove TODO from io_storagePaul Beesley2019-03-121-3/+0
| | | | | | | | | | | | | | | | This TODO was added five years ago so I assume that there is not going to be a shutdown API added after all. Change-Id: If0f4e2066454df773bd9bf41ed65d3a10248a2d3 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | Merge pull request #1874 from hadi-asyrafi/qspi_bootSoby Mathew2019-03-131-0/+251
|\ \ | | | | | | intel: QSPI boot enablement
| * | intel: QSPI boot enablementMuhammad Hadi Asyrafi Abdul Halim2019-03-131-0/+251
| | | | | | | | | | | | | | | | | | Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
* | | Merge pull request #1858 from thloh85-intel/dwmmc_fixesSoby Mathew2019-03-131-1/+28
|\ \ \ | | | | | | | | drivers: synopsys: Fix synopsys MMC driver
| * | | drivers: synopsys: Fix synopsys MMC driverTien Hock, Loh2019-03-121-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some issues with synopsys MMC driver: - CMD8 should not expect data (for SD) - ACMD51 should expect data (Send SCR for SD) - dw_prepare should not dictate size to be MMC_BLOCK_SIZE, block size is now handled in the dw_prepare function - after the CMD completes, when doing dw_read, we need to invalidate cache and wait for the data transfer to complete - Need to set FIFO threshold, otherwise DMA might never get the interrupt to read or write Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
* | | | Merge pull request #1856 from masahisak/synquacer-scmi-supportSoby Mathew2019-03-133-0/+90
|\ \ \ \ | |_|_|/ |/| | | plat/synquacer: enable SCMI support
| * | | plat/synquacer: enable SCMI supportMasahisa Kojima2019-03-133-0/+90
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | Enable the SCMI protocol support in SynQuacer platform. Aside from power domain, system power and apcore management protocol, this commit adds the vendor specific protocol(0x80). This vendor specific protocol is used to get the dram mapping information from SCP. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
* / | mmc: stm32_sdmmc2: fill ocr_voltageYann Gautier2019-03-081-0/+1
|/ / | | | | | | | | | | | | | | STM32MP1 SDMMC device voltage is 3.3V. We should then precise the 2 ranges 3.2 to 3.3V and 3.3 to 3.4V in ocr_voltage field. Change-Id: I88e479f8f16bfe608a7808eace0df3fdec48deab Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | Merge pull request #1863 from thloh85-intel/mmc_fixesDimitris Papastamos2019-03-081-4/+6
|\ \ | | | | | | drivers: mmc: Fix some issues with MMC stack
| * | drivers: mmc: Fix some issues with MMC stackTien Hock, Loh2019-03-071-4/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | Some bugs in MMC stack needs to be fixed: - scr cannot be local as this will cause cache issue when invalidating after the read DMA transfer is completed - ACMD41 needs to send voltage information in initialization, otherwise the command is a query, thus will not initialize the controller - when checking device state, retry until the retries counter goes to zero before failing Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
* | Merge pull request #1847 from jts-arm/mbedtlsAntonio Niño Díaz2019-03-051-1/+19
|\ \ | | | | | | Remove Mbed TLS dependency from plat_bl_common.c
| * | Remove Mbed TLS dependency from plat_bl_common.cJohn Tsichritzis2019-02-281-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the shared Mbed TLS heap optimisation introduced in 6d01a463, common code files were depending on Mbed TLS specific headers. This dependency is now removed by moving the default, unoptimised heap implementation inside the Mbed TLS specific files. Change-Id: I11ea3eb4474f0d9b6cb79a2afd73a51a4a9b8994 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* | | rcar_gen3: drivers: pfc: Configure GP5_09 as input on ULCBMarek Vasut2019-03-044-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | Configure the GPIO5 09 pin as input on the ULCB board by default, since the pin is routed on the expansion connector and not connected to anything by default. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* | | rcar_gen3: Add M3-W 3.0 supportMarek Vasut2019-03-049-18/+365
| | | | | | | | | | | | | | | | | | | | | Add support for the M3W 3.0 SoC and synchronize the upstream ATF with Renesas downstream ATF release v2.0.1. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* | | Minor changes to documentation and commentsAntonio Nino Diaz2019-02-282-4/+4
|/ / | | | | | | | | | | | | Fix some typos and clarify some sentences. Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | rpi3: sdhost: SDHost driver improvementYing-Chun Liu (PaulLiu)2019-02-271-30/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit improves the SDHost driver for RPi3 as following: * Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on block reading. * In some low probability that SEND_OP_COND might results CRC7 error. We can consider that the command runs correctly. We don't need to retry this command so removing the code for retry. * Using MMC_BUS_WIDTH_1 as MMC default value to improve the stability. * Increase the clock to 50Mhz in data mode to speed up the io. * Change the pull resistors configuration to gain more stability. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
* | Merge pull request #1836 from Yann-lms/docs_and_m4Antonio Niño Díaz2019-02-221-0/+78
|\ \ | | | | | | Update documentation for STM32MP1 and add Cortex-M4 support
| * | stm32mp1: add minimal support for co-processor Cortex-M4Yann Gautier2019-02-201-0/+78
| |/ | | | | | | | | | | | | | | | | | | STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4. The support for Cortex-M4 clocks is added when configuring the clock tree. Some minimal security features to allow communications between A7 and M4 are also added. Change-Id: I60417e244a476f60a2758f4969700b2684056665 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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