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author | Aditya Angadi <aditya.angadi@arm.com> | 2019-04-16 11:30:25 +0530 |
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committer | Aditya Angadi <aditya.angadi@arm.com> | 2019-04-17 18:24:35 +0530 |
commit | f79abf5e98005aa12d8d0f145810e5b46e2d808b (patch) | |
tree | 00d4021c4dc864eb81356764d9f2dff62afdef29 /drivers | |
parent | 5d149bdb18c0c6fb0aa76f32e0ffbb9f9269c994 (diff) | |
download | platform_external_arm-trusted-firmware-f79abf5e98005aa12d8d0f145810e5b46e2d808b.tar.gz platform_external_arm-trusted-firmware-f79abf5e98005aa12d8d0f145810e5b46e2d808b.tar.bz2 platform_external_arm-trusted-firmware-f79abf5e98005aa12d8d0f145810e5b46e2d808b.zip |
drivers/sbsa: add sbsa watchdog driver
Add a driver for configuring the SBSA Generic Watchdog which aids in
the detection of errant system behaviour.
Change-Id: I5a1e7149c69fd8b85be7dfbcf511f431339946f4
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/arm/sbsa/sbsa.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/drivers/arm/sbsa/sbsa.c b/drivers/arm/sbsa/sbsa.c new file mode 100644 index 000000000..6f00a6019 --- /dev/null +++ b/drivers/arm/sbsa/sbsa.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <plat/common/platform.h> +#include <drivers/arm/sbsa.h> +#include <lib/mmio.h> +#include <stdint_.h> +#include <assert.h> + +void sbsa_watchdog_offset_reg_write(uintptr_t base, uint64_t value) +{ + assert((value >> SBSA_WDOG_WOR_WIDTH) == 0); + mmio_write_32(base + SBSA_WDOG_WOR_LOW_OFFSET, + ((uint32_t)value & UINT32_MAX)); + mmio_write_32(base + SBSA_WDOG_WOR_HIGH_OFFSET, (uint32_t)(value >> 32)); +} + +/* + * Start the watchdog timer at base address "base" for a + * period of "ms" milliseconds.The watchdog has to be + * refreshed within this time period. + */ +void sbsa_wdog_start(uintptr_t base, uint64_t ms) +{ + uint64_t counter_freq; + uint64_t offset_reg_value; + + counter_freq = (uint64_t)plat_get_syscnt_freq2(); + offset_reg_value = ms * counter_freq / 1000; + + sbsa_watchdog_offset_reg_write(base, offset_reg_value); + mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, SBSA_WDOG_WCS_EN); +} + +/* Stop the watchdog */ +void sbsa_wdog_stop(uintptr_t base) +{ + mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, (0x0)); +} |