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* Merge "TF-A GICv3 driver: Change API for GICR_IPRIORITYR accessors" into ↵joanna.farley2020-04-073-7/+144
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| * TF-A GICv3 driver: Change API for GICR_IPRIORITYR accessorsAlexei Fedorov2020-04-073-7/+144
| | | | | | | | | | | | | | | | | | | | | | | | To support compatibility with previous GICv3 driver version this patch: - restores original API for gicr_read_ipriority() and gicr_wrtite_ipriority() functions; - adds accessor functions for GICR_XXX0,1 registers, e.g. GICR_IGROUPR0, GICR_ICFGR0, GICR_ICFGR1, etc. Change-Id: I796a312a61665ff384e3d9de2f4b3c60f700b43b Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | gic multichip: add support for claytonVijayenthiran Subramaniam2020-04-071-2/+12
|/ | | | | | | | | | | | | GIC-Clayton supports multichip operation mode which allows it to connect upto 16 other GIC-Clayton instances. GIC-Clayton's multichip programming and operation remains same as GIC-600 with a minor change in the SPI_BLOCKS and SPI_BLOCK_MIN shifts to accommodate additional SPI ranges. So identify if the GIC v4 extension is enabled by the platform makefile and appropriately select the SPI_BLOCKS and SPI_BLOCK_MIN shifts. Change-Id: I95fd80ef16af6c7ca09e2335539187b133052d41 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
* TF-A: Add GICv4 extension for GIC driverAlexei Fedorov2020-04-072-6/+18
| | | | | | | | | | This patch adds support for GICv4 extension. New `GIC_ENABLE_V4_EXTN` option passed to gicv3.mk makefile was added, and enables GICv4 related changes when set to 1. This option defaults to 0. Change-Id: I30ebe1b7a98d3a54863900f37eda4589c707a288 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* TF-A GICv3 driver: Add extended PPI and SPI rangeAlexei Fedorov2020-04-066-480/+943
| | | | | | | | | | This patch provides support for GICv3.1 extended PPI and SPI range. The option is enabled by setting to 1 and passing `GIC_EXT_INTID` build flag to gicv3.mk makefile. This option defaults to 0 with no extended range support. Change-Id: I7d09086fe22ea531c5df51a8a1efd8928458d394 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Merge changes from topic "brcm_initial_support" into integrationManish Pandey2020-04-0315-1/+5673
|\ | | | | | | | | | | | | | | | | | | | | | | | | * changes: doc: brcm: Add documentation file for brcm stingray platform drivers: Add SPI Nor flash support drivers: Add iproc spi driver drivers: Add emmc driver for Broadcom platforms Add BL31 support for Broadcom stingray platform Add BL2 support for Broadcom stingray platform Add bl31 support common across Broadcom platforms Add bl2 setup code common across Broadcom platforms drivers: Add support to retrieve plat_toc_flags
| * drivers: Add SPI Nor flash supportSheetal Tigadoli2020-04-032-0/+368
| | | | | | | | | | | | | | Add SPI Nor flash support Change-Id: I0cde3fdb4dcad5bcaf445b3bb48e279332bd28af Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
| * drivers: Add iproc spi driverSheetal Tigadoli2020-04-033-0/+455
| | | | | | | | | | | | | | Add iproc spi driver Change-Id: I652efab1efd9c487974dae9cb9d98b9b8e3759c4 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
| * drivers: Add emmc driver for Broadcom platformsSheetal Tigadoli2020-04-034-0/+3567
| | | | | | | | | | | | | | Add emmc driver for Broadcom platforms Change-Id: I126a6dfccd41062cb0b856f2c2fb1f724730b95e Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
| * Add BL31 support for Broadcom stingray platformSheetal Tigadoli2020-04-031-0/+398
| | | | | | | | | | Change-Id: Icfef5b6923dc292e637001045a334c499d346fe9 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
| * Add BL2 support for Broadcom stingray platformSheetal Tigadoli2020-04-034-0/+859
| | | | | | | | | | Change-Id: I5daa3f2b4b9d85cb857547a588571a9aa8ad05c2 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
| * drivers: Add support to retrieve plat_toc_flagsScott Branden2020-04-011-1/+26
| | | | | | | | | | | | | | | | | | | | Add support to retrieve plat_toc_flags value from FIP header flags. plat_toc_flags is for platform specific use. It is stored in FIP header by fiptool using --plat-toc-flags option. Change-Id: Ibadd91b4f28e6503f4426e4efd404bbe512ad124 Signed-off-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
* | cryptocell: add support for Cryptocell 713Gilad Ben-Yossef2020-04-013-1/+385
|/ | | | | | | | | | | Add Crypto 713 support as crypto module and NVM counter provider. As files under include/drivers/arm/cryptocell/713/ are copied verbatim from the CryptoCell SBROM lib project they are filtered from checkpatch coding style check. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Change-Id: I7c361772f00ca7d96481f81ac6cbb2704467e52c
* Merge "TF-A GICv3 driver: Introduce makefile" into integrationManish Pandey2020-03-311-0/+34
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| * TF-A GICv3 driver: Introduce makefileAlexei Fedorov2020-03-301-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document. NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles. Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | Merge changes from topic "ddr_map" into integrationOlivier Deprez2020-03-301-4/+7
|\ \ | |/ |/| | | | | | | | | | | * changes: stm32mp1: use stm32mp_get_ddr_ns_size() function stm32mp1: set XN attribute for some areas in BL2 stm32mp1: dynamically map DDR later and non-cacheable during its test stm32mp1: add a function to get non-secure DDR size
| * stm32mp1: dynamically map DDR later and non-cacheable during its testYann Gautier2020-03-261-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A speculative accesses to DDR could be done whereas it was not reachable and could lead to bus stall. To correct this the dynamic mapping in MMU is used. A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute, once DDR access is setup. It is then unmapped and a new mapping DDR is done with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE) load. The disabling of cache during DDR tests is also removed, as now useless. A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done instead. PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32. BL33 max size is also updated to take into account the secure and shared memory areas. Those are used in OP-TEE case. Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | FVP: Add BL2 hash calculation in BL1Alexei Fedorov2020-03-251-2/+16
|/ | | | | | | | This patch provides support for measured boot by adding calculation of BL2 image hash in BL1 and writing these data in TB_FW_CONFIG DTB. Change-Id: Ic074a7ed19b14956719c271c805b35d147b7cec1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* io: io_stm32image: correct possible NULL pointer dereferenceYann Gautier2020-03-231-1/+2
| | | | | | | | | | This issue was found with cppcheck in our downstream code: [drivers/st/io/io_stm32image.c:234] -> [drivers/st/io/io_stm32image.c:244]: (warning) Either the condition 'buffer!=0U' is redundant or there is possible null pointer dereference: local_buffer. Change-Id: Ieb615b7e485dc93bbeeed4cd8bf845eb84c14ac9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* nand: stm32_fmc2_nand: correct xor_ecc.val assigned valueYann Gautier2020-03-231-2/+2
| | | | | | | | The variable is wrongly set to 0L, whereas it is an unsigned int, it should then be 0U. Change-Id: I0b164c0ea598ec8a503f1693da2f3789f59da238 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* spi: stm32_qspi: correct static analysis issuesYann Gautier2020-03-231-4/+5
| | | | | | | | | | | | | | | | Sparse issue: drivers/st/spi/stm32_qspi.c:445:5: warning: symbol 'stm32_qspi_init' was not declared. Should it be static? Cppcheck issue: [drivers/st/spi/stm32_qspi.c:175] -> [drivers/st/spi/stm32_qspi.c:187]: (style) Variable 'len' is reassigned a value before the old one has been used. [drivers/st/spi/stm32_qspi.c:178]: (style) The scope of the variable 'timeout' can be reduced. Change-Id: I575fb50766355a6717cbd193fc4a80ff1923014c Signed-off-by: Yann Gautier <yann.gautier@st.com>
* rpi3: gpio: Simplify GPIO setupAndre Przywara2020-03-171-9/+3
| | | | | | | | | | | | | | There is really no reason to use and pass around a struct when its only member is the (fixed) base address. Remove the struct and just use the base address on its own inside the GPIO driver. Then set the base address automatically. This simplifies GPIO setup for users, which now don't need to deal with zeroing a struct and setting the base address anymore. Change-Id: I3060f7859e3f8ef9a24cc8fb38307b5da943f127 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge "TF-A GICv3 driver: Separate GICD and GICR accessor functions" into ↵Mark Dykes2020-03-114-284/+396
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| * TF-A GICv3 driver: Separate GICD and GICR accessor functionsAlexei Fedorov2020-03-104-284/+396
| | | | | | | | | | | | | | | | | | | | | | | | This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | Merge "Necessary fix in drivers to upgrade to mbedtls-2.18.0" into integrationMark Dykes2020-03-102-1/+3
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| * | Necessary fix in drivers to upgrade to mbedtls-2.18.0Madhukar Pappireddy2020-03-082-1/+3
| | | | | | | | | | | | | | | | | | | | | Include x509.h header file explicitly. Update docs. Change-Id: If2e52c2cd3056654406b7b6779b67eea5cc04a48 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | Merge changes from topic "sb/dualroot" into integrationSandrine Bailleux2020-03-101-0/+814
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | * changes: Build system: Changes to drive cert_create for dualroot CoT cert_create: Define the dualroot CoT Introduce a new "dualroot" chain of trust
| * | Introduce a new "dualroot" chain of trustSandrine Bailleux2020-02-241-0/+814
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new chain of trust defines 2 independent signing domains: 1) One for the silicon firmware (BL1, BL2, BL31) and optionally the Trusted OS. It is rooted in the Silicon ROTPK, just as in the TBBR CoT. 2) One for the Normal World Bootloader (BL33). It is rooted in a new key called Platform ROTPK, or PROTPK for short. In terms of certificates chain, - Signing domain 1) is similar to what TBBR advocates (see page 21 of the TBBR specification), except that the Non-Trusted World Public Key has been removed from the Trusted Key Certificate. - Signing domain 2) only contains the Non-Trusted World Content certificate, which provides the hash of the Non-Trusted World Bootloader. Compared to the TBBR CoT, there's no Non-Trusted World Key certificate for simplicity. Change-Id: I62f1e952522d84470acc360cf5ee63e4c4b0b4d9 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | | Merge changes from topic "tbbr/fw_enc" into integrationSandrine Bailleux2020-03-095-4/+403
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: docs: qemu: Add instructions to boot using FIP image docs: Update docs with firmware encryption feature qemu: Support optional encryption of BL31 and BL32 images qemu: Update flash address map to keep FIP in secure FLASH0 Makefile: Add support to optionally encrypt BL31 and BL32 tools: Add firmware authenticated encryption tool TBB: Add an IO abstraction layer to load encrypted firmwares drivers: crypto: Add authenticated decryption framework
| * | TBB: Add an IO abstraction layer to load encrypted firmwaresSumit Garg2020-03-061-0/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TBBR spec advocates for optional encryption of firmwares (see optional requirement: R060_TBBR_FUNCTION). So add an IO abstaction layer to support firmware decryption that can be stacked above any underlying IO/ packaging layer like FIP etc. It aims to provide a framework to load any encrypted IO payload. Also, add plat_get_enc_key_info() to be implemented in a platform specific manner as handling of encryption key may vary from one platform to another. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I9892e0ddf00ebecb8981301dbfa41ea23e078b03
| * | drivers: crypto: Add authenticated decryption frameworkSumit Garg2020-03-064-4/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add framework for autheticated decryption of data. Currently this patch optionally imports mbedtls library as a backend if build option "DECRYPTION_SUPPORT = aes_gcm" is set to perform authenticated decryption using AES-GCM algorithm. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I2966f0e79033151012bf4ffc66f484cd949e7271
* | | driver/arm/css: minor bug fixManish Pandey2020-03-051-4/+4
|/ / | | | | | | | | | | | | | | | | The cpu index was wrongly checked causing it to assert always. Since this code path is exercised only during TF test "NODE_HW_STAT", which queries Power state from SCP, this bug was not detected earlier. Change-Id: Ia25cef4c0aa23ed08092df39134937a2601c21ac Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
* | Merge "allwinner: Add a msgbox driver for use with SCPI" into integrationOlivier Deprez2020-02-261-0/+95
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| * | allwinner: Add a msgbox driver for use with SCPISamuel Holland2020-02-121-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | The function names follow the naming convention used by the existing ARM SCPI client. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I543bae7d46e206eb405dbedfcf7aeba88a12ca48
* | | Merge changes from topic "console_t_cleanup" into integrationMark Dykes2020-02-257-48/+43
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: marvell: Consolidate console register calls uniphier: Use generic console_t data structure spe: Use generic console_t data structure LS 16550: Use generic console_t data structure stm32: Use generic console_t data structure rcar: Use generic console_t data structure a3700: Use generic console_t data structure 16550: Use generic console_t data structure imx: Use generic console_t data structure
| * | | stm32: Use generic console_t data structureAndre Przywara2020-02-251-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: Iea6ca26ff4903c33f0fad27fec96fdbabd4e0a91 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | rcar: Use generic console_t data structureAndre Przywara2020-02-252-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I836e26ff1771abf21fd460d0ee40e90a452e9b43 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | a3700: Use generic console_t data structureAndre Przywara2020-02-251-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I89c3ab2ed85ab941d8b38ced48474feb4aaa8b7e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | 16550: Use generic console_t data structureAndre Przywara2020-02-252-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | imx: Use generic console_t data structureAndre Przywara2020-02-251-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I058f793e4024fa7291e432f5be374a77faf16f36 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | Merge changes from topic "console_t_cleanup" into integrationMark Dykes2020-02-254-20/+20
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: coreboot: Use generic base address skeletton: Use generic console_t data structure cdns: Use generic console_t data structure
| * | | coreboot: Use generic base addressAndre Przywara2020-02-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location for the coreboot memory console. This removes the base member from the coreboot specific data structure, but keeps the struct console_cbmc_t and its size member. Change-Id: I7f1dffd41392ba3fe5c07090aea761a42313fb5b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | skeletton: Use generic console_t data structureAndre Przywara2020-02-252-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I347849424782333149e5912a25cc0ab9d277a201 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | cdns: Use generic console_t data structureAndre Przywara2020-02-251-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I9f8b55414ab7965e431e3e86d182eabd511f32a4 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | Merge "pl011: Use generic console_t data structure" into integrationMark Dykes2020-02-252-18/+18
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| * | | pl011: Use generic console_t data structureAndre Przywara2020-02-252-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I7a23327394d142af4b293ea7ccd90b843c54587c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | Merge "meson: Use generic console_t data structure" into integrationMark Dykes2020-02-251-9/+9
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| * | | meson: Use generic console_t data structureAndre Przywara2020-02-251-9/+9
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I07a07677153d3671ced776671e4f107824d3df16 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge "arm/css/scpi: Don't panic if the SCP fails to respond" into integrationMark Dykes2020-02-251-6/+16
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| * arm/css/scpi: Don't panic if the SCP fails to respondSamuel Holland2020-02-121-6/+16
| | | | | | | | | | | | | | | | | | Instead, pass back the error to the calling function. This allows platform code to fall back to another PSCI implementation if scpi_wait_ready() or a later SCPI command fails. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ib4411e63c2512857f09ffffe1c405358dddeb4a6
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