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author | Olivier Deprez <olivier.deprez@arm.com> | 2020-03-30 15:27:32 +0000 |
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committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2020-03-30 15:27:32 +0000 |
commit | de8f9cd4cd3c9292c9bf0578ed139f3c37ca5a2c (patch) | |
tree | 42c876d893465ce21d8201b8443ced7987ccda8e /drivers | |
parent | ee91cd2ed35d148b02639e130a0656b29f7d5a7b (diff) | |
parent | 5813e6edbc81c9cb0959007cbd86e30c7c87c46c (diff) | |
download | platform_external_arm-trusted-firmware-de8f9cd4cd3c9292c9bf0578ed139f3c37ca5a2c.tar.gz platform_external_arm-trusted-firmware-de8f9cd4cd3c9292c9bf0578ed139f3c37ca5a2c.tar.bz2 platform_external_arm-trusted-firmware-de8f9cd4cd3c9292c9bf0578ed139f3c37ca5a2c.zip |
Merge changes from topic "ddr_map" into integration
* changes:
stm32mp1: use stm32mp_get_ddr_ns_size() function
stm32mp1: set XN attribute for some areas in BL2
stm32mp1: dynamically map DDR later and non-cacheable during its test
stm32mp1: add a function to get non-secure DDR size
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/st/ddr/stm32mp1_ram.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c index 4ae55fcc7..40cd4554f 100644 --- a/drivers/st/ddr/stm32mp1_ram.c +++ b/drivers/st/ddr/stm32mp1_ram.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -250,8 +250,9 @@ static int stm32mp1_ddr_setup(void) VERBOSE("%s : ram size(%x, %x)\n", __func__, (uint32_t)priv->info.base, (uint32_t)priv->info.size); - write_sctlr(read_sctlr() & ~SCTLR_C_BIT); - dcsw_op_all(DC_OP_CISW); + if (stm32mp_map_ddr_non_cacheable() != 0) { + panic(); + } uret = ddr_test_data_bus(); if (uret != 0U) { @@ -274,7 +275,9 @@ static int stm32mp1_ddr_setup(void) panic(); } - write_sctlr(read_sctlr() | SCTLR_C_BIT); + if (stm32mp_unmap_ddr() != 0) { + panic(); + } return 0; } |