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* Workaround for Cortex N1 erratum 1946160johpow012021-01-131-0/+4
| | | | | | | | | | | | | | | Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present starting from r0p0 but this workaround applies to revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
* Workaround for Cortex A78 erratum 1951500johpow012021-01-131-0/+4
| | | | | | | | | | | | | Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This workaround works on revisions r1p0 and r1p1, in r0p0 there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
* Workaround for Cortex A78 erratum 1941498johpow012021-01-121-0/+3
| | | | | | | | | | | | Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
* Workaround for Cortex A76 erratum 1946160johpow012020-12-181-0/+3
| | | | | | | | | | | | | | Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions of the A76 processor core. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present in revisions r0p0 - r4p1 but this workaround only applies to revisions r3p0 - r4p1, there is no workaround for older versions. SDEN can be found here: https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327
* Add support for Neoverse-N2 CPUs.Javier Almansa Sobrino2020-11-301-1/+2
| | | | | | | Enable basic support for Neoverse-N2 CPUs. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
* Revert workaround for A77 erratum 1800714johpow012020-11-121-3/+0
| | | | | | | | | | | This errata workaround did not work as intended and was revised in subsequent SDEN releases so we are reverting this change. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe
* Revert workaround for A76 erratum 1800710johpow012020-11-121-3/+0
| | | | | | | | | | | This errata workaround did not work as intended and was revised in subsequent SDEN releases so we are reverting this change. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4684 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I560749a5b55e22fbe49d3f428a8b9545d6bdaaf0
* Workaround for Cortex A77 erratum 1925769johpow012020-10-071-0/+3
| | | | | | | | | | | | | Cortex A77 erratum 1925769 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9
* Workaround for Cortex A76 erratum 1868343johpow012020-10-031-0/+3
| | | | | | | | | | | | | | | | | Cortex A76 erratum 1868343 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. This workaround is the same as workarounds for errata 1262606 and 1275112, so all 3 have been combined into one function call. SDEN can be found here: https://documentation-service.arm.com/static/5f2bed6d60a93e65927bc8e7 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7f2f9965f495540a1f84bb7dcc28aff45d6cee5d
* Workaround for Cortex A77 erratum 1508412laurenw-arm2020-09-251-0/+3
| | | | | | | | | | | | Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0. The workaround is a write sequence to several implementation defined registers based on A77 revision. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
* doc: Correct CPACR.FPEN usagePeng Fan2020-09-141-1/+1
| | | | | | | | To avoid trapping from EL0/1, FPEN bits need to be set 0x3, not clearing. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: Ic34e9aeb876872883c5f040618ed6d50f21dacd0
* Workaround for Neoverse N1 erratum 1868343johpow012020-09-101-0/+3
| | | | | | | | | | | | | | Neoverse N1 erratum 1868343 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. SDEN can be found here: https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844
* doc: Update description for AT speculative workaroundManish V Badarkhe2020-08-181-0/+16
| | | | | | | | | | | Documented the CPU specific build macros created for AT speculative workaround. Updated the description of 'ERRATA_SPECULATIVE_AT' errata workaround option. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ie46a80d4e8183c1d5c8b153f08742a04d41a2af2
* Fix broken links to various sections across docsMadhukar Pappireddy2020-08-032-9/+13
| | | | | | | | | | | These broken links were found with the help of this command: $> sphinx-build -M linkcheck . build A sample broken link is reported as follows: (line 80) -local- firmware-design.rst#secure-el1-payloads-and-dispatchers Change-Id: I5dcefdd4b8040908658115647e957f6c2c5da7c2 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* Fix broken link in documentationjohpow012020-07-281-1/+1
| | | | | | | | | The link to the exception handling framework page on the System Design / Firmware Design / Section 4.3 just links to itself, so I changed it to link to the exception handling framework component document. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I6711b423a789b2b3d1921671e8497fffa8ba33d1
* Revert workaround for Neoverse N1 erratum 1800710johpow012020-07-231-3/+0
| | | | | | | | | | | | | | | This reverts commit 11af40b6308ac75c83e874129bb79bc3a58060bf, reversing changes made to 2afcf1d4b845272791b75c8285108c4dcd91e2b9. This errata workaround did not work as intended so we are reverting this change. In the future, when the corrected workaround is published in an SDEN, we will push a new workaround. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97
* Merge "Workaround for Neoverse N1 erratum 1800710" into integrationLauren Wehrmeister2020-07-011-0/+3
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| * Workaround for Neoverse N1 erratum 1800710johpow012020-06-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Neoverse N1 erratum 1800710 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6
* | doc: RAS: fixing broken linksManish Pandey2020-06-301-0/+2
| | | | | | | | | | | | | | | | There were some links in the file "ras.rst" which were broken, this patch fixes all the broken links in this file. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I00cf080e9338af5786239a4843cb4c2e0cc9d99d
* | Merge changes from topic "fw_config_handoff" into integrationSandrine Bailleux2020-06-261-6/+10
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | * changes: doc: Update memory layout for firmware configuration area plat/arm: Increase size of firmware configuration area plat/arm: Load and populate fw_config and tb_fw_config fconf: Handle error from fconf_load_config plat/arm: Update the fw_config load call and populate it's information fconf: Allow fconf to load additional firmware configuration fconf: Clean confused naming between TB_FW and FW_CONFIG tbbr/dualroot: Add fw_config image in chain of trust cert_tool: Update cert_tool for fw_config image support fiptool: Add fw_config in FIP plat/arm: Rentroduce tb_fw_config device tree
| * doc: Update memory layout for firmware configuration areaManish V Badarkhe2020-06-251-6/+10
| | | | | | | | | | | | | | | | | | Captured the increase in firmware configuration area from 4KB to 8kB in memory layout document. Updated the documentation to provide details about fw_config separately. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ifbec443ced479301be65827b49ff4fe447e9109f
* | Workaround for Cortex A77 erratum 1800714johpow012020-06-251-0/+5
|/ | | | | | | | | | | | | | | | | Cortex A77 erratum 1800714 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. Since this is the first errata workaround implemented for Cortex A77, this patch also adds the required cortex_a77_reset_func in the file lib/cpus/aarch64/cortex_a77.S. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I844de34ee1bd0268f80794e2d9542de2f30fd3ad
* Workaround for Cortex A76 erratum 1800710johpow012020-06-221-0/+3
| | | | | | | | | | | | | Cortex A76 erratum 1800710 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493
* Workaround for Cortex A76 erratum 1791580johpow012020-06-221-0/+3
| | | | | | | | | | | | | Cortex A76 erratum 1791580 is a Cat B erratum present in earlier revisions of the Cortex A76. The workaround is to set a bit in the implementation defined CPUACTLR2 register, which forces atomic store operations to write-back memory to be performed in the L1 data cache. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925
* Rename Cortex-Hercules to Cortex-A78Jimmy Brisson2020-06-011-5/+4
| | | | | Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
* Cleanup the code for TBBR CoT descriptorsManish V Badarkhe2020-05-191-6/+8
| | | | | | | | | | CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c and tbbr_cot_bl2.c respectively. Common CoT used across BL1 and BL2 are moved to tbbr_cot_common.c. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I2252ac8a6960b3431bcaafdb3ea4fb2d01b79cf5
* doc: Fixup some SMCCC linksSandrine Bailleux2020-04-171-2/+2
| | | | | | | | | This is a fixup for patch 3ba55a3c5fa260c9218be1adff8f39fc2a568d68 ("docs: Update SMCCC doc, other changes for release"), where some links names got changed but their references didn't. Change-Id: I980d04dde338f3539a2ec1ae2e807440587b1cf5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* docs: Update SMCCC doc, other changes for releaselaurenw-arm2020-04-162-4/+4
| | | | | Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ie842d6a9919776de151a4e9304f870aede07c47a
* Merge "juno/sgm: Maximize space allocated to SCP_BL2" into integrationSandrine Bailleux2020-03-131-2/+2
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| * juno/sgm: Maximize space allocated to SCP_BL2Chris Kay2020-03-121-2/+2
| | | | | | | | | | | | | | | | | | | | To accommodate the increasing size of the SCP_BL2 binary, the base address of the memory region allocated to SCP_BL2 has been moved downwards from its current (mostly) arbitrary address to the beginning of the non-shared trusted SRAM. Change-Id: I086a3765bf3ea88f45525223d765dc0dbad6b434 Signed-off-by: Chris Kay <chris.kay@arm.com>
* | Mention COT build option in trusted-board-boot-build.rstSandrine Bailleux2020-03-121-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 3bff910dc16ad5ed97d470064b25481d3674732b ("Introduce COT build option"), it is now possible to select a different Chain of Trust than the TBBR-Client one. Make a few adjustments in the documentation to reflect that. Also make some minor improvements (fixing typos, better formatting, ...) along the way. Change-Id: I3bbadc441557e1e13311b6fd053fdab6b10b1ba2 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | Update cryptographic algorithms in TBBR docSandrine Bailleux2020-03-121-12/+13
|/ | | | | | | | | | | | | | | | The TBBR documentation has been written along with an early implementation of the code. At that time, the range of supported encryption and hash algorithms was failry limited. Since then, support for other algorithms has been added in TF-A but the documentation has not been updated. Instead of listing them all, which would clutter this document while still leaving it at risk of going stale in the future, remove specific references to the original algorithms and point the reader at the relevant comprehensive document for further details. Change-Id: I29dc50bc1d53b728091a1fbaa1c3970fb999f7d5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* Merge "Fix crash dump for lower EL" into integrationMark Dykes2020-03-111-77/+98
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| * Fix crash dump for lower ELAlexei Fedorov2020-03-061-77/+98
| | | | | | | | | | | | | | | | | | This patch provides a fix for incorrect crash dump data for lower EL when TF-A is built with HANDLE_EA_EL3_FIRST=1 option which enables routing of External Aborts and SErrors to EL3. Change-Id: I9d5e6775e6aad21db5b78362da6c3a3d897df977 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | docs: Update docs with firmware encryption featureSumit Garg2020-03-092-1/+37
|/ | | | | | | Update documentation with optional firmware encryption feature. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I26691b18e1ee52a73090954260f26f2865c4e05a
* doc: Fix variables names in TBBR CoT documentationSandrine Bailleux2020-03-021-14/+14
| | | | | | | | | | In commit 516beb585c23056820a854b12c77a6f62cbc5c8b ("TBB: apply TBBR naming convention to certificates and extensions"), some of the variables used in the TBBR chain of trust got renamed but the documentation did not get properly updated everywhere to reflect these changes. Change-Id: Ie8e2146882c2d3538c5b8c968d1bdaf5ea2a6e53 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* cpus: higher performance non-cacheable load forwardingVarun Wadekar2020-02-201-0/+7
| | | | | | | | | | | | | | | The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable non-cacheable streaming enhancement. Platforms can set this bit only if their memory system meets the requirement that cache line fill requests from the Cortex-A57 processor are atomic. This patch adds support to enable higher performance non-cacheable load forwarding for such platforms. Platforms must enable this support by setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their makefiles. This flag is disabled by default. Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* Merge "Update docs with PMU security information" into integrationManish Pandey2020-02-191-2/+2
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| * Update docs with PMU security informationPetre-Ionut Tudor2020-02-121-2/+2
| | | | | | | | | | | | | | | | This patch adds information on the PMU configuration registers and security considerations related to the PMU. Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Change-Id: I36b15060b9830a77d3f47f293c0a6dafa3c581fb
* | Adds option to read ROTPK from registers for FVPMax Shvetsov2020-02-061-11/+10
|/ | | | | | | | | | | | | | | | | Enables usage of ARM_ROTPK_LOCATION=regs for FVP board. Removes hard-coded developer keys. Instead, setting ARM_ROTPK_LOCATION=devel_* takes keys from default directory. In case of ROT_KEY specified - generates a new hash and replaces the original. Note: Juno board was tested by original feature author and was not tested for this patch since we don't have access to the private key. Juno implementation was moved to board-specific file without changing functionality. It is not known whether byte-swapping is still needed for this platform. Change-Id: I0fdbaca0415cdcd78f3a388551c2e478c01ed986 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
* Neovers N1: added support to update presence of External LLCManish Pandey2020-01-271-0/+5
| | | | | | | | | | | | CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external last level cache(LLC) in the system, the reset value is internal LLC. To cater for the platforms(like N1SDP) which has external LLC present introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be enabled by platform port. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
* Merge "bl31: Split into two separate memory regions" into integrationAlexei Fedorov2020-01-021-0/+5
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| * bl31: Split into two separate memory regionsSamuel Holland2019-12-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms are extremely memory constrained and must split BL31 between multiple non-contiguous areas in SRAM. Allow the NOBITS sections (.bss, stacks, page tables, and coherent memory) to be placed in a separate region of RAM from the loaded firmware image. Because the NOBITS region may be at a lower address than the rest of BL31, __RW_{START,END}__ and __BL31_{START,END}__ cannot include this region, or el3_entrypoint_common would attempt to invalidate the dcache for the entire address space. New symbols __NOBITS_{START,END}__ are added when SEPARATE_NOBITS_REGION is enabled, and the dcached for the NOBITS region is invalidated separately. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Idedfec5e4dbee77e94f2fdd356e6ae6f4dc79d37
* | Workaround for Hercules erratum 1688305Madhukar Pappireddy2019-12-231-0/+6
|/ | | | | | | | | | Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions of Hercules core. The erratum can be avoided by setting bit 1 of the implementation defined register CPUACTLR2_EL1 to 1 to prevent store- release from being dispatched before it is the oldest. Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* Merge "Changes to support updated register usage in SMCCC v1.2" into integrationAlexei Fedorov2019-11-291-2/+2
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| * Changes to support updated register usage in SMCCC v1.2Madhukar Pappireddy2019-11-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From AArch64 state, arguments are passed in registers W0-W7(X0-X7) and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls. From AArch32 state, arguments are passed in registers R0-R7 and results are returned in registers R0-R7 for SMC32 calls. Most of the functions and macros already existed to support using upto 8 registers for passing/returning parameters/results. Added few helper macros for SMC calls from AArch32 state. Link to the specification: https://developer.arm.com/docs/den0028/c Change-Id: I87976b42454dc3fc45c8343e9640aa78210e9741 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | doc: Split the User Guide into multiple filesPaul Beesley2019-11-276-14/+218
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The User Guide document has grown organically over time and now covers a wide range of topics, making it difficult to skim read and extract information from. Currently, it covers these topics and maybe a couple more: - Requirements (hardware, tools, libs) - Checking out the repo - Basic build instructions - A comprehensive list of build flags - FIP packaging - Building specifically for Juno - Firmware update images - EL3 payloads - Preloaded BL33 boot flow - Running on FVPs - Running on Juno I have separated these out into a few groups that become new documents. Broadly speaking, build instructions for the tools, for TF-A generally, and for specific scenarios are separated. Content relating to specific platforms (Juno and the FVPs are Arm-specific platforms, essentially) has been moved into the documentation that is specific to those platforms, under docs/plat/arm. Change-Id: Ica87c52d8cd4f577332be0b0738998ea3ba3bbec Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* doc: Misc syntax and spelling fixesPaul Beesley2019-10-111-2/+2
| | | | | | | | | | Tidying up a few Sphinx warnings that had built-up over time. None of these are critical but it cleans up the Sphinx output. At the same time, fixing some spelling errors that were detected. Change-Id: I38209e235481eed287f8008c6de9dedd6b12ab2e Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* doc: Convert internal links to RST formatPaul Beesley2019-10-086-93/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently links between documents are using the format: <path/to/><filename>.rst This was required for services like GitHub because they render each document in isolation - linking to another document is like linking to any other file, just provide the full path. However, with the new approach, the .rst files are only the raw source for the documents. Once the documents have been rendered the output is now in another format (HTML in our case) and so, when linking to another document, the link must point to the rendered version and not the .rst file. The RST spec provides a few methods for linking between content. The parent of this patch enabled the automatic creation of anchors for document titles - we will use these anchors as the targets for our links. Additional anchors can be added by hand if needed, on section and sub-section titles, for example. An example of this new format, for a document with the title "Firmware Design" is :ref:`Firmware Design`. One big advantage of this is that anchors are not dependent on paths. We can then move documents around, even between directories, without breaking any links between documents. Links will need to be updated only if the title of a document changes. Change-Id: I9e2340a61dd424cbd8fd1ecc2dc166f460d81703 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* Merge "Neoverse N1 Errata Workaround 1542419" into integrationSoby Mathew2019-10-071-0/+3
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