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* Fix MISRA C issues in BL1/BL2/BL31John Powell2020-04-0310-162/+172
| | | | | | | | | | Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code. Mainly issues like not using boolean expressions in conditionals, conflicting variable names, ignoring return values without (void), adding explicit casts, etc. Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a Signed-off-by: John Powell <john.powell@arm.com>
* Merge "Add support to pass the nt_fw_config DTB to OP-TEE." into integrationAlexei Fedorov2020-04-011-20/+49
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| * Add support to pass the nt_fw_config DTB to OP-TEE.Javier Almansa Sobrino2020-04-011-20/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | At the moment, OP-TEE has no support to receive a DTB in Secure Memory so it cannot receive TOS_FW_CONFIG_ID as it is supposed to happen on any BL32 image. Instead, when OP-TEE is enable as BL32 payload, NT_FW_CONFIG_ID is passed. This MUST be reverted as soon as OP-TEE has support for receiving DTBs from Secure Memory. Change-Id: I9a873f42e94f2f99a60b638333e7afba1505aec9 Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
* | Merge changes from topic "rpi_cpu_off" into integrationManish Pandey2020-04-018-183/+111
|\ \ | | | | | | | | | | | | | | | | | | * changes: rpi: Implement PSCI CPU_OFF rpi: rpi3_pwr_domain_on(): Use MMIO accessor rpi: move plat_helpers.S to common
| * | rpi: Implement PSCI CPU_OFFAndrei Warkentin2020-04-014-10/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We simulate the PSCI CPU_OFF operation by reseting the core via RMR. For secondaries, that already puts them in the holding pen waiting for a "warm boot" request as part of PSCI CPU_ON. For the BSP, we have to add logic to distinguish a regular boot from a CPU_OFF state, where, like the secondaries, the BSP needs to wait foor a "warm boot" request as part of CPU_ON. Testing done: - ACS suite now passes more tests (since it repeatedly calls code on secondaries via CPU_ON). - Linux testing including offlining/onlineing CPU0, e.g. "echo 0 > /sys/devices/system/cpu/cpu0/online". Change-Id: Id0ae11a0ee0721b20fa2578b54dadc72dcbd69e0 Link: https://developer.trustedfirmware.org/T686 Signed-off-by: Andrei Warkentin <andrey.warkentin@gmail.com> [Andre: adapt to unified plat_helpers.S, smaller fixes] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | rpi: rpi3_pwr_domain_on(): Use MMIO accessorAndre Przywara2020-04-011-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When writing to arbitrary locations in memory using a constructed pointer, there is no guarantee that the compiler does not optimise away the access, since it cannot detect any dependency. One typical solution is to use the "volatile" keyword, but using MMIO accessors in usually the better answer, to avoid torn writes. Replace the usage of an array with such an MMIO accessor function in rpi3_pwr_domain_on(), to make sure the write is really happening. Change-Id: Ia18163c95e92f1557471089fd18abc6dc7fee0c7 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | rpi: move plat_helpers.S to commonAndre Przywara2020-04-017-171/+37
| |/ | | | | | | | | | | | | | | | | | | | | | | The plat_helpers.S file was almost identical between its RPi3 and RPi4 versions. Unify the two files, moving it into the common/ directory. This adds a plat_rpi_get_model() function, which can be used to trigger RPi4 specific action, detected at runtime. We use that to do the RPi4 specific L2 cache initialisation. Change-Id: I2295704fd6dde7c76fe83b6d98c7bf998d4bf074 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | uniphier: support read-only xlat tablesMasahiro Yamada2020-04-012-0/+20
| | | | | | | | | | | | | | | | | | | | | | BL2 for this platform uses mmap_add_dynamic_region(), but BL31 and BL32 (TSP) only use static mapping. So, BL31 and BL32 can make the tables read-only after enabling MMU. Enable ALLOW_RO_XLAT_TABLES by default. Change-Id: Ib59c44697163629119888bb6abd47fa144f09ba3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | uniphier: use enable_mmu() in common functionMasahiro Yamada2020-04-014-5/+2
| | | | | | | | | | | | | | | | | | | | Currently, enable_mmu_el1() or enable_mmu_el3() is kept outside the common function because the appropriate one must be chosen. Use enable_mmu() and move it to the common function. Change-Id: If2fb651691a7b6be05674f5cf730ae067ba95d4b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | doc: Fix "unexpected indentation" warning.Louis Mayencourt2020-04-014-1/+21
| | | | | | | | | | Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: I521eed6466fdfef18a92f5237912cb402441044a
* | doc: Update fconf uml diagramsLouis Mayencourt2020-04-012-6/+6
| | | | | | | | | | | | | | Update the plantuml diagrams to match the latest modification in fconf. Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: I90f55bba0fd039a3f7e1bd39661cf849fccd64f5
* | Enable MTE supportManish V Badarkhe2020-04-013-0/+38
|/ | | | | | | | | | | | | | | | | | | | Enable MTE support by adding memory tag option in Makefile This option is available only when ARMv8.5-MemTag is implemented MTE options are added in latest clang and armclang compiler which support below options: for clang <version 11.0.0> 1. -march=arm8.5-a+memtag 2. -fsanitize=memtag for armclang <version 6.12> 1. -march=arm8.5-a+memtag 2. -mmemtag-stack Set the option SUPPORT_STACK_MEMTAG=yes to enable memory stack tagging. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I4e0bbde4e9769ce03ead6f550158e22f32c1c413
* Merge "doc: Fix broken external link for Odroid C2"Sandrine Bailleux2020-04-011-1/+1
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| * doc: Fix broken external link for Odroid C2Heinrich Schuchardt2020-03-311-1/+1
| | | | | | | | | | | | | | | | | | The file README.odroid-c2 has been moved in the U-Boot repository. Reference the official uplink repository. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Change-Id: Ie72c7aefd6363a406f88ad2c87faee1c7a2125a3
* | Merge "plat: imx: imx8qx: provide debug uart num as build param" into ↵Mark Dykes2020-03-313-9/+54
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| * | plat: imx: imx8qx: provide debug uart num as build paramIgor Opaniuk2020-03-233-9/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. This removes hardcoded iomux/clk/addr configuration for debug uart, provides possibility (as a workaround, till that information isn't provided via DT) to set this configuration during compile time via IMX_DEBUG_UART build flag. Also for Colibri i.MX8QXP different pinmux configuration is applied for UART3, FLEXCAN2_RX/TX pads are muxed to ADMA_UART3_RX/TX. 2. Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A35 doesn't make sense (since UART pinmux/clock configuration is applied for UART only when DEBUG_CONSOLE_A35 is enabled. Check similar commit for i.MX8QM 98a69dfd4a("plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE")). Usage: $ make PLAT=imx8qx IMX_DEBUG_UART=3 DEBUG_CONSOLE=1 bl31 Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I5d04939b2e8ee1a5f4b2f3c6241977d3c6e91760
* | | Merge "Update code freeze and release target date for 2.3" into integrationMark Dykes2020-03-311-2/+2
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| * | | Update code freeze and release target date for 2.3laurenw-arm2020-03-311-2/+2
| | |/ | |/| | | | | | | | | | Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Icf0a5737852e4f025dd8ce3748594ad25da43045
* | | Merge "xlat_tables_v2: add enable_mmu()" into integrationMark Dykes2020-03-312-0/+20
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| * | | xlat_tables_v2: add enable_mmu()Masahiro Yamada2020-03-312-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable_mmu_* has a different function name, so it is not handy in the shared code. enable_mmu() calls an appropriate one depending on the exception level. Change-Id: I0657968bfcb91c32733f75f9259f550a5c35b1c3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | Merge "Add get_current_el_maybe_constant()" into integrationMark Dykes2020-03-311-0/+17
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| * | | Add get_current_el_maybe_constant()Masahiro Yamada2020-03-311-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some cases where we want to run EL-dependent code in the shared code. We could use #ifdef, but it leaves slight possibility where we do not know the exception level at the build-time (e.g. library code). The counter approach is to use get_current_el(), but it is run-time detection, so all EL code is linked, some of which might be unneeded. This commit adds get_current_el_maybe_constant(). This is a static inline function that returns a constant value if we know the exception level at build-time. This is mostly the case. if (get_current_el_maybe_constant() == 1) { /* do something for EL1 */ } else if (get_current_el_maybe_constant() == 3) { /* do something for EL3 */ } If get_current_el_maybe_constant() is build-time constant, the compiler will optimize out the unreachable code. If such code is included from the library code, it is not built-time constant. In this case, it falls back to get_current_el(), so it still works. Change-Id: Idb03c20342a5b5173fe2d6b40e1fac7998675ad3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | Merge "Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3 globally for C files" into ↵Mark Dykes2020-03-311-0/+12
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| * | | Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3 globally for C filesMasahiro Yamada2020-03-311-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The build system defines the IMAGE_BL* macro when compiling each image. This is useful to distinguish which image the current file is being built for by using #if defined(IMAGE_BL2) or #if defined(IMAGE_BL31), or whatever. There are some cases where we are more interested in which exception level the current file is being built for. include/lib/cpus/{aarch32,aarch64}/cpu_macros.S defines IMAGE_AT_EL3, but we do not have it globally. Pass IMAGE_AT_EL1 or IMAGE_AT_EL3 to BL*_CFLAGS so that it is available from all C code. The library code (libc.a, libmbedtls.a, etc.) is exceptional cases, where the code can be shared between BL images. Other than that, we know the exception level at the build time, and this macro will be useful in the shared code. Change-Id: I7c8a1da10726906adfba981cfe8464dff111d6b0 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | Merge "fconf: exclude fconf_dyn_cfg_getter.c from BL1_SOURCES" into integrationMark Dykes2020-03-311-3/+3
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| * | | | fconf: exclude fconf_dyn_cfg_getter.c from BL1_SOURCESMasahiro Yamada2020-03-311-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fconf_dyn_cfg_getter.c calls FCONF_REGISTER_POPULATOR(), which populates the fconf_populator structure. However, bl1/bl1.ld.S does not have: __FCONF_POPULATOR_START__ = .; KEEP(*(.fconf_populator)) __FCONF_POPULATOR_END__ = .; So, this is not linked to bl1.elf We could change either bl1/bl1.lds.S or lib/fconf/fconf.mk to make them consistent. I chose to fix up fconf.mk to keep the current behavior. This is a groundwork to factor out the common code from linker scripts. Change-Id: I07b7ad4db4ec77b57acf1588fffd0b06306d7293 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | | Merge "bl32: sp_min: reduce the alignment for fconf_populator" into integrationMark Dykes2020-03-311-2/+2
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| * | | | bl32: sp_min: reduce the alignment for fconf_populatorMasahiro Yamada2020-03-311-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sp_min.ld.S is used for aarch32. ALIGN(4) is used for alignment of the other structures. I do not think struct fconf_populator is a special case. Let's use ALIGN(4) here too. Perhaps, this is just a copy-paste mistake of commit 26d1e0c33098 ("fconf: necessary modifications to support fconf in BL31 & SP_MIN"). Change-Id: I29f4c68680842c1b5ef913934b4ccf378e9bfcfb Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | | Merge "plat: pass -D option to BL*_CPPFLAGS instead of BL*_CFLAGS" into ↵Mark Dykes2020-03-313-12/+12
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| * | | | plat: pass -D option to BL*_CPPFLAGS instead of BL*_CFLAGSMasahiro Yamada2020-03-313-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -D is a preprocessor flag that defines a macro. So, adding it to BL*_CPPFLAGS makes more sense. You can reference it not only from .c files but also from .S files. Change-Id: Ib4f2f27a3ed3eae476a6a32da7ab5225ad0649de Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | | Merge "Build: introduce per-BL CPPFLAGS and ASFLAGS" into integrationMark Dykes2020-03-311-6/+7
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| * | | | Build: introduce per-BL CPPFLAGS and ASFLAGSMasahiro Yamada2020-03-311-6/+7
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, BL*_CFLAGS and BL*_LDFLAGS are supported. For completion, this adds BL*_CPPFLAGS and BL*_ASFLAGS. My main motivation is to pass -D<macro> to BL*_CPPFLAGS so that the macro can be used from all source files. Change-Id: I0ca1e4e26386bef7fed999af140ee7cce7c2f8ef Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | Merge "Create separate header for ARM specific SMCCC defines" into integrationOlivier Deprez2020-03-318-6/+21
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| * | | | Create separate header for ARM specific SMCCC definesManish V Badarkhe2020-03-308-6/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved SMCCC defines from plat_arm.h to new <smccc_def.h> header and include this header in all ARM platforms. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I4cbc69c7b9307461de87b7c7bf200dd9b810e485
* | | | | Merge "Makefile: don't use $(CC) before value is explicit set" into integrationSandrine Bailleux2020-03-311-20/+20
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| * | | | | Makefile: don't use $(CC) before value is explicit setAhmad Fatoum2020-03-311-20/+20
|/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unless specified in the environment, $(CC) expands to some generic host C compiler like cc or c99. We set our own value for $(CC), but only few lines later. Move the first use of the $(CC) variable behind the definition to correct this. Change-Id: I45344e063d21ddfe22b7ad77954e85c1c46087bd Fixes: 1684b8733 ("Use clang assembler when clang compiler is used") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* | | | | Merge "TF-A GICv3 driver: Introduce makefile" into integrationManish Pandey2020-03-3120-118/+148
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| * | | | | TF-A GICv3 driver: Introduce makefileAlexei Fedorov2020-03-3020-118/+148
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document. NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles. Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | | | | Merge "Tegra: fixup GIC init from the 'on_finish' handler" into integrationSandrine Bailleux2020-03-311-5/+12
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| * | | | | Tegra: fixup GIC init from the 'on_finish' handlerVarun Wadekar2020-03-221-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e9e19fb2fe684a740afc4820b3ee4cc38ad67d70 accidentally removed the GIC init routine required to initialze the distributor on system resume. This patch fixes this anomaly and initializes the distributor on system resume. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I3fdc694404faa509952f2d90b1f16541165e583e
* | | | | | Merge "Tegra186: increase memory mapped regions" into integrationSandrine Bailleux2020-03-311-1/+1
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| * | | | | Tegra186: increase memory mapped regionsVarun Wadekar2020-03-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch increases MAX_MMAP_REGIONS to 30 to accommodate the additional dynamic memory mapped region, during Trusty boot. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I461186a3aff5040f14715b87502fc5f1db3bea6e
* | | | | | Merge "plat/sgm775: Add support for dynamic config using fconf" into integrationManish Pandey2020-03-302-7/+18
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| * | | | | | plat/sgm775: Add support for dynamic config using fconfMadhukar Pappireddy2020-03-302-7/+18
| | |_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Necessary changes to platform makefile to include fw_config device tree and package it in fip.bin 2. Removed hw_config node from fw_config dts as there is no HW_CONFIG device tree source for sgm775 3. Added mbedtls_heap related properties for TBBR functionality Change-Id: I26b940c65b17ad2fb5537141f8649785bb0fd4ad Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | | | | Merge "Flush dcache when storing timestamp" into integrationOlivier Deprez2020-03-301-5/+3
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| * | | | | | Flush dcache when storing timestampZelalem2020-03-271-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DynamIQ CPU FVPs, stats test cases are failing when hardware-assisted coherency is enabled due to a corrupt timestamp value. Investigation of the issue indicates that on these models the timestamp value is stored in cache instead of memory. This patch flushes the dcache when the timestamp is stored to make sure it is stored in memory. Change-Id: I05cd54ba5991a5a96dd07f1e08b5212273201411 Signed-off-by: Zelalem <zelalem.aweke@arm.com>
* | | | | | | Merge changes from topic "ddr_map" into integrationOlivier Deprez2020-03-3010-51/+99
|\ \ \ \ \ \ \ | |_|_|_|_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: stm32mp1: use stm32mp_get_ddr_ns_size() function stm32mp1: set XN attribute for some areas in BL2 stm32mp1: dynamically map DDR later and non-cacheable during its test stm32mp1: add a function to get non-secure DDR size
| * | | | | | stm32mp1: use stm32mp_get_ddr_ns_size() functionYann Gautier2020-03-262-21/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using dt_get_ddr_size() and withdrawing the secure and shared memory areas, use stm32mp_get_ddr_ns_size() function. Change-Id: I5608fd7873589ea0e1262ba7d2ee3e52b53d9a7d Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | | | | stm32mp1: set XN attribute for some areas in BL2Yann Gautier2020-03-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DTB and BL32 area should not be set as executable in MMU during BL2 execution, hence set those areas as MT_RO_DATA. Change-Id: I87c47a1e7fda761e541ec98a5b294588384d31db Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | | | | | stm32mp1: dynamically map DDR later and non-cacheable during its testYann Gautier2020-03-266-25/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A speculative accesses to DDR could be done whereas it was not reachable and could lead to bus stall. To correct this the dynamic mapping in MMU is used. A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute, once DDR access is setup. It is then unmapped and a new mapping DDR is done with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE) load. The disabling of cache during DDR tests is also removed, as now useless. A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done instead. PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32. BL33 max size is also updated to take into account the secure and shared memory areas. Those are used in OP-TEE case. Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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