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* Rename symbols and files relating to CVE-2017-5715Dimitris Papastamos2018-05-2314-155/+155
| | | | | | | | This patch renames symbols and files relating to CVE-2017-5715 to make it easier to introduce new symbols and files for new CVE mitigations. Change-Id: I24c23822862ca73648c772885f1690bed043dbc7 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Merge pull request #1386 from soby-mathew/sm/dyn_bl31Dimitris Papastamos2018-05-2327-74/+562
|\ | | | | Extend dynamic configuration
| * FVP: Add dummy configs for BL31, BL32 and BL33Soby Mathew2018-05-2112-45/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds soc_fw_config, tos_fw_config and nt_fw_config to the FVP. The config files are placeholders and do not have any useful bindings defined. The tos_fw_config is packaged in FIP and loaded by BL2 only if SPD=tspd. The load address of these configs are specified in tb_fw_config via new bindings defined for these configs. Currently, in FVP, the soc_fw_config and tos_fw_config is loaded in the page between BL2_BASE and ARM_SHARED_RAM. This memory was typically used for BL32 when ARM_TSP_RAM_LOCATION=tsram but since we cannot fit BL32 in that space anymore, it should be safe to use this memory for these configs. There is also a runtime check in arm_bl2_dyn_cfg_init() which ensures that this overlap doesn't happen. The previous arm_dyn_get_hwconfig_info() is modified to accept configs other than hw_config and hence renamed to arm_dyn_get_config_load_info(). The patch also corrects the definition of ARM_TB_FW_CONFIG_LIMIT to be BL2_BASE. Change-Id: I03a137d9fa1f92c862c254be808b8330cfd17a5a Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * Dynamic cfg: Enable support on CoT for other configsSoby Mathew2018-05-188-9/+145
| | | | | | | | | | | | | | | | | | | | This patch implements support for adding dynamic configurations for BL31 (soc_fw_config), BL32 (tos_fw_config) and BL33 (nt_fw_config). The necessary cert tool support and changes to default chain of trust are made for these configs. Change-Id: I25f266277b5b5501a196d2f2f79639d838794518 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * FVP: Enable capability to disable auth via dynamic configSoby Mathew2018-05-187-4/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds capability to FVP to disable authentication dynamically via the `disable_auth` property in TB_FW_CONFIG. Both BL1 and BL2 parses the TB_FW_CONFIG for the `disable_auth` property and invokes the `load_dyn_disable_auth()` API to disable authentication if the property is set to 1. The DYN_DISABLE_AUTH is enabled by default for FVP as it is a development platform. Note that the TB_FW_CONFIG has to be authenticated by BL1 irrespective of these settings. The arm_bl2_dyn_cfg_init() is now earlier in bl2_plat_preload_setup() rather than in bl2_platform_setup() as we need to get the value of `disable_auth` property prior to authentication of any image by BL2. Change-Id: I734acd59572849793e5020ec44c6ac51f654a4d1 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * Allow disabling authentication dynamicallySoby Mathew2018-05-185-20/+86
| | | | | | | | | | | | | | | | | | | | This patch allows platforms to dynamically disable authentication of images during cold boot. This capability is controlled via the DYN_DISABLE_AUTH build flag and is only meant for development purposes. Change-Id: Ia3df8f898824319bb76d5cc855b5ad6c3d227260 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | Merge pull request #1393 from geesun/correct_commentDimitris Papastamos2018-05-221-2/+2
|\ \ | | | | | | Correct some typo errors in comment
| * | Correct some typo errors in commentQixiang Xu2018-05-221-2/+2
| |/ | | | | | | | | | | | | File: include/common/aarch64/el3_common_macros.S Change-Id: I619401e961a3f627ad8864781b5f90bc747c3ddb Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
* | Merge pull request #1390 from soby-mathew/sm/fvp_rm_dtbDimitris Papastamos2018-05-229-19/+29
|\ \ | | | | | | Remove the DTBs and update userguide for FVP
| * | Docs: Update user guide for Dynamic Config on FVPSoby Mathew2018-05-211-19/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From TF-A v1.5, FVP supports loading the kernel FDT through firmware as part of dynamic configuration feature. This means that the FDT no longer needs to be loaded via Model parameters. This patch updates the user guide to reflect the same. Change-Id: I79833beeaae44a1564f6512c3a473625e5959f65 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
| * | Dynamic_config: remove the FVP dtb filesSoby Mathew2018-05-218-0/+0
| |/ | | | | | | | | | | | | | | | | Since FVP enables dynamic configuration by default, the DT blobs are compiled from source and included in FIP during build. Hence this patch removes the dtb files from the `fdts` folder. Change-Id: Ic155ecd257384a33eb2aa38c9b4430e47b09cd31 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | Merge pull request #1359 from danielboulby-arm/db/match_flags_typeDimitris Papastamos2018-05-212-4/+8
|\ \ | |/ |/| Ensure read and write of flags defined in the console struct are 32 bit
| * Ensure read and write of flags are 32 bitDaniel Boulby2018-05-172-4/+8
| | | | | | | | | | | | | | | | | | | | In 'console_set_scope' and when registering a console, field 'flags' of 'console_t' is assigned a 32-bit value. However, when it is actually used, the functions perform 64-bit reads to access its value. This patch changes all 64-bit reads to 32-bit reads. Change-Id: I181349371409e60065335f078857946fa3c32dc1 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* | Merge pull request #1369 from sivadur/xilinxdiffdanh-arm2018-05-1717-271/+692
|\ \ | | | | | | Xilinx platform mangement related changes
| * | zynqmp: Add wdt timeout restart functionalitySiva Durga Prasad Paladugu2018-05-176-0/+243
| | | | | | | | | | | | | | | | | | | | | This patch adds support to restart system incase of wdt timeout. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | zynqmp: Fix EG/EV detection logicSiva Durga Prasad Paladugu2018-05-172-25/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vcu disable bit in efuse ipdisable register is valid only if PL powered up so, consider PL powerup status for determing EG/EV part. If PL is not powered up, display EG/EV as a part of string. The PL powerup status will be filled by pmufw based on PL PROGB status in the 9th bit of version field.This patch also used IPI to get this info from pmufw instead of directly accessing the registers. Accessing this info from pmufw using IPI fixes the issue of PMUFW access denied error for reading IPDISABLE register. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
| * | zynqmp: Add new API for processing secure imagesSiva Durga Prasad Paladugu2018-05-174-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds new API for processing secure images. This API is used for authentication and decryption of secure images using xilsecure in pmufw. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | xilinx: zynqmp: pm_service: Fix APU only restartTejas Patel2018-05-173-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing code blocks each IPI send request in ipi_mb_notify() function till pmu clears respective bit in ipi observation register. After sending PM_SYSTEM_SHUTDOWN request to PMU, PMU will restart APU. While PMU is restarting APU, ATF is running out of OCM, which can cause read/write hang from/to OCM. There is no need to wait for notification from PMU in case of SystemShutdown request in ATF, as APU is going to restart. This patch fixes APU only restart issue. Signed-off-by: Tejas Patel <tejasp@xilinx.com> Acked-by: Wendy Liang <wendy.liang@xilinx.com>
| * | plat: xilinx: zynqmp: Make fpga load blocking until completedSiva Durga Prasad Paladugu2018-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch makes bitstream load blocking call and waits until bitstream is loaded successfully or return with error. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Avesh Khan <aveshk@xilinx.com>
| * | plat: xilinx: zynqmp: Remove GET_CALLBACK_DATA functionSiva Durga Prasad Paladugu2018-05-173-24/+0
| | | | | | | | | | | | | | | | | | | | | GET_CALLBACK_DATA function is not required now. IPI mailbox can be used instead of GET_CALLBACK_DATA function. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | zynqmp: pm_service: Make PMU IPI-1 channel unsecureRajan Vaja2018-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PMU IPI-1 is used for callbacks from PMU to master. Unsecure master can also receive callbacks from PMU, so make PMU IPI-1 as non-secure. All requests from master(s) to PMU would still go on PMU IPI-1 secure channel. Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
| * | zynqmp: pm: Remove unnecessary header includesRajan Vaja2018-05-171-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove includes of gic_common.h and string.h which are not required. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Acked-by: Jolly Shah <jollys@xilinx.com>
| * | xilinx: zynqmp: Remove PMU Firmware checksSiva Durga Prasad Paladugu2018-05-174-198/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx now requires the PMU FW when using ATF, so it doesn't make sense to maintain checks for the PMU FW in ATF. This also means that cases where ATF came up before the PMU FW (such as on QEMU) ATF will now hang waiting for the PMU FW instead of aborting. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
| * | zynqmp: pm: Reverse logic for detecting that the PMU firmware is loadedSiva Durga Prasad Paladugu2018-05-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use positive logic (pm_up instead of pm_down) to check whether PMU services are available. This change also puts the variable into the BSS section rather than the Data section as the variable is now initialized to 0 rather than 1. Signed-off-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | plat: zynqmp: Don't panic() if we can't find the FSBL structAlistair Francis2018-05-172-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we can't find the FSBL handoff struct don't panic and just use the defaults instead. We still print a warning to the user to let them know what we couldn't find it. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
| * | plat: zynqmp: Let fsbl_atf_handover() return an error statusSiva Durga Prasad Paladugu2018-05-173-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | Instead of calling panic() in fsbl_atf_handover() return the error status so that bl31_early_platform_setup() can act accordingly. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | Include "bl_common.h" in Xilinx zynqmp_private.hWendy Liang2018-05-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Type "entry_point_info_t" is used in zynqmp_private.h. It is defined in "bl_common.h". The header file which defines the type should be included. Signed-off-by: Wendy Liang <jliang@xilinx.com>
| * | zynqmp: pm: Added APIs for xilsecure linux supportSiva Durga Prasad Paladugu2018-05-173-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | Added SHA to calculate SHA3 hash,RSA to encrypt data with public key and decrypt with private key and AES to do symmetric encryption with User key or device key. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | plat: zynqmp: Add support for CG/EG/EV device detectionSiva Durga Prasad Paladugu2018-05-172-3/+77
| | | | | | | | | | | | | | | | | | | | | | | | Read ipdisable reg which needs to be used for cg/eg/ev device detection. ATF runs in EL3 that's why this read can be done directly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | aarch64: zynqmp: Add new Ids for RFSoCSiva Durga Prasad Paladugu2018-05-171-0/+24
| | | | | | | | | | | | | | | | | | | | | Add new id codes for RFSoC's. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynqmp: Fix CSU ID SVD mask fo getting chip IDSiva Durga Prasad Paladugu2018-05-171-1/+2
| | | | | | | | | | | | | | | | | | | | | This patch corrects the SVD mask for getting chip ID using 0xe is wrong and 0x7 is correct. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
| * | zynqmp: pm: Allow to set shutdown scope via pm_system_shutdown APISiva Durga Prasad Paladugu2018-05-174-3/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | psci system_reset and system_off calls now retrieve shutdown scope on the fly. The default scope is system, but it can be changed by calling pm_system_shutdown(2, scope) Until full support for different restart scopes becomes available with PSCI 1.1 this change allows users to set the reboot scope to match their application needs. Possible scope values: 0 - APU subsystem: does not affect RPU, PMU or PL 1 - PS only: shutdown/restart entire PS without affecting PL 2 - System: shutdown/restart applies to entire system Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
| * | zynqmp: pm: Implement PM_INIT_FINALIZE PM API callFilip Drazic2018-05-173-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PM_INIT_FINALIZE PM API is required to inform the PFW that APU is done with requesting nodes and that not-requested nodes can be powered down. If PM is not enabled, this call will never be made and PFW will never power down any of the nodes which APU can use. Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
| * | zynqmp: pm: Rename PM_INIT to PM_INIT_FINALIZEFilip Drazic2018-05-171-1/+1
| | | | | | | | | | | | Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
| * | zynqmp: pm: Implemented new pm API to load secure imagesSiva Durga Prasad Paladugu2018-05-173-0/+36
| | | | | | | | | | | | | | | | | | | | | This patch adds pm_secure_rsaaes() API to provide access to the xilsecure library for loading secure images Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | xilinx: zynqmp: Read bootmode register using PM APISiva Durga Prasad Paladugu2018-05-171-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | Read boot mode register using pm_mmio_read if pmu is present otherwise access it directly using mmio_read_32(). Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
| * | zynqmp: pm: Decode start address related SMC arguments for pm_req_wakeupFilip Drazic2018-05-171-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pm_req_wakeup PM API accepts start address (64-bit unsiged integer) and a flag stating if address should be used. To save an argument of the SMC call, flag is encoded in the LSB of the address, since addresses are word aligned. Decode start address and use-address flag in the PM SMC handler and pass them to pm_req_wakeup. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Will Wong <willw@xilinx.com>
| * | zynqmp: pm: Move pm_client_wakeup call from pm_req_wakeupFilip Drazic2018-05-172-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call to pm_client_wakeup from pm_req_wakeup prevented the PM API call to be used to wake up non-APU processor (e.g. from higher ELs), since it clears power down request for specified APU processor. Move this function out of pm_client_wakeup to allow passing wake up requests to the PMU for other processor in the system. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Will Wong <willw@xilinx.com>
| * | zynqmp: pm: Remove unused NODE_AFI, add NODE_EXTERNMirela Simonovic2018-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | NODE_EXTERN is the slave node which represents an external wake source. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <willw@xilinx.com>
| * | zynqmp: pm: Add support for setting suspend-to-RAM modeSiva Durga Prasad Paladugu2018-05-173-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Beside standard suspend-to-RAM state, Zynq MPSoC supports suspend-to-RAM state with additional power savings, called power-off suspend-to-RAM. If this mode is set, only NODE_EXTERN must be set as wake source. Standard suspend-to-RAM procedure is unchanged. This patch adds support for setting suspend mode from higher ELs and ensuring that all conditions for power-off suspend mode are set. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
| * | zynqmp: pm: Implement pm_get_node_status API functionAnes Hadziahmetagic2018-05-173-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pm_get_node_status API function returns 3 values: -status: Current power state of the node -requirements: Current requirements for the node -usage: Current usage of the node The last two values only apply to slave nodes. Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com> Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Will Wong <willw@xilinx.com>
* | | Merge pull request #1340 from Andre-ARM/sec-irqs-fixesDimitris Papastamos2018-05-173-11/+6
|\ \ \ | | | | | | | | Fix support for systems without secure interrupts
| * | | gicv3: Fix support for systems without secure interruptsAndre Przywara2018-04-032-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Accessing the interrupt_props array only happens inside a loop over interrupt_props_num, so the GICv3 driver can cope with no secure interrupts. This allows us to relax the asserts that insists on a non-NULL interrupt_props pointer and at least one secure interrupt. This enables GICv3 platforms which have no need for a secure interrupt. This only covers the non-deprecated code paths. Change-Id: I49db291906512f56af065772f69acb281dfbdcfb Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | gicv2: Fix support for systems without secure interruptsSamuel Holland2018-04-031-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Accessing the interrupt_props array only happens inside a loop over interrupt_props_num, so the GICv2 driver can cope with no secure interrupts. As in fact we have already some asserts in place that respect that, lets change the final place where we insist on a non-NULL pointer to relax that. This enables GICv2 platforms which have no need for a secure interrupt. This only covers the non-deprecated code paths. Also we remove a now redundant assert(). Change-Id: Id100ea978643d8558335ad28649d55743fe9bd4c Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | Merge pull request #1384 from rockchip-linux/for_m0_patchDimitris Papastamos2018-05-1719-111/+175
|\ \ \ \ | |_|/ / |/| | | for rk3399 suspend/resume
| * | | rockchip/rk3399: Add watchdog support in pmusramDerek Basehore2018-05-156-36/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To catch early hangs in resume, this sets up the watchdog before anything else in the pmusram code (ignoring setting up the stack...). This uses hard coded settings for the watchdog until the proper watchdog restore later on in the firmware/kernel. This also restores the old watchdog register values before the PLLs are restored to make sure we don't temporarily switch over to a 1/3s timeout on the watchdog when the pclk_wdt goes from 4MHz to 100MHz. Change-Id: I8f7652089a88783271b17482117b4609330abe80 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
| * | | rockchip/rk3399: Split M0 binary into twoLin Huang2018-05-1514-74/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the m0 code run in SRAM before, but we need to watch PMU_POWER_ST when SOC enter into FSM, and SRAM will shutdown during this time, so this code need run in PMUSRAM. But PMUSRAM only 8K space, we can not put all the m0 binary into PMUSRAM, Split the M0 binary into two, dram part still run in SRAM, and suspend part run in PMUSRAM. Change-Id: Ie08bdf3e2b8838f12b9297fe60ab0aad219684b1 Signed-off-by: Lin Huang <hl@rock-chips.com>
| * | | rockchip/rk3399: improve pmu powermode configure when suspendLin Huang2018-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | we need to enable PMU_WKUP_RST_EN for pmu powermode configure, since enable wakeup reset will hold the soc status, so the SOC will not affect by some power or other single glitch when resume, and keep the soc in the right status. And it not need to enable DDRIO_RET_HW_DE_REQ, the ddr resume will do it manual. Change-Id: Ib4af897ffb3cb63dc2aa9a6002e5d9ef86ee4a49 Signed-off-by: Lin Huang <hl@rock-chips.com>
* | | | Merge pull request #1387 from vishwanathahg/sgi575/core_pos_calcDimitris Papastamos2018-05-167-57/+44
|\ \ \ \ | |_|_|/ |/| | | Sgi575/core pos calc
| * | | css/sgi: rework the core position calculation functionVishwanatha HG2018-05-164-20/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MT bit in MPIDR is always set for SGI platforms and so the core position calculation code is updated to take into account the thread affinity value as well. Change-Id: I7b2a52707f607dc3859c6bbcd2b145b7987cb4ed Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Vishwanatha HG <vishwanatha.hg@arm.com>
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