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-rw-r--r--include/lib/cpus/aarch64/cortex_a57.h2
-rw-r--r--include/lib/cpus/aarch64/cortex_a76.h4
-rw-r--r--include/lib/cpus/aarch64/cortex_a77.h10
-rw-r--r--include/lib/cpus/aarch64/cortex_a78.h (renamed from include/lib/cpus/aarch64/cortex_hercules.h)35
-rw-r--r--include/lib/cpus/aarch64/cortex_a78_ae.h14
-rw-r--r--include/lib/cpus/aarch64/cortex_hercules_ae.h14
-rw-r--r--include/lib/cpus/aarch64/cortex_klein.h23
-rw-r--r--include/lib/cpus/aarch64/cortex_matterhorn.h23
-rw-r--r--include/lib/cpus/aarch64/cpu_macros.S4
-rw-r--r--include/lib/cpus/aarch64/denver.h10
-rw-r--r--include/lib/cpus/aarch64/generic.h18
-rw-r--r--include/lib/cpus/aarch64/neoverse_n2.h31
-rw-r--r--include/lib/cpus/aarch64/neoverse_n_common.h18
-rw-r--r--include/lib/cpus/aarch64/neoverse_v1.h (renamed from include/lib/cpus/aarch64/neoverse_zeus.h)16
-rw-r--r--include/lib/cpus/aarch64/rainier.h66
-rw-r--r--include/lib/cpus/errata_report.h3
16 files changed, 246 insertions, 45 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index 102ff60c3..dc40e31ad 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,6 +55,7 @@
#define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38)
#define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
#define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)
+#define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24)
#define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25)
#define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h
index 7dc7e068a..a61825f1b 100644
--- a/include/lib/cpus/aarch64/cortex_a76.h
+++ b/include/lib/cpus/aarch64/cortex_a76.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,6 +32,8 @@
#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
+#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
+
#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
#define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index 0467ef3bb..0a42a5d77 100644
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,6 +16,7 @@
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
/*******************************************************************************
* CPU Power Control register specific definitions.
@@ -23,4 +24,11 @@
#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
+#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0
+#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1
+#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2
+#define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3
+#define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4
+#define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5
+
#endif /* CORTEX_A77_H */
diff --git a/include/lib/cpus/aarch64/cortex_hercules.h b/include/lib/cpus/aarch64/cortex_a78.h
index d5ca85ed2..caa512046 100644
--- a/include/lib/cpus/aarch64/cortex_hercules.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -1,44 +1,45 @@
/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef CORTEX_HERCULES_H
-#define CORTEX_HERCULES_H
+#ifndef CORTEX_A78_H
+#define CORTEX_A78_H
#include <lib/utils_def.h>
-#define CORTEX_HERCULES_MIDR U(0x410FD410)
+#define CORTEX_A78_MIDR U(0x410FD410)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
-#define CORTEX_HERCULES_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
-#define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
+#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30)
+#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
-#define CORTEX_HERCULES_ACTLR2_EL1 S3_0_C15_C1_1
-#define CORTEX_HERCULES_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
+#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
+#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.
******************************************************************************/
-#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
-#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
-#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
-#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
+#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
+#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
+#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
+#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
-#define CORTEX_HERCULES_AMU_GROUP0_MASK U(0xF)
-#define CORTEX_HERCULES_AMU_GROUP1_MASK U(0x7)
+#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
+#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
-#endif /* CORTEX_HERCULES_H */
+#endif /* CORTEX_A78_H */
diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h
new file mode 100644
index 000000000..24ae7eeac
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a78_ae.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A78_AE_H
+#define CORTEX_A78_AE_H
+
+#include <cortex_a78.h>
+
+#define CORTEX_A78_AE_MIDR U(0x410FD420)
+
+#endif /* CORTEX_A78_AE_H */
diff --git a/include/lib/cpus/aarch64/cortex_hercules_ae.h b/include/lib/cpus/aarch64/cortex_hercules_ae.h
deleted file mode 100644
index 795563bc3..000000000
--- a/include/lib/cpus/aarch64/cortex_hercules_ae.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_HERCULES_AE_H
-#define CORTEX_HERCULES_AE_H
-
-#include <cortex_hercules.h>
-
-#define CORTEX_HERCULES_AE_MIDR U(0x410FD420)
-
-#endif /* CORTEX_HERCULES_AE_H */
diff --git a/include/lib/cpus/aarch64/cortex_klein.h b/include/lib/cpus/aarch64/cortex_klein.h
new file mode 100644
index 000000000..729b3bf0a
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_klein.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2020, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_KLEIN_H
+#define CORTEX_KLEIN_H
+
+#define CORTEX_KLEIN_MIDR U(0x410FD460)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_KLEIN_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_KLEIN_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_KLEIN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_KLEIN_H */
diff --git a/include/lib/cpus/aarch64/cortex_matterhorn.h b/include/lib/cpus/aarch64/cortex_matterhorn.h
new file mode 100644
index 000000000..018553359
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_matterhorn.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2020, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_MATTERHORN_H
+#define CORTEX_MATTERHORN_H
+
+#define CORTEX_MATTERHORN_MIDR U(0x410FD470)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_MATTERHORN_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_MATTERHORN_H */
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index c83824d77..92891ce38 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -25,10 +25,6 @@
/* Word size for 64-bit CPUs */
#define CPU_WORD_SIZE 8
-#if defined(IMAGE_BL1) || defined(IMAGE_BL31) ||(defined(IMAGE_BL2) && BL2_AT_EL3)
-#define IMAGE_AT_EL3
-#endif
-
/*
* Whether errata status needs reporting. Errata status is printed in debug
* builds for both BL1 and BL31 images.
diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h
index 02657a0fb..24b6a870c 100644
--- a/include/lib/cpus/aarch64/denver.h
+++ b/include/lib/cpus/aarch64/denver.h
@@ -13,6 +13,11 @@
#define DENVER_MIDR_PN2 U(0x4E0F0020)
#define DENVER_MIDR_PN3 U(0x4E0F0030)
#define DENVER_MIDR_PN4 U(0x4E0F0040)
+#define DENVER_MIDR_PN5 U(0x4E0F0050)
+#define DENVER_MIDR_PN6 U(0x4E0F0060)
+#define DENVER_MIDR_PN7 U(0x4E0F0070)
+#define DENVER_MIDR_PN8 U(0x4E0F0080)
+#define DENVER_MIDR_PN9 U(0x4E0F0090)
/* Implementer code in the MIDR register */
#define DENVER_IMPL U(0x4E)
@@ -34,6 +39,11 @@
#define DENVER_CPU_PMSTATE_C7 U(0x7)
#define DENVER_CPU_PMSTATE_MASK U(0xF)
+/* ACTRL_ELx bits to enable dual execution*/
+#define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9)
+#define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9)
+#define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4)
+
#ifndef __ASSEMBLER__
/* Disable Dynamic Code Optimisation */
diff --git a/include/lib/cpus/aarch64/generic.h b/include/lib/cpus/aarch64/generic.h
new file mode 100644
index 000000000..53df58761
--- /dev/null
+++ b/include/lib/cpus/aarch64/generic.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserverd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AARCH64_GENERIC_H
+#define AARCH64_GENERIC_H
+
+#include <lib/utils_def.h>
+
+/*
+ * 0x0 value on the MIDR implementer value is reserved for software use,
+ * so use an MIDR value of 0 for a default CPU library.
+ */
+#define AARCH64_GENERIC_MIDR U(0)
+
+#endif /* AARCH64_GENERIC_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
new file mode 100644
index 000000000..7cbd8c17b
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_N2_H
+#define NEOVERSE_N2_H
+
+/* Neoverse N2 ID register for revision r0p0 */
+#define NEOVERSE_N2_MIDR U(0x410FD490)
+
+/*******************************************************************************
+ * CPU Power control register
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
+#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
+#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
+
+#endif /* NEOVERSE_N2_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n_common.h b/include/lib/cpus/aarch64/neoverse_n_common.h
new file mode 100644
index 000000000..7cb91cd05
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_n_common.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_N_COMMON_H
+#define NEOVERSE_N_COMMON_H
+
+/******************************************************************************
+ * Neoverse Nx CPU Configuration register definitions
+ *****************************************************************************/
+#define CPUCFR_EL1 S3_0_C15_C0_0
+
+/* SCU bit of CPU Configuration Register, EL1 */
+#define SCU_SHIFT U(2)
+
+#endif /* NEOVERSE_N_COMMON_H */
diff --git a/include/lib/cpus/aarch64/neoverse_zeus.h b/include/lib/cpus/aarch64/neoverse_v1.h
index f0947271d..650eb4d41 100644
--- a/include/lib/cpus/aarch64/neoverse_zeus.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -1,23 +1,23 @@
/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef NEOVERSE_ZEUS_H
-#define NEOVERSE_ZEUS_H
+#ifndef NEOVERSE_V1_H
+#define NEOVERSE_V1_H
-#define NEOVERSE_ZEUS_MIDR U(0x410FD400)
+#define NEOVERSE_V1_MIDR U(0x410FD400)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
-#define NEOVERSE_ZEUS_CPUECTLR_EL1 S3_0_C15_C1_4
+#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
-#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-#endif /* NEOVERSE_ZEUS_H */
+#endif /* NEOVERSE_V1_H */
diff --git a/include/lib/cpus/aarch64/rainier.h b/include/lib/cpus/aarch64/rainier.h
new file mode 100644
index 000000000..978661ff6
--- /dev/null
+++ b/include/lib/cpus/aarch64/rainier.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RAINIER_H
+#define RAINIER_H
+
+#include <lib/utils_def.h>
+
+/* RAINIER MIDR for revision 0 */
+#define RAINIER_MIDR U(0x3f0f4120)
+
+/* Exception Syndrome register EC code for IC Trap */
+#define RAINIER_EC_IC_TRAP U(0x1f)
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions.
+ ******************************************************************************/
+#define RAINIER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+
+/* Definitions of register field mask in RAINIER_CPUPWRCTLR_EL1 */
+#define RAINIER_CORE_PWRDN_EN_MASK U(0x1)
+
+#define RAINIER_ACTLR_AMEN_BIT (U(1) << 4)
+
+#define RAINIER_AMU_NR_COUNTERS U(5)
+#define RAINIER_AMU_GROUP0_MASK U(0x1f)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define RAINIER_CPUECTLR_EL1 S3_0_C15_C1_4
+
+#define RAINIER_WS_THR_L2_MASK (ULL(3) << 24)
+#define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define RAINIER_CPUACTLR_EL1 S3_0_C15_C1_0
+
+#define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
+#define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
+
+#define RAINIER_CPUACTLR2_EL1 S3_0_C15_C1_1
+
+#define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
+#define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
+#define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
+#define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
+#define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
+#define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
+
+#define RAINIER_CPUACTLR3_EL1 S3_0_C15_C1_2
+
+#define RAINIER_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
+
+/* Instruction patching registers */
+#define CPUPSELR_EL3 S3_6_C15_C8_0
+#define CPUPCR_EL3 S3_6_C15_C8_1
+#define CPUPOR_EL3 S3_6_C15_C8_2
+#define CPUPMR_EL3 S3_6_C15_C8_3
+
+#endif /* RAINIER_H */
diff --git a/include/lib/cpus/errata_report.h b/include/lib/cpus/errata_report.h
index 7cac77ebe..efdedf0aa 100644
--- a/include/lib/cpus/errata_report.h
+++ b/include/lib/cpus/errata_report.h
@@ -30,4 +30,7 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported);
#define ERRATA_APPLIES 1
#define ERRATA_MISSING 2
+/* Macro to get CPU revision code for checking errata version compatibility. */
+#define CPU_REV(r, p) ((r << 4) | p)
+
#endif /* ERRATA_REPORT_H */
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-14 16:23:14 +0000