diff options
Diffstat (limited to 'include')
191 files changed, 8176 insertions, 2697 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 20175481f..c30073b8c 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -102,6 +102,11 @@ /* CSSELR definitions */ #define LEVEL_SHIFT U(1) +/* ID_DFR1_EL1 definitions */ +#define ID_DFR1_MTPMU_SHIFT U(0) +#define ID_DFR1_MTPMU_MASK U(0xf) +#define ID_DFR1_MTPMU_SUPPORTED U(1) + /* ID_MMFR4 definitions */ #define ID_MMFR4_CNP_SHIFT U(12) #define ID_MMFR4_CNP_LENGTH U(4) @@ -126,6 +131,9 @@ #define ID_PFR1_GENTIMER_MASK U(0xf) #define ID_PFR1_GIC_SHIFT U(28) #define ID_PFR1_GIC_MASK U(0xf) +#define ID_PFR1_SEC_SHIFT U(4) +#define ID_PFR1_SEC_MASK U(0xf) +#define ID_PFR1_ELx_ENABLED U(1) /* SCTLR definitions */ #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \ @@ -164,6 +172,7 @@ #define SDCR_SCCD_BIT (U(1) << 23) #define SDCR_SPME_BIT (U(1) << 17) #define SDCR_RESET_VAL U(0x0) +#define SDCR_MTPME_BIT (U(1) << 28) /* HSCTLR definitions */ #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ @@ -183,23 +192,23 @@ /* CPACR definitions */ #define CPACR_FPEN(x) ((x) << 20) -#define CPACR_FP_TRAP_PL0 U(0x1) -#define CPACR_FP_TRAP_ALL U(0x2) -#define CPACR_FP_TRAP_NONE U(0x3) +#define CPACR_FP_TRAP_PL0 UL(0x1) +#define CPACR_FP_TRAP_ALL UL(0x2) +#define CPACR_FP_TRAP_NONE UL(0x3) /* SCR definitions */ -#define SCR_TWE_BIT (U(1) << 13) -#define SCR_TWI_BIT (U(1) << 12) -#define SCR_SIF_BIT (U(1) << 9) -#define SCR_HCE_BIT (U(1) << 8) -#define SCR_SCD_BIT (U(1) << 7) -#define SCR_NET_BIT (U(1) << 6) -#define SCR_AW_BIT (U(1) << 5) -#define SCR_FW_BIT (U(1) << 4) -#define SCR_EA_BIT (U(1) << 3) -#define SCR_FIQ_BIT (U(1) << 2) -#define SCR_IRQ_BIT (U(1) << 1) -#define SCR_NS_BIT (U(1) << 0) +#define SCR_TWE_BIT (UL(1) << 13) +#define SCR_TWI_BIT (UL(1) << 12) +#define SCR_SIF_BIT (UL(1) << 9) +#define SCR_HCE_BIT (UL(1) << 8) +#define SCR_SCD_BIT (UL(1) << 7) +#define SCR_NET_BIT (UL(1) << 6) +#define SCR_AW_BIT (UL(1) << 5) +#define SCR_FW_BIT (UL(1) << 4) +#define SCR_EA_BIT (UL(1) << 3) +#define SCR_FIQ_BIT (UL(1) << 2) +#define SCR_IRQ_BIT (UL(1) << 1) +#define SCR_NS_BIT (UL(1) << 0) #define SCR_VALID_BIT_MASK U(0x33ff) #define SCR_RESET_VAL U(0x0) @@ -244,6 +253,7 @@ #define VTTBR_BADDR_SHIFT U(0) /* HDCR definitions */ +#define HDCR_MTPME_BIT (U(1) << 28) #define HDCR_HLP_BIT (U(1) << 26) #define HDCR_HPME_BIT (U(1) << 7) #define HDCR_RESET_VAL U(0x0) @@ -388,13 +398,17 @@ #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) -#define SPSR_MODE32(mode, isa, endian, aif) \ - ((MODE_RW_32 << MODE_RW_SHIFT | \ - ((mode) & MODE32_MASK) << MODE32_SHIFT | \ - ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ - ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ - ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) & \ - (~(SPSR_SSBS_BIT))) +#define SPSR_MODE32(mode, isa, endian, aif) \ +( \ + ( \ + (MODE_RW_32 << MODE_RW_SHIFT) | \ + (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ + (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ + (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ + (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \ + ) & \ + (~(SPSR_SSBS_BIT)) \ +) /* * TTBR definitions @@ -499,6 +513,7 @@ #define CTR p15, 0, c0, c0, 1 #define CNTFRQ p15, 0, c14, c0, 0 #define ID_MMFR4 p15, 0, c0, c2, 6 +#define ID_DFR1 p15, 0, c0, c3, 5 #define ID_PFR0 p15, 0, c0, c1, 0 #define ID_PFR1 p15, 0, c0, c1, 1 #define MAIR0 p15, 0, c10, c2, 0 @@ -697,4 +712,24 @@ #define AMEVTYPER1E p15, 0, c13, c15, 6 #define AMEVTYPER1F p15, 0, c13, c15, 7 +/* AMCFGR definitions */ +#define AMCFGR_NCG_SHIFT U(28) +#define AMCFGR_NCG_MASK U(0xf) +#define AMCFGR_N_SHIFT U(0) +#define AMCFGR_N_MASK U(0xff) + +/* AMCGCR definitions */ +#define AMCGCR_CG1NC_SHIFT U(8) +#define AMCGCR_CG1NC_MASK U(0xff) + +/******************************************************************************* + * Definitions for DynamicIQ Shared Unit registers + ******************************************************************************/ +#define CLUSTERPWRDN p15, 0, c15, c3, 6 + +/* CLUSTERPWRDN register definitions */ +#define DSU_CLUSTER_PWR_OFF 0 +#define DSU_CLUSTER_PWR_ON 1 +#define DSU_CLUSTER_PWR_MASK U(1) + #endif /* ARCH_H */ diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h index cbac84b93..82efb188a 100644 --- a/include/arch/aarch32/arch_helpers.h +++ b/include/arch/aarch32/arch_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,7 @@ #define ARCH_HELPERS_H #include <cdefs.h> +#include <stdbool.h> #include <stdint.h> #include <string.h> @@ -165,7 +166,7 @@ static inline void _op(void) \ #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ static inline void _op ## _type(void) \ { \ - __asm__ (#_op " " #_type); \ + __asm__ (#_op " " #_type : : : "memory"); \ } /* Define function for system instruction with register parameter */ @@ -178,6 +179,7 @@ static inline void _op ## _type(u_register_t v) \ void flush_dcache_range(uintptr_t addr, size_t size); void clean_dcache_range(uintptr_t addr, size_t size); void inv_dcache_range(uintptr_t addr, size_t size); +bool is_dcache_enabled(void); void dcsw_op_louis(u_register_t op_type); void dcsw_op_all(u_register_t op_type); @@ -298,11 +300,16 @@ DEFINE_COPROCR_RW_FUNCS(prrr, PRRR) DEFINE_COPROCR_RW_FUNCS(nmrr, NMRR) DEFINE_COPROCR_RW_FUNCS(dacr, DACR) +/* Coproc registers for 32bit AMU support */ +DEFINE_COPROCR_READ_FUNC(amcfgr, AMCFGR) +DEFINE_COPROCR_READ_FUNC(amcgcr, AMCGCR) + DEFINE_COPROCR_RW_FUNCS(amcntenset0, AMCNTENSET0) DEFINE_COPROCR_RW_FUNCS(amcntenset1, AMCNTENSET1) DEFINE_COPROCR_RW_FUNCS(amcntenclr0, AMCNTENCLR0) DEFINE_COPROCR_RW_FUNCS(amcntenclr1, AMCNTENCLR1) +/* Coproc registers for 64bit AMU support */ DEFINE_COPROCR_RW_FUNCS_64(amevcntr00, AMEVCNTR00) DEFINE_COPROCR_RW_FUNCS_64(amevcntr01, AMEVCNTR01) DEFINE_COPROCR_RW_FUNCS_64(amevcntr02, AMEVCNTR02) @@ -334,6 +341,11 @@ DEFINE_DCOP_PARAM_FUNC(cvac, DCCIMVAC) DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC) #endif +/* + * DynamIQ Shared Unit power management + */ +DEFINE_COPROCR_RW_FUNCS(clusterpwrdn, CLUSTERPWRDN) + /* Previously defined accessor functions with incomplete register names */ #define dsb() dsbsy() #define dmb() dmbsy() diff --git a/include/arch/aarch32/asm_macros.S b/include/arch/aarch32/asm_macros.S index 8cfa21231..f75da0ce6 100644 --- a/include/arch/aarch32/asm_macros.S +++ b/include/arch/aarch32/asm_macros.S @@ -95,11 +95,29 @@ #if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION) /* + * Macro for mitigating against speculative execution. * ARMv7 cores without Virtualization extension do not support the * eret instruction. */ - .macro eret + .macro exception_return movs pc, lr + dsb nsh + isb + .endm + +#else + /* + * Macro for mitigating against speculative execution beyond ERET. + * If possible use Speculation Barrier instruction defined in ARMv8.5 + */ + .macro exception_return + eret +#if ARM_ARCH_AT_LEAST(8, 5) + sb +#else + dsb nsh + isb +#endif .endm #endif diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 7559de446..580dd95b7 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -242,6 +242,10 @@ cps #MODE32_mon isb +#if DISABLE_MTPMU + bl mtpmu_disable +#endif + .if \_warm_boot_mailbox /* ------------------------------------------------------------- * This code will be executed for both warm and cold resets. @@ -329,6 +333,11 @@ bl inv_dcache_range #endif + /* + * zeromem uses r12 whereas it is used to save previous BL arg3, + * save it in r7 + */ + mov r7, r12 ldr r0, =__BSS_START__ ldr r1, =__BSS_SIZE__ bl zeromem @@ -339,6 +348,9 @@ bl zeromem #endif + /* Restore r12 */ + mov r12, r7 + #if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) /* ----------------------------------------------------- * Copy data from ROM to RAM. diff --git a/include/arch/aarch32/smccc_macros.S b/include/arch/aarch32/smccc_macros.S index 4ec229218..ea7835a42 100644 --- a/include/arch/aarch32/smccc_macros.S +++ b/include/arch/aarch32/smccc_macros.S @@ -235,7 +235,7 @@ /* Restore the rest of the general purpose registers */ ldm r0, {r0-r12} - eret + exception_return .endm #endif /* SMCCC_MACROS_S */ diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 1fcd0f9ba..2cdc7b230 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -96,6 +97,32 @@ #define ICC_SGI0R_EL1 S3_0_c12_c11_7 /******************************************************************************* + * Definitions for EL2 system registers for save/restore routine + ******************************************************************************/ + +#define CNTPOFF_EL2 S3_4_C14_C0_6 +#define HAFGRTR_EL2 S3_4_C3_C1_6 +#define HDFGRTR_EL2 S3_4_C3_C1_4 +#define HDFGWTR_EL2 S3_4_C3_C1_5 +#define HFGITR_EL2 S3_4_C1_C1_6 +#define HFGRTR_EL2 S3_4_C1_C1_4 +#define HFGWTR_EL2 S3_4_C1_C1_5 +#define ICH_HCR_EL2 S3_4_C12_C11_0 +#define ICH_VMCR_EL2 S3_4_C12_C11_7 +#define MPAMVPM0_EL2 S3_4_C10_C5_0 +#define MPAMVPM1_EL2 S3_4_C10_C5_1 +#define MPAMVPM2_EL2 S3_4_C10_C5_2 +#define MPAMVPM3_EL2 S3_4_C10_C5_3 +#define MPAMVPM4_EL2 S3_4_C10_C5_4 +#define MPAMVPM5_EL2 S3_4_C10_C5_5 +#define MPAMVPM6_EL2 S3_4_C10_C5_6 +#define MPAMVPM7_EL2 S3_4_C10_C5_7 +#define MPAMVPMV_EL2 S3_4_C10_C4_1 +#define TRFCR_EL2 S3_4_C1_C2_1 +#define PMSCR_EL2 S3_4_C9_C9_0 +#define TFSR_EL2 S3_4_C5_C6_0 + +/******************************************************************************* * Generic timer memory mapped registers & offsets ******************************************************************************/ #define CNTCR_OFF U(0x000) @@ -161,6 +188,15 @@ #define ID_AA64DFR0_PMS_SHIFT U(32) #define ID_AA64DFR0_PMS_MASK ULL(0xf) +/* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ +#define ID_AA64DFR0_MTPMU_SHIFT U(48) +#define ID_AA64DFR0_MTPMU_MASK ULL(0xf) +#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) + +/* ID_AA64ISAR0_EL1 definitions */ +#define ID_AA64ISAR0_RNDR_SHIFT U(60) +#define ID_AA64ISAR0_RNDR_MASK ULL(0xf) + /* ID_AA64ISAR1_EL1 definitions */ #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 #define ID_AA64ISAR1_GPI_SHIFT U(28) @@ -184,6 +220,17 @@ #define PARANGE_0101 U(48) #define PARANGE_0110 U(52) +#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) +#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) +#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) +#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) +#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) + +#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) +#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) +#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) +#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) + #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) @@ -199,6 +246,19 @@ #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) +/* ID_AA64MMFR1_EL1 definitions */ +#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) +#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) +#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) +#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) + +#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) +#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) +#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) +#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) +#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) +#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) + /* ID_AA64MMFR2_EL1 definitions */ #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 @@ -222,9 +282,20 @@ #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) -#define MTE_UNIMPLEMENTED ULL(0) -#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */ -#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */ +/* Memory Tagging Extension is not implemented */ +#define MTE_UNIMPLEMENTED U(0) +/* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ +#define MTE_IMPLEMENTED_EL0 U(1) +/* FEAT_MTE2: Full MTE is implemented */ +#define MTE_IMPLEMENTED_ELX U(2) +/* + * FEAT_MTE3: MTE is implemented with support for + * asymmetric Tag Check Fault handling + */ +#define MTE_IMPLEMENTED_ASY U(3) + +#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) +#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) /* ID_PFR1_EL1 definitions */ #define ID_PFR1_VIRTEXT_SHIFT U(12) @@ -237,8 +308,9 @@ (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) -#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ - (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) +#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ + (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) + #define SCTLR_AARCH32_EL1_RES1 \ ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ (U(1) << 4) | (U(1) << 3)) @@ -253,9 +325,12 @@ #define SCTLR_SA_BIT (ULL(1) << 3) #define SCTLR_SA0_BIT (ULL(1) << 4) #define SCTLR_CP15BEN_BIT (ULL(1) << 5) +#define SCTLR_nAA_BIT (ULL(1) << 6) #define SCTLR_ITD_BIT (ULL(1) << 7) #define SCTLR_SED_BIT (ULL(1) << 8) #define SCTLR_UMA_BIT (ULL(1) << 9) +#define SCTLR_EnRCTX_BIT (ULL(1) << 10) +#define SCTLR_EOS_BIT (ULL(1) << 11) #define SCTLR_I_BIT (ULL(1) << 12) #define SCTLR_EnDB_BIT (ULL(1) << 13) #define SCTLR_DZE_BIT (ULL(1) << 14) @@ -263,48 +338,99 @@ #define SCTLR_NTWI_BIT (ULL(1) << 16) #define SCTLR_NTWE_BIT (ULL(1) << 18) #define SCTLR_WXN_BIT (ULL(1) << 19) -#define SCTLR_UWXN_BIT (ULL(1) << 20) +#define SCTLR_TSCXT_BIT (ULL(1) << 20) #define SCTLR_IESB_BIT (ULL(1) << 21) +#define SCTLR_EIS_BIT (ULL(1) << 22) +#define SCTLR_SPAN_BIT (ULL(1) << 23) #define SCTLR_E0E_BIT (ULL(1) << 24) #define SCTLR_EE_BIT (ULL(1) << 25) #define SCTLR_UCI_BIT (ULL(1) << 26) #define SCTLR_EnDA_BIT (ULL(1) << 27) +#define SCTLR_nTLSMD_BIT (ULL(1) << 28) +#define SCTLR_LSMAOE_BIT (ULL(1) << 29) #define SCTLR_EnIB_BIT (ULL(1) << 30) #define SCTLR_EnIA_BIT (ULL(1) << 31) #define SCTLR_BT0_BIT (ULL(1) << 35) #define SCTLR_BT1_BIT (ULL(1) << 36) #define SCTLR_BT_BIT (ULL(1) << 36) +#define SCTLR_ITFSB_BIT (ULL(1) << 37) +#define SCTLR_TCF0_SHIFT U(38) +#define SCTLR_TCF0_MASK ULL(3) + +/* Tag Check Faults in EL0 have no effect on the PE */ +#define SCTLR_TCF0_NO_EFFECT U(0) +/* Tag Check Faults in EL0 cause a synchronous exception */ +#define SCTLR_TCF0_SYNC U(1) +/* Tag Check Faults in EL0 are asynchronously accumulated */ +#define SCTLR_TCF0_ASYNC U(2) +/* + * Tag Check Faults in EL0 cause a synchronous exception on reads, + * and are asynchronously accumulated on writes + */ +#define SCTLR_TCF0_SYNCR_ASYNCW U(3) + +#define SCTLR_TCF_SHIFT U(40) +#define SCTLR_TCF_MASK ULL(3) + +/* Tag Check Faults in EL1 have no effect on the PE */ +#define SCTLR_TCF_NO_EFFECT U(0) +/* Tag Check Faults in EL1 cause a synchronous exception */ +#define SCTLR_TCF_SYNC U(1) +/* Tag Check Faults in EL1 are asynchronously accumulated */ +#define SCTLR_TCF_ASYNC U(2) +/* + * Tag Check Faults in EL1 cause a synchronous exception on reads, + * and are asynchronously accumulated on writes + */ +#define SCTLR_TCF_SYNCR_ASYNCW U(3) + +#define SCTLR_ATA0_BIT (ULL(1) << 42) +#define SCTLR_ATA_BIT (ULL(1) << 43) #define SCTLR_DSSBS_BIT (ULL(1) << 44) +#define SCTLR_TWEDEn_BIT (ULL(1) << 45) +#define SCTLR_TWEDEL_SHIFT U(46) +#define SCTLR_TWEDEL_MASK ULL(0xf) +#define SCTLR_EnASR_BIT (ULL(1) << 54) +#define SCTLR_EnAS0_BIT (ULL(1) << 55) +#define SCTLR_EnALS_BIT (ULL(1) << 56) +#define SCTLR_EPAN_BIT (ULL(1) << 57) #define SCTLR_RESET_VAL SCTLR_EL3_RES1 -/* CPACR_El1 definitions */ +/* CPACR_EL1 definitions */ #define CPACR_EL1_FPEN(x) ((x) << 20) -#define CPACR_EL1_FP_TRAP_EL0 U(0x1) -#define CPACR_EL1_FP_TRAP_ALL U(0x2) -#define CPACR_EL1_FP_TRAP_NONE U(0x3) +#define CPACR_EL1_FP_TRAP_EL0 UL(0x1) +#define CPACR_EL1_FP_TRAP_ALL UL(0x2) +#define CPACR_EL1_FP_TRAP_NONE UL(0x3) /* SCR definitions */ #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) -#define SCR_ATA_BIT (U(1) << 26) -#define SCR_FIEN_BIT (U(1) << 21) -#define SCR_EEL2_BIT (U(1) << 18) -#define SCR_API_BIT (U(1) << 17) -#define SCR_APK_BIT (U(1) << 16) -#define SCR_TWE_BIT (U(1) << 13) -#define SCR_TWI_BIT (U(1) << 12) -#define SCR_ST_BIT (U(1) << 11) -#define SCR_RW_BIT (U(1) << 10) -#define SCR_SIF_BIT (U(1) << 9) -#define SCR_HCE_BIT (U(1) << 8) -#define SCR_SMD_BIT (U(1) << 7) -#define SCR_EA_BIT (U(1) << 3) -#define SCR_FIQ_BIT (U(1) << 2) -#define SCR_IRQ_BIT (U(1) << 1) -#define SCR_NS_BIT (U(1) << 0) +#define SCR_TWEDEL_SHIFT U(30) +#define SCR_TWEDEL_MASK ULL(0xf) +#define SCR_TWEDEn_BIT (UL(1) << 29) +#define SCR_ECVEN_BIT (UL(1) << 28) +#define SCR_FGTEN_BIT (UL(1) << 27) +#define SCR_ATA_BIT (UL(1) << 26) +#define SCR_FIEN_BIT (UL(1) << 21) +#define SCR_EEL2_BIT (UL(1) << 18) +#define SCR_API_BIT (UL(1) << 17) +#define SCR_APK_BIT (UL(1) << 16) +#define SCR_TERR_BIT (UL(1) << 15) +#define SCR_TWE_BIT (UL(1) << 13) +#define SCR_TWI_BIT (UL(1) << 12) +#define SCR_ST_BIT (UL(1) << 11) +#define SCR_RW_BIT (UL(1) << 10) +#define SCR_SIF_BIT (UL(1) << 9) +#define SCR_HCE_BIT (UL(1) << 8) +#define SCR_SMD_BIT (UL(1) << 7) +#define SCR_EA_BIT (UL(1) << 3) +#define SCR_FIQ_BIT (UL(1) << 2) +#define SCR_IRQ_BIT (UL(1) << 1) +#define SCR_NS_BIT (UL(1) << 0) #define SCR_VALID_BIT_MASK U(0x2f8f) #define SCR_RESET_VAL SCR_RES1_BITS /* MDCR_EL3 definitions */ +#define MDCR_MTPME_BIT (ULL(1) << 28) #define MDCR_SCCD_BIT (ULL(1) << 23) #define MDCR_SPME_BIT (ULL(1) << 17) #define MDCR_SDD_BIT (ULL(1) << 16) @@ -320,6 +446,7 @@ #define MDCR_EL3_RESET_VAL ULL(0x0) /* MDCR_EL2 definitions */ +#define MDCR_EL2_MTPME (U(1) << 28) #define MDCR_EL2_HLP (U(1) << 26) #define MDCR_EL2_HCCD (U(1) << 23) #define MDCR_EL2_TTRF (U(1) << 19) @@ -354,6 +481,7 @@ /* HCR definitions */ #define HCR_API_BIT (ULL(1) << 41) #define HCR_APK_BIT (ULL(1) << 40) +#define HCR_E2H_BIT (ULL(1) << 34) #define HCR_TGE_BIT (ULL(1) << 27) #define HCR_RW_SHIFT U(31) #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) @@ -425,6 +553,9 @@ #define SPSR_M_AARCH64 U(0x0) #define SPSR_M_AARCH32 U(0x1) +#define SPSR_EL_SHIFT U(2) +#define SPSR_EL_WIDTH U(2) + #define SPSR_SSBS_BIT_AARCH64 BIT_64(12) #define SPSR_SSBS_BIT_AARCH32 BIT_64(23) @@ -530,6 +661,7 @@ #define MODE_EL_SHIFT U(0x2) #define MODE_EL_MASK U(0x3) +#define MODE_EL_WIDTH U(0x2) #define MODE_EL3 U(0x3) #define MODE_EL2 U(0x2) #define MODE_EL1 U(0x1) @@ -597,6 +729,10 @@ #define CNTP_CTL_IMASK_MASK U(1) #define CNTP_CTL_ISTATUS_MASK U(1) +/* Physical timer control macros */ +#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) +#define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) + /* Exception Syndrome register bits and bobs */ #define ESR_EC_SHIFT U(26) #define ESR_EC_MASK U(0x3f) @@ -836,9 +972,14 @@ #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 +/* AMCFGR_EL0 definitions */ +#define AMCFGR_EL0_NCG_SHIFT U(28) +#define AMCFGR_EL0_NCG_MASK U(0xf) +#define AMCFGR_EL0_N_SHIFT U(0) +#define AMCFGR_EL0_N_MASK U(0xff) + /* AMCGCR_EL0 definitions */ #define AMCGCR_EL0_CG1NC_SHIFT U(8) -#define AMCGCR_EL0_CG1NC_LENGTH U(8) #define AMCGCR_EL0_CG1NC_MASK U(0xff) /* MPAM register definitions */ @@ -912,4 +1053,14 @@ #define RGSR_EL1 S3_0_C1_C0_5 #define GCR_EL1 S3_0_C1_C0_6 +/******************************************************************************* + * Definitions for DynamicIQ Shared Unit registers + ******************************************************************************/ +#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 + +/* CLUSTERPWRDN_EL1 register definitions */ +#define DSU_CLUSTER_PWR_OFF 0 +#define DSU_CLUSTER_PWR_ON 1 +#define DSU_CLUSTER_PWR_MASK U(1) + #endif /* ARCH_H */ diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 0491f48c6..671b3dc60 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -52,4 +52,51 @@ static inline unsigned int get_armv8_5_mte_support(void) ID_AA64PFR1_EL1_MTE_MASK); } +static inline bool is_armv8_4_sel2_present(void) +{ + return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SEL2_SHIFT) & + ID_AA64PFR0_SEL2_MASK) == 1ULL; +} + +static inline bool is_armv8_6_twed_present(void) +{ + return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_TWED_SHIFT) & + ID_AA64MMFR1_EL1_TWED_MASK) == ID_AA64MMFR1_EL1_TWED_SUPPORTED); +} + +static inline bool is_armv8_6_fgt_present(void) +{ + return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) & + ID_AA64MMFR0_EL1_FGT_MASK) == ID_AA64MMFR0_EL1_FGT_SUPPORTED; +} + +static inline unsigned long int get_armv8_6_ecv_support(void) +{ + return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_ECV_SHIFT) & + ID_AA64MMFR0_EL1_ECV_MASK); +} + +static inline bool is_armv8_5_rng_present(void) +{ + return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_RNDR_SHIFT) & + ID_AA64ISAR0_RNDR_MASK); +} + +/* + * Return MPAM version: + * + * 0x00: None Armv8.0 or later + * 0x01: v0.1 Armv8.4 or later + * 0x10: v1.0 Armv8.2 or later + * 0x11: v1.1 Armv8.4 or later + * + */ +static inline unsigned int get_mpam_version(void) +{ + return (unsigned int)((((read_id_aa64pfr0_el1() >> + ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | + ((read_id_aa64pfr1_el1() >> + ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); +} + #endif /* ARCH_FEATURES_H */ diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index c60f2e8f7..7fafafc5a 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,11 +69,18 @@ static inline void _op(void) \ __asm__ (#_op); \ } +/* Define function for system instruction with register parameter */ +#define DEFINE_SYSOP_PARAM_FUNC(_op) \ +static inline void _op(uint64_t v) \ +{ \ + __asm__ (#_op " %0" : : "r" (v)); \ +} + /* Define function for system instruction with type specifier */ #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ static inline void _op ## _type(void) \ { \ - __asm__ (#_op " " #_type); \ + __asm__ (#_op " " #_type : : : "memory"); \ } /* Define function for system instruction with register parameter */ @@ -211,9 +218,15 @@ DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r) DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r) DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) +/******************************************************************************* + * Strip Pointer Authentication Code + ******************************************************************************/ +DEFINE_SYSOP_PARAM_FUNC(xpaci) + void flush_dcache_range(uintptr_t addr, size_t size); void clean_dcache_range(uintptr_t addr, size_t size); void inv_dcache_range(uintptr_t addr, size_t size); +bool is_dcache_enabled(void); void dcsw_op_louis(u_register_t op_type); void dcsw_op_all(u_register_t op_type); @@ -232,6 +245,7 @@ void disable_mmu_icache_el3(void); DEFINE_SYSREG_RW_FUNCS(par_el1) DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1) DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1) @@ -345,6 +359,7 @@ void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, DEFINE_SYSREG_READ_FUNC(midr_el1) DEFINE_SYSREG_READ_FUNC(mpidr_el1) DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64mmfr1_el1) DEFINE_SYSREG_RW_FUNCS(scr_el3) DEFINE_SYSREG_RW_FUNCS(hcr_el2) @@ -468,7 +483,8 @@ DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) -DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0) +DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0) +DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0) DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) @@ -507,6 +523,13 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) +/* Armv8.5 FEAT_RNG Registers */ +DEFINE_SYSREG_READ_FUNC(rndr) +DEFINE_SYSREG_READ_FUNC(rndrrs) + +/* DynamIQ Shared Unit power management */ +DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1) + #define IS_IN_EL(x) \ (GET_EL(read_CurrentEl()) == MODE_EL##x) @@ -519,6 +542,23 @@ static inline unsigned int get_current_el(void) return GET_EL(read_CurrentEl()); } +static inline unsigned int get_current_el_maybe_constant(void) +{ +#if defined(IMAGE_AT_EL1) + return 1; +#elif defined(IMAGE_AT_EL2) + return 2; /* no use-case in TF-A */ +#elif defined(IMAGE_AT_EL3) + return 3; +#else + /* + * If we do not know which exception level this is being built for + * (e.g. built for library), fall back to run-time detection. + */ + return get_current_el(); +#endif +} + /* * Check if an EL is implemented from AA64PFR0 register fields. */ @@ -552,4 +592,27 @@ static inline uint64_t el_implemented(unsigned int el) #define read_cpacr() read_cpacr_el1() #define write_cpacr(_v) write_cpacr_el1(_v) +#define read_clusterpwrdn() read_clusterpwrdn_el1() +#define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v) + +#if ERRATA_SPECULATIVE_AT +/* + * Assuming SCTLR.M bit is already enabled + * 1. Enable page table walk by clearing TCR_EL1.EPDx bits + * 2. Execute AT instruction for lower EL1/0 + * 3. Disable page table walk by setting TCR_EL1.EPDx bits + */ +#define AT(_at_inst, _va) \ +{ \ + assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \ + write_tcr_el1(read_tcr_el1() & ~(TCR_EPD0_BIT | TCR_EPD1_BIT)); \ + isb(); \ + _at_inst(_va); \ + write_tcr_el1(read_tcr_el1() | (TCR_EPD0_BIT | TCR_EPD1_BIT)); \ + isb(); \ +} +#else +#define AT(_at_inst, _va) _at_inst(_va); +#endif + #endif /* ARCH_HELPERS_H */ diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S index a7d5a3dd6..cbb9f0be8 100644 --- a/include/arch/aarch64/asm_macros.S +++ b/include/arch/aarch64/asm_macros.S @@ -220,11 +220,16 @@ /* * Macro for mitigating against speculative execution beyond ERET. + * If possible use Speculation Barrier instruction defined in ARMv8.5 */ .macro exception_return eret - dsb nsh +#if ARM_ARCH_AT_LEAST(8, 5) + sb +#else + dsb nsh isb +#endif .endm #endif /* ASM_MACROS_S */ diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index 156b18a4f..f75998351 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,8 @@ #include <arch.h> #include <asm_macros.S> +#include <context.h> +#include <lib/xlat_tables/xlat_tables_defs.h> /* * Helper macro to initialise EL3 registers we care about. @@ -275,6 +277,10 @@ isb .endif /* _init_sctlr */ +#if DISABLE_MTPMU + bl mtpmu_disable +#endif + .if \_warm_boot_mailbox /* ------------------------------------------------------------- * This code will be executed for both warm and cold resets. @@ -303,7 +309,7 @@ */ pie_fixup: ldr x0, =pie_fixup - and x0, x0, #~(PAGE_SIZE - 1) + and x0, x0, #~(PAGE_SIZE_MASK) mov_imm x1, \_pie_fixup_size add x1, x1, x0 bl fixup_gdt_reloc @@ -442,4 +448,42 @@ #endif .endm + .macro apply_at_speculative_wa +#if ERRATA_SPECULATIVE_AT + /* + * Explicitly save x30 so as to free up a register and to enable + * branching and also, save x29 which will be used in the called + * function + */ + stp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] + bl save_and_update_ptw_el1_sys_regs + ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] +#endif + .endm + + .macro restore_ptw_el1_sys_regs +#if ERRATA_SPECULATIVE_AT + /* ----------------------------------------------------------- + * In case of ERRATA_SPECULATIVE_AT, must follow below order + * to ensure that page table walk is not enabled until + * restoration of all EL1 system registers. TCR_EL1 register + * should be updated at the end which restores previous page + * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB + * ensures that CPU does below steps in order. + * + * 1. Ensure all other system registers are written before + * updating SCTLR_EL1 using ISB. + * 2. Restore SCTLR_EL1 register. + * 3. Ensure SCTLR_EL1 written successfully using ISB. + * 4. Restore TCR_EL1 register. + * ----------------------------------------------------------- + */ + isb + ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1] + msr sctlr_el1, x28 + isb + msr tcr_el1, x29 +#endif + .endm + #endif /* EL3_COMMON_MACROS_S */ diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h index d81f43404..21d3ae7b7 100644 --- a/include/bl1/bl1.h +++ b/include/bl1/bl1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,8 +26,8 @@ /* * BL1 SMC version */ -#define BL1_SMC_MAJOR_VER 0x0 -#define BL1_SMC_MINOR_VER 0x1 +#define BL1_SMC_MAJOR_VER UL(0x0) +#define BL1_SMC_MINOR_VER UL(0x1) /* * Defines for FWU SMC function ids. @@ -67,16 +67,16 @@ struct entry_point_info; -register_t bl1_smc_wrapper(uint32_t smc_fid, +u_register_t bl1_smc_wrapper(uint32_t smc_fid, void *cookie, void *handle, unsigned int flags); -register_t bl1_smc_handler(unsigned int smc_fid, - register_t x1, - register_t x2, - register_t x3, - register_t x4, +u_register_t bl1_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, void *cookie, void *handle, unsigned int flags); diff --git a/include/bl32/payloads/tlk.h b/include/bl32/payloads/tlk.h index ce8e3e890..290f32923 100644 --- a/include/bl32/payloads/tlk.h +++ b/include/bl32/payloads/tlk.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,10 +24,13 @@ #define TLK_SS_REGISTER_HANDLER TLK_TOS_YIELD_FID(0x3) #define TLK_REGISTER_NS_DRAM_RANGES TLK_TOS_YIELD_FID(0x4) #define TLK_SET_ROOT_OF_TRUST TLK_TOS_YIELD_FID(0x5) +#define TLK_SET_BL_VERSION TLK_TOS_YIELD_FID(0x6) +#define TLK_LOCK_BL_INTERFACE TLK_TOS_YIELD_FID(0x7) +#define TLK_BL_RPMB_SERVICE TLK_TOS_YIELD_FID(0x8) #define TLK_RESUME_FID TLK_TOS_YIELD_FID(0x100) #define TLK_SYSTEM_SUSPEND TLK_TOS_YIELD_FID(0xE001) #define TLK_SYSTEM_RESUME TLK_TOS_YIELD_FID(0xE002) -#define TLK_SYSTEM_OFF TLK_TOS_YIELD_FID(0xE003) +#define TLK_IRQ_FIRED TLK_TOS_YIELD_FID(0xE004) /* * SMC function IDs that TLK uses to signal various forms of completions @@ -38,7 +42,7 @@ #define TLK_VA_TRANSLATE (0x32000004 | (ULL(1) << 31)) #define TLK_SUSPEND_DONE (0x32000005 | (ULL(1) << 31)) #define TLK_RESUME_DONE (0x32000006 | (ULL(1) << 31)) -#define TLK_SYSTEM_OFF_DONE (0x32000007 | (ULL(1) << 31)) +#define TLK_IRQ_DONE (0x32000008 | (ULL(1) << 31)) /* * Trusted Application specific function IDs diff --git a/include/common/bl_common.ld.h b/include/common/bl_common.ld.h new file mode 100644 index 000000000..ab3391aa2 --- /dev/null +++ b/include/common/bl_common.ld.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BL_COMMON_LD_H +#define BL_COMMON_LD_H + +#include <platform_def.h> + +#ifdef __aarch64__ +#define STRUCT_ALIGN 8 +#define BSS_ALIGN 16 +#else +#define STRUCT_ALIGN 4 +#define BSS_ALIGN 8 +#endif + +#ifndef DATA_ALIGN +#define DATA_ALIGN 1 +#endif + +#define CPU_OPS \ + . = ALIGN(STRUCT_ALIGN); \ + __CPU_OPS_START__ = .; \ + KEEP(*(cpu_ops)) \ + __CPU_OPS_END__ = .; + +#define PARSER_LIB_DESCS \ + . = ALIGN(STRUCT_ALIGN); \ + __PARSER_LIB_DESCS_START__ = .; \ + KEEP(*(.img_parser_lib_descs)) \ + __PARSER_LIB_DESCS_END__ = .; + +#define RT_SVC_DESCS \ + . = ALIGN(STRUCT_ALIGN); \ + __RT_SVC_DESCS_START__ = .; \ + KEEP(*(rt_svc_descs)) \ + __RT_SVC_DESCS_END__ = .; + +#define PMF_SVC_DESCS \ + . = ALIGN(STRUCT_ALIGN); \ + __PMF_SVC_DESCS_START__ = .; \ + KEEP(*(pmf_svc_descs)) \ + __PMF_SVC_DESCS_END__ = .; + +#define FCONF_POPULATOR \ + . = ALIGN(STRUCT_ALIGN); \ + __FCONF_POPULATOR_START__ = .; \ + KEEP(*(.fconf_populator)) \ + __FCONF_POPULATOR_END__ = .; + +/* + * Keep the .got section in the RO section as it is patched prior to enabling + * the MMU and having the .got in RO is better for security. GOT is a table of + * addresses so ensure pointer size alignment. + */ +#define GOT \ + . = ALIGN(STRUCT_ALIGN); \ + __GOT_START__ = .; \ + *(.got) \ + __GOT_END__ = .; + +/* + * The base xlat table + * + * It is put into the rodata section if PLAT_RO_XLAT_TABLES=1, + * or into the bss section otherwise. + */ +#define BASE_XLAT_TABLE \ + . = ALIGN(16); \ + *(base_xlat_table) + +#if PLAT_RO_XLAT_TABLES +#define BASE_XLAT_TABLE_RO BASE_XLAT_TABLE +#define BASE_XLAT_TABLE_BSS +#else +#define BASE_XLAT_TABLE_RO +#define BASE_XLAT_TABLE_BSS BASE_XLAT_TABLE +#endif + +#define RODATA_COMMON \ + RT_SVC_DESCS \ + FCONF_POPULATOR \ + PMF_SVC_DESCS \ + PARSER_LIB_DESCS \ + CPU_OPS \ + GOT \ + BASE_XLAT_TABLE_RO + +/* + * .data must be placed at a lower address than the stacks if the stack + * protector is enabled. Alternatively, the .data.stack_protector_canary + * section can be placed independently of the main .data section. + */ +#define DATA_SECTION \ + .data . : ALIGN(DATA_ALIGN) { \ + __DATA_START__ = .; \ + *(SORT_BY_ALIGNMENT(.data*)) \ + __DATA_END__ = .; \ + } + +/* + * .rela.dyn needs to come after .data for the read-elf utility to parse + * this section correctly. + */ +#define RELA_SECTION \ + .rela.dyn : ALIGN(STRUCT_ALIGN) { \ + __RELA_START__ = .; \ + *(.rela*) \ + __RELA_END__ = .; \ + } + +#if !(defined(IMAGE_BL31) && RECLAIM_INIT_CODE) +#define STACK_SECTION \ + stacks (NOLOAD) : { \ + __STACKS_START__ = .; \ + *(tzfw_normal_stacks) \ + __STACKS_END__ = .; \ + } +#endif + +/* + * If BL doesn't use any bakery lock then __PERCPU_BAKERY_LOCK_SIZE__ + * will be zero. For this reason, the only two valid values for + * __PERCPU_BAKERY_LOCK_SIZE__ are 0 or the platform defined value + * PLAT_PERCPU_BAKERY_LOCK_SIZE. + */ +#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE +#define BAKERY_LOCK_SIZE_CHECK \ + ASSERT((__PERCPU_BAKERY_LOCK_SIZE__ == 0) || \ + (__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE), \ + "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); +#else +#define BAKERY_LOCK_SIZE_CHECK +#endif + +/* + * Bakery locks are stored in normal .bss memory + * + * Each lock's data is spread across multiple cache lines, one per CPU, + * but multiple locks can share the same cache line. + * The compiler will allocate enough memory for one CPU's bakery locks, + * the remaining cache lines are allocated by the linker script + */ +#if !USE_COHERENT_MEM +#define BAKERY_LOCK_NORMAL \ + . = ALIGN(CACHE_WRITEBACK_GRANULE); \ + __BAKERY_LOCK_START__ = .; \ + __PERCPU_BAKERY_LOCK_START__ = .; \ + *(bakery_lock) \ + . = ALIGN(CACHE_WRITEBACK_GRANULE); \ + __PERCPU_BAKERY_LOCK_END__ = .; \ + __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); \ + . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); \ + __BAKERY_LOCK_END__ = .; \ + BAKERY_LOCK_SIZE_CHECK +#else +#define BAKERY_LOCK_NORMAL +#endif + +/* + * Time-stamps are stored in normal .bss memory + * + * The compiler will allocate enough memory for one CPU's time-stamps, + * the remaining memory for other CPUs is allocated by the + * linker script + */ +#define PMF_TIMESTAMP \ + . = ALIGN(CACHE_WRITEBACK_GRANULE); \ + __PMF_TIMESTAMP_START__ = .; \ + KEEP(*(pmf_timestamp_array)) \ + . = ALIGN(CACHE_WRITEBACK_GRANULE); \ + __PMF_PERCPU_TIMESTAMP_END__ = .; \ + __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); \ + . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); \ + __PMF_TIMESTAMP_END__ = .; + + +/* + * The .bss section gets initialised to 0 at runtime. + * Its base address has bigger alignment for better performance of the + * zero-initialization code. + */ +#define BSS_SECTION \ + .bss (NOLOAD) : ALIGN(BSS_ALIGN) { \ + __BSS_START__ = .; \ + *(SORT_BY_ALIGNMENT(.bss*)) \ + *(COMMON) \ + BAKERY_LOCK_NORMAL \ + PMF_TIMESTAMP \ + BASE_XLAT_TABLE_BSS \ + __BSS_END__ = .; \ + } + +/* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section. The tables are initialized to zero by the translation + * tables library. + */ +#define XLAT_TABLE_SECTION \ + xlat_table (NOLOAD) : { \ + *(xlat_table) \ + } + +#endif /* BL_COMMON_LD_H */ diff --git a/include/common/debug.h b/include/common/debug.h index 245e69865..ed0e8bf97 100644 --- a/include/common/debug.h +++ b/include/common/debug.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -91,6 +91,7 @@ #if ENABLE_BACKTRACE void backtrace(const char *cookie); +const char *get_el_str(unsigned int el); #else #define backtrace(x) #endif @@ -100,7 +101,7 @@ void __dead2 do_panic(void); #define panic() \ do { \ backtrace(__func__); \ - (void)console_flush(); \ + console_flush(); \ do_panic(); \ } while (false) diff --git a/include/common/fdt_fixup.h b/include/common/fdt_fixup.h index 0248de9cf..2e9d49d53 100644 --- a/include/common/fdt_fixup.h +++ b/include/common/fdt_fixup.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,5 +11,9 @@ int dt_add_psci_node(void *fdt); int dt_add_psci_cpu_enable_methods(void *fdt); int fdt_add_reserved_memory(void *dtb, const char *node_name, uintptr_t base, size_t size); +int fdt_add_cpus_node(void *dtb, unsigned int afflv0, + unsigned int afflv1, unsigned int afflv2); +int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores, + unsigned int gicr_frame_size); #endif /* FDT_FIXUP_H */ diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h index f467958b7..a571092e3 100644 --- a/include/common/fdt_wrappers.h +++ b/include/common/fdt_wrappers.h @@ -9,13 +9,19 @@ #ifndef FDT_WRAPPERS_H #define FDT_WRAPPERS_H +#include <libfdt_env.h> + /* Number of cells, given total length in bytes. Each cell is 4 bytes long */ #define NCELLS(len) ((len) / 4U) -int fdtw_read_cells(const void *dtb, int node, const char *prop, - unsigned int cells, void *value); -int fdtw_read_array(const void *dtb, int node, const char *prop, - unsigned int cells, void *value); +int fdt_read_uint32(const void *dtb, int node, const char *prop_name, + uint32_t *value); +uint32_t fdt_read_uint32_default(const void *dtb, int node, + const char *prop_name, uint32_t dflt_value); +int fdt_read_uint64(const void *dtb, int node, const char *prop_name, + uint64_t *value); +int fdt_read_uint32_array(const void *dtb, int node, const char *prop_name, + unsigned int cells, uint32_t *value); int fdtw_read_string(const void *dtb, int node, const char *prop, char *str, size_t size); int fdtw_write_inplace_cells(void *dtb, int node, const char *prop, @@ -24,5 +30,20 @@ int fdtw_read_bytes(const void *dtb, int node, const char *prop, unsigned int length, void *value); int fdtw_write_inplace_bytes(void *dtb, int node, const char *prop, unsigned int length, const void *data); +int fdt_get_reg_props_by_index(const void *dtb, int node, int index, + uintptr_t *base, size_t *size); +int fdt_get_reg_props_by_name(const void *dtb, int node, const char *name, + uintptr_t *base, size_t *size); +int fdt_get_stdout_node_offset(const void *dtb); + +uint64_t fdtw_translate_address(const void *dtb, int bus_node, + uint64_t base_address); + +static inline uint32_t fdt_blob_size(const void *dtb) +{ + const uint32_t *dtb_header = dtb; + + return fdt32_to_cpu(dtb_header[1]); +} #endif /* FDT_WRAPPERS_H */ diff --git a/include/common/nv_cntr_ids.h b/include/common/nv_cntr_ids.h new file mode 100644 index 000000000..a15c431d0 --- /dev/null +++ b/include/common/nv_cntr_ids.h @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define TRUSTED_NV_CTR_ID U(0) +#define NON_TRUSTED_NV_CTR_ID U(1) +#define MAX_NV_CTR_IDS U(2) diff --git a/include/common/tbbr/cot_def.h b/include/common/tbbr/cot_def.h index 33350a0d3..6ce7f80c1 100644 --- a/include/common/tbbr/cot_def.h +++ b/include/common/tbbr/cot_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,7 +8,44 @@ #define COT_DEF_H /* TBBR CoT definitions */ - +#if defined(SPD_spmd) +#define COT_MAX_VERIFIED_PARAMS 8 +#else #define COT_MAX_VERIFIED_PARAMS 4 +#endif + +/* + * Maximum key and hash sizes (in DER format). + * + * Both RSA and ECDSA keys may be used at the same time. In this case, the key + * buffers must be big enough to hold either. As RSA keys are bigger than ECDSA + * ones for all key sizes we support, they impose the minimum size of these + * buffers. + */ +#if TF_MBEDTLS_USE_RSA +#if TF_MBEDTLS_KEY_SIZE == 1024 +#define PK_DER_LEN 162 +#elif TF_MBEDTLS_KEY_SIZE == 2048 +#define PK_DER_LEN 294 +#elif TF_MBEDTLS_KEY_SIZE == 3072 +#define PK_DER_LEN 422 +#elif TF_MBEDTLS_KEY_SIZE == 4096 +#define PK_DER_LEN 550 +#else +#error "Invalid value for TF_MBEDTLS_KEY_SIZE" +#endif +#else /* Only using ECDSA keys. */ +#define PK_DER_LEN 91 +#endif + +#if TF_MBEDTLS_HASH_ALG_ID == TF_MBEDTLS_SHA256 +#define HASH_DER_LEN 51 +#elif TF_MBEDTLS_HASH_ALG_ID == TF_MBEDTLS_SHA384 +#define HASH_DER_LEN 67 +#elif TF_MBEDTLS_HASH_ALG_ID == TF_MBEDTLS_SHA512 +#define HASH_DER_LEN 83 +#else +#error "Invalid value for TF_MBEDTLS_HASH_ALG_ID" +#endif #endif /* COT_DEF_H */ diff --git a/include/common/tbbr/tbbr_img_def.h b/include/common/tbbr/tbbr_img_def.h index 1701995a7..bd125e672 100644 --- a/include/common/tbbr/tbbr_img_def.h +++ b/include/common/tbbr/tbbr_img_def.h @@ -9,4 +9,21 @@ #include <export/common/tbbr/tbbr_img_def_exp.h> +#if defined(SPD_spmd) +#define SIP_SP_CONTENT_CERT_ID MAX_IMAGE_IDS +#define PLAT_SP_CONTENT_CERT_ID (MAX_IMAGE_IDS + 1) +#define SP_PKG1_ID (MAX_IMAGE_IDS + 2) +#define SP_PKG2_ID (MAX_IMAGE_IDS + 3) +#define SP_PKG3_ID (MAX_IMAGE_IDS + 4) +#define SP_PKG4_ID (MAX_IMAGE_IDS + 5) +#define SP_PKG5_ID (MAX_IMAGE_IDS + 6) +#define SP_PKG6_ID (MAX_IMAGE_IDS + 7) +#define SP_PKG7_ID (MAX_IMAGE_IDS + 8) +#define SP_PKG8_ID (MAX_IMAGE_IDS + 9) +#define MAX_SP_IDS U(8) +#define MAX_NUMBER_IDS (MAX_IMAGE_IDS + MAX_SP_IDS + U(2)) +#else +#define MAX_NUMBER_IDS MAX_IMAGE_IDS +#endif + #endif /* TBBR_IMG_DEF_H */ diff --git a/include/drivers/allwinner/axp.h b/include/drivers/allwinner/axp.h index 9c0035f96..222820b12 100644 --- a/include/drivers/allwinner/axp.h +++ b/include/drivers/allwinner/axp.h @@ -9,6 +9,10 @@ #include <stdint.h> +#define AXP20X_MODE_REG 0x3e +#define AXP20X_MODE_I2C 0x00 +#define AXP20X_MODE_RSB 0x7c + #define NA 0xff enum { diff --git a/include/drivers/amlogic/meson_console.h b/include/drivers/amlogic/meson_console.h index 70e3b0bd4..8d52d794b 100644 --- a/include/drivers/amlogic/meson_console.h +++ b/include/drivers/amlogic/meson_console.h @@ -9,17 +9,10 @@ #include <drivers/console.h> -#define CONSOLE_T_MESON_BASE CONSOLE_T_DRVDATA - #ifndef __ASSEMBLER__ #include <stdint.h> -typedef struct { - console_t console; - uintptr_t base; -} console_meson_t; - /* * Initialize a new meson console instance and register it with the console * framework. The |console| pointer must point to storage that will be valid @@ -30,7 +23,7 @@ typedef struct { * order to make this function future-proof. */ int console_meson_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - console_meson_t *console); + console_t *console); #endif /*__ASSEMBLER__*/ diff --git a/include/drivers/arm/cryptocell/713/bsv_api.h b/include/drivers/arm/cryptocell/713/bsv_api.h new file mode 100644 index 000000000..dc494735c --- /dev/null +++ b/include/drivers/arm/cryptocell/713/bsv_api.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BSV_API_H +#define _BSV_API_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! +@file +@brief This file contains the Boot Services APIs and definitions. + +@defgroup cc_bsv_api CryptoCell Boot Services APIs and definitions +@{ +@ingroup cc_bsv +*/ + +#include "cc_pal_types.h" +#include "cc_sec_defs.h" +#include "cc_boot_defs.h" + +/* Life cycle state definitions. */ +#define CC_BSV_CHIP_MANUFACTURE_LCS 0x0 /*!< The CM life-cycle state (LCS) value. */ +#define CC_BSV_DEVICE_MANUFACTURE_LCS 0x1 /*!< The DM life-cycle state (LCS) value. */ +#define CC_BSV_SECURE_LCS 0x5 /*!< The Secure life-cycle state (LCS) value. */ +#define CC_BSV_RMA_LCS 0x7 /*!< The RMA life-cycle state (LCS) value. */ +#define CC_BSV_INVALID_LCS 0xff /*!< The invalid life-cycle state (LCS) value. */ + +/*---------------------------- + TYPES +-----------------------------------*/ + +/*---------------------------- + PUBLIC FUNCTIONS +-----------------------------------*/ + + +/*! +@brief This function verifies the product and version numbers of the HW, and initializes it. + +\warning This function must be the first CryptoCell-7xx SBROM library API called. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvInit( + unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ + ); + +/*! +@brief This function retrieves the HW LCS and performs validity checks. + +If the LCS is RMA, it also sets the OTP secret keys to a fixed value. + +@note An error is returned if there is an invalid LCS. If this happens, your code must +completely disable the device. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvGetAndInitLcs( + unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ + uint32_t *pLcs /*!< [out] The value of the current LCS. */ + ); + +/*! +@brief This function retrieves the LCS from the NVM manager. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvLcsGet( + unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ + uint32_t *pLcs /*!< [out] The value of the current LCS. */ + ); + +/*! +@brief This function reads software revocation counter from OTP memory, according to the provided sw version index. +SW version is stored in NVM counter and represented by ones. Meaning seVersion=5 would be stored as binary 0b11111; +hence: + the maximal of trusted is 32 + the maximal of non-trusted is 224 + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvSwVersionGet( + unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ + CCSbSwVersionId_t id, /*!< [in] Enumeration defining the trusted/non-trusted counter to read. */ + uint32_t *swVersion /*!< [out] The value of the requested counter as read from OTP memory. */ + ); + +/*! +@brief This function sets the NVM counter according to swVersionID (trusted/non-trusted). + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvSwVersionSet( + unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ + CCSbSwVersionId_t id, /*!< [in] Enumeration defining the trusted/non-trusted counter to read. */ + uint32_t swVersion /*!< [in] New value of the counter to be programmed in OTP memory. */ + ); + +/*! +@brief This function sets the "fatal error" flag in the NVM manager, to disable the use of +any HW keys or security services. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvFatalErrorSet( + unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ + ); + +/*! +@brief This function retrieves the public key hash from OTP memory, according to the provided index. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvPubKeyHashGet( + unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ + CCSbPubKeyIndexType_t keyIndex, /*!< [in] Enumeration defining the key hash to retrieve: 128-bit HBK0, 128-bit HBK1, or 256-bit HBK. */ + uint32_t *hashedPubKey, /*!< [out] A buffer to contain the public key HASH. */ + uint32_t hashResultSizeWords /*!< [in] The size of the hash in 32-bit words: + - Must be 4 for 128-bit hash. + - Must be 8 for 256bit hash. */ + ); + +/*! +@brief This function permanently sets the RMA LCS for the ICV and the OEM. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvRMAModeEnable( + unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ + ); + +/*! +@brief This function is called by the ICV code, to disable the OEM code from changing the ICV RMA bit flag. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvICVRMAFlagBitLock( + unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ + ); + +/*! +@brief This function locks the defined ICV class keys from further usage. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvICVKeyLock( + unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ + CCBool_t isICVProvisioningKeyLock, /*!< [in] Should the provisioning key be locked. */ + CCBool_t isICVCodeEncKeyLock /*!< [in] Should the encryption key be locked. */ + ); + + +/*! +@brief This function retrieves the value of "secure disable" bit. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvSecureDisableGet( + unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ + CCBool_t *isSDEnabled /*!< [out] The value of the SD Enable bit. */ + ); + + +/*! +@brief This function derives the platform key (Kplt) from the Kpicv, and then decrypts the customer key (Kcst) +from the EKcst (burned in the OTP). The decryption is done only in Secure and RMA LCS mode using AES-ECB. +The customer ROM should invoke this function during early boot, prior to running any non-ROM code, only if Kcst exists. +The resulting Kcst is saved in a HW register. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvCustomerKeyDecrypt( + unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ + ); +#ifdef __cplusplus +} +#endif + +/*! +@brief This function derives the unique SoC_ID for the device, as hashed (Hbk || AES_CMAC (HUK)). + +@note SoC_ID is required to create debug certificates. + +The OEM or ICV must provide a method for a developer to discover the SoC_ID of a target +device without having to first enable debugging. +One suggested implementation is to have the device ROM code compute the SoC_ID and place +it in a specific location in the flash memory, from where it can be accessed by the developer. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvSocIDCompute( + unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ + CCHashResult_t hashResult /*!< [out] The derived SoC_ID. */ + ); + +#endif /* _BSV_API_H */ + +/** +@} + */ + diff --git a/include/drivers/arm/cryptocell/713/bsv_crypto_api.h b/include/drivers/arm/cryptocell/713/bsv_crypto_api.h new file mode 100644 index 000000000..1e6057931 --- /dev/null +++ b/include/drivers/arm/cryptocell/713/bsv_crypto_api.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BSV_CRYPTO_API_H +#define _BSV_CRYPTO_API_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! +@file +@brief This file contains the cryptographic ROM APIs of the Boot Services. + +@defgroup cc_bsv_crypto_api CryptoCell Boot Services cryptographic ROM APIs +@{ +@ingroup cc_bsv +*/ + +#include "cc_pal_types.h" +#include "cc_sec_defs.h" +#include "cc_address_defs.h" +#include "bsv_crypto_defs.h" + +/*---------------------------- + PUBLIC FUNCTIONS +-----------------------------------*/ + +/*! +@brief This function calculates the SHA-256 digest over contiguous memory +in an integrated operation. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvSha256( + unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ + uint8_t *pDataIn, /*!< [in] A pointer to the input buffer to be hashed. The buffer must be contiguous. */ + size_t dataSize, /*!< [in] The size of the data to be hashed, in bytes. */ + CCHashResult_t hashBuff /*!< [out] A pointer to a word-aligned 32-byte buffer. */ + ); + + +/*! +@brief This function allows you to calculate SHA256 digest of an image with decryption base on AES-CTR, +with HW or user key. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. (in this case, hashBuff will be returned clean, while the output data should be cleaned by the user). +*/ +CCError_t CC_BsvCryptoImageDecrypt( unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ + CCBsvflowMode_t flow, /*!< [in] The supported operations are: HASH, AES to HASH, AES and HASH. */ + CCBsvKeyType_t keyType, /*!< [in] The key type to use: Kce, Kceicv, or user key. */ + uint8_t *pUserKey, /*!< [in] A pointer to the user key buffer in case keyType is CC_BSV_USER_KEY. */ + size_t userKeySize, /*!< [in] The user key size in bytes (128bits) in case keyType is CC_BSV_USER_KEY. */ + uint8_t *pIvBuf, /*!< [in] A pointer to the IV / counter buffer. */ + uint8_t *pInputData, /*!< [in] A pointer to the input data. */ + uint8_t *pOutputData, /*!< [out] A pointer to the output buffer. (optional – should be null in case of hash only). */ + size_t dataSize, /*!< [in] The size of the input data in bytes. MUST be multiple of AES block size. */ + CCHashResult_t hashBuff /*!< [out] A pointer to a word-aligned 32-byte digest output buffer. */ + ); + +#ifdef __cplusplus +} +#endif + +#endif + +/** +@} + */ + diff --git a/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h b/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h new file mode 100644 index 000000000..406e1effb --- /dev/null +++ b/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BSV_CRYPTO_ASYM_API_H +#define _BSV_CRYPTO_ASYM_API_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! +@file +@brief This file contains the cryptographic Asymmetric ROM APIs of the Boot Services. + +@defgroup cc_bsv_crypto_asym_api CryptoCell Boot Services cryptographic Asymmetric ROM APIs +@{ +@ingroup cc_bsv +*/ + +#include "cc_pal_types.h" +#include "cc_pka_hw_plat_defs.h" +#include "cc_sec_defs.h" +#include "bsv_crypto_api.h" + +/*! Defines the workspace size in bytes needed for internal Asymmetric operations. */ +#define BSV_RSA_WORKSPACE_MIN_SIZE (4*BSV_CERT_RSA_KEY_SIZE_IN_BYTES +\ + 2*RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_BYTES) + +/*! Definition for the RSA public modulus array. */ +typedef uint32_t CCBsvNBuff_t[BSV_CERT_RSA_KEY_SIZE_IN_WORDS]; + +/*! Definition for the RSA Barrett mod tag array. */ +typedef uint32_t CCBsvNpBuff_t[RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_BYTES]; + +/*! Definition for the RSA signature array. */ +typedef uint32_t CCBsvSignature_t[BSV_CERT_RSA_KEY_SIZE_IN_WORDS]; + + +/*---------------------------- + PUBLIC FUNCTIONS +-----------------------------------*/ + +/*! +@brief This function performs the primitive operation of RSA, meaning exponent and modulus. + outBuff = (pInBuff ^ Exp) mod NBuff. ( Exp = 0x10001 ) + + The function supports 2k and 3K bit size of modulus, based on compile time define. + There are no restriction on pInBuff location, however its size must be equal to BSV_RSA_KEY_SIZE_IN_BYTES and its + value must be smaller than the modulus. + + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvRsaPrimVerify (unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ + CCBsvNBuff_t NBuff, /*!< [in] The modulus buffer big endian format. */ + CCBsvNpBuff_t NpBuff, /*!< [in] The barret tag buffer big endian format - optional. */ + uint32_t *pInBuff, /*!< [in] The DataIn buffer to be encrypted. */ + size_t inBuffSize, /*!< [in] The DataIn buffer size in bytes, must be BSV_RSA_KEY_SIZE_IN_BYTES. */ + CCBsvSignature_t pOutBuff, /*!< [out] The encrypted buffer in big endian format. */ + uint32_t *pWorkSpace, /*!< [in] The pointer to user allocated buffer for internal use. */ + size_t workBufferSize /*!< [in] The size in bytes of pWorkSpace, must be at-least BSV_RSA_WORKSPACE_MIN_SIZE. */ +); + + +/*! +@brief This function performs RSA PSS verify. + + The function should support 2k and 3K bit size of modulus, based on compile time define. + +@return \c CC_OK on success. +@return A non-zero value from bsv_error.h on failure. +*/ +CCError_t CC_BsvRsaPssVerify (unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ + CCBsvNBuff_t NBuff, /*!< [in] The modulus buffer big endian format. */ + CCBsvNpBuff_t NpBuff, /*!< [in] The barret tag buffer big endian format - optional. */ + CCBsvSignature_t signature, /*!< [in] The signature buffer to verify - big endian format. */ + CCHashResult_t hashedData, /*!< [in] The data-in buffer to be verified as sha256 digest. */ + uint32_t *pWorkSpace, /*!< [in] The pointer to user allocated buffer for internal use. */ + size_t workBufferSize, /*!< [in] The size in bytes of pWorkSpace, must be at-least BSV_RSA_WORKSPACE_MIN_SIZE. */ + CCBool_t *pIsVerified /*!< [out] The flag indicates whether the signature is verified or not. + If verified value will be CC_TRUE, otherwise CC_FALSE */ +); + + + +#ifdef __cplusplus +} +#endif + +#endif + +/** +@} + */ + diff --git a/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h b/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h new file mode 100644 index 000000000..9ea354deb --- /dev/null +++ b/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BSV_CRYPTO_DEFS_H +#define _BSV_CRYPTO_DEFS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! +@file +@brief This file contains the definitions of the cryptographic ROM APIs. + +@defgroup cc_bsv_crypto_defs CryptoCell Boot Services cryptographic ROM API definitions +@{ +@ingroup cc_bsv +*/ + +/*! AES supported HW key code table. */ +typedef enum { + + CC_BSV_USER_KEY = 0, /*!< Definition for a user key. */ + CC_BSV_HUK_KEY = 1, /*!< Definition for the HW unique key. */ + CC_BSV_RTL_KEY = 2, /*!< Definition for the RTL key. */ + CC_BSV_SESSION_KEY = 3, /*!< Definition for the Session key. */ + CC_BSV_CE_KEY = 4, /*!< Definition for the Kce. */ + CC_BSV_PLT_KEY = 5, /*!< Definition for the Platform key. */ + CC_BSV_KCST_KEY = 6, /*!< Definition for Kcst. */ + CC_BSV_ICV_PROV_KEY = 0xd, /*!< Definition for the Kpicv. */ + CC_BSV_ICV_CE_KEY = 0xe, /*!< Definition for the Kceicv. */ + CC_BSV_PROV_KEY = 0xf, /*!< Definition for the Kcp. */ + CC_BSV_END_OF_KEY_TYPE = INT32_MAX, /*!< Reserved. */ +}CCBsvKeyType_t; + +/*! AES directions. */ +typedef enum bsvAesDirection { + BSV_AES_DIRECTION_ENCRYPT = 0, /*!< Encrypt.*/ + BSV_AES_DIRECTION_DECRYPT = 1, /*!< Decrypt.*/ + BSV_AES_NUM_OF_ENCRYPT_MODES, /*!< The maximal number of operations. */ + BSV_AES_DIRECTION_RESERVE32B = INT32_MAX /*!< Reserved.*/ +}bsvAesDirection_t; + +/*! Definitions of the cryptographic flow supported as part of the Secure Boot. */ +typedef enum { + CC_BSV_CRYPTO_HASH_MODE = 0, /*!< Hash mode only. */ + CC_BSV_CRYPTO_AES_CTR_AND_HASH_MODE = 1, /*!< Data goes into the AES and Hash engines. */ + CC_BSV_CRYPTO_AES_CTR_TO_HASH_MODE = 2 /*!< Data goes into the AES and from the AES to the Hash engine. */ +}CCBsvflowMode_t; + +/*! CryptoImage HW completion sequence mode */ +typedef enum +{ + BSV_CRYPTO_COMPLETION_NO_WAIT = 0, /*!< The driver waits only before reading the output. */ + BSV_CRYPTO_COMPLETION_WAIT_UPON_END = 1 /*!< The driver waits after each chunk of data. */ +}bsvCryptoCompletionMode_t; + + +/*! AES-CMAC result size, in words. */ +#define CC_BSV_CMAC_RESULT_SIZE_IN_WORDS 4 /* 128b */ +/*! AES-CMAC result size, in bytes. */ +#define CC_BSV_CMAC_RESULT_SIZE_IN_BYTES 16 /* 128b */ +/*! AES-CCM 128bit key size, in bytes. */ +#define CC_BSV_CCM_KEY_SIZE_BYTES 16 +/*! AES-CCM 128bit key size, in words. */ +#define CC_BSV_CCM_KEY_SIZE_WORDS 4 +/*! AES-CCM NONCE size, in bytes. */ +#define CC_BSV_CCM_NONCE_SIZE_BYTES 12 + + +/*! AES-CMAC result buffer. */ +typedef uint32_t CCBsvCmacResult_t[CC_BSV_CMAC_RESULT_SIZE_IN_WORDS]; +/*! AES-CCM key buffer.*/ +typedef uint32_t CCBsvCcmKey_t[CC_BSV_CCM_KEY_SIZE_WORDS]; +/*! AES-CCM nonce buffer.*/ +typedef uint8_t CCBsvCcmNonce_t[CC_BSV_CCM_NONCE_SIZE_BYTES]; +/*! AES-CCM MAC buffer.*/ +typedef uint8_t CCBsvCcmMacRes_t[CC_BSV_CMAC_RESULT_SIZE_IN_BYTES]; + + +#ifdef __cplusplus +} +#endif + +#endif + +/** +@} + */ + diff --git a/include/drivers/arm/cryptocell/713/bsv_error.h b/include/drivers/arm/cryptocell/713/bsv_error.h new file mode 100644 index 000000000..4d72e60aa --- /dev/null +++ b/include/drivers/arm/cryptocell/713/bsv_error.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BSV_ERROR_H +#define _BSV_ERROR_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! +@file +@brief This file defines the error code types that are returned from the Boot Services APIs. + +@defgroup cc_bsv_error CryptoCell Boot Services error codes +@{ +@ingroup cc_bsv +*/ + +/*! Defines the base address for Boot Services errors. */ +#define CC_BSV_BASE_ERROR 0x0B000000 +/*! Defines the base address for Boot Services cryptographic errors. */ +#define CC_BSV_CRYPTO_ERROR 0x0C000000 + +/*! Illegal input parameter. */ +#define CC_BSV_ILLEGAL_INPUT_PARAM_ERR (CC_BSV_BASE_ERROR + 0x00000001) +/*! Illegal HUK value. */ +#define CC_BSV_ILLEGAL_HUK_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000002) +/*! Illegal Kcp value. */ +#define CC_BSV_ILLEGAL_KCP_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000003) +/*! Illegal Kce value. */ +#define CC_BSV_ILLEGAL_KCE_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000004) +/*! Illegal Kpicv value. */ +#define CC_BSV_ILLEGAL_KPICV_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000005) +/*! Illegal Kceicv value. */ +#define CC_BSV_ILLEGAL_KCEICV_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000006) +/*! Illegal EKcst value. */ +#define CC_BSV_ILLEGAL_EKCST_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000007) +/*! Hash boot key not programmed in the OTP. */ +#define CC_BSV_HASH_NOT_PROGRAMMED_ERR (CC_BSV_BASE_ERROR + 0x00000008) +/*! Illegal Hash boot key zero count in the OTP. */ +#define CC_BSV_HBK_ZERO_COUNT_ERR (CC_BSV_BASE_ERROR + 0x00000009) +/*! Illegal LCS. */ +#define CC_BSV_ILLEGAL_LCS_ERR (CC_BSV_BASE_ERROR + 0x0000000A) +/*! OTP write compare failure. */ +#define CC_BSV_OTP_WRITE_CMP_FAIL_ERR (CC_BSV_BASE_ERROR + 0x0000000B) +/*! OTP access error */ +#define CC_BSV_OTP_ACCESS_ERR (CC_BSV_BASE_ERROR + 0x0000000C) +/*! Erase key in OTP failed. */ +#define CC_BSV_ERASE_KEY_FAILED_ERR (CC_BSV_BASE_ERROR + 0x0000000D) +/*! Illegal PIDR. */ +#define CC_BSV_ILLEGAL_PIDR_ERR (CC_BSV_BASE_ERROR + 0x0000000E) +/*! Illegal CIDR. */ +#define CC_BSV_ILLEGAL_CIDR_ERR (CC_BSV_BASE_ERROR + 0x0000000F) +/*! Device failed to move to fatal error state. */ +#define CC_BSV_FAILED_TO_SET_FATAL_ERR (CC_BSV_BASE_ERROR + 0x00000010) +/*! Failed to set RMA LCS. */ +#define CC_BSV_FAILED_TO_SET_RMA_ERR (CC_BSV_BASE_ERROR + 0x00000011) +/*! Illegal RMA indication. */ +#define CC_BSV_ILLEGAL_RMA_INDICATION_ERR (CC_BSV_BASE_ERROR + 0x00000012) +/*! Boot Services version is not initialized. */ +#define CC_BSV_VER_IS_NOT_INITIALIZED_ERR (CC_BSV_BASE_ERROR + 0x00000013) +/*! APB secure mode is locked. */ +#define CC_BSV_APB_SECURE_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000014) +/*! APB privilege mode is locked. */ +#define CC_BSV_APB_PRIVILEG_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000015) +/*! Illegal operation. */ +#define CC_BSV_ILLEGAL_OPERATION_ERR (CC_BSV_BASE_ERROR + 0x00000016) +/*! Illegal asset size. */ +#define CC_BSV_ILLEGAL_ASSET_SIZE_ERR (CC_BSV_BASE_ERROR + 0x00000017) +/*! Illegal asset value. */ +#define CC_BSV_ILLEGAL_ASSET_VAL_ERR (CC_BSV_BASE_ERROR + 0x00000018) +/*! Kpicv is locked. */ +#define CC_BSV_KPICV_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000019) +/*! Illegal SW version. */ +#define CC_BSV_ILLEGAL_SW_VERSION_ERR (CC_BSV_BASE_ERROR + 0x0000001A) +/*! AO write operation. */ +#define CC_BSV_AO_WRITE_FAILED_ERR (CC_BSV_BASE_ERROR + 0x0000001B) +/*! Chip state is already initialized. */ +#define CC_BSV_CHIP_INITIALIZED_ERR (CC_BSV_BASE_ERROR + 0x0000001C) +/*! SP is not enabled. */ +#define CC_BSV_SP_NOT_ENABLED_ERR (CC_BSV_BASE_ERROR + 0x0000001D) +/*! Production secure provisioning - header fields. */ +#define CC_BSV_PROD_PKG_HEADER_ERR (CC_BSV_BASE_ERROR + 0x0000001E) +/*! Production secure provisioning - header MAC. */ +#define CC_BSV_PROD_PKG_HEADER_MAC_ERR (CC_BSV_BASE_ERROR + 0x0000001F) +/*! Overrun buffer or size. */ +#define CC_BSV_OVERRUN_ERR (CC_BSV_BASE_ERROR + 0x00000020) +/*! Kceicv is locked. */ +#define CC_BSV_KCEICV_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000021) +/*! Chip indication is CHIP_STATE_ERROR. */ +#define CC_BSV_CHIP_INDICATION_ERR (CC_BSV_BASE_ERROR + 0x00000022) +/*! Device is locked in fatal error state. */ +#define CC_BSV_FATAL_ERR_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000023) +/*! Device has security disable feature enabled. */ +#define CC_BSV_SECURE_DISABLE_ERROR (CC_BSV_BASE_ERROR + 0x00000024) +/*! Device has Kcst in disabled state */ +#define CC_BSV_KCST_DISABLE_ERROR (CC_BSV_BASE_ERROR + 0x00000025) + + +/*! Illegal data-in pointer. */ +#define CC_BSV_CRYPTO_INVALID_DATA_IN_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000001) +/*! Illegal data-out pointer. */ +#define CC_BSV_CRYPTO_INVALID_DATA_OUT_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000002) +/*! Illegal data size. */ +#define CC_BSV_CRYPTO_INVALID_DATA_SIZE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000003) +/*! Illegal key type. */ +#define CC_BSV_CRYPTO_INVALID_KEY_TYPE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000004) +/*! Illegal key size. */ +#define CC_BSV_CRYPTO_INVALID_KEY_SIZE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000005) +/*! Invalid key pointer. */ +#define CC_BSV_CRYPTO_INVALID_KEY_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000006) +/*! Illegal key DMA type. */ +#define CC_BSV_CRYPTO_INVALID_KEY_DMA_TYPE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000007) +/*! Illegal IV pointer. */ +#define CC_BSV_CRYPTO_INVALID_IV_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000008) +/*! Illegal cipher mode. */ +#define CC_BSV_CRYPTO_INVALID_CIPHER_MODE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000009) +/*! Illegal result buffer pointer. */ +#define CC_BSV_CRYPTO_INVALID_RESULT_BUFFER_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000A) +/*! Invalid DMA type. */ +#define CC_BSV_CRYPTO_INVALID_DMA_TYPE_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000B) +/*! Invalid in/out buffers overlapping. */ +#define CC_BSV_CRYPTO_DATA_OUT_DATA_IN_OVERLAP_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000C) +/*! Invalid KDF label size. */ +#define CC_BSV_CRYPTO_ILLEGAL_KDF_LABEL_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000D) +/*! Invalid KDF Context size. */ +#define CC_BSV_CRYPTO_ILLEGAL_KDF_CONTEXT_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000E) +/*! Invalid CCM key. */ +#define CC_BSV_CCM_INVALID_KEY_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000f) +/*! Invalid CCM Nonce. */ +#define CC_BSV_CCM_INVALID_NONCE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000010) +/*! Invalid CCM associated data. */ +#define CC_BSV_CCM_INVALID_ASSOC_DATA_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000011) +/*! Invalid CCM text data. */ +#define CC_BSV_CCM_INVALID_TEXT_DATA_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000012) +/*! Invalid CCM-MAC buffer. */ +#define CC_BSV_CCM_INVALID_MAC_BUF_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000013) +/*! CCM-MAC comparison failed. */ +#define CC_BSV_CCM_TAG_LENGTH_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000014) +/*! CCM-MAC comparison failed. */ +#define CC_BSV_CCM_MAC_INVALID_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000015) +/*! Illegal flow mode. */ +#define CC_BSV_CRYPTO_INVALID_FLOW_MODE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000016) + +#ifdef __cplusplus +} +#endif + +#endif + +/** +@} + */ + + + diff --git a/include/drivers/arm/cryptocell/713/cc_address_defs.h b/include/drivers/arm/cryptocell/713/cc_address_defs.h new file mode 100644 index 000000000..0abc15c70 --- /dev/null +++ b/include/drivers/arm/cryptocell/713/cc_address_defs.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CC_ADDRESS_DEFS_H +#define _CC_ADDRESS_DEFS_H + +/*! +@file +@brief This file contains general definitions. +*/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "cc_pal_types.h" + +/************************ Defines ******************************/ + +/** + * Address types within CC + */ +/*! Definition of DMA address type, can be 32 bits or 64 bits according to CryptoCell's HW. */ +typedef uint64_t CCDmaAddr_t; +/*! Definition of CryptoCell address type, can be 32 bits or 64 bits according to platform. */ +typedef uint64_t CCAddr_t; +/*! Definition of CC SRAM address type, can be 32 bits according to CryptoCell's HW. */ +typedef uint32_t CCSramAddr_t; + +/* + * CCSramAddr_t is being cast into pointer type which can be 64 bit. + */ +/*! Definition of MACRO that casts SRAM addresses to pointer types. */ +#define CCSramAddr2Ptr(sramAddr) ((uintptr_t)sramAddr) + +#ifdef __cplusplus +} +#endif + +#endif + +/** + @} + */ + + diff --git a/include/drivers/arm/cryptocell/713/cc_boot_defs.h b/include/drivers/arm/cryptocell/713/cc_boot_defs.h new file mode 100644 index 000000000..4d29a6d00 --- /dev/null +++ b/include/drivers/arm/cryptocell/713/cc_boot_defs.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CC_BOOT_DEFS_H +#define _CC_BOOT_DEFS_H + +/*! + @file + @brief This file contains general definitions of types and enums of Boot APIs. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*! Version counters value. */ +typedef enum { + + CC_SW_VERSION_TRUSTED = 0, /*!< Trusted counter. */ + CC_SW_VERSION_NON_TRUSTED, /*!< Non trusted counter. */ + CC_SW_VERSION_MAX = 0x7FFFFFFF /*!< Reserved */ +} CCSbSwVersionId_t; + +/*! The hash boot key definition. */ +typedef enum { + CC_SB_HASH_BOOT_KEY_0_128B = 0, /*!< Hbk0: 128-bit truncated SHA-256 digest of PubKB0. Used by ICV */ + CC_SB_HASH_BOOT_KEY_1_128B = 1, /*!< Hbk1: 128-bit truncated SHA-256 digest of PubKB1. Used by OEM */ + CC_SB_HASH_BOOT_KEY_256B = 2, /*!< Hbk: 256-bit SHA-256 digest of public key. */ + CC_SB_HASH_BOOT_NOT_USED = 0xF, /*!< Hbk is not used. */ + CC_SB_HASH_MAX_NUM = 0x7FFFFFFF, /*!< Reserved. */ +} CCSbPubKeyIndexType_t; + +/*! Chip state. */ +typedef enum { + CHIP_STATE_NOT_INITIALIZED = 0, /*! Chip is not initialized. */ + CHIP_STATE_TEST = 1, /*! Chip is in Production state. */ + CHIP_STATE_PRODUCTION = 2, /*! Chip is in Production state. */ + CHIP_STATE_ERROR = 3, /*! Chip is in Error state. */ +} CCBsvChipState_t; +#ifdef __cplusplus +} +#endif + +#endif /*_CC_BOOT_DEFS_H */ + +/** +@} + */ diff --git a/include/drivers/arm/cryptocell/713/cc_pal_types.h b/include/drivers/arm/cryptocell/713/cc_pal_types.h new file mode 100644 index 000000000..4ab3960d3 --- /dev/null +++ b/include/drivers/arm/cryptocell/713/cc_pal_types.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CC_PAL_TYPES_H +#define CC_PAL_TYPES_H + +/*! +@file +@brief This file contains platform-dependent definitions and types of the PAL layer. + +@defgroup cc_pal_types CryptoCell platform-dependent PAL layer definitions and types +@{ +@ingroup cc_pal + + @{ + @ingroup cc_pal + @} +*/ + +#include "cc_pal_types_plat.h" + +/*! Definition of Boolean type.*/ +typedef enum { + /*! Boolean false.*/ + CC_FALSE = 0, + /*! Boolean true.*/ + CC_TRUE = 1 +} CCBool_t; + +/*! Success. */ +#define CC_SUCCESS 0UL +/*! Failure. */ +#define CC_FAIL 1UL + +/*! Success (OK). */ +#define CC_OK 0 + +/*! This macro handles unused parameters in the code, to avoid compilation warnings. */ +#define CC_UNUSED_PARAM(prm) ((void)prm) + +/*! The maximal uint32 value.*/ +#define CC_MAX_UINT32_VAL (0xFFFFFFFF) + + +/* Minimal and Maximal macros */ +#ifdef min +/*! Definition for minimal calculation. */ +#define CC_MIN(a,b) min( a , b ) +#else +/*! Definition for minimal calculation. */ +#define CC_MIN( a , b ) ( ( (a) < (b) ) ? (a) : (b) ) +#endif + +#ifdef max +/*! Definition for maximal calculation. */ +#define CC_MAX(a,b) max( a , b ) +#else +/*! Definition for maximal calculation.. */ +#define CC_MAX( a , b ) ( ( (a) > (b) ) ? (a) : (b) ) +#endif + +/*! This macro calculates the number of full Bytes from bits, where seven bits are one Byte. */ +#define CALC_FULL_BYTES(numBits) ((numBits)/CC_BITS_IN_BYTE + (((numBits) & (CC_BITS_IN_BYTE-1)) > 0)) +/*! This macro calculates the number of full 32-bit words from bits where 31 bits are one word. */ +#define CALC_FULL_32BIT_WORDS(numBits) ((numBits)/CC_BITS_IN_32BIT_WORD + (((numBits) & (CC_BITS_IN_32BIT_WORD-1)) > 0)) +/*! This macro calculates the number of full 32-bit words from Bytes where three Bytes are one word. */ +#define CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) ((sizeBytes)/CC_32BIT_WORD_SIZE + (((sizeBytes) & (CC_32BIT_WORD_SIZE-1)) > 0)) +/*! This macro calculates the number of full 32-bit words from 64-bits dwords. */ +#define CALC_32BIT_WORDS_FROM_64BIT_DWORD(sizeWords) (sizeWords * CC_32BIT_WORD_IN_64BIT_DWORD) +/*! This macro rounds up bits to 32-bit words. */ +#define ROUNDUP_BITS_TO_32BIT_WORD(numBits) (CALC_FULL_32BIT_WORDS(numBits) * CC_BITS_IN_32BIT_WORD) +/*! This macro rounds up bits to Bytes. */ +#define ROUNDUP_BITS_TO_BYTES(numBits) (CALC_FULL_BYTES(numBits) * CC_BITS_IN_BYTE) +/*! This macro rounds up bytes to 32-bit words. */ +#define ROUNDUP_BYTES_TO_32BIT_WORD(sizeBytes) (CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) * CC_32BIT_WORD_SIZE) +/*! This macro calculates the number Bytes from words. */ +#define CALC_WORDS_TO_BYTES(numwords) ((numwords)*CC_32BIT_WORD_SIZE) +/*! Definition of 1 KB in Bytes. */ +#define CC_1K_SIZE_IN_BYTES 1024 +/*! Definition of number of bits in a Byte. */ +#define CC_BITS_IN_BYTE 8 +/*! Definition of number of bits in a 32-bits word. */ +#define CC_BITS_IN_32BIT_WORD 32 +/*! Definition of number of Bytes in a 32-bits word. */ +#define CC_32BIT_WORD_SIZE 4 +/*! Definition of number of 32-bits words in a 64-bits dword. */ +#define CC_32BIT_WORD_IN_64BIT_DWORD 2 + + +#endif + +/** +@} + */ + + + diff --git a/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h new file mode 100644 index 000000000..984847217 --- /dev/null +++ b/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*! @file +@brief This file contains basic type definitions that are platform-dependent. +*/ +#ifndef _CC_PAL_TYPES_PLAT_H +#define _CC_PAL_TYPES_PLAT_H +/* Host specific types for standard (ISO-C99) compilant platforms */ + +#include <stddef.h> +#include <stdint.h> + +typedef uint32_t CCStatus; + +#define CCError_t CCStatus +#define CC_INFINITE 0xFFFFFFFF + +#define CEXPORT_C +#define CIMPORT_C + +#endif /*_CC_PAL_TYPES_PLAT_H*/ diff --git a/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h b/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h new file mode 100644 index 000000000..1a1bce0ab --- /dev/null +++ b/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CC_PKA_HW_PLAT_DEFS_H +#define _CC_PKA_HW_PLAT_DEFS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#include "cc_pal_types.h" +/*! +@file +@brief Contains the enums and definitions that are used in the PKA code (definitions that are platform dependent). +*/ + +/*! The size of the PKA engine word. */ +#define CC_PKA_WORD_SIZE_IN_BITS 128 + +/*! The maximal supported size of modulus in RSA in bits. */ +#define CC_RSA_MAX_VALID_KEY_SIZE_VALUE_IN_BITS 4096 +/*! The maximal supported size of key-generation in RSA in bits. */ +#define CC_RSA_MAX_KEY_GENERATION_HW_SIZE_BITS 4096 + +/*! Secure boot/debug certificate RSA public modulus key size in bits. */ +#if (KEY_SIZE == 3072) + #define BSV_CERT_RSA_KEY_SIZE_IN_BITS 3072 +#else + #define BSV_CERT_RSA_KEY_SIZE_IN_BITS 2048 +#endif +/*! Secure boot/debug certificate RSA public modulus key size in bytes. */ +#define BSV_CERT_RSA_KEY_SIZE_IN_BYTES (BSV_CERT_RSA_KEY_SIZE_IN_BITS/CC_BITS_IN_BYTE) +/*! Secure boot/debug certificate RSA public modulus key size in words. */ +#define BSV_CERT_RSA_KEY_SIZE_IN_WORDS (BSV_CERT_RSA_KEY_SIZE_IN_BITS/CC_BITS_IN_32BIT_WORD) + +/*! The maximal count of extra bits in PKA operations. */ +#define PKA_EXTRA_BITS 8 +/*! The number of memory registers in PKA operations. */ +#define PKA_MAX_COUNT_OF_PHYS_MEM_REGS 32 + +/*! Size of buffer for Barrett modulus tag in words. */ +#define RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_WORDS 5 +/*! Size of buffer for Barrett modulus tag in bytes. */ +#define RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_BYTES (RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_WORDS*CC_32BIT_WORD_SIZE) + + + +#ifdef __cplusplus +} +#endif + +#endif //_CC_PKA_HW_PLAT_DEFS_H + +/** + @} + */ + diff --git a/include/drivers/arm/cryptocell/713/cc_sec_defs.h b/include/drivers/arm/cryptocell/713/cc_sec_defs.h new file mode 100644 index 000000000..8fb698ff5 --- /dev/null +++ b/include/drivers/arm/cryptocell/713/cc_sec_defs.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CC_SEC_DEFS_H +#define _CC_SEC_DEFS_H + +/*! +@file +@brief This file contains general definitions and types. +*/ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "cc_pal_types.h" + +/*! Hashblock size in words. */ +#define HASH_BLOCK_SIZE_IN_WORDS 16 +/*! Hash - SHA2 results in words. */ +#define HASH_RESULT_SIZE_IN_WORDS 8 +/*! Hash - SHA2 results in bytes. */ +#define HASH_RESULT_SIZE_IN_BYTES 32 + +/*! Definition for hash result array. */ +typedef uint32_t CCHashResult_t[HASH_RESULT_SIZE_IN_WORDS]; + +/*! Definition for converting pointer to Host address. */ +#define CONVERT_TO_ADDR(ptr) (unsigned long)ptr + +/*! Definition for converting pointer to SRAM address. */ +#define CONVERT_TO_SRAM_ADDR(ptr) (0xFFFFFFFF & ptr) + +/*! The data size of the signed SW image, in bytes. */ +/*!\internal ContentCertImageRecord_t includes: HS(8W) + 64-b dstAddr(2W) + imgSize(1W) + isCodeEncUsed(1W) */ +#define SW_REC_SIGNED_DATA_SIZE_IN_BYTES 48 + +/*! The data size of the unsigned SW image, in bytes. */ +/*!\internal CCSbSwImgAddData_t includes: 64-b srcAddr(2W)*/ +#define SW_REC_NONE_SIGNED_DATA_SIZE_IN_BYTES 8 + +/*! The additional data size - storage address and length of the unsigned SW image, in words. */ +#define SW_REC_NONE_SIGNED_DATA_SIZE_IN_WORDS SW_REC_NONE_SIGNED_DATA_SIZE_IN_BYTES/CC_32BIT_WORD_SIZE + +/*! The additional data section size, in bytes. */ +#define CC_SB_MAX_SIZE_ADDITIONAL_DATA_BYTES 128 + +/*! Indication of whether or not to load the SW image to memory. */ +#define CC_SW_COMP_NO_MEM_LOAD_INDICATION 0xFFFFFFFFFFFFFFFFUL + +/*! Indication of product version, stored in certificate version field. */ +#define CC_SB_CERT_VERSION_PROJ_PRD 0x713 + +#ifdef __cplusplus +} +#endif + +#endif + +/** +@} + */ + + + diff --git a/include/drivers/arm/css/css_mhu_doorbell.h b/include/drivers/arm/css/css_mhu_doorbell.h index e6f7a1bd1..88302fd7b 100644 --- a/include/drivers/arm/css/css_mhu_doorbell.h +++ b/include/drivers/arm/css/css_mhu_doorbell.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,13 +11,13 @@ #include <lib/mmio.h> -/* MHUv2 Base Address */ -#define MHUV2_BASE_ADDR PLAT_MHUV2_BASE +/* MHUv2 Frame Base Mask */ +#define MHU_V2_FRAME_BASE_MASK UL(~0xFFF) /* MHUv2 Control Registers Offsets */ -#define MHU_V2_MSG_NO_CAP_OFFSET 0xF80 -#define MHU_V2_ACCESS_REQ_OFFSET 0xF88 -#define MHU_V2_ACCESS_READY_OFFSET 0xF8C +#define MHU_V2_MSG_NO_CAP_OFFSET UL(0xF80) +#define MHU_V2_ACCESS_REQ_OFFSET UL(0xF88) +#define MHU_V2_ACCESS_READY_OFFSET UL(0xF8C) #define SENDER_REG_STAT(_channel) (0x20 * (_channel)) #define SENDER_REG_SET(_channel) ((0x20 * (_channel)) + 0xC) diff --git a/include/drivers/arm/css/css_scp.h b/include/drivers/arm/css/css_scp.h index f3c08c52f..2b506eaaf 100644 --- a/include/drivers/arm/css/css_scp.h +++ b/include/drivers/arm/css/css_scp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,13 +40,13 @@ int css_scp_boot_ready(void); /* * All CSS platforms load SCP_BL2/SCP_BL2U just below BL2 (this is where BL31 * usually resides except when ARM_BL31_IN_DRAM is - * set). Ensure that SCP_BL2/SCP_BL2U do not overflow into tb_fw_config. + * set). Ensure that SCP_BL2/SCP_BL2U do not overflow into fw_config. */ CASSERT(SCP_BL2_LIMIT <= BL2_BASE, assert_scp_bl2_overwrite_bl2); CASSERT(SCP_BL2U_LIMIT <= BL2_BASE, assert_scp_bl2u_overwrite_bl2); -CASSERT(SCP_BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_scp_bl2_overflow); -CASSERT(SCP_BL2U_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow); +CASSERT(SCP_BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2_overflow); +CASSERT(SCP_BL2U_BASE >= ARM_FW_CONFIG_LIMIT, assert_scp_bl2u_overflow); #endif #endif /* CSS_SCP_H */ diff --git a/include/drivers/arm/css/scmi.h b/include/drivers/arm/css/scmi.h index 1f8dc6cce..e8a2863a9 100644 --- a/include/drivers/arm/css/scmi.h +++ b/include/drivers/arm/css/scmi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -162,7 +162,7 @@ int scmi_ap_core_set_reset_addr(void *p, uint64_t reset_addr, uint32_t attr); int scmi_ap_core_get_reset_addr(void *p, uint64_t *reset_addr, uint32_t *attr); /* API to get the platform specific SCMI channel information. */ -scmi_channel_plat_info_t *plat_css_get_scmi_info(void); +scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id); /* API to override default PSCI callbacks for platforms that support SCMI. */ const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops); diff --git a/include/drivers/arm/gic_common.h b/include/drivers/arm/gic_common.h index 3ac1b43ff..dc23721bb 100644 --- a/include/drivers/arm/gic_common.h +++ b/include/drivers/arm/gic_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,7 +40,7 @@ #define GIC_HIGHEST_NS_PRIORITY U(0x80) /******************************************************************************* - * GIC Distributor interface register offsets that are common to GICv3 & GICv2 + * Common GIC Distributor interface register offsets ******************************************************************************/ #define GICD_CTLR U(0x0) #define GICD_TYPER U(0x4) @@ -61,19 +61,17 @@ #define CTLR_ENABLE_G0_MASK U(0x1) #define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT) - /******************************************************************************* - * GIC Distributor interface register constants that are common to GICv3 & GICv2 + * Common GIC Distributor interface register constants ******************************************************************************/ #define PIDR2_ARCH_REV_SHIFT 4 #define PIDR2_ARCH_REV_MASK U(0xf) -/* GICv3 revision as reported by the PIDR2 register */ -#define ARCH_REV_GICV3 U(0x3) -/* GICv2 revision as reported by the PIDR2 register */ -#define ARCH_REV_GICV2 U(0x2) -/* GICv1 revision as reported by the PIDR2 register */ +/* GIC revision as reported by PIDR2.ArchRev register field */ #define ARCH_REV_GICV1 U(0x1) +#define ARCH_REV_GICV2 U(0x2) +#define ARCH_REV_GICV3 U(0x3) +#define ARCH_REV_GICV4 U(0x4) #define IGROUPR_SHIFT 5 #define ISENABLER_SHIFT 5 diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index c4f42d04d..d8ac4cb33 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,7 +8,7 @@ #define GICV3_H /******************************************************************************* - * GICv3 miscellaneous definitions + * GICv3 and 3.1 miscellaneous definitions ******************************************************************************/ /* Interrupt group definitions */ #define INTR_GROUP1S U(0) @@ -25,20 +25,85 @@ /* GICv3 can only target up to 16 PEs with SGI */ #define GICV3_MAX_SGI_TARGETS U(16) +/* PPIs INTIDs 16-31 */ +#define MAX_PPI_ID U(31) + +#if GIC_EXT_INTID + +/* GICv3.1 extended PPIs INTIDs 1056-1119 */ +#define MIN_EPPI_ID U(1056) +#define MAX_EPPI_ID U(1119) + +/* Total number of GICv3.1 EPPIs */ +#define TOTAL_EPPI_INTR_NUM (MAX_EPPI_ID - MIN_EPPI_ID + U(1)) + +/* Total number of GICv3.1 PPIs and EPPIs */ +#define TOTAL_PRIVATE_INTR_NUM (TOTAL_PCPU_INTR_NUM + TOTAL_EPPI_INTR_NUM) + +/* GICv3.1 extended SPIs INTIDs 4096 - 5119 */ +#define MIN_ESPI_ID U(4096) +#define MAX_ESPI_ID U(5119) + +/* Total number of GICv3.1 ESPIs */ +#define TOTAL_ESPI_INTR_NUM (MAX_ESPI_ID - MIN_ESPI_ID + U(1)) + +/* Total number of GICv3.1 SPIs and ESPIs */ +#define TOTAL_SHARED_INTR_NUM (TOTAL_SPI_INTR_NUM + TOTAL_ESPI_INTR_NUM) + +/* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ +#define IS_SGI_PPI(id) (((id) <= MAX_PPI_ID) || \ + (((id) >= MIN_EPPI_ID) && \ + ((id) <= MAX_EPPI_ID))) + +/* SPIs: 32-1019, ESPIs: 4096-5119 */ +#define IS_SPI(id) ((((id) >= MIN_SPI_ID) && \ + ((id) <= MAX_SPI_ID)) || \ + (((id) >= MIN_ESPI_ID) && \ + ((id) <= MAX_ESPI_ID))) +#else /* GICv3 */ + +/* Total number of GICv3 PPIs */ +#define TOTAL_PRIVATE_INTR_NUM TOTAL_PCPU_INTR_NUM + +/* Total number of GICv3 SPIs */ +#define TOTAL_SHARED_INTR_NUM TOTAL_SPI_INTR_NUM + +/* SGIs: 0-15, PPIs: 16-31 */ +#define IS_SGI_PPI(id) ((id) <= MAX_PPI_ID) + +/* SPIs: 32-1019 */ +#define IS_SPI(id) (((id) >= MIN_SPI_ID) && ((id) <= MAX_SPI_ID)) + +#endif /* GIC_EXT_INTID */ + /******************************************************************************* - * GICv3 specific Distributor interface register offsets and constants. + * GICv3 and 3.1 specific Distributor interface register offsets and constants ******************************************************************************/ +#define GICD_TYPER2 U(0x0c) #define GICD_STATUSR U(0x10) #define GICD_SETSPI_NSR U(0x40) #define GICD_CLRSPI_NSR U(0x48) #define GICD_SETSPI_SR U(0x50) -#define GICD_CLRSPI_SR U(0x50) +#define GICD_CLRSPI_SR U(0x58) #define GICD_IGRPMODR U(0xd00) +#define GICD_IGROUPRE U(0x1000) +#define GICD_ISENABLERE U(0x1200) +#define GICD_ICENABLERE U(0x1400) +#define GICD_ISPENDRE U(0x1600) +#define GICD_ICPENDRE U(0x1800) +#define GICD_ISACTIVERE U(0x1a00) +#define GICD_ICACTIVERE U(0x1c00) +#define GICD_IPRIORITYRE U(0x2000) +#define GICD_ICFGRE U(0x3000) +#define GICD_IGRPMODRE U(0x3400) +#define GICD_NSACRE U(0x3600) /* - * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and - * n >= 32, making the effective offset as 0x6100. + * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt ID + * and n >= 32, making the effective offset as 0x6100 */ #define GICD_IROUTER U(0x6000) +#define GICD_IROUTERE U(0x8000) + #define GICD_PIDR2_GICV3 U(0xffe8) #define IGRPMODR_SHIFT 5 @@ -78,14 +143,26 @@ #define NUM_OF_DIST_REGS 30 +/* GICD_TYPER shifts and masks */ +#define TYPER_ESPI U(1 << 8) +#define TYPER_DVIS U(1 << 18) +#define TYPER_ESPI_RANGE_MASK U(0x1f) +#define TYPER_ESPI_RANGE_SHIFT U(27) +#define TYPER_ESPI_RANGE U(TYPER_ESPI_MASK << TYPER_ESPI_SHIFT) + /******************************************************************************* - * GICv3 Re-distributor interface registers & constants + * Common GIC Redistributor interface registers & constants ******************************************************************************/ +#if GIC_ENABLE_V4_EXTN +#define GICR_PCPUBASE_SHIFT 0x12 +#else #define GICR_PCPUBASE_SHIFT 0x11 +#endif #define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */ #define GICR_CTLR U(0x0) #define GICR_IIDR U(0x04) #define GICR_TYPER U(0x08) +#define GICR_STATUSR U(0x10) #define GICR_WAKER U(0x14) #define GICR_PROPBASER U(0x70) #define GICR_PENDBASER U(0x78) @@ -102,6 +179,16 @@ #define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + U(0xd00)) #define GICR_NSACR (GICR_SGIBASE_OFFSET + U(0xe00)) +#define GICR_IGROUPR GICR_IGROUPR0 +#define GICR_ISENABLER GICR_ISENABLER0 +#define GICR_ICENABLER GICR_ICENABLER0 +#define GICR_ISPENDR GICR_ISPENDR0 +#define GICR_ICPENDR GICR_ICPENDR0 +#define GICR_ISACTIVER GICR_ISACTIVER0 +#define GICR_ICACTIVER GICR_ICACTIVER0 +#define GICR_ICFGR GICR_ICFGR0 +#define GICR_IGRPMODR GICR_IGRPMODR0 + /* GICR_CTLR bit definitions */ #define GICR_CTLR_UWP_SHIFT 31 #define GICR_CTLR_UWP_MASK U(0x1) @@ -132,12 +219,21 @@ #define TYPER_LAST_BIT BIT_32(TYPER_LAST_SHIFT) -#define NUM_OF_REDIST_REGS 30 +#define TYPER_PPI_NUM_SHIFT U(27) +#define TYPER_PPI_NUM_MASK U(0x1f) + +/* GICR_IIDR bit definitions */ +#define IIDR_PRODUCT_ID_MASK U(0xff000000) +#define IIDR_VARIANT_MASK U(0x000f0000) +#define IIDR_REVISION_MASK U(0x0000f000) +#define IIDR_IMPLEMENTER_MASK U(0x00000fff) +#define IIDR_MODEL_MASK (IIDR_PRODUCT_ID_MASK | \ + IIDR_IMPLEMENTER_MASK) /******************************************************************************* - * GICv3 CPU interface registers & constants + * GICv3 and 3.1 CPU interface registers & constants ******************************************************************************/ -/* ICC_SRE bit definitions*/ +/* ICC_SRE bit definitions */ #define ICC_SRE_EN_BIT BIT_32(3) #define ICC_SRE_DIB_BIT BIT_32(2) #define ICC_SRE_DFB_BIT BIT_32(1) @@ -192,9 +288,8 @@ ((_tgt) & SGIR_TGT_MASK)) /***************************************************************************** - * GICv3 ITS registers and constants + * GICv3 and 3.1 ITS registers and constants *****************************************************************************/ - #define GITS_CTLR U(0x0) #define GITS_IIDR U(0x4) #define GITS_TYPER U(0x8) @@ -205,8 +300,7 @@ /* GITS_CTLR bit definitions */ #define GITS_CTLR_ENABLED_BIT BIT_32(0) -#define GITS_CTLR_QUIESCENT_SHIFT 31 -#define GITS_CTLR_QUIESCENT_BIT BIT_32(GITS_CTLR_QUIESCENT_SHIFT) +#define GITS_CTLR_QUIESCENT_BIT BIT_32(1) #ifndef __ASSEMBLER__ @@ -224,7 +318,7 @@ static inline bool gicv3_is_intr_id_special_identifier(unsigned int id) } /******************************************************************************* - * Helper GICv3 macros for SEL1 + * Helper GICv3 and 3.1 macros for SEL1 ******************************************************************************/ static inline uint32_t gicv3_acknowledge_interrupt_sel1(void) { @@ -238,6 +332,18 @@ static inline uint32_t gicv3_get_pending_interrupt_id_sel1(void) static inline void gicv3_end_of_interrupt_sel1(unsigned int id) { + /* + * Interrupt request deassertion from peripheral to GIC happens + * by clearing interrupt condition by a write to the peripheral + * register. It is desired that the write transfer is complete + * before the core tries to change GIC state from 'AP/Active' to + * a new state on seeing 'EOI write'. + * Since ICC interface writes are not ordered against Device + * memory writes, a barrier is required to ensure the ordering. + * The dsb will also ensure *completion* of previous writes with + * DEVICE nGnRnE attribute. + */ + dsbishst(); write_icc_eoir1_el1(id); } @@ -251,18 +357,30 @@ static inline uint32_t gicv3_acknowledge_interrupt(void) static inline void gicv3_end_of_interrupt(unsigned int id) { + /* + * Interrupt request deassertion from peripheral to GIC happens + * by clearing interrupt condition by a write to the peripheral + * register. It is desired that the write transfer is complete + * before the core tries to change GIC state from 'AP/Active' to + * a new state on seeing 'EOI write'. + * Since ICC interface writes are not ordered against Device + * memory writes, a barrier is required to ensure the ordering. + * The dsb will also ensure *completion* of previous writes with + * DEVICE nGnRnE attribute. + */ + dsbishst(); return write_icc_eoir0_el1(id); } /* - * This macro returns the total number of GICD registers corresponding to - * the name. + * This macro returns the total number of GICD/GICR registers corresponding to + * the register name */ #define GICD_NUM_REGS(reg_name) \ - DIV_ROUND_UP_2EVAL(TOTAL_SPI_INTR_NUM, (1 << reg_name ## _SHIFT)) + DIV_ROUND_UP_2EVAL(TOTAL_SHARED_INTR_NUM, (1 << reg_name##_SHIFT)) #define GICR_NUM_REGS(reg_name) \ - DIV_ROUND_UP_2EVAL(TOTAL_PCPU_INTR_NUM, (1 << reg_name ## _SHIFT)) + DIV_ROUND_UP_2EVAL(TOTAL_PRIVATE_INTR_NUM, (1 << reg_name##_SHIFT)) /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ #define INT_ID_MASK U(0xffffff) @@ -325,20 +443,19 @@ typedef struct gicv3_redist_ctx { /* 32 bits registers */ uint32_t gicr_ctlr; - uint32_t gicr_igroupr0; - uint32_t gicr_isenabler0; - uint32_t gicr_ispendr0; - uint32_t gicr_isactiver0; + uint32_t gicr_igroupr[GICR_NUM_REGS(IGROUPR)]; + uint32_t gicr_isenabler[GICR_NUM_REGS(ISENABLER)]; + uint32_t gicr_ispendr[GICR_NUM_REGS(ISPENDR)]; + uint32_t gicr_isactiver[GICR_NUM_REGS(ISACTIVER)]; uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)]; - uint32_t gicr_icfgr0; - uint32_t gicr_icfgr1; - uint32_t gicr_igrpmodr0; + uint32_t gicr_icfgr[GICR_NUM_REGS(ICFGR)]; + uint32_t gicr_igrpmodr[GICR_NUM_REGS(IGRPMODR)]; uint32_t gicr_nsacr; } gicv3_redist_ctx_t; typedef struct gicv3_dist_ctx { /* 64 bits registers */ - uint64_t gicd_irouter[TOTAL_SPI_INTR_NUM]; + uint64_t gicd_irouter[TOTAL_SHARED_INTR_NUM]; /* 32 bits registers */ uint32_t gicd_ctlr; @@ -371,6 +488,7 @@ void gicv3_distif_init(void); void gicv3_rdistif_init(unsigned int proc_num); void gicv3_rdistif_on(unsigned int proc_num); void gicv3_rdistif_off(unsigned int proc_num); +unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame); void gicv3_cpuif_enable(unsigned int proc_num); void gicv3_cpuif_disable(unsigned int proc_num); unsigned int gicv3_get_pending_interrupt_type(void); diff --git a/include/drivers/arm/pl011.h b/include/drivers/arm/pl011.h index 8733d1964..ebc664348 100644 --- a/include/drivers/arm/pl011.h +++ b/include/drivers/arm/pl011.h @@ -81,17 +81,10 @@ #endif /* !PL011_GENERIC_UART */ -#define CONSOLE_T_PL011_BASE CONSOLE_T_DRVDATA - #ifndef __ASSEMBLER__ #include <stdint.h> -typedef struct { - console_t console; - uintptr_t base; -} console_pl011_t; - /* * Initialize a new PL011 console instance and register it with the console * framework. The |console| pointer must point to storage that will be valid @@ -99,7 +92,7 @@ typedef struct { * Its contents will be reinitialized from scratch. */ int console_pl011_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - console_pl011_t *console); + console_t *console); #endif /*__ASSEMBLER__*/ diff --git a/include/drivers/arm/tzc_dmc620.h b/include/drivers/arm/tzc_dmc620.h index e0e6760b2..26c444d10 100644 --- a/include/drivers/arm/tzc_dmc620.h +++ b/include/drivers/arm/tzc_dmc620.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -32,16 +32,16 @@ /* Address offsets of access address next registers */ #define DMC620_ACC_ADDR_MIN_31_00_NEXT(region_no) \ (DMC620_ACC_ADDR_MIN_31_00_NEXT_BASE + \ - (region_no * DMC620_ACC_ADDR_NEXT_SIZE)) + ((region_no) * DMC620_ACC_ADDR_NEXT_SIZE)) #define DMC620_ACC_ADDR_MIN_47_32_NEXT(region_no) \ (DMC620_ACC_ADDR_MIN_47_32_NEXT_BASE + \ - (region_no * DMC620_ACC_ADDR_NEXT_SIZE)) + ((region_no) * DMC620_ACC_ADDR_NEXT_SIZE)) #define DMC620_ACC_ADDR_MAX_31_00_NEXT(region_no) \ (DMC620_ACC_ADDR_MAX_31_00_NEXT_BASE + \ - (region_no * DMC620_ACC_ADDR_NEXT_SIZE)) + ((region_no) * DMC620_ACC_ADDR_NEXT_SIZE)) #define DMC620_ACC_ADDR_MAX_47_32_NEXT(region_no) \ (DMC620_ACC_ADDR_MAX_47_32_NEXT_BASE + \ - (region_no * DMC620_ACC_ADDR_NEXT_SIZE)) + ((region_no) * DMC620_ACC_ADDR_NEXT_SIZE)) /* Number of TZC address regions in DMC-620 */ #define DMC620_ACC_ADDR_COUNT U(8) diff --git a/include/drivers/auth/auth_mod.h b/include/drivers/auth/auth_mod.h index 6c48124b5..d1fd52c86 100644 --- a/include/drivers/auth/auth_mod.h +++ b/include/drivers/auth/auth_mod.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,12 +14,25 @@ #include <drivers/auth/auth_common.h> #include <drivers/auth/img_parser_mod.h> +#include <lib/utils_def.h> + /* * Image flags */ #define IMG_FLAG_AUTHENTICATED (1 << 0) - +#if COT_DESC_IN_DTB && !IMAGE_BL1 +/* + * Authentication image descriptor + */ +typedef struct auth_img_desc_s { + unsigned int img_id; + img_type_t img_type; + const struct auth_img_desc_s *parent; + auth_method_desc_t *img_auth_methods; + auth_param_desc_t *authenticated_data; +} auth_img_desc_t; +#else /* * Authentication image descriptor */ @@ -30,6 +43,7 @@ typedef struct auth_img_desc_s { const auth_method_desc_t *const img_auth_methods; const auth_param_desc_t *const authenticated_data; } auth_img_desc_t; +#endif /* COT_DESC_IN_DTB && !IMAGE_BL1 */ /* Public functions */ void auth_mod_init(void); @@ -41,11 +55,36 @@ int auth_mod_verify_img(unsigned int img_id, /* Macro to register a CoT defined as an array of auth_img_desc_t pointers */ #define REGISTER_COT(_cot) \ const auth_img_desc_t *const *const cot_desc_ptr = (_cot); \ + const size_t cot_desc_size = ARRAY_SIZE(_cot); \ unsigned int auth_img_flags[MAX_NUMBER_IDS] extern const auth_img_desc_t *const *const cot_desc_ptr; +extern const size_t cot_desc_size; extern unsigned int auth_img_flags[MAX_NUMBER_IDS]; +#if defined(SPD_spmd) + +#define DEFINE_SIP_SP_PKG(n) DEFINE_SP_PKG(n, sip_sp_content_cert) +#define DEFINE_PLAT_SP_PKG(n) DEFINE_SP_PKG(n, plat_sp_content_cert) + +#define DEFINE_SP_PKG(n, cert) \ + static const auth_img_desc_t sp_pkg##n = { \ + .img_id = SP_PKG##n##_ID, \ + .img_type = IMG_RAW, \ + .parent = &cert, \ + .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { \ + [0] = { \ + .type = AUTH_METHOD_HASH, \ + .param.hash = { \ + .data = &raw_data, \ + .hash = &sp_pkg##n##_hash \ + } \ + } \ + } \ + } + +#endif + #endif /* TRUSTED_BOARD_BOOT */ #endif /* AUTH_MOD_H */ diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h index f211035d7..71cf67306 100644 --- a/include/drivers/auth/crypto_mod.h +++ b/include/drivers/auth/crypto_mod.h @@ -13,9 +13,18 @@ enum crypto_ret_value { CRYPTO_ERR_INIT, CRYPTO_ERR_HASH, CRYPTO_ERR_SIGNATURE, + CRYPTO_ERR_DECRYPTION, CRYPTO_ERR_UNKNOWN }; +#define CRYPTO_MAX_IV_SIZE 16U +#define CRYPTO_MAX_TAG_SIZE 16U + +/* Decryption algorithm */ +enum crypto_dec_algo { + CRYPTO_GCM_DECRYPT = 0 +}; + /* * Cryptographic library descriptor */ @@ -44,6 +53,15 @@ typedef struct crypto_lib_desc_s { unsigned int data_len, unsigned char *output); #endif /* MEASURED_BOOT */ + /* + * Authenticated decryption. Return one of the + * 'enum crypto_ret_value' options. + */ + int (*auth_decrypt)(enum crypto_dec_algo dec_algo, void *data_ptr, + size_t len, const void *key, unsigned int key_len, + unsigned int key_flags, const void *iv, + unsigned int iv_len, const void *tag, + unsigned int tag_len); } crypto_lib_desc_t; /* Public functions */ @@ -54,6 +72,11 @@ int crypto_mod_verify_signature(void *data_ptr, unsigned int data_len, void *pk_ptr, unsigned int pk_len); int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, void *digest_info_ptr, unsigned int digest_info_len); +int crypto_mod_auth_decrypt(enum crypto_dec_algo dec_algo, void *data_ptr, + size_t len, const void *key, unsigned int key_len, + unsigned int key_flags, const void *iv, + unsigned int iv_len, const void *tag, + unsigned int tag_len); #if MEASURED_BOOT int crypto_mod_calc_hash(unsigned int alg, void *data_ptr, @@ -61,21 +84,24 @@ int crypto_mod_calc_hash(unsigned int alg, void *data_ptr, /* Macro to register a cryptographic library */ #define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \ - _calc_hash) \ + _calc_hash, _auth_decrypt) \ const crypto_lib_desc_t crypto_lib_desc = { \ .name = _name, \ .init = _init, \ .verify_signature = _verify_signature, \ .verify_hash = _verify_hash, \ - .calc_hash = _calc_hash \ + .calc_hash = _calc_hash, \ + .auth_decrypt = _auth_decrypt \ } #else -#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash) \ +#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \ + _auth_decrypt) \ const crypto_lib_desc_t crypto_lib_desc = { \ .name = _name, \ .init = _init, \ .verify_signature = _verify_signature, \ - .verify_hash = _verify_hash \ + .verify_hash = _verify_hash, \ + .auth_decrypt = _auth_decrypt \ } #endif /* MEASURED_BOOT */ diff --git a/include/drivers/auth/mbedtls/mbedtls_config.h b/include/drivers/auth/mbedtls/mbedtls_config.h index 6e179bbd1..ad39fa906 100644 --- a/include/drivers/auth/mbedtls/mbedtls_config.h +++ b/include/drivers/auth/mbedtls/mbedtls_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -63,6 +63,7 @@ #define MBEDTLS_ECDSA_C #define MBEDTLS_ECP_C #define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_ECP_NO_INTERNAL_RNG #endif #if TF_MBEDTLS_USE_RSA #define MBEDTLS_RSA_C @@ -79,6 +80,12 @@ #define MBEDTLS_X509_USE_C #define MBEDTLS_X509_CRT_PARSE_C +#if TF_MBEDTLS_USE_AES_GCM +#define MBEDTLS_AES_C +#define MBEDTLS_CIPHER_C +#define MBEDTLS_GCM_C +#endif + /* MPI / BIGNUM options */ #define MBEDTLS_MPI_WINDOW_SIZE 2 @@ -95,6 +102,12 @@ /* Memory buffer allocator options */ #define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8 +/* + * Prevent the use of 128-bit division which + * creates dependency on external libraries. + */ +#define MBEDTLS_NO_UDBL_DIVISION + #ifndef __ASSEMBLER__ /* System headers required to build mbed TLS with the current configuration */ #include <stdlib.h> diff --git a/include/drivers/auth/tbbr_cot_common.h b/include/drivers/auth/tbbr_cot_common.h new file mode 100644 index 000000000..a51faee1a --- /dev/null +++ b/include/drivers/auth/tbbr_cot_common.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TBBR_COT_COMMON_H +#define TBBR_COT_COMMON_H + +#include <drivers/auth/auth_mod.h> + +extern unsigned char tb_fw_hash_buf[HASH_DER_LEN]; +extern unsigned char scp_fw_hash_buf[HASH_DER_LEN]; +extern unsigned char nt_world_bl_hash_buf[HASH_DER_LEN]; + +extern auth_param_type_desc_t trusted_nv_ctr; +extern auth_param_type_desc_t subject_pk; +extern auth_param_type_desc_t sig; +extern auth_param_type_desc_t sig_alg; +extern auth_param_type_desc_t raw_data; + +extern auth_param_type_desc_t tb_fw_hash; +extern auth_param_type_desc_t tb_fw_config_hash; +extern auth_param_type_desc_t fw_config_hash; + +extern const auth_img_desc_t trusted_boot_fw_cert; +extern const auth_img_desc_t hw_config; + +#endif /* TBBR_COT_COMMON_H */ diff --git a/include/drivers/brcm/chimp.h b/include/drivers/brcm/chimp.h new file mode 100644 index 000000000..02d528b9f --- /dev/null +++ b/include/drivers/brcm/chimp.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SR_CHIMP_H +#define SR_CHIMP_H + +#include <common/bl_common.h> +#include <common/debug.h> +#include <lib/mmio.h> + +#include <platform_def.h> + +#define CHIMP_WINDOW_SIZE 0x400000 +#define CHIMP_ERROR_OFFSET 28 +#define CHIMP_ERROR_MASK 0xf0000000 + +#ifndef EMULATION_SETUP +#define CHIMP_HANDSHAKE_TIMEOUT_MS 10000 +#else +/* + * 1hr timeout for test in emulator + * By doing this ChiMP is given a chance to boot + * fully from the QSPI + * (on Palladium this takes upto 50 min depending on QSPI clk) + */ + +#define CHIMP_HANDSHAKE_TIMEOUT_MS 3600000 +#endif + +#define CHIMP_BPE_MODE_ID_PATTERN (0x25000000) +#define CHIMP_BPE_MODE_ID_MASK (0x7f000000) +#define NIC_RESET_RELEASE_TIMEOUT_US (10) + +/* written by M0, used by ChiMP ROM */ +#define SR_IN_SMARTNIC_MODE_BIT 0 +/* written by M0, used by ChiMP ROM */ +#define SR_CHIMP_SECURE_BOOT_BIT 1 +/* cleared by AP, set by ChiMP BC2 code */ +#define SR_FLASH_ACCESS_DONE_BIT 2 + +#ifdef USE_CHIMP +void bcm_chimp_write(uintptr_t addr, uint32_t value); +uint32_t bcm_chimp_read(uintptr_t addr); +uint32_t bcm_chimp_read_ctrl(uint32_t offset); +void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits); +void bcm_chimp_setbits(uintptr_t addr, uint32_t bits); +int bcm_chimp_is_nic_mode(void); +void bcm_chimp_fru_prog_done(bool status); +int bcm_chimp_handshake_done(void); +int bcm_chimp_wait_handshake(void); +/* Fastboot-related*/ +int bcm_chimp_initiate_fastboot(int fastboot_type); +#else +static inline void bcm_chimp_write(uintptr_t addr, uint32_t value) +{ +} +static inline uint32_t bcm_chimp_read(uintptr_t addr) +{ + return 0; +} +static inline uint32_t bcm_chimp_read_ctrl(uint32_t offset) +{ + return 0; +} +static inline void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits) +{ +} +static inline void bcm_chimp_setbits(uintptr_t addr, uint32_t bits) +{ +} +static inline int bcm_chimp_is_nic_mode(void) +{ + return 0; +} +static inline void bcm_chimp_fru_prog_done(bool status) +{ +} +static inline int bcm_chimp_handshake_done(void) +{ + return 0; +} +static inline int bcm_chimp_wait_handshake(void) +{ + return 0; +} +static inline int bcm_chimp_initiate_fastboot(int fastboot_type) +{ + return 0; +} +#endif /* USE_CHIMP */ +#endif diff --git a/include/drivers/brcm/chimp_nv_defs.h b/include/drivers/brcm/chimp_nv_defs.h new file mode 100644 index 000000000..9be361f6e --- /dev/null +++ b/include/drivers/brcm/chimp_nv_defs.h @@ -0,0 +1,419 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BNXNVM_DEFS_H +#define BNXNVM_DEFS_H + +#if defined(__GNUC__) + #define PACKED_STRUCT __packed +#else /* non-GCC compiler */ + +#ifndef DOS_DRIVERS + #pragma pack(push) + #pragma pack(1) +#endif + #define PACKED_STRUCT +#endif + +typedef uint32_t u32_t; +typedef uint8_t u8_t; +typedef uint16_t u16_t; + +#define BNXNVM_DEFAULT_BLOCK_SIZE 4096 +#define BNXNVM_UNUSED_BYTE_VALUE 0xff + +#define NV_MAX_BLOCK_SIZE 16384 + +#define BITS_PER_BYTE (8) +#define SIZEOF_IN_BITS(x) (sizeof(x)*BITS_PER_BYTE) + +/************************/ +/* byte-swapping macros */ +/************************/ +#define BYTE_SWAP_16(x) \ + ((((u16_t)(x) & 0xff00) >> 8) | \ + (((u16_t)(x) & 0x00ff) << 8)) +#define BYTE_SWAP_32(x) \ + ((((u32_t)(x) & 0xff000000) >> 24) | \ + (((u32_t)(x) & 0x00ff0000) >> 8) | \ + (((u32_t)(x) & 0x0000ff00) << 8) | \ + (((u32_t)(x) & 0x000000ff) << 24)) + +/* auto-detect integer size */ +#define BYTE_SWAP_INT(x) \ + (SIZEOF_IN_BITS(x) == 16 ? BYTE_SWAP_16(x) : \ + SIZEOF_IN_BITS(x) == 32 ? BYTE_SWAP_32(x) : (x)) + +/********************************/ +/* Architecture-specific macros */ +/********************************/ +#ifdef __BIG_ENDIAN__ /* e.g. Motorola */ + + #define BE_INT16(x) (x) + #define BE_INT32(x) (x) + #define BE_INT(x) (x) + #define LE_INT16(x) BYTE_SWAP_16(x) + #define LE_INT32(x) BYTE_SWAP_32(x) + #define LE_INT(x) BYTE_SWAP_INT(x) + +#else /* Little Endian (e.g. Intel) */ + + #define LE_INT16(x) (x) + #define LE_INT32(x) (x) + #define LE_INT(x) (x) + #define BE_INT16(x) BYTE_SWAP_16(x) + #define BE_INT32(x) BYTE_SWAP_32(x) + #define BE_INT(x) BYTE_SWAP_INT(x) + +#endif + + +enum { + NV_OK = 0, + NV_NOT_NVRAM, + NV_BAD_MB, + NV_BAD_DIR_HEADER, + NV_BAD_DIR_ENTRY, + NV_FW_NOT_FOUND, +}; + +typedef struct { +#define BNXNVM_MASTER_BLOCK_SIG BE_INT32(0x424E5834) /*"BNX4"*/ + /* Signature*/ + u32_t sig; + /* Length of Master Block Header, in bytes [32] */ + u32_t length; + /* Block size, in bytes [4096] */ + u32_t block_size; + /* Byte-offset to Directory Block (translated) */ + u32_t directory_offset; + /* Byte-offset to Block Redirection Table (non-translated) */ + u32_t redirect_offset; + /* Size, in bytes of Reserved Blocks region (at end of NVRAM) */ + u32_t reserved_size; + /* + * Size of NVRAM (in bytes) - may be used to + * override auto-detected size + */ + u32_t nvram_size; + /* CRC-32 (IEEE 802.3 compatible) of the above */ + u32_t chksum; +} PACKED_STRUCT bnxnvm_master_block_header_t; + +typedef struct { +#define BNXNVM_DIRECTORY_BLOCK_SIG BE_INT32(0x44697230) /* "Dir0" */ + /* Signature */ + u32_t sig; + /* Length of Directory Header, in bytes [16] */ + u32_t length; + /* Number of Directory Entries */ + u32_t entries; + /* Length of each Directory Entry, in bytes [24] */ + u32_t entry_length; +} PACKED_STRUCT bnxnvm_directory_block_header_t; + +typedef struct { + /* Directory Entry Type (see enum bnxnvm_directory_type) */ + u16_t type; + /* Instance of this Directory Entry type (0-based) */ + u16_t ordinal; + /* + * Directory Entry Extension flags used to identify + * secondary instances of a type:ordinal combinations + */ + u16_t ext; + /* Directory Entry Attribute flags used to describe the item contents */ + u16_t attr; + /* Item location in NVRAM specified as offset (in bytes) */ + u32_t item_location; + /* + * Length of NVRAM item in bytes + * (including padding - multiple of block size) + */ + u32_t item_length; + /* Length of item data in bytes (excluding padding) */ + u32_t data_length; + /* + * CRC-32 (IEEE 802.3 compatible) of item data + * (excluding padding) (optional) + */ + u32_t data_chksum; +} PACKED_STRUCT bnxnvm_directory_entry_t; + +enum bnxnvm_version_format { + /* US-ASCII string (not necessarily null-terminated) */ + BNX_VERSION_FMT_ASCII = 0, + /* Each field 16-bits, displayed as unpadded decimal (e.g. "1.2.3.4") */ + BNX_VERSION_FMT_DEC = 1, + /* A single hexadecimal value, up to 64-bits (no dots) */ + BNX_VERSION_FMT_HEX = 2, + /* Multiple version values (three 8-bit version fields) */ + BNX_VERSION_FMT_MULTI = 3 +}; + +/* This structure definition must not change: */ +typedef struct { + u16_t flags; /* bit-flags (defaults to 0x0000) */ + u8_t version_format; /* enum bnxnvm_version_format */ + u8_t version_length; /* in bytes */ + u8_t version[16]; /* version value */ + u16_t dir_type; /* enum bnxnvm_directory_type */ + /* size of the entire trailer (to locate end of component data) */ + u16_t trailer_length; +#define BNXNVM_COMPONENT_TRAILER_SIG BE_INT32(0x54726c72) /* "Trlr" */ + u32_t sig; + u32_t chksum; /* CRC-32 of all bytes to this point */ +} PACKED_STRUCT bnxnvm_component_trailer_base_t; + +typedef struct { + /* + * new trailer members (e.g. digital signature) + * go here (insert at top): + */ + u8_t rsa_sig[256]; /* 2048-bit RSA-encrypted SHA-256 hash */ + bnxnvm_component_trailer_base_t base; +} PACKED_STRUCT bnxnvm_component_trailer_t; + +#define BNX_MAX_LEN_DIR_NAME 12 +#define BNX_MAX_LEN_DIR_DESC 50 +/********************************************************* + * NVRAM Directory Entry/Item Types, Names, and Descriptions + * + * If you see a name or description that needs improvement, + * please correct it or raise for discussion. + * When adding a new directory type, it would be appreciated + * if you also updated ../../libs/nvm/bnxt_nvm_str.c. + * DIR_NAME macros may contain up to 12 alpha-numeric + * US-ASCII characters only, camelCase is preferred for clarity. + * DIR_DESC macros may contain up to 50 US-ASCII characters + * providing a verbose description of the directory type. + */ +enum bnxnvm_directory_type { + /* 0x00 Unused directory entry, available for use */ + BNX_DIR_TYPE_UNUSED = 0, +#define BNX_DIR_NAME_UNUSED "unused" +#define BNX_DIR_DESC_UNUSED "Deleted directory entry, available for reuse" + /* 0x01 Package installation log */ + BNX_DIR_TYPE_PKG_LOG = 1, +#define BNX_DIR_NAME_PKG_LOG "pkgLog" +#define BNX_DIR_DESC_PKG_LOG "Package Installation Log" + BNX_DIR_TYPE_CHIMP_PATCH = 3, +#define BNX_DIR_NAME_CHIMP_PATCH "chimpPatch" +#define BNX_DIR_DESC_CHIMP_PATCH "ChiMP Patch Firmware" + /* 0x04 ChiMP firmware: Boot Code phase 1 */ + BNX_DIR_TYPE_BOOTCODE = 4, +#define BNX_DIR_NAME_BOOTCODE "chimpBoot" +#define BNX_DIR_DESC_BOOTCODE "Chip Management Processor Boot Firmware" + /* 0x05 VPD data block */ + BNX_DIR_TYPE_VPD = 5, +#define BNX_DIR_NAME_VPD "VPD" +#define BNX_DIR_DESC_VPD "Vital Product Data" + /* 0x06 Exp ROM MBA */ + BNX_DIR_TYPE_EXP_ROM_MBA = 6, +#define BNX_DIR_NAME_EXP_ROM_MBA "MBA" +#define BNX_DIR_DESC_EXP_ROM_MBA "Multiple Boot Agent Expansion ROM" + BNX_DIR_TYPE_AVS = 7, /* 0x07 AVS FW */ +#define BNX_DIR_NAME_AVS "AVS" +#define BNX_DIR_DESC_AVS "Adaptive Voltage Scaling Firmware" + BNX_DIR_TYPE_PCIE = 8, /* 0x08 PCIE FW */ +#define BNX_DIR_NAME_PCIE "PCIEucode" +#define BNX_DIR_DESC_PCIE "PCIe Microcode" + BNX_DIR_TYPE_PORT_MACRO = 9, /* 0x09 PORT MACRO FW */ +#define BNX_DIR_NAME_PORT_MACRO "portMacro" +#define BNX_DIR_DESC_PORT_MACRO "Port Macro Firmware" + BNX_DIR_TYPE_APE_FW = 10, /* 0x0A APE Firmware */ +#define BNX_DIR_NAME_APE_FW "apeFW" +#define BNX_DIR_DESC_APE_FW "Application Processing Engine Firmware" + /* 0x0B Patch firmware executed by APE ROM */ + BNX_DIR_TYPE_APE_PATCH = 11, +#define BNX_DIR_NAME_APE_PATCH "apePatch" +#define BNX_DIR_DESC_APE_PATCH "APE Patch Firmware" + BNX_DIR_TYPE_KONG_FW = 12, /* 0x0C Kong Firmware */ +#define BNX_DIR_NAME_KONG_FW "kongFW" +#define BNX_DIR_DESC_KONG_FW "Kong Firmware" + /* 0x0D Patch firmware executed by Kong ROM */ + BNX_DIR_TYPE_KONG_PATCH = 13, +#define BNX_DIR_NAME_KONG_PATCH "kongPatch" +#define BNX_DIR_DESC_KONG_PATCH "Kong Patch Firmware" + BNX_DIR_TYPE_BONO_FW = 14, /* 0x0E Bono Firmware */ +#define BNX_DIR_NAME_BONO_FW "bonoFW" +#define BNX_DIR_DESC_BONO_FW "Bono Firmware" + /* 0x0F Patch firmware executed by Bono ROM */ + BNX_DIR_TYPE_BONO_PATCH = 15, +#define BNX_DIR_NAME_BONO_PATCH "bonoPatch" +#define BNX_DIR_DESC_BONO_PATCH "Bono Patch Firmware" + BNX_DIR_TYPE_TANG_FW = 16, /* 0x10 Tang firmware */ +#define BNX_DIR_NAME_TANG_FW "tangFW" +#define BNX_DIR_DESC_TANG_FW "Tang Firmware" + /* 0x11 Patch firmware executed by Tang ROM */ + BNX_DIR_TYPE_TANG_PATCH = 17, +#define BNX_DIR_NAME_TANG_PATCH "tangPatch" +#define BNX_DIR_DESC_TANG_PATCH "Tang Patch Firmware" + /* 0x12 ChiMP firmware: Boot Code phase 2 (loaded by phase 1) */ + BNX_DIR_TYPE_BOOTCODE_2 = 18, +#define BNX_DIR_NAME_BOOTCODE_2 "chimpHWRM" +#define BNX_DIR_DESC_BOOTCODE_2 "ChiMP Hardware Resource Manager Firmware" + BNX_DIR_TYPE_CCM = 19, /* 0x13 CCM ROM binary */ +#define BNX_DIR_NAME_CCM "CCM" +#define BNX_DIR_DESC_CCM "Comprehensive Configuration Management" + /* 0x14 PCI-IDs, PCI-related configuration properties */ + BNX_DIR_TYPE_PCI_CFG = 20, +#define BNX_DIR_NAME_PCI_CFG "pciCFG" +#define BNX_DIR_DESC_PCI_CFG "PCIe Configuration Data" + + BNX_DIR_TYPE_TSCF_UCODE = 21, /* 0x15 TSCF micro-code */ +#define BNX_DIR_NAME_TSCF_UCODE "PHYucode" +#define BNX_DIR_DESC_TSCF_UCODE "Falcon PHY Microcode" + BNX_DIR_TYPE_ISCSI_BOOT = 22, /* 0x16 iSCSI Boot */ +#define BNX_DIR_NAME_ISCSI_BOOT "iSCSIboot" +#define BNX_DIR_DESC_ISCSI_BOOT "iSCSI Boot Software Initiator" + /* 0x18 iSCSI Boot IPV6 - ***DEPRECATED*** */ + BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24, + /* 0x19 iSCSI Boot IPV4N6 - ***DEPRECATED*** */ + BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25, + BNX_DIR_TYPE_ISCSI_BOOT_CFG = 26, /* 0x1a iSCSI Boot CFG v6 */ +#define BNX_DIR_NAME_ISCSI_BOOT_CFG "iSCSIcfg" +#define BNX_DIR_DESC_ISCSI_BOOT_CFG "iSCSI Boot Configuration Data" + BNX_DIR_TYPE_EXT_PHY = 27, /* 0x1b External PHY FW */ +#define BNX_DIR_NAME_EXT_PHY "extPHYfw" +#define BNX_DIR_DESC_EXT_PHY "External PHY Firmware" + BNX_DIR_TYPE_MODULES_PN = 28, /* 0x1c Modules PartNum list */ +#define BNX_DIR_NAME_MODULES_PN "modPartNums" +#define BNX_DIR_DESC_MODULES_PN "Optical Modules Part Number List" + BNX_DIR_TYPE_SHARED_CFG = 40, /* 0x28 shared configuration block */ +#define BNX_DIR_NAME_SHARED_CFG "sharedCFG" +#define BNX_DIR_DESC_SHARED_CFG "Shared Configuration Data" + BNX_DIR_TYPE_PORT_CFG = 41, /* 0x29 port configuration block */ +#define BNX_DIR_NAME_PORT_CFG "portCFG" +#define BNX_DIR_DESC_PORT_CFG "Port Configuration Data" + BNX_DIR_TYPE_FUNC_CFG = 42, /* 0x2A func configuration block */ +#define BNX_DIR_NAME_FUNC_CFG "funcCFG" +#define BNX_DIR_DESC_FUNC_CFG "Function Configuration Data" + + /* Management Firmware (TruManage) related dir entries*/ + /* 0x30 Management firmware configuration (see BMCFG library)*/ + BNX_DIR_TYPE_MGMT_CFG = 48, +#define BNX_DIR_NAME_MGMT_CFG "mgmtCFG" +#define BNX_DIR_DESC_MGMT_CFG "Out-of-band Management Configuration Data" + BNX_DIR_TYPE_MGMT_DATA = 49, /* 0x31 "Opaque Management Data" */ +#define BNX_DIR_NAME_MGMT_DATA "mgmtData" +#define BNX_DIR_DESC_MGMT_DATA "Out-of-band Management Data" + BNX_DIR_TYPE_MGMT_WEB_DATA = 50, /* 0x32 "Web GUI" file data */ +#define BNX_DIR_NAME_MGMT_WEB_DATA "webData" +#define BNX_DIR_DESC_MGMT_WEB_DATA "Out-of-band Management Web Data" + /* 0x33 "Web GUI" file metadata */ + BNX_DIR_TYPE_MGMT_WEB_META = 51, +#define BNX_DIR_NAME_MGMT_WEB_META "webMeta" +#define BNX_DIR_DESC_MGMT_WEB_META "Out-of-band Management Web Metadata" + /* 0x34 Management firmware Event Log (a.k.a. "SEL") */ + BNX_DIR_TYPE_MGMT_EVENT_LOG = 52, +#define BNX_DIR_NAME_MGMT_EVENT_LOG "eventLog" +#define BNX_DIR_DESC_MGMT_EVENT_LOG "Out-of-band Management Event Log" + /* 0x35 Management firmware Audit Log */ + BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53 +#define BNX_DIR_NAME_MGMT_AUDIT_LOG "auditLog" +#define BNX_DIR_DESC_MGMT_AUDIT_LOG "Out-of-band Management Audit Log" + +}; + +/* For backwards compatibility only, may be removed later */ +#define BNX_DIR_TYPE_ISCSI_BOOT_CFG6 BNX_DIR_TYPE_ISCSI_BOOT_CFG + +/* Firmware NVM items of "APE BIN" format are identified with + * the following macro: + */ +#define BNX_DIR_TYPE_IS_APE_BIN_FMT(type)\ + ((type) == BNX_DIR_TYPE_CHIMP_PATCH \ + || (type) == BNX_DIR_TYPE_BOOTCODE \ + || (type) == BNX_DIR_TYPE_BOOTCODE_2 \ + || (type) == BNX_DIR_TYPE_APE_FW \ + || (type) == BNX_DIR_TYPE_APE_PATCH \ + || (type) == BNX_DIR_TYPE_TANG_FW \ + || (type) == BNX_DIR_TYPE_TANG_PATCH \ + || (type) == BNX_DIR_TYPE_KONG_FW \ + || (type) == BNX_DIR_TYPE_KONG_PATCH \ + || (type) == BNX_DIR_TYPE_BONO_FW \ + || (type) == BNX_DIR_TYPE_BONO_PATCH \ + ) + +/* Other (non APE BIN) executable NVM items are identified with + * the following macro: + */ +#define BNX_DIR_TYPE_IS_OTHER_EXEC(type)\ + ((type) == BNX_DIR_TYPE_AVS \ + || (type) == BNX_DIR_TYPE_EXP_ROM_MBA \ + || (type) == BNX_DIR_TYPE_PCIE \ + || (type) == BNX_DIR_TYPE_TSCF_UCODE \ + || (type) == BNX_DIR_TYPE_EXT_PHY \ + || (type) == BNX_DIR_TYPE_CCM \ + || (type) == BNX_DIR_TYPE_ISCSI_BOOT \ + ) + +/* Executable NVM items (e.g. microcode, firmware, software) identified + * with the following macro + */ +#define BNX_DIR_TYPE_IS_EXECUTABLE(type) \ + (BNX_DIR_TYPE_IS_APE_BIN_FMT(type) \ + || BNX_DIR_TYPE_IS_OTHER_EXEC(type)) + +#define BNX_DIR_ORDINAL_FIRST 0 /* Ordinals are 0-based */ + +/* No extension flags for this directory entry */ +#define BNX_DIR_EXT_NONE 0 +/* Directory entry is inactive (not used, not hidden, + * not available for reuse) + */ +#define BNX_DIR_EXT_INACTIVE (1 << 0) +/* Directory content is a temporary staging location for + * updating the primary (non-update) directory entry contents + * (e.g. performing a secure firmware update) + */ +#define BNX_DIR_EXT_UPDATE (1 << 1) + +/* No attribute flags set for this directory entry */ +#define BNX_DIR_ATTR_NONE 0 +/* Directory entry checksum of contents is purposely incorrect */ +#define BNX_DIR_ATTR_NO_CHKSUM (1 << 0) +/* Directory contents are in the form of a property-stream + * (e.g. configuration properties) + */ +#define BNX_DIR_ATTR_PROP_STREAM (1 << 1) +/* Directory content (e.g. iSCSI boot) supports IPv4 */ +#define BNX_DIR_ATTR_IPv4 (1 << 2) +/* Directory content (e.g. iSCSI boot) supports IPv6 */ +#define BNX_DIR_ATTR_IPv6 (1 << 3) +/* Directory content includes standard NVM component trailer + * (bnxnvm_component_trailer_t) + */ +#define BNX_DIR_ATTR_TRAILER (1 << 4) + +/* Index of tab-delimited fields in each package log + * (BNX_DIR_TYPE_PKG_LOG) record (\n-terminated line): + */ +enum bnxnvm_pkglog_field_index { + /* Package installation date/time in ISO-8601 format */ + BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0, + /* Installed package description (from package header) or "N/A" */ + BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1, + /* Installed package version string (from package header) or "N/A" */ + BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2, + /* Installed package creation/modification timestamp (ISO-8601) */ + BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3, + /* Installed package checksum in hexadecimal (CRC-32) or "N/A" */ + BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4, + /* Total number of packaged items applied in this installation */ + BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, + /* Hexadecimal bit-mask identifying which items were installed */ + BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6 +}; + +#if !defined(__GNUC__) +#ifndef DOS_DRIVERS + #pragma pack(pop) /* original packing */ +#endif +#endif + +#endif /* Don't add anything after this line */ diff --git a/include/drivers/brcm/dmu.h b/include/drivers/brcm/dmu.h new file mode 100644 index 000000000..3a57bbdee --- /dev/null +++ b/include/drivers/brcm/dmu.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2015 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DMU_H +#define DMU_H + +/* Clock field should be 2 bits only */ +#define CLKCONFIG_MASK 0x3 + +/* argument */ +struct DmuBlockEnable { + uint32_t sotp:1; + uint32_t pka_rng:1; + uint32_t crypto:1; + uint32_t spl:1; + uint32_t cdru_vgm:1; + uint32_t apbs_s0_idm:1; + uint32_t smau_s0_idm:1; +}; + +/* prototype */ +uint32_t bcm_dmu_block_enable(struct DmuBlockEnable dbe); +uint32_t bcm_dmu_block_disable(struct DmuBlockEnable dbe); +uint32_t bcm_set_ihost_pll_freq(uint32_t cluster_num, int ihost_pll_freq_sel); +uint32_t bcm_get_ihost_pll_freq(uint32_t cluster_num); + +#define PLL_FREQ_BYPASS 0x0 +#define PLL_FREQ_FULL 0x1 +#define PLL_FREQ_HALF 0x2 +#define PLL_FREQ_QRTR 0x3 + +#endif diff --git a/include/drivers/brcm/emmc/bcm_emmc.h b/include/drivers/brcm/emmc/bcm_emmc.h new file mode 100644 index 000000000..67f060229 --- /dev/null +++ b/include/drivers/brcm/emmc/bcm_emmc.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EMMC_H +#define EMMC_H + +#include <stdint.h> + +#include <common/debug.h> + +#include <platform_def.h> + +#include "emmc_chal_types.h" +#include "emmc_chal_sd.h" +#include "emmc_csl_sdprot.h" +#include "emmc_csl_sdcmd.h" +#include "emmc_pboot_hal_memory_drv.h" + +/* ------------------------------------------------------------------- */ +#define EXT_CSD_SIZE 512 + +#ifdef PLAT_SD_MAX_READ_LENGTH +#define SD_MAX_READ_LENGTH PLAT_SD_MAX_READ_LENGTH +#ifdef USE_EMMC_LARGE_BLK_TRANSFER_LENGTH +#define SD_MAX_BLK_TRANSFER_LENGTH 0x10000000 +#else +#define SD_MAX_BLK_TRANSFER_LENGTH 0x1000 +#endif +#else +#define SD_MAX_READ_LENGTH EMMC_BLOCK_SIZE +#define SD_MAX_BLK_TRANSFER_LENGTH EMMC_BLOCK_SIZE +#endif + +struct emmc_global_buffer { + union { + uint8_t Ext_CSD_storage[EXT_CSD_SIZE]; + uint8_t tempbuf[SD_MAX_READ_LENGTH]; + } u; +}; + +struct emmc_global_vars { + struct sd_card_data cardData; + struct sd_handle sdHandle; + struct sd_dev sdDevice; + struct sd_card_info sdCard; + unsigned int init_done; +}; + +#define ICFG_SDIO0_CAP0__SLOT_TYPE_R 27 +#define ICFG_SDIO0_CAP0__INT_MODE_R 26 +#define ICFG_SDIO0_CAP0__SYS_BUS_64BIT_R 25 +#define ICFG_SDIO0_CAP0__VOLTAGE_1P8V_R 24 +#define ICFG_SDIO0_CAP0__VOLTAGE_3P0V_R 23 +#define ICFG_SDIO0_CAP0__VOLTAGE_3P3V_R 22 +#define ICFG_SDIO0_CAP0__SUSPEND_RESUME_R 21 +#define ICFG_SDIO0_CAP0__SDMA_R 20 +#define ICFG_SDIO0_CAP0__HIGH_SPEED_R 19 +#define ICFG_SDIO0_CAP0__ADMA2_R 18 +#define ICFG_SDIO0_CAP0__EXTENDED_MEDIA_R 17 +#define ICFG_SDIO0_CAP0__MAX_BLOCK_LEN_R 15 +#define ICFG_SDIO0_CAP0__BASE_CLK_FREQ_R 7 +#define ICFG_SDIO0_CAP0__TIMEOUT_UNIT_R 6 +#define ICFG_SDIO0_CAP0__TIMEOUT_CLK_FREQ_R 0 +#define ICFG_SDIO0_CAP1__SPI_BLOCK_MODE_R 22 +#define ICFG_SDIO0_CAP1__SPI_MODE_R 21 +#define ICFG_SDIO0_CAP1__CLK_MULT_R 13 +#define ICFG_SDIO0_CAP1__RETUNING_MODE_R 11 +#define ICFG_SDIO0_CAP1__TUNE_SDR50_R 10 +#define ICFG_SDIO0_CAP1__TIME_RETUNE_R 6 +#define ICFG_SDIO0_CAP1__DRIVER_D_R 5 +#define ICFG_SDIO0_CAP1__DRIVER_C_R 4 +#define ICFG_SDIO0_CAP1__DRIVER_A_R 3 +#define ICFG_SDIO0_CAP1__DDR50_R 2 +#define ICFG_SDIO0_CAP1__SDR104_R 1 +#define ICFG_SDIO0_CAP1__SDR50_R 0 + +#define SDIO0_CTRL_REGS_BASE_ADDR (SDIO0_EMMCSDXC_SYSADDR) +#define SDIO0_IDM_RESET_CTRL_ADDR (SDIO_IDM0_IDM_RESET_CONTROL) + +#define EMMC_CTRL_REGS_BASE_ADDR SDIO0_CTRL_REGS_BASE_ADDR +#define EMMC_IDM_RESET_CTRL_ADDR SDIO0_IDM_RESET_CTRL_ADDR +#define EMMC_IDM_IO_CTRL_DIRECT_ADDR SDIO_IDM0_IO_CONTROL_DIRECT + +extern struct emmc_global_buffer *emmc_global_buf_ptr; + +extern struct emmc_global_vars *emmc_global_vars_ptr; + +#define EMMC_CARD_DETECT_TIMEOUT_MS 1200 +#define EMMC_CMD_TIMEOUT_MS 200 +#define EMMC_BUSY_CMD_TIMEOUT_MS 200 +#define EMMC_CLOCK_SETTING_TIMEOUT_MS 100 +#define EMMC_WFE_RETRY 40000 +#define EMMC_WFE_RETRY_DELAY_US 10 + +#ifdef EMMC_DEBUG +#define EMMC_TRACE INFO +#else +#define EMMC_TRACE(...) +#endif + +#endif /* EMMC_H */ diff --git a/include/drivers/brcm/emmc/emmc_api.h b/include/drivers/brcm/emmc/emmc_api.h new file mode 100644 index 000000000..c4c2a5803 --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_api.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EMMC_API_H +#define EMMC_API_H + +#include "bcm_emmc.h" +#include "emmc_pboot_hal_memory_drv.h" + +#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE +/* + * The erasable unit of the eMMC is the Erase Group + * Erase group is measured in write blocks which + * are the basic writable units of the Device + * EMMC_ERASE_GROUP_SIZE is the number of writeable + * units (each unit is 512 bytes) + */ + +/* Start address (sector) */ +#define EMMC_ERASE_START_BLOCK 0x0 +/* Number of blocks to be erased */ +#define EMMC_ERASE_BLOCK_COUNT 0x1 + +#define EMMC_ERASE_USER_AREA 0 +#define EMMC_ERASE_BOOT_PARTITION1 1 +#define EMMC_ERASE_BOOT_PARTITION2 2 + +/* eMMC partition to be erased */ +#define EMMC_ERASE_PARTITION EMMC_ERASE_USER_AREA +#endif + +uint32_t bcm_emmc_init(bool card_rdy_only); +void emmc_deinit(void); + +#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE +int emmc_erase(uintptr_t mem_addr, size_t num_of_blocks, uint32_t partition); +#endif + +uint32_t emmc_partition_select(uint32_t partition); +uint32_t emmc_read(uintptr_t mem_addr, uintptr_t storage_addr, + size_t storage_size, size_t bytes_to_read); +uint32_t emmc_write(uintptr_t mem_addr, uintptr_t data_addr, + size_t bytes_to_write); +#endif /* EMMC_API_H */ diff --git a/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h b/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h new file mode 100644 index 000000000..96c333da4 --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_brcm_rdb_sd4_top.h @@ -0,0 +1,1116 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BRCM_RDB_SD4_EMMC_TOP_H +#define BRCM_RDB_SD4_EMMC_TOP_H + +#define SD4_EMMC_TOP_SYSADDR_OFFSET 0x00000000 +#define SD4_EMMC_TOP_SYSADDR_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_SYSADDR_TYPE uint32_t +#define SD4_EMMC_TOP_SYSADDR_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_SYSADDR_SYSADDR_SHIFT 0 +#define SD4_EMMC_TOP_SYSADDR_SYSADDR_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_BLOCK_OFFSET 0x00000004 +#define SD4_EMMC_TOP_BLOCK_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_BLOCK_TYPE uint32_t +#define SD4_EMMC_TOP_BLOCK_RESERVED_MASK 0x00008000 +#define SD4_EMMC_TOP_BLOCK_BCNT_SHIFT 16 +#define SD4_EMMC_TOP_BLOCK_BCNT_MASK 0xFFFF0000 +#define SD4_EMMC_TOP_BLOCK_HSBS_SHIFT 12 +#define SD4_EMMC_TOP_BLOCK_HSBS_MASK 0x00007000 +#define SD4_EMMC_TOP_BLOCK_TBS_SHIFT 0 +#define SD4_EMMC_TOP_BLOCK_TBS_MASK 0x00000FFF + +#define SD4_EMMC_TOP_ARG_OFFSET 0x00000008 +#define SD4_EMMC_TOP_ARG_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_ARG_TYPE uint32_t +#define SD4_EMMC_TOP_ARG_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_ARG_ARG_SHIFT 0 +#define SD4_EMMC_TOP_ARG_ARG_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_CMD_OFFSET 0x0000000C +#define SD4_EMMC_TOP_CMD_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CMD_TYPE uint32_t +#define SD4_EMMC_TOP_CMD_RESERVED_MASK 0xC004FFC0 +#define SD4_EMMC_TOP_CMD_CIDX_SHIFT 24 +#define SD4_EMMC_TOP_CMD_CIDX_MASK 0x3F000000 +#define SD4_EMMC_TOP_CMD_CTYP_SHIFT 22 +#define SD4_EMMC_TOP_CMD_CTYP_MASK 0x00C00000 +#define SD4_EMMC_TOP_CMD_DPS_SHIFT 21 +#define SD4_EMMC_TOP_CMD_DPS_MASK 0x00200000 +#define SD4_EMMC_TOP_CMD_CCHK_EN_SHIFT 20 +#define SD4_EMMC_TOP_CMD_CCHK_EN_MASK 0x00100000 +#define SD4_EMMC_TOP_CMD_CRC_EN_SHIFT 19 +#define SD4_EMMC_TOP_CMD_CRC_EN_MASK 0x00080000 +#define SD4_EMMC_TOP_CMD_RTSEL_SHIFT 16 +#define SD4_EMMC_TOP_CMD_RTSEL_MASK 0x00030000 +#define SD4_EMMC_TOP_CMD_MSBS_SHIFT 5 +#define SD4_EMMC_TOP_CMD_MSBS_MASK 0x00000020 +#define SD4_EMMC_TOP_CMD_DTDS_SHIFT 4 +#define SD4_EMMC_TOP_CMD_DTDS_MASK 0x00000010 +#define SD4_EMMC_TOP_CMD_ACMDEN_SHIFT 2 +#define SD4_EMMC_TOP_CMD_ACMDEN_MASK 0x0000000C +#define SD4_EMMC_TOP_CMD_BCEN_SHIFT 1 +#define SD4_EMMC_TOP_CMD_BCEN_MASK 0x00000002 +#define SD4_EMMC_TOP_CMD_DMA_SHIFT 0 +#define SD4_EMMC_TOP_CMD_DMA_MASK 0x00000001 + +#define SD4_EMMC_TOP_CMD_SD4_OFFSET 0x0000000C +#define SD4_EMMC_TOP_CMD_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CMD_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_CMD_SD4_RESERVED_MASK 0xC004FE00 +#define SD4_EMMC_TOP_CMD_SD4_CIDX_SHIFT 24 +#define SD4_EMMC_TOP_CMD_SD4_CIDX_MASK 0x3F000000 +#define SD4_EMMC_TOP_CMD_SD4_CTYP_SHIFT 22 +#define SD4_EMMC_TOP_CMD_SD4_CTYP_MASK 0x00C00000 +#define SD4_EMMC_TOP_CMD_SD4_DPS_SHIFT 21 +#define SD4_EMMC_TOP_CMD_SD4_DPS_MASK 0x00200000 +#define SD4_EMMC_TOP_CMD_SD4_CCHK_EN_SHIFT 20 +#define SD4_EMMC_TOP_CMD_SD4_CCHK_EN_MASK 0x00100000 +#define SD4_EMMC_TOP_CMD_SD4_CRC_EN_SHIFT 19 +#define SD4_EMMC_TOP_CMD_SD4_CRC_EN_MASK 0x00080000 +#define SD4_EMMC_TOP_CMD_SD4_RTSEL_SHIFT 16 +#define SD4_EMMC_TOP_CMD_SD4_RTSEL_MASK 0x00030000 +#define SD4_EMMC_TOP_CMD_SD4_RESPIRQDIS_SHIFT 8 +#define SD4_EMMC_TOP_CMD_SD4_RESPIRQDIS_MASK 0x00000100 +#define SD4_EMMC_TOP_CMD_SD4_RESPERRCHKEN_SHIFT 7 +#define SD4_EMMC_TOP_CMD_SD4_RESPERRCHKEN_MASK 0x00000080 +#define SD4_EMMC_TOP_CMD_SD4_RESPR1R5_SHIFT 6 +#define SD4_EMMC_TOP_CMD_SD4_RESPR1R5_MASK 0x00000040 +#define SD4_EMMC_TOP_CMD_SD4_MSBS_SHIFT 5 +#define SD4_EMMC_TOP_CMD_SD4_MSBS_MASK 0x00000020 +#define SD4_EMMC_TOP_CMD_SD4_DTDS_SHIFT 4 +#define SD4_EMMC_TOP_CMD_SD4_DTDS_MASK 0x00000010 +#define SD4_EMMC_TOP_CMD_SD4_ACMDEN_SHIFT 2 +#define SD4_EMMC_TOP_CMD_SD4_ACMDEN_MASK 0x0000000C +#define SD4_EMMC_TOP_CMD_SD4_BCEN_SHIFT 1 +#define SD4_EMMC_TOP_CMD_SD4_BCEN_MASK 0x00000002 +#define SD4_EMMC_TOP_CMD_SD4_DMA_SHIFT 0 +#define SD4_EMMC_TOP_CMD_SD4_DMA_MASK 0x00000001 + +#define SD4_EMMC_TOP_RESP0_OFFSET 0x00000010 +#define SD4_EMMC_TOP_RESP0_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_RESP0_TYPE uint32_t +#define SD4_EMMC_TOP_RESP0_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_RESP0_RESP0_SHIFT 0 +#define SD4_EMMC_TOP_RESP0_RESP0_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_RESP2_OFFSET 0x00000014 +#define SD4_EMMC_TOP_RESP2_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_RESP2_TYPE uint32_t +#define SD4_EMMC_TOP_RESP2_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_RESP2_RESP2_SHIFT 0 +#define SD4_EMMC_TOP_RESP2_RESP2_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_RESP4_OFFSET 0x00000018 +#define SD4_EMMC_TOP_RESP4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_RESP4_TYPE uint32_t +#define SD4_EMMC_TOP_RESP4_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_RESP4_RESP4_SHIFT 0 +#define SD4_EMMC_TOP_RESP4_RESP4_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_RESP6_OFFSET 0x0000001C +#define SD4_EMMC_TOP_RESP6_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_RESP6_TYPE uint32_t +#define SD4_EMMC_TOP_RESP6_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_RESP6_RESP6_SHIFT 0 +#define SD4_EMMC_TOP_RESP6_RESP6_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_BUFDAT_OFFSET 0x00000020 +#define SD4_EMMC_TOP_BUFDAT_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_BUFDAT_TYPE uint32_t +#define SD4_EMMC_TOP_BUFDAT_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_BUFDAT_BUFDAT_SHIFT 0 +#define SD4_EMMC_TOP_BUFDAT_BUFDAT_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_PSTATE_OFFSET 0x00000024 +#define SD4_EMMC_TOP_PSTATE_DEFAULT 0x1FFC0000 +#define SD4_EMMC_TOP_PSTATE_TYPE uint32_t +#define SD4_EMMC_TOP_PSTATE_RESERVED_MASK 0xE000F0F0 +#define SD4_EMMC_TOP_PSTATE_DLS7_4_SHIFT 25 +#define SD4_EMMC_TOP_PSTATE_DLS7_4_MASK 0x1E000000 +#define SD4_EMMC_TOP_PSTATE_CLSL_SHIFT 24 +#define SD4_EMMC_TOP_PSTATE_CLSL_MASK 0x01000000 +#define SD4_EMMC_TOP_PSTATE_DLS3_0_SHIFT 20 +#define SD4_EMMC_TOP_PSTATE_DLS3_0_MASK 0x00F00000 +#define SD4_EMMC_TOP_PSTATE_WPSL_SHIFT 19 +#define SD4_EMMC_TOP_PSTATE_WPSL_MASK 0x00080000 +#define SD4_EMMC_TOP_PSTATE_CDPL_SHIFT 18 +#define SD4_EMMC_TOP_PSTATE_CDPL_MASK 0x00040000 +#define SD4_EMMC_TOP_PSTATE_CSS_SHIFT 17 +#define SD4_EMMC_TOP_PSTATE_CSS_MASK 0x00020000 +#define SD4_EMMC_TOP_PSTATE_CINS_SHIFT 16 +#define SD4_EMMC_TOP_PSTATE_CINS_MASK 0x00010000 +#define SD4_EMMC_TOP_PSTATE_BREN_SHIFT 11 +#define SD4_EMMC_TOP_PSTATE_BREN_MASK 0x00000800 +#define SD4_EMMC_TOP_PSTATE_BWEN_SHIFT 10 +#define SD4_EMMC_TOP_PSTATE_BWEN_MASK 0x00000400 +#define SD4_EMMC_TOP_PSTATE_RXACT_SHIFT 9 +#define SD4_EMMC_TOP_PSTATE_RXACT_MASK 0x00000200 +#define SD4_EMMC_TOP_PSTATE_WXACT_SHIFT 8 +#define SD4_EMMC_TOP_PSTATE_WXACT_MASK 0x00000100 +#define SD4_EMMC_TOP_PSTATE_RETUNE_REQ_SHIFT 3 +#define SD4_EMMC_TOP_PSTATE_RETUNE_REQ_MASK 0x00000008 +#define SD4_EMMC_TOP_PSTATE_DATACT_SHIFT 2 +#define SD4_EMMC_TOP_PSTATE_DATACT_MASK 0x00000004 +#define SD4_EMMC_TOP_PSTATE_DATINH_SHIFT 1 +#define SD4_EMMC_TOP_PSTATE_DATINH_MASK 0x00000002 +#define SD4_EMMC_TOP_PSTATE_CMDINH_SHIFT 0 +#define SD4_EMMC_TOP_PSTATE_CMDINH_MASK 0x00000001 + +#define SD4_EMMC_TOP_PSTATE_SD4_OFFSET 0x00000024 +#define SD4_EMMC_TOP_PSTATE_SD4_DEFAULT 0x01FC00F0 +#define SD4_EMMC_TOP_PSTATE_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_PSTATE_SD4_RESERVED_MASK 0x1E00F000 +#define SD4_EMMC_TOP_PSTATE_SD4_STBLDET_SHIFT 31 +#define SD4_EMMC_TOP_PSTATE_SD4_STBLDET_MASK 0x80000000 +#define SD4_EMMC_TOP_PSTATE_SD4_LANESYNC_SHIFT 30 +#define SD4_EMMC_TOP_PSTATE_SD4_LANESYNC_MASK 0x40000000 +#define SD4_EMMC_TOP_PSTATE_SD4_INDORMNTSTATE_SHIFT 29 +#define SD4_EMMC_TOP_PSTATE_SD4_INDORMNTSTATE_MASK 0x20000000 +#define SD4_EMMC_TOP_PSTATE_SD4_CLSL_SHIFT 24 +#define SD4_EMMC_TOP_PSTATE_SD4_CLSL_MASK 0x01000000 +#define SD4_EMMC_TOP_PSTATE_SD4_DLS3_0_SHIFT 20 +#define SD4_EMMC_TOP_PSTATE_SD4_DLS3_0_MASK 0x00F00000 +#define SD4_EMMC_TOP_PSTATE_SD4_WPSL_SHIFT 19 +#define SD4_EMMC_TOP_PSTATE_SD4_WPSL_MASK 0x00080000 +#define SD4_EMMC_TOP_PSTATE_SD4_CDPL_SHIFT 18 +#define SD4_EMMC_TOP_PSTATE_SD4_CDPL_MASK 0x00040000 +#define SD4_EMMC_TOP_PSTATE_SD4_CSS_SHIFT 17 +#define SD4_EMMC_TOP_PSTATE_SD4_CSS_MASK 0x00020000 +#define SD4_EMMC_TOP_PSTATE_SD4_CINS_SHIFT 16 +#define SD4_EMMC_TOP_PSTATE_SD4_CINS_MASK 0x00010000 +#define SD4_EMMC_TOP_PSTATE_SD4_BREN_SHIFT 11 +#define SD4_EMMC_TOP_PSTATE_SD4_BREN_MASK 0x00000800 +#define SD4_EMMC_TOP_PSTATE_SD4_BWEN_SHIFT 10 +#define SD4_EMMC_TOP_PSTATE_SD4_BWEN_MASK 0x00000400 +#define SD4_EMMC_TOP_PSTATE_SD4_RXACT_SHIFT 9 +#define SD4_EMMC_TOP_PSTATE_SD4_RXACT_MASK 0x00000200 +#define SD4_EMMC_TOP_PSTATE_SD4_WXACT_SHIFT 8 +#define SD4_EMMC_TOP_PSTATE_SD4_WXACT_MASK 0x00000100 +#define SD4_EMMC_TOP_PSTATE_SD4_DLS7_4_SHIFT 4 +#define SD4_EMMC_TOP_PSTATE_SD4_DLS7_4_MASK 0x000000F0 +#define SD4_EMMC_TOP_PSTATE_SD4_RETUNE_REQ_SHIFT 3 +#define SD4_EMMC_TOP_PSTATE_SD4_RETUNE_REQ_MASK 0x00000008 +#define SD4_EMMC_TOP_PSTATE_SD4_DATACT_SHIFT 2 +#define SD4_EMMC_TOP_PSTATE_SD4_DATACT_MASK 0x00000004 +#define SD4_EMMC_TOP_PSTATE_SD4_DATINH_SHIFT 1 +#define SD4_EMMC_TOP_PSTATE_SD4_DATINH_MASK 0x00000002 +#define SD4_EMMC_TOP_PSTATE_SD4_CMDINH_SHIFT 0 +#define SD4_EMMC_TOP_PSTATE_SD4_CMDINH_MASK 0x00000001 + +#define SD4_EMMC_TOP_CTRL_OFFSET 0x00000028 +#define SD4_EMMC_TOP_CTRL_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CTRL_TYPE uint32_t +#define SD4_EMMC_TOP_CTRL_RESERVED_MASK 0xF800E000 +#define SD4_EMMC_TOP_CTRL_WAKENRMV_SHIFT 26 +#define SD4_EMMC_TOP_CTRL_WAKENRMV_MASK 0x04000000 +#define SD4_EMMC_TOP_CTRL_WAKENINS_SHIFT 25 +#define SD4_EMMC_TOP_CTRL_WAKENINS_MASK 0x02000000 +#define SD4_EMMC_TOP_CTRL_WAKENIRQ_SHIFT 24 +#define SD4_EMMC_TOP_CTRL_WAKENIRQ_MASK 0x01000000 +#define SD4_EMMC_TOP_CTRL_BOOTACK_SHIFT 23 +#define SD4_EMMC_TOP_CTRL_BOOTACK_MASK 0x00800000 +#define SD4_EMMC_TOP_CTRL_ATLBOOTEN_SHIFT 22 +#define SD4_EMMC_TOP_CTRL_ATLBOOTEN_MASK 0x00400000 +#define SD4_EMMC_TOP_CTRL_BOOTEN_SHIFT 21 +#define SD4_EMMC_TOP_CTRL_BOOTEN_MASK 0x00200000 +#define SD4_EMMC_TOP_CTRL_SPIMODE_SHIFT 20 +#define SD4_EMMC_TOP_CTRL_SPIMODE_MASK 0x00100000 +#define SD4_EMMC_TOP_CTRL_BLKIRQ_SHIFT 19 +#define SD4_EMMC_TOP_CTRL_BLKIRQ_MASK 0x00080000 +#define SD4_EMMC_TOP_CTRL_RDWTCRTL_SHIFT 18 +#define SD4_EMMC_TOP_CTRL_RDWTCRTL_MASK 0x00040000 +#define SD4_EMMC_TOP_CTRL_CONTREQ_SHIFT 17 +#define SD4_EMMC_TOP_CTRL_CONTREQ_MASK 0x00020000 +#define SD4_EMMC_TOP_CTRL_BLKSTPREQ_SHIFT 16 +#define SD4_EMMC_TOP_CTRL_BLKSTPREQ_MASK 0x00010000 +#define SD4_EMMC_TOP_CTRL_HRESET_SHIFT 12 +#define SD4_EMMC_TOP_CTRL_HRESET_MASK 0x00001000 +#define SD4_EMMC_TOP_CTRL_SDVSELVDD1_SHIFT 9 +#define SD4_EMMC_TOP_CTRL_SDVSELVDD1_MASK 0x00000E00 +#define SD4_EMMC_TOP_CTRL_SDPWR_SHIFT 8 +#define SD4_EMMC_TOP_CTRL_SDPWR_MASK 0x00000100 +#define SD4_EMMC_TOP_CTRL_CDSD_SHIFT 7 +#define SD4_EMMC_TOP_CTRL_CDSD_MASK 0x00000080 +#define SD4_EMMC_TOP_CTRL_CDTL_SHIFT 6 +#define SD4_EMMC_TOP_CTRL_CDTL_MASK 0x00000040 +#define SD4_EMMC_TOP_CTRL_SDB_SHIFT 5 +#define SD4_EMMC_TOP_CTRL_SDB_MASK 0x00000020 +#define SD4_EMMC_TOP_CTRL_DMASEL_SHIFT 3 +#define SD4_EMMC_TOP_CTRL_DMASEL_MASK 0x00000018 +#define SD4_EMMC_TOP_CTRL_HSEN_SHIFT 2 +#define SD4_EMMC_TOP_CTRL_HSEN_MASK 0x00000004 +#define SD4_EMMC_TOP_CTRL_DXTW_SHIFT 1 +#define SD4_EMMC_TOP_CTRL_DXTW_MASK 0x00000002 +#define SD4_EMMC_TOP_CTRL_LEDCTL_SHIFT 0 +#define SD4_EMMC_TOP_CTRL_LEDCTL_MASK 0x00000001 + +#define SD4_EMMC_TOP_CTRL_SD4_OFFSET 0x00000028 +#define SD4_EMMC_TOP_CTRL_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CTRL_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_CTRL_SD4_RESERVED_MASK 0xF8F00000 +#define SD4_EMMC_TOP_CTRL_SD4_WAKENRMV_SHIFT 26 +#define SD4_EMMC_TOP_CTRL_SD4_WAKENRMV_MASK 0x04000000 +#define SD4_EMMC_TOP_CTRL_SD4_WAKENINS_SHIFT 25 +#define SD4_EMMC_TOP_CTRL_SD4_WAKENINS_MASK 0x02000000 +#define SD4_EMMC_TOP_CTRL_SD4_WAKENIRQ_SHIFT 24 +#define SD4_EMMC_TOP_CTRL_SD4_WAKENIRQ_MASK 0x01000000 +#define SD4_EMMC_TOP_CTRL_SD4_BLKIRQ_SHIFT 19 +#define SD4_EMMC_TOP_CTRL_SD4_BLKIRQ_MASK 0x00080000 +#define SD4_EMMC_TOP_CTRL_SD4_RDWTCRTL_SHIFT 18 +#define SD4_EMMC_TOP_CTRL_SD4_RDWTCRTL_MASK 0x00040000 +#define SD4_EMMC_TOP_CTRL_SD4_CONTREQ_SHIFT 17 +#define SD4_EMMC_TOP_CTRL_SD4_CONTREQ_MASK 0x00020000 +#define SD4_EMMC_TOP_CTRL_SD4_BLKSTPREQ_SHIFT 16 +#define SD4_EMMC_TOP_CTRL_SD4_BLKSTPREQ_MASK 0x00010000 +#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD2_SHIFT 13 +#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD2_MASK 0x0000E000 +#define SD4_EMMC_TOP_CTRL_SD4_SDPWRVDD2_SHIFT 12 +#define SD4_EMMC_TOP_CTRL_SD4_SDPWRVDD2_MASK 0x00001000 +#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD1_SHIFT 9 +#define SD4_EMMC_TOP_CTRL_SD4_SDVSELVDD1_MASK 0x00000E00 +#define SD4_EMMC_TOP_CTRL_SD4_SDPWR_SHIFT 8 +#define SD4_EMMC_TOP_CTRL_SD4_SDPWR_MASK 0x00000100 +#define SD4_EMMC_TOP_CTRL_SD4_CDSD_SHIFT 7 +#define SD4_EMMC_TOP_CTRL_SD4_CDSD_MASK 0x00000080 +#define SD4_EMMC_TOP_CTRL_SD4_CDTL_SHIFT 6 +#define SD4_EMMC_TOP_CTRL_SD4_CDTL_MASK 0x00000040 +#define SD4_EMMC_TOP_CTRL_SD4_SDB_SHIFT 5 +#define SD4_EMMC_TOP_CTRL_SD4_SDB_MASK 0x00000020 +#define SD4_EMMC_TOP_CTRL_SD4_DMASEL_SHIFT 3 +#define SD4_EMMC_TOP_CTRL_SD4_DMASEL_MASK 0x00000018 +#define SD4_EMMC_TOP_CTRL_SD4_HSEN_SHIFT 2 +#define SD4_EMMC_TOP_CTRL_SD4_HSEN_MASK 0x00000004 +#define SD4_EMMC_TOP_CTRL_SD4_DXTW_SHIFT 1 +#define SD4_EMMC_TOP_CTRL_SD4_DXTW_MASK 0x00000002 +#define SD4_EMMC_TOP_CTRL_SD4_LEDCTL_SHIFT 0 +#define SD4_EMMC_TOP_CTRL_SD4_LEDCTL_MASK 0x00000001 + +#define SD4_EMMC_TOP_CTRL1_OFFSET 0x0000002C +#define SD4_EMMC_TOP_CTRL1_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CTRL1_TYPE uint32_t +#define SD4_EMMC_TOP_CTRL1_RESERVED_MASK 0xF8F00018 +#define SD4_EMMC_TOP_CTRL1_DATRST_SHIFT 26 +#define SD4_EMMC_TOP_CTRL1_DATRST_MASK 0x04000000 +#define SD4_EMMC_TOP_CTRL1_CMDRST_SHIFT 25 +#define SD4_EMMC_TOP_CTRL1_CMDRST_MASK 0x02000000 +#define SD4_EMMC_TOP_CTRL1_RST_SHIFT 24 +#define SD4_EMMC_TOP_CTRL1_RST_MASK 0x01000000 +#define SD4_EMMC_TOP_CTRL1_DTCNT_SHIFT 16 +#define SD4_EMMC_TOP_CTRL1_DTCNT_MASK 0x000F0000 +#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_SHIFT 8 +#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_MASK 0x0000FF00 +#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_SHIFT 6 +#define SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_MASK 0x000000C0 +#define SD4_EMMC_TOP_CTRL1_CLKGENSEL_SHIFT 5 +#define SD4_EMMC_TOP_CTRL1_CLKGENSEL_MASK 0x00000020 +#define SD4_EMMC_TOP_CTRL1_SDCLKEN_SHIFT 2 +#define SD4_EMMC_TOP_CTRL1_SDCLKEN_MASK 0x00000004 +#define SD4_EMMC_TOP_CTRL1_ICLKSTB_SHIFT 1 +#define SD4_EMMC_TOP_CTRL1_ICLKSTB_MASK 0x00000002 +#define SD4_EMMC_TOP_CTRL1_ICLKEN_SHIFT 0 +#define SD4_EMMC_TOP_CTRL1_ICLKEN_MASK 0x00000001 + +#define SD4_EMMC_TOP_INTR_OFFSET 0x00000030 +#define SD4_EMMC_TOP_INTR_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_INTR_TYPE uint32_t +#define SD4_EMMC_TOP_INTR_RESERVED_MASK 0xEC000000 +#define SD4_EMMC_TOP_INTR_TRESPERR_SHIFT 28 +#define SD4_EMMC_TOP_INTR_TRESPERR_MASK 0x10000000 +#define SD4_EMMC_TOP_INTR_ADMAERR_SHIFT 25 +#define SD4_EMMC_TOP_INTR_ADMAERR_MASK 0x02000000 +#define SD4_EMMC_TOP_INTR_CMDERROR_SHIFT 24 +#define SD4_EMMC_TOP_INTR_CMDERROR_MASK 0x01000000 +#define SD4_EMMC_TOP_INTR_IERR_SHIFT 23 +#define SD4_EMMC_TOP_INTR_IERR_MASK 0x00800000 +#define SD4_EMMC_TOP_INTR_DEBERR_SHIFT 22 +#define SD4_EMMC_TOP_INTR_DEBERR_MASK 0x00400000 +#define SD4_EMMC_TOP_INTR_DCRCERR_SHIFT 21 +#define SD4_EMMC_TOP_INTR_DCRCERR_MASK 0x00200000 +#define SD4_EMMC_TOP_INTR_DTOERR_SHIFT 20 +#define SD4_EMMC_TOP_INTR_DTOERR_MASK 0x00100000 +#define SD4_EMMC_TOP_INTR_CMDIDXERR_SHIFT 19 +#define SD4_EMMC_TOP_INTR_CMDIDXERR_MASK 0x00080000 +#define SD4_EMMC_TOP_INTR_CEBERR_SHIFT 18 +#define SD4_EMMC_TOP_INTR_CEBERR_MASK 0x00040000 +#define SD4_EMMC_TOP_INTR_CCRCERR_SHIFT 17 +#define SD4_EMMC_TOP_INTR_CCRCERR_MASK 0x00020000 +#define SD4_EMMC_TOP_INTR_CTOERR_SHIFT 16 +#define SD4_EMMC_TOP_INTR_CTOERR_MASK 0x00010000 +#define SD4_EMMC_TOP_INTR_ERRIRQ_SHIFT 15 +#define SD4_EMMC_TOP_INTR_ERRIRQ_MASK 0x00008000 +#define SD4_EMMC_TOP_INTR_BTIRQ_SHIFT 14 +#define SD4_EMMC_TOP_INTR_BTIRQ_MASK 0x00004000 +#define SD4_EMMC_TOP_INTR_BTACKRX_SHIFT 13 +#define SD4_EMMC_TOP_INTR_BTACKRX_MASK 0x00002000 +#define SD4_EMMC_TOP_INTR_RETUNE_EVENT_SHIFT 12 +#define SD4_EMMC_TOP_INTR_RETUNE_EVENT_MASK 0x00001000 +#define SD4_EMMC_TOP_INTR_INT_C_SHIFT 11 +#define SD4_EMMC_TOP_INTR_INT_C_MASK 0x00000800 +#define SD4_EMMC_TOP_INTR_INT_B_SHIFT 10 +#define SD4_EMMC_TOP_INTR_INT_B_MASK 0x00000400 +#define SD4_EMMC_TOP_INTR_INT_A_SHIFT 9 +#define SD4_EMMC_TOP_INTR_INT_A_MASK 0x00000200 +#define SD4_EMMC_TOP_INTR_CRDIRQ_SHIFT 8 +#define SD4_EMMC_TOP_INTR_CRDIRQ_MASK 0x00000100 +#define SD4_EMMC_TOP_INTR_CRDRMV_SHIFT 7 +#define SD4_EMMC_TOP_INTR_CRDRMV_MASK 0x00000080 +#define SD4_EMMC_TOP_INTR_CRDINS_SHIFT 6 +#define SD4_EMMC_TOP_INTR_CRDINS_MASK 0x00000040 +#define SD4_EMMC_TOP_INTR_BRRDY_SHIFT 5 +#define SD4_EMMC_TOP_INTR_BRRDY_MASK 0x00000020 +#define SD4_EMMC_TOP_INTR_BWRDY_SHIFT 4 +#define SD4_EMMC_TOP_INTR_BWRDY_MASK 0x00000010 +#define SD4_EMMC_TOP_INTR_DMAIRQ_SHIFT 3 +#define SD4_EMMC_TOP_INTR_DMAIRQ_MASK 0x00000008 +#define SD4_EMMC_TOP_INTR_BLKENT_SHIFT 2 +#define SD4_EMMC_TOP_INTR_BLKENT_MASK 0x00000004 +#define SD4_EMMC_TOP_INTR_TXDONE_SHIFT 1 +#define SD4_EMMC_TOP_INTR_TXDONE_MASK 0x00000002 +#define SD4_EMMC_TOP_INTR_CMDDONE_SHIFT 0 +#define SD4_EMMC_TOP_INTR_CMDDONE_MASK 0x00000001 + +#define SD4_EMMC_TOP_INTR_SD4_OFFSET 0x00000030 +#define SD4_EMMC_TOP_INTR_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_INTR_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_INTR_SD4_RESERVED_MASK 0xF0006000 +#define SD4_EMMC_TOP_INTR_SD4_TRESPERR_SHIFT 27 +#define SD4_EMMC_TOP_INTR_SD4_TRESPERR_MASK 0x08000000 +#define SD4_EMMC_TOP_INTR_SD4_TUNEERR_SHIFT 26 +#define SD4_EMMC_TOP_INTR_SD4_TUNEERR_MASK 0x04000000 +#define SD4_EMMC_TOP_INTR_SD4_ADMAERR_SHIFT 25 +#define SD4_EMMC_TOP_INTR_SD4_ADMAERR_MASK 0x02000000 +#define SD4_EMMC_TOP_INTR_SD4_CMDERROR_SHIFT 24 +#define SD4_EMMC_TOP_INTR_SD4_CMDERROR_MASK 0x01000000 +#define SD4_EMMC_TOP_INTR_SD4_IERR_SHIFT 23 +#define SD4_EMMC_TOP_INTR_SD4_IERR_MASK 0x00800000 +#define SD4_EMMC_TOP_INTR_SD4_DEBERR_SHIFT 22 +#define SD4_EMMC_TOP_INTR_SD4_DEBERR_MASK 0x00400000 +#define SD4_EMMC_TOP_INTR_SD4_DCRCERR_SHIFT 21 +#define SD4_EMMC_TOP_INTR_SD4_DCRCERR_MASK 0x00200000 +#define SD4_EMMC_TOP_INTR_SD4_DTOERR_SHIFT 20 +#define SD4_EMMC_TOP_INTR_SD4_DTOERR_MASK 0x00100000 +#define SD4_EMMC_TOP_INTR_SD4_CMDIDXERR_SHIFT 19 +#define SD4_EMMC_TOP_INTR_SD4_CMDIDXERR_MASK 0x00080000 +#define SD4_EMMC_TOP_INTR_SD4_CEBERR_SHIFT 18 +#define SD4_EMMC_TOP_INTR_SD4_CEBERR_MASK 0x00040000 +#define SD4_EMMC_TOP_INTR_SD4_CCRCERR_SHIFT 17 +#define SD4_EMMC_TOP_INTR_SD4_CCRCERR_MASK 0x00020000 +#define SD4_EMMC_TOP_INTR_SD4_CTOERR_SHIFT 16 +#define SD4_EMMC_TOP_INTR_SD4_CTOERR_MASK 0x00010000 +#define SD4_EMMC_TOP_INTR_SD4_ERRIRQ_SHIFT 15 +#define SD4_EMMC_TOP_INTR_SD4_ERRIRQ_MASK 0x00008000 +#define SD4_EMMC_TOP_INTR_SD4_RETUNE_EVENT_SHIFT 12 +#define SD4_EMMC_TOP_INTR_SD4_RETUNE_EVENT_MASK 0x00001000 +#define SD4_EMMC_TOP_INTR_SD4_INT_C_SHIFT 11 +#define SD4_EMMC_TOP_INTR_SD4_INT_C_MASK 0x00000800 +#define SD4_EMMC_TOP_INTR_SD4_INT_B_SHIFT 10 +#define SD4_EMMC_TOP_INTR_SD4_INT_B_MASK 0x00000400 +#define SD4_EMMC_TOP_INTR_SD4_INT_A_SHIFT 9 +#define SD4_EMMC_TOP_INTR_SD4_INT_A_MASK 0x00000200 +#define SD4_EMMC_TOP_INTR_SD4_CRDIRQ_SHIFT 8 +#define SD4_EMMC_TOP_INTR_SD4_CRDIRQ_MASK 0x00000100 +#define SD4_EMMC_TOP_INTR_SD4_CRDRMV_SHIFT 7 +#define SD4_EMMC_TOP_INTR_SD4_CRDRMV_MASK 0x00000080 +#define SD4_EMMC_TOP_INTR_SD4_CRDINS_SHIFT 6 +#define SD4_EMMC_TOP_INTR_SD4_CRDINS_MASK 0x00000040 +#define SD4_EMMC_TOP_INTR_SD4_BRRDY_SHIFT 5 +#define SD4_EMMC_TOP_INTR_SD4_BRRDY_MASK 0x00000020 +#define SD4_EMMC_TOP_INTR_SD4_BWRDY_SHIFT 4 +#define SD4_EMMC_TOP_INTR_SD4_BWRDY_MASK 0x00000010 +#define SD4_EMMC_TOP_INTR_SD4_DMAIRQ_SHIFT 3 +#define SD4_EMMC_TOP_INTR_SD4_DMAIRQ_MASK 0x00000008 +#define SD4_EMMC_TOP_INTR_SD4_BLKENT_SHIFT 2 +#define SD4_EMMC_TOP_INTR_SD4_BLKENT_MASK 0x00000004 +#define SD4_EMMC_TOP_INTR_SD4_TXDONE_SHIFT 1 +#define SD4_EMMC_TOP_INTR_SD4_TXDONE_MASK 0x00000002 +#define SD4_EMMC_TOP_INTR_SD4_CMDDONE_SHIFT 0 +#define SD4_EMMC_TOP_INTR_SD4_CMDDONE_MASK 0x00000001 + +#define SD4_EMMC_TOP_INTREN1_OFFSET 0x00000034 +#define SD4_EMMC_TOP_INTREN1_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_INTREN1_TYPE uint32_t +#define SD4_EMMC_TOP_INTREN1_RESERVED_MASK 0xEC000000 +#define SD4_EMMC_TOP_INTREN1_TRESPERREN_SHIFT 28 +#define SD4_EMMC_TOP_INTREN1_TRESPERREN_MASK 0x10000000 +#define SD4_EMMC_TOP_INTREN1_ADMAEREN_SHIFT 25 +#define SD4_EMMC_TOP_INTREN1_ADMAEREN_MASK 0x02000000 +#define SD4_EMMC_TOP_INTREN1_CMDERREN_SHIFT 24 +#define SD4_EMMC_TOP_INTREN1_CMDERREN_MASK 0x01000000 +#define SD4_EMMC_TOP_INTREN1_ILIMERREN_SHIFT 23 +#define SD4_EMMC_TOP_INTREN1_ILIMERREN_MASK 0x00800000 +#define SD4_EMMC_TOP_INTREN1_DEBERREN_SHIFT 22 +#define SD4_EMMC_TOP_INTREN1_DEBERREN_MASK 0x00400000 +#define SD4_EMMC_TOP_INTREN1_DCRCERREN_SHIFT 21 +#define SD4_EMMC_TOP_INTREN1_DCRCERREN_MASK 0x00200000 +#define SD4_EMMC_TOP_INTREN1_DTOERREN_SHIFT 20 +#define SD4_EMMC_TOP_INTREN1_DTOERREN_MASK 0x00100000 +#define SD4_EMMC_TOP_INTREN1_CIDXERREN_SHIFT 19 +#define SD4_EMMC_TOP_INTREN1_CIDXERREN_MASK 0x00080000 +#define SD4_EMMC_TOP_INTREN1_CEBERREN_SHIFT 18 +#define SD4_EMMC_TOP_INTREN1_CEBERREN_MASK 0x00040000 +#define SD4_EMMC_TOP_INTREN1_CMDCRCEN_SHIFT 17 +#define SD4_EMMC_TOP_INTREN1_CMDCRCEN_MASK 0x00020000 +#define SD4_EMMC_TOP_INTREN1_CMDTOEN_SHIFT 16 +#define SD4_EMMC_TOP_INTREN1_CMDTOEN_MASK 0x00010000 +#define SD4_EMMC_TOP_INTREN1_FIXZ_SHIFT 15 +#define SD4_EMMC_TOP_INTREN1_FIXZ_MASK 0x00008000 +#define SD4_EMMC_TOP_INTREN1_BTIRQEN_SHIFT 14 +#define SD4_EMMC_TOP_INTREN1_BTIRQEN_MASK 0x00004000 +#define SD4_EMMC_TOP_INTREN1_BTACKRXEN_SHIFT 13 +#define SD4_EMMC_TOP_INTREN1_BTACKRXEN_MASK 0x00002000 +#define SD4_EMMC_TOP_INTREN1_RETUNE_EVENTEN_SHIFT 12 +#define SD4_EMMC_TOP_INTREN1_RETUNE_EVENTEN_MASK 0x00001000 +#define SD4_EMMC_TOP_INTREN1_INT_C_EN_SHIFT 11 +#define SD4_EMMC_TOP_INTREN1_INT_C_EN_MASK 0x00000800 +#define SD4_EMMC_TOP_INTREN1_INT_B_EN_SHIFT 10 +#define SD4_EMMC_TOP_INTREN1_INT_B_EN_MASK 0x00000400 +#define SD4_EMMC_TOP_INTREN1_INT_A_EN_SHIFT 9 +#define SD4_EMMC_TOP_INTREN1_INT_A_EN_MASK 0x00000200 +#define SD4_EMMC_TOP_INTREN1_CIRQEN_SHIFT 8 +#define SD4_EMMC_TOP_INTREN1_CIRQEN_MASK 0x00000100 +#define SD4_EMMC_TOP_INTREN1_CRDRMVEN_SHIFT 7 +#define SD4_EMMC_TOP_INTREN1_CRDRMVEN_MASK 0x00000080 +#define SD4_EMMC_TOP_INTREN1_CRDINSEN_SHIFT 6 +#define SD4_EMMC_TOP_INTREN1_CRDINSEN_MASK 0x00000040 +#define SD4_EMMC_TOP_INTREN1_BUFRREN_SHIFT 5 +#define SD4_EMMC_TOP_INTREN1_BUFRREN_MASK 0x00000020 +#define SD4_EMMC_TOP_INTREN1_BUFWREN_SHIFT 4 +#define SD4_EMMC_TOP_INTREN1_BUFWREN_MASK 0x00000010 +#define SD4_EMMC_TOP_INTREN1_DMAIRQEN_SHIFT 3 +#define SD4_EMMC_TOP_INTREN1_DMAIRQEN_MASK 0x00000008 +#define SD4_EMMC_TOP_INTREN1_BLKEN_SHIFT 2 +#define SD4_EMMC_TOP_INTREN1_BLKEN_MASK 0x00000004 +#define SD4_EMMC_TOP_INTREN1_TXDONEEN_SHIFT 1 +#define SD4_EMMC_TOP_INTREN1_TXDONEEN_MASK 0x00000002 +#define SD4_EMMC_TOP_INTREN1_CMDDONEEN_SHIFT 0 +#define SD4_EMMC_TOP_INTREN1_CMDDONEEN_MASK 0x00000001 + +#define SD4_EMMC_TOP_INTREN1_SD4_OFFSET 0x00000034 +#define SD4_EMMC_TOP_INTREN1_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_INTREN1_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_INTREN1_SD4_RESERVED_MASK 0x00006000 +#define SD4_EMMC_TOP_INTREN1_SD4_VNDRERREN_SHIFT 28 +#define SD4_EMMC_TOP_INTREN1_SD4_VNDRERREN_MASK 0xF0000000 +#define SD4_EMMC_TOP_INTREN1_SD4_TRESPERREN_SHIFT 27 +#define SD4_EMMC_TOP_INTREN1_SD4_TRESPERREN_MASK 0x08000000 +#define SD4_EMMC_TOP_INTREN1_SD4_TUNEERREN_SHIFT 26 +#define SD4_EMMC_TOP_INTREN1_SD4_TUNEERREN_MASK 0x04000000 +#define SD4_EMMC_TOP_INTREN1_SD4_ADMAEREN_SHIFT 25 +#define SD4_EMMC_TOP_INTREN1_SD4_ADMAEREN_MASK 0x02000000 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDERREN_SHIFT 24 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDERREN_MASK 0x01000000 +#define SD4_EMMC_TOP_INTREN1_SD4_ILIMERREN_SHIFT 23 +#define SD4_EMMC_TOP_INTREN1_SD4_ILIMERREN_MASK 0x00800000 +#define SD4_EMMC_TOP_INTREN1_SD4_DEBERREN_SHIFT 22 +#define SD4_EMMC_TOP_INTREN1_SD4_DEBERREN_MASK 0x00400000 +#define SD4_EMMC_TOP_INTREN1_SD4_DCRCERREN_SHIFT 21 +#define SD4_EMMC_TOP_INTREN1_SD4_DCRCERREN_MASK 0x00200000 +#define SD4_EMMC_TOP_INTREN1_SD4_DTOERREN_SHIFT 20 +#define SD4_EMMC_TOP_INTREN1_SD4_DTOERREN_MASK 0x00100000 +#define SD4_EMMC_TOP_INTREN1_SD4_CIDXERREN_SHIFT 19 +#define SD4_EMMC_TOP_INTREN1_SD4_CIDXERREN_MASK 0x00080000 +#define SD4_EMMC_TOP_INTREN1_SD4_CEBERREN_SHIFT 18 +#define SD4_EMMC_TOP_INTREN1_SD4_CEBERREN_MASK 0x00040000 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDCRCEN_SHIFT 17 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDCRCEN_MASK 0x00020000 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDTOEN_SHIFT 16 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDTOEN_MASK 0x00010000 +#define SD4_EMMC_TOP_INTREN1_SD4_FIXZ_SHIFT 15 +#define SD4_EMMC_TOP_INTREN1_SD4_FIXZ_MASK 0x00008000 +#define SD4_EMMC_TOP_INTREN1_SD4_RETUNE_EVENTEN_SHIFT 12 +#define SD4_EMMC_TOP_INTREN1_SD4_RETUNE_EVENTEN_MASK 0x00001000 +#define SD4_EMMC_TOP_INTREN1_SD4_INT_C_EN_SHIFT 11 +#define SD4_EMMC_TOP_INTREN1_SD4_INT_C_EN_MASK 0x00000800 +#define SD4_EMMC_TOP_INTREN1_SD4_INT_B_EN_SHIFT 10 +#define SD4_EMMC_TOP_INTREN1_SD4_INT_B_EN_MASK 0x00000400 +#define SD4_EMMC_TOP_INTREN1_SD4_INT_A_EN_SHIFT 9 +#define SD4_EMMC_TOP_INTREN1_SD4_INT_A_EN_MASK 0x00000200 +#define SD4_EMMC_TOP_INTREN1_SD4_CIRQEN_SHIFT 8 +#define SD4_EMMC_TOP_INTREN1_SD4_CIRQEN_MASK 0x00000100 +#define SD4_EMMC_TOP_INTREN1_SD4_CRDRMVEN_SHIFT 7 +#define SD4_EMMC_TOP_INTREN1_SD4_CRDRMVEN_MASK 0x00000080 +#define SD4_EMMC_TOP_INTREN1_SD4_CRDINSEN_SHIFT 6 +#define SD4_EMMC_TOP_INTREN1_SD4_CRDINSEN_MASK 0x00000040 +#define SD4_EMMC_TOP_INTREN1_SD4_BUFRREN_SHIFT 5 +#define SD4_EMMC_TOP_INTREN1_SD4_BUFRREN_MASK 0x00000020 +#define SD4_EMMC_TOP_INTREN1_SD4_BUFWREN_SHIFT 4 +#define SD4_EMMC_TOP_INTREN1_SD4_BUFWREN_MASK 0x00000010 +#define SD4_EMMC_TOP_INTREN1_SD4_DMAIRQEN_SHIFT 3 +#define SD4_EMMC_TOP_INTREN1_SD4_DMAIRQEN_MASK 0x00000008 +#define SD4_EMMC_TOP_INTREN1_SD4_BLKEN_SHIFT 2 +#define SD4_EMMC_TOP_INTREN1_SD4_BLKEN_MASK 0x00000004 +#define SD4_EMMC_TOP_INTREN1_SD4_TXDONEEN_SHIFT 1 +#define SD4_EMMC_TOP_INTREN1_SD4_TXDONEEN_MASK 0x00000002 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDDONEEN_SHIFT 0 +#define SD4_EMMC_TOP_INTREN1_SD4_CMDDONEEN_MASK 0x00000001 + +#define SD4_EMMC_TOP_INTREN2_OFFSET 0x00000038 +#define SD4_EMMC_TOP_INTREN2_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_INTREN2_TYPE uint32_t +#define SD4_EMMC_TOP_INTREN2_RESERVED_MASK 0xEC000000 +#define SD4_EMMC_TOP_INTREN2_TRESPERRSEN_SHIFT 28 +#define SD4_EMMC_TOP_INTREN2_TRESPERRSEN_MASK 0x10000000 +#define SD4_EMMC_TOP_INTREN2_ADMASIGEN_SHIFT 25 +#define SD4_EMMC_TOP_INTREN2_ADMASIGEN_MASK 0x02000000 +#define SD4_EMMC_TOP_INTREN2_CMDSIGEN_SHIFT 24 +#define SD4_EMMC_TOP_INTREN2_CMDSIGEN_MASK 0x01000000 +#define SD4_EMMC_TOP_INTREN2_ILIMSIGEN_SHIFT 23 +#define SD4_EMMC_TOP_INTREN2_ILIMSIGEN_MASK 0x00800000 +#define SD4_EMMC_TOP_INTREN2_DEBSIGEN_SHIFT 22 +#define SD4_EMMC_TOP_INTREN2_DEBSIGEN_MASK 0x00400000 +#define SD4_EMMC_TOP_INTREN2_DCRCSIGEN_SHIFT 21 +#define SD4_EMMC_TOP_INTREN2_DCRCSIGEN_MASK 0x00200000 +#define SD4_EMMC_TOP_INTREN2_DTOSIGEN_SHIFT 20 +#define SD4_EMMC_TOP_INTREN2_DTOSIGEN_MASK 0x00100000 +#define SD4_EMMC_TOP_INTREN2_CIDXSIGEN_SHIFT 19 +#define SD4_EMMC_TOP_INTREN2_CIDXSIGEN_MASK 0x00080000 +#define SD4_EMMC_TOP_INTREN2_CEBSIGEN_SHIFT 18 +#define SD4_EMMC_TOP_INTREN2_CEBSIGEN_MASK 0x00040000 +#define SD4_EMMC_TOP_INTREN2_CMDCRCSIGEN_SHIFT 17 +#define SD4_EMMC_TOP_INTREN2_CMDCRCSIGEN_MASK 0x00020000 +#define SD4_EMMC_TOP_INTREN2_CMDTOSIGEN_SHIFT 16 +#define SD4_EMMC_TOP_INTREN2_CMDTOSIGEN_MASK 0x00010000 +#define SD4_EMMC_TOP_INTREN2_FIXZERO_SHIFT 15 +#define SD4_EMMC_TOP_INTREN2_FIXZERO_MASK 0x00008000 +#define SD4_EMMC_TOP_INTREN2_BTIRQSEN_SHIFT 14 +#define SD4_EMMC_TOP_INTREN2_BTIRQSEN_MASK 0x00004000 +#define SD4_EMMC_TOP_INTREN2_BTACKRXSEN_SHIFT 13 +#define SD4_EMMC_TOP_INTREN2_BTACKRXSEN_MASK 0x00002000 +#define SD4_EMMC_TOP_INTREN2_RETUNE_EVENTSIGEN_SHIFT 12 +#define SD4_EMMC_TOP_INTREN2_RETUNE_EVENTSIGEN_MASK 0x00001000 +#define SD4_EMMC_TOP_INTREN2_INT_C_SIGEN_SHIFT 11 +#define SD4_EMMC_TOP_INTREN2_INT_C_SIGEN_MASK 0x00000800 +#define SD4_EMMC_TOP_INTREN2_INT_B_SIGEN_SHIFT 10 +#define SD4_EMMC_TOP_INTREN2_INT_B_SIGEN_MASK 0x00000400 +#define SD4_EMMC_TOP_INTREN2_INT_A_SIGEN_SHIFT 9 +#define SD4_EMMC_TOP_INTREN2_INT_A_SIGEN_MASK 0x00000200 +#define SD4_EMMC_TOP_INTREN2_CRDIRQEN_SHIFT 8 +#define SD4_EMMC_TOP_INTREN2_CRDIRQEN_MASK 0x00000100 +#define SD4_EMMC_TOP_INTREN2_CRDRVMEN_SHIFT 7 +#define SD4_EMMC_TOP_INTREN2_CRDRVMEN_MASK 0x00000080 +#define SD4_EMMC_TOP_INTREN2_CRDINSEN_SHIFT 6 +#define SD4_EMMC_TOP_INTREN2_CRDINSEN_MASK 0x00000040 +#define SD4_EMMC_TOP_INTREN2_BUFRRDYEN_SHIFT 5 +#define SD4_EMMC_TOP_INTREN2_BUFRRDYEN_MASK 0x00000020 +#define SD4_EMMC_TOP_INTREN2_BUFWRDYEN_SHIFT 4 +#define SD4_EMMC_TOP_INTREN2_BUFWRDYEN_MASK 0x00000010 +#define SD4_EMMC_TOP_INTREN2_DMAIRQEN_SHIFT 3 +#define SD4_EMMC_TOP_INTREN2_DMAIRQEN_MASK 0x00000008 +#define SD4_EMMC_TOP_INTREN2_BLKGAPEN_SHIFT 2 +#define SD4_EMMC_TOP_INTREN2_BLKGAPEN_MASK 0x00000004 +#define SD4_EMMC_TOP_INTREN2_TXDONE_SHIFT 1 +#define SD4_EMMC_TOP_INTREN2_TXDONE_MASK 0x00000002 +#define SD4_EMMC_TOP_INTREN2_CMDDONE_SHIFT 0 +#define SD4_EMMC_TOP_INTREN2_CMDDONE_MASK 0x00000001 + +#define SD4_EMMC_TOP_INTREN2_SD4_OFFSET 0x00000038 +#define SD4_EMMC_TOP_INTREN2_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_INTREN2_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_INTREN2_SD4_RESERVED_MASK 0xF0006000 +#define SD4_EMMC_TOP_INTREN2_SD4_TRESPERRSEN_SHIFT 27 +#define SD4_EMMC_TOP_INTREN2_SD4_TRESPERRSEN_MASK 0x08000000 +#define SD4_EMMC_TOP_INTREN2_SD4_TUNERRSIGEN_SHIFT 26 +#define SD4_EMMC_TOP_INTREN2_SD4_TUNERRSIGEN_MASK 0x04000000 +#define SD4_EMMC_TOP_INTREN2_SD4_ADMASIGEN_SHIFT 25 +#define SD4_EMMC_TOP_INTREN2_SD4_ADMASIGEN_MASK 0x02000000 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDSIGEN_SHIFT 24 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDSIGEN_MASK 0x01000000 +#define SD4_EMMC_TOP_INTREN2_SD4_ILIMSIGEN_SHIFT 23 +#define SD4_EMMC_TOP_INTREN2_SD4_ILIMSIGEN_MASK 0x00800000 +#define SD4_EMMC_TOP_INTREN2_SD4_DEBSIGEN_SHIFT 22 +#define SD4_EMMC_TOP_INTREN2_SD4_DEBSIGEN_MASK 0x00400000 +#define SD4_EMMC_TOP_INTREN2_SD4_DCRCSIGEN_SHIFT 21 +#define SD4_EMMC_TOP_INTREN2_SD4_DCRCSIGEN_MASK 0x00200000 +#define SD4_EMMC_TOP_INTREN2_SD4_DTOSIGEN_SHIFT 20 +#define SD4_EMMC_TOP_INTREN2_SD4_DTOSIGEN_MASK 0x00100000 +#define SD4_EMMC_TOP_INTREN2_SD4_CIDXSIGEN_SHIFT 19 +#define SD4_EMMC_TOP_INTREN2_SD4_CIDXSIGEN_MASK 0x00080000 +#define SD4_EMMC_TOP_INTREN2_SD4_CEBSIGEN_SHIFT 18 +#define SD4_EMMC_TOP_INTREN2_SD4_CEBSIGEN_MASK 0x00040000 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDCRCSIGEN_SHIFT 17 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDCRCSIGEN_MASK 0x00020000 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDTOSIGEN_SHIFT 16 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDTOSIGEN_MASK 0x00010000 +#define SD4_EMMC_TOP_INTREN2_SD4_FIXZERO_SHIFT 15 +#define SD4_EMMC_TOP_INTREN2_SD4_FIXZERO_MASK 0x00008000 +#define SD4_EMMC_TOP_INTREN2_SD4_RETUNE_EVENTSIGEN_SHIFT 12 +#define SD4_EMMC_TOP_INTREN2_SD4_RETUNE_EVENTSIGEN_MASK 0x00001000 +#define SD4_EMMC_TOP_INTREN2_SD4_INT_C_SIGEN_SHIFT 11 +#define SD4_EMMC_TOP_INTREN2_SD4_INT_C_SIGEN_MASK 0x00000800 +#define SD4_EMMC_TOP_INTREN2_SD4_INT_B_SIGEN_SHIFT 10 +#define SD4_EMMC_TOP_INTREN2_SD4_INT_B_SIGEN_MASK 0x00000400 +#define SD4_EMMC_TOP_INTREN2_SD4_INT_A_SIGEN_SHIFT 9 +#define SD4_EMMC_TOP_INTREN2_SD4_INT_A_SIGEN_MASK 0x00000200 +#define SD4_EMMC_TOP_INTREN2_SD4_CRDIRQEN_SHIFT 8 +#define SD4_EMMC_TOP_INTREN2_SD4_CRDIRQEN_MASK 0x00000100 +#define SD4_EMMC_TOP_INTREN2_SD4_CRDRVMEN_SHIFT 7 +#define SD4_EMMC_TOP_INTREN2_SD4_CRDRVMEN_MASK 0x00000080 +#define SD4_EMMC_TOP_INTREN2_SD4_CRDINSEN_SHIFT 6 +#define SD4_EMMC_TOP_INTREN2_SD4_CRDINSEN_MASK 0x00000040 +#define SD4_EMMC_TOP_INTREN2_SD4_BUFRRDYEN_SHIFT 5 +#define SD4_EMMC_TOP_INTREN2_SD4_BUFRRDYEN_MASK 0x00000020 +#define SD4_EMMC_TOP_INTREN2_SD4_BUFWRDYEN_SHIFT 4 +#define SD4_EMMC_TOP_INTREN2_SD4_BUFWRDYEN_MASK 0x00000010 +#define SD4_EMMC_TOP_INTREN2_SD4_DMAIRQEN_SHIFT 3 +#define SD4_EMMC_TOP_INTREN2_SD4_DMAIRQEN_MASK 0x00000008 +#define SD4_EMMC_TOP_INTREN2_SD4_BLKGAPEN_SHIFT 2 +#define SD4_EMMC_TOP_INTREN2_SD4_BLKGAPEN_MASK 0x00000004 +#define SD4_EMMC_TOP_INTREN2_SD4_TXDONE_SHIFT 1 +#define SD4_EMMC_TOP_INTREN2_SD4_TXDONE_MASK 0x00000002 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDDONE_SHIFT 0 +#define SD4_EMMC_TOP_INTREN2_SD4_CMDDONE_MASK 0x00000001 + +#define SD4_EMMC_TOP_ERRSTAT_OFFSET 0x0000003C +#define SD4_EMMC_TOP_ERRSTAT_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_ERRSTAT_TYPE uint32_t +#define SD4_EMMC_TOP_ERRSTAT_RESERVED_MASK 0x3F00FF60 +#define SD4_EMMC_TOP_ERRSTAT_PRESETEN_SHIFT 31 +#define SD4_EMMC_TOP_ERRSTAT_PRESETEN_MASK 0x80000000 +#define SD4_EMMC_TOP_ERRSTAT_ASYNC_INTREN_SHIFT 30 +#define SD4_EMMC_TOP_ERRSTAT_ASYNC_INTREN_MASK 0x40000000 +#define SD4_EMMC_TOP_ERRSTAT_SAMPLECLOCKSEL_SHIFT 23 +#define SD4_EMMC_TOP_ERRSTAT_SAMPLECLOCKSEL_MASK 0x00800000 +#define SD4_EMMC_TOP_ERRSTAT_EXECTUNE_SHIFT 22 +#define SD4_EMMC_TOP_ERRSTAT_EXECTUNE_MASK 0x00400000 +#define SD4_EMMC_TOP_ERRSTAT_DRVSTRESEL_SHIFT 20 +#define SD4_EMMC_TOP_ERRSTAT_DRVSTRESEL_MASK 0x00300000 +#define SD4_EMMC_TOP_ERRSTAT_EN1P8V_SHIFT 19 +#define SD4_EMMC_TOP_ERRSTAT_EN1P8V_MASK 0x00080000 +#define SD4_EMMC_TOP_ERRSTAT_UHSMODESEL_SHIFT 16 +#define SD4_EMMC_TOP_ERRSTAT_UHSMODESEL_MASK 0x00070000 +#define SD4_EMMC_TOP_ERRSTAT_NOCMD_SHIFT 7 +#define SD4_EMMC_TOP_ERRSTAT_NOCMD_MASK 0x00000080 +#define SD4_EMMC_TOP_ERRSTAT_CMDIDXERR_SHIFT 4 +#define SD4_EMMC_TOP_ERRSTAT_CMDIDXERR_MASK 0x00000010 +#define SD4_EMMC_TOP_ERRSTAT_CMDENDERR_SHIFT 3 +#define SD4_EMMC_TOP_ERRSTAT_CMDENDERR_MASK 0x00000008 +#define SD4_EMMC_TOP_ERRSTAT_CMDCRCERR_SHIFT 2 +#define SD4_EMMC_TOP_ERRSTAT_CMDCRCERR_MASK 0x00000004 +#define SD4_EMMC_TOP_ERRSTAT_CMDTOERR_SHIFT 1 +#define SD4_EMMC_TOP_ERRSTAT_CMDTOERR_MASK 0x00000002 +#define SD4_EMMC_TOP_ERRSTAT_CMDNOEXEC_SHIFT 0 +#define SD4_EMMC_TOP_ERRSTAT_CMDNOEXEC_MASK 0x00000001 + +#define SD4_EMMC_TOP_ERRSTAT_SD4_OFFSET 0x0000003C +#define SD4_EMMC_TOP_ERRSTAT_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_ERRSTAT_SD4_RESERVED_MASK 0x0E00FF40 +#define SD4_EMMC_TOP_ERRSTAT_SD4_PRESETEN_SHIFT 31 +#define SD4_EMMC_TOP_ERRSTAT_SD4_PRESETEN_MASK 0x80000000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_ASYNC_INTREN_SHIFT 30 +#define SD4_EMMC_TOP_ERRSTAT_SD4_ASYNC_INTREN_MASK 0x40000000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_ADDR64_SHIFT 29 +#define SD4_EMMC_TOP_ERRSTAT_SD4_ADDR64_MASK 0x20000000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_HOSTVER4_00_SHIFT 28 +#define SD4_EMMC_TOP_ERRSTAT_SD4_HOSTVER4_00_MASK 0x10000000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_UHS2INTFEN_SHIFT 24 +#define SD4_EMMC_TOP_ERRSTAT_SD4_UHS2INTFEN_MASK 0x01000000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_SAMPLECLOCKSEL_SHIFT 23 +#define SD4_EMMC_TOP_ERRSTAT_SD4_SAMPLECLOCKSEL_MASK 0x00800000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_EXECTUNE_SHIFT 22 +#define SD4_EMMC_TOP_ERRSTAT_SD4_EXECTUNE_MASK 0x00400000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_DRVSTRESEL_SHIFT 20 +#define SD4_EMMC_TOP_ERRSTAT_SD4_DRVSTRESEL_MASK 0x00300000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_EN1P8V_SHIFT 19 +#define SD4_EMMC_TOP_ERRSTAT_SD4_EN1P8V_MASK 0x00080000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_UHSMODESEL_SHIFT 16 +#define SD4_EMMC_TOP_ERRSTAT_SD4_UHSMODESEL_MASK 0x00070000 +#define SD4_EMMC_TOP_ERRSTAT_SD4_NOCMD_SHIFT 7 +#define SD4_EMMC_TOP_ERRSTAT_SD4_NOCMD_MASK 0x00000080 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDRESPERR_SHIFT 5 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDRESPERR_MASK 0x00000020 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDIDXERR_SHIFT 4 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDIDXERR_MASK 0x00000010 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDENDERR_SHIFT 3 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDENDERR_MASK 0x00000008 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDCRCERR_SHIFT 2 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDCRCERR_MASK 0x00000004 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDTOERR_SHIFT 1 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDTOERR_MASK 0x00000002 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDNOEXEC_SHIFT 0 +#define SD4_EMMC_TOP_ERRSTAT_SD4_CMDNOEXEC_MASK 0x00000001 + +#define SD4_EMMC_TOP_CAPABILITIES1_OFFSET 0x00000040 +#define SD4_EMMC_TOP_CAPABILITIES1_DEFAULT 0x17EFD0B0 +#define SD4_EMMC_TOP_CAPABILITIES1_TYPE uint32_t +#define SD4_EMMC_TOP_CAPABILITIES1_RESERVED_MASK 0x08100040 +#define SD4_EMMC_TOP_CAPABILITIES1_SLOTTYPE_SHIFT 30 +#define SD4_EMMC_TOP_CAPABILITIES1_SLOTTYPE_MASK 0xC0000000 +#define SD4_EMMC_TOP_CAPABILITIES1_ASYNCHIRQ_SHIFT 29 +#define SD4_EMMC_TOP_CAPABILITIES1_ASYNCHIRQ_MASK 0x20000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SYSBUS64_SHIFT 28 +#define SD4_EMMC_TOP_CAPABILITIES1_SYSBUS64_MASK 0x10000000 +#define SD4_EMMC_TOP_CAPABILITIES1_V18_SHIFT 26 +#define SD4_EMMC_TOP_CAPABILITIES1_V18_MASK 0x04000000 +#define SD4_EMMC_TOP_CAPABILITIES1_V3_SHIFT 25 +#define SD4_EMMC_TOP_CAPABILITIES1_V3_MASK 0x02000000 +#define SD4_EMMC_TOP_CAPABILITIES1_V33_SHIFT 24 +#define SD4_EMMC_TOP_CAPABILITIES1_V33_MASK 0x01000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SUPRSM_SHIFT 23 +#define SD4_EMMC_TOP_CAPABILITIES1_SUPRSM_MASK 0x00800000 +#define SD4_EMMC_TOP_CAPABILITIES1_SDMA_SHIFT 22 +#define SD4_EMMC_TOP_CAPABILITIES1_SDMA_MASK 0x00400000 +#define SD4_EMMC_TOP_CAPABILITIES1_HSPEED_SHIFT 21 +#define SD4_EMMC_TOP_CAPABILITIES1_HSPEED_MASK 0x00200000 +#define SD4_EMMC_TOP_CAPABILITIES1_ADMA2_SHIFT 19 +#define SD4_EMMC_TOP_CAPABILITIES1_ADMA2_MASK 0x00080000 +#define SD4_EMMC_TOP_CAPABILITIES1_EXTBUSMED_SHIFT 18 +#define SD4_EMMC_TOP_CAPABILITIES1_EXTBUSMED_MASK 0x00040000 +#define SD4_EMMC_TOP_CAPABILITIES1_MAXBLK_SHIFT 16 +#define SD4_EMMC_TOP_CAPABILITIES1_MAXBLK_MASK 0x00030000 +#define SD4_EMMC_TOP_CAPABILITIES1_BCLK_SHIFT 8 +#define SD4_EMMC_TOP_CAPABILITIES1_BCLK_MASK 0x0000FF00 +#define SD4_EMMC_TOP_CAPABILITIES1_TOUT_SHIFT 7 +#define SD4_EMMC_TOP_CAPABILITIES1_TOUT_MASK 0x00000080 +#define SD4_EMMC_TOP_CAPABILITIES1_TOUTFREQ_SHIFT 0 +#define SD4_EMMC_TOP_CAPABILITIES1_TOUTFREQ_MASK 0x0000003F + +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_OFFSET 0x00000040 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_DEFAULT 0x10E934B4 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_RESERVED_MASK 0x08100040 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SLOTTYPE_SHIFT 30 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SLOTTYPE_MASK 0xC0000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ASYNCHIRQ_SHIFT 29 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ASYNCHIRQ_MASK 0x20000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SYSBUS64_SHIFT 28 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SYSBUS64_MASK 0x10000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V18_SHIFT 26 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V18_MASK 0x04000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V3_SHIFT 25 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V3_MASK 0x02000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V33_SHIFT 24 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_V33_MASK 0x01000000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SUPRSM_SHIFT 23 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SUPRSM_MASK 0x00800000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SDMA_SHIFT 22 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_SDMA_MASK 0x00400000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_HSPEED_SHIFT 21 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_HSPEED_MASK 0x00200000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ADMA2_SHIFT 19 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_ADMA2_MASK 0x00080000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_EXTBUSMED_SHIFT 18 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_EXTBUSMED_MASK 0x00040000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_MAXBLK_SHIFT 16 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_MAXBLK_MASK 0x00030000 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_BCLK_SHIFT 8 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_BCLK_MASK 0x0000FF00 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUT_SHIFT 7 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUT_MASK 0x00000080 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUTFREQ_SHIFT 0 +#define SD4_EMMC_TOP_CAPABILITIES1_SD4_TOUTFREQ_MASK 0x0000003F + +#define SD4_EMMC_TOP_CAPABILITIES2_OFFSET 0x00000044 +#define SD4_EMMC_TOP_CAPABILITIES2_DEFAULT 0x03002177 +#define SD4_EMMC_TOP_CAPABILITIES2_TYPE uint32_t +#define SD4_EMMC_TOP_CAPABILITIES2_RESERVED_MASK 0xFC001088 +#define SD4_EMMC_TOP_CAPABILITIES2_SPIBLOCKMODE_SHIFT 25 +#define SD4_EMMC_TOP_CAPABILITIES2_SPIBLOCKMODE_MASK 0x02000000 +#define SD4_EMMC_TOP_CAPABILITIES2_SPIMODE_CAP_SHIFT 24 +#define SD4_EMMC_TOP_CAPABILITIES2_SPIMODE_CAP_MASK 0x01000000 +#define SD4_EMMC_TOP_CAPABILITIES2_CLOCKMULT_SHIFT 16 +#define SD4_EMMC_TOP_CAPABILITIES2_CLOCKMULT_MASK 0x00FF0000 +#define SD4_EMMC_TOP_CAPABILITIES2_RETUNE_MODE_SHIFT 14 +#define SD4_EMMC_TOP_CAPABILITIES2_RETUNE_MODE_MASK 0x0000C000 +#define SD4_EMMC_TOP_CAPABILITIES2_USETUNE_SDR50_SHIFT 13 +#define SD4_EMMC_TOP_CAPABILITIES2_USETUNE_SDR50_MASK 0x00002000 +#define SD4_EMMC_TOP_CAPABILITIES2_TMRCNT_RETUNE_SHIFT 8 +#define SD4_EMMC_TOP_CAPABILITIES2_TMRCNT_RETUNE_MASK 0x00000F00 +#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPED_SHIFT 6 +#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPED_MASK 0x00000040 +#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEC_SHIFT 5 +#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEC_MASK 0x00000020 +#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEA_SHIFT 4 +#define SD4_EMMC_TOP_CAPABILITIES2_DRVR_TYPEA_MASK 0x00000010 +#define SD4_EMMC_TOP_CAPABILITIES2_DDR50_SHIFT 2 +#define SD4_EMMC_TOP_CAPABILITIES2_DDR50_MASK 0x00000004 +#define SD4_EMMC_TOP_CAPABILITIES2_SDR104_SHIFT 1 +#define SD4_EMMC_TOP_CAPABILITIES2_SDR104_MASK 0x00000002 +#define SD4_EMMC_TOP_CAPABILITIES2_SDR50_SHIFT 0 +#define SD4_EMMC_TOP_CAPABILITIES2_SDR50_MASK 0x00000001 + +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_OFFSET 0x00000044 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DEFAULT 0x10000064 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_RESERVED_MASK 0xE7001080 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_VDD2_18_SHIFT 28 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_VDD2_18_MASK 0x10000000 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_ADMA3_SHIFT 27 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_ADMA3_MASK 0x08000000 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_CLOCKMULT_SHIFT 16 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_CLOCKMULT_MASK 0x00FF0000 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_RETUNE_MODE_SHIFT 14 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_RETUNE_MODE_MASK 0x0000C000 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_USETUNE_SDR50_SHIFT 13 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_USETUNE_SDR50_MASK 0x00002000 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_TMRCNT_RETUNE_SHIFT 8 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_TMRCNT_RETUNE_MASK 0x00000F00 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPED_SHIFT 6 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPED_MASK 0x00000040 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEC_SHIFT 5 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEC_MASK 0x00000020 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEA_SHIFT 4 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DRVR_TYPEA_MASK 0x00000010 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_UHS_II_SHIFT 3 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_UHS_II_MASK 0x00000008 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DDR50_SHIFT 2 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_DDR50_MASK 0x00000004 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR104_SHIFT 1 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR104_MASK 0x00000002 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR50_SHIFT 0 +#define SD4_EMMC_TOP_CAPABILITIES2_SD4_SDR50_MASK 0x00000001 + +#define SD4_EMMC_TOP_MAX_A1_OFFSET 0x00000048 +#define SD4_EMMC_TOP_MAX_A1_DEFAULT 0x00000001 +#define SD4_EMMC_TOP_MAX_A1_TYPE uint32_t +#define SD4_EMMC_TOP_MAX_A1_RESERVED_MASK 0xFF000000 +#define SD4_EMMC_TOP_MAX_A1_MAXA18_SHIFT 16 +#define SD4_EMMC_TOP_MAX_A1_MAXA18_MASK 0x00FF0000 +#define SD4_EMMC_TOP_MAX_A1_MAXA30_SHIFT 8 +#define SD4_EMMC_TOP_MAX_A1_MAXA30_MASK 0x0000FF00 +#define SD4_EMMC_TOP_MAX_A1_MAXA33_SHIFT 0 +#define SD4_EMMC_TOP_MAX_A1_MAXA33_MASK 0x000000FF + +#define SD4_EMMC_TOP_MAX_A2_OFFSET 0x0000004C +#define SD4_EMMC_TOP_MAX_A2_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_MAX_A2_TYPE uint32_t +#define SD4_EMMC_TOP_MAX_A2_RESERVED_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_MAX_A2_SD4_OFFSET 0x0000004C +#define SD4_EMMC_TOP_MAX_A2_SD4_DEFAULT 0x00000001 +#define SD4_EMMC_TOP_MAX_A2_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_MAX_A2_SD4_RESERVED_MASK 0xFFFFFF00 +#define SD4_EMMC_TOP_MAX_A2_SD4_MAXAVDD2_SHIFT 0 +#define SD4_EMMC_TOP_MAX_A2_SD4_MAXAVDD2_MASK 0x000000FF + +#define SD4_EMMC_TOP_CMDENTSTAT_OFFSET 0x00000050 +#define SD4_EMMC_TOP_CMDENTSTAT_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CMDENTSTAT_TYPE uint32_t +#define SD4_EMMC_TOP_CMDENTSTAT_RESERVED_MASK 0x2C00FF60 +#define SD4_EMMC_TOP_CMDENTSTAT_VSES_SHIFT 30 +#define SD4_EMMC_TOP_CMDENTSTAT_VSES_MASK 0xC0000000 +#define SD4_EMMC_TOP_CMDENTSTAT_TRERR_SHIFT 28 +#define SD4_EMMC_TOP_CMDENTSTAT_TRERR_MASK 0x10000000 +#define SD4_EMMC_TOP_CMDENTSTAT_ADMAERR_SHIFT 25 +#define SD4_EMMC_TOP_CMDENTSTAT_ADMAERR_MASK 0x02000000 +#define SD4_EMMC_TOP_CMDENTSTAT_ACMDERR_SHIFT 24 +#define SD4_EMMC_TOP_CMDENTSTAT_ACMDERR_MASK 0x01000000 +#define SD4_EMMC_TOP_CMDENTSTAT_ILERR_SHIFT 23 +#define SD4_EMMC_TOP_CMDENTSTAT_ILERR_MASK 0x00800000 +#define SD4_EMMC_TOP_CMDENTSTAT_DENDERR_SHIFT 22 +#define SD4_EMMC_TOP_CMDENTSTAT_DENDERR_MASK 0x00400000 +#define SD4_EMMC_TOP_CMDENTSTAT_DCRCERR_SHIFT 21 +#define SD4_EMMC_TOP_CMDENTSTAT_DCRCERR_MASK 0x00200000 +#define SD4_EMMC_TOP_CMDENTSTAT_DTOUTERR_SHIFT 20 +#define SD4_EMMC_TOP_CMDENTSTAT_DTOUTERR_MASK 0x00100000 +#define SD4_EMMC_TOP_CMDENTSTAT_CIDXERR_SHIFT 19 +#define SD4_EMMC_TOP_CMDENTSTAT_CIDXERR_MASK 0x00080000 +#define SD4_EMMC_TOP_CMDENTSTAT_CENDERR_SHIFT 18 +#define SD4_EMMC_TOP_CMDENTSTAT_CENDERR_MASK 0x00040000 +#define SD4_EMMC_TOP_CMDENTSTAT_CCRCERR_SHIFT 17 +#define SD4_EMMC_TOP_CMDENTSTAT_CCRCERR_MASK 0x00020000 +#define SD4_EMMC_TOP_CMDENTSTAT_CTOUTERR_SHIFT 16 +#define SD4_EMMC_TOP_CMDENTSTAT_CTOUTERR_MASK 0x00010000 +#define SD4_EMMC_TOP_CMDENTSTAT_NOFRCENT_SHIFT 7 +#define SD4_EMMC_TOP_CMDENTSTAT_NOFRCENT_MASK 0x00000080 +#define SD4_EMMC_TOP_CMDENTSTAT_IDXERR_SHIFT 4 +#define SD4_EMMC_TOP_CMDENTSTAT_IDXERR_MASK 0x00000010 +#define SD4_EMMC_TOP_CMDENTSTAT_EBITERR_SHIFT 3 +#define SD4_EMMC_TOP_CMDENTSTAT_EBITERR_MASK 0x00000008 +#define SD4_EMMC_TOP_CMDENTSTAT_CRCERR_SHIFT 2 +#define SD4_EMMC_TOP_CMDENTSTAT_CRCERR_MASK 0x00000004 +#define SD4_EMMC_TOP_CMDENTSTAT_TOUTERR_SHIFT 1 +#define SD4_EMMC_TOP_CMDENTSTAT_TOUTERR_MASK 0x00000002 +#define SD4_EMMC_TOP_CMDENTSTAT_AUTONOEX_SHIFT 0 +#define SD4_EMMC_TOP_CMDENTSTAT_AUTONOEX_MASK 0x00000001 + +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_OFFSET 0x00000050 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESERVED_MASK 0x0000FF40 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_VSES_SHIFT 28 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_VSES_MASK 0xF0000000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TRESPERR_SHIFT 27 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TRESPERR_MASK 0x08000000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TUNERR_SHIFT 26 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TUNERR_MASK 0x04000000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ADMAERR_SHIFT 25 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ADMAERR_MASK 0x02000000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ACMDERR_SHIFT 24 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ACMDERR_MASK 0x01000000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ILERR_SHIFT 23 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_ILERR_MASK 0x00800000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DENDERR_SHIFT 22 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DENDERR_MASK 0x00400000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DCRCERR_SHIFT 21 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DCRCERR_MASK 0x00200000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DTOUTERR_SHIFT 20 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_DTOUTERR_MASK 0x00100000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CIDXERR_SHIFT 19 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CIDXERR_MASK 0x00080000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CENDERR_SHIFT 18 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CENDERR_MASK 0x00040000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CCRCERR_SHIFT 17 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CCRCERR_MASK 0x00020000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CTOUTERR_SHIFT 16 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CTOUTERR_MASK 0x00010000 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_NOFRCENT_SHIFT 7 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_NOFRCENT_MASK 0x00000080 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESPERR_SHIFT 5 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_RESPERR_MASK 0x00000020 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_IDXERR_SHIFT 4 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_IDXERR_MASK 0x00000010 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_EBITERR_SHIFT 3 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_EBITERR_MASK 0x00000008 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CRCERR_SHIFT 2 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_CRCERR_MASK 0x00000004 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TOUTERR_SHIFT 1 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_TOUTERR_MASK 0x00000002 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_AUTONOEX_SHIFT 0 +#define SD4_EMMC_TOP_CMDENTSTAT_SD4_AUTONOEX_MASK 0x00000001 + +#define SD4_EMMC_TOP_ADMAERR_OFFSET 0x00000054 +#define SD4_EMMC_TOP_ADMAERR_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_ADMAERR_TYPE uint32_t +#define SD4_EMMC_TOP_ADMAERR_RESERVED_MASK 0xFFFFFFF8 +#define SD4_EMMC_TOP_ADMAERR_ADMALERR_SHIFT 2 +#define SD4_EMMC_TOP_ADMAERR_ADMALERR_MASK 0x00000004 +#define SD4_EMMC_TOP_ADMAERR_ADMAERR_SHIFT 0 +#define SD4_EMMC_TOP_ADMAERR_ADMAERR_MASK 0x00000003 + +#define SD4_EMMC_TOP_ADMAADDR0_OFFSET 0x00000058 +#define SD4_EMMC_TOP_ADMAADDR0_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_ADMAADDR0_TYPE uint32_t +#define SD4_EMMC_TOP_ADMAADDR0_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_ADMAADDR0_ADMAADDR0_SHIFT 0 +#define SD4_EMMC_TOP_ADMAADDR0_ADMAADDR0_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_ADMAADDR1_OFFSET 0x0000005C +#define SD4_EMMC_TOP_ADMAADDR1_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_ADMAADDR1_TYPE uint32_t +#define SD4_EMMC_TOP_ADMAADDR1_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_ADMAADDR1_ADMAADDR1_SHIFT 0 +#define SD4_EMMC_TOP_ADMAADDR1_ADMAADDR1_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_PRESETVAL1_OFFSET 0x00000060 +#define SD4_EMMC_TOP_PRESETVAL1_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_PRESETVAL1_TYPE uint32_t +#define SD4_EMMC_TOP_PRESETVAL1_RESERVED_MASK 0x38003800 +#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_DFS_SHIFT 30 +#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_DFS_MASK 0xC0000000 +#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_DFS_SHIFT 26 +#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_DFS_MASK 0x04000000 +#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_DFS_SHIFT 16 +#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_DFS_MASK 0x03FF0000 +#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_INIT_SHIFT 14 +#define SD4_EMMC_TOP_PRESETVAL1_DRVS_SEL_INIT_MASK 0x0000C000 +#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_INIT_SHIFT 10 +#define SD4_EMMC_TOP_PRESETVAL1_CLKGENSEL_INIT_MASK 0x00000400 +#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_INIT_SHIFT 0 +#define SD4_EMMC_TOP_PRESETVAL1_FREQ_SEL_INIT_MASK 0x000003FF + +#define SD4_EMMC_TOP_PRESETVAL2_OFFSET 0x00000064 +#define SD4_EMMC_TOP_PRESETVAL2_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_PRESETVAL2_TYPE uint32_t +#define SD4_EMMC_TOP_PRESETVAL2_RESERVED_MASK 0x38003800 +#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_SDR12_SHIFT 30 +#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_SDR12_MASK 0xC0000000 +#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_SDR12_SHIFT 26 +#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_SDR12_MASK 0x04000000 +#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_SDR12_SHIFT 16 +#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_SDR12_MASK 0x03FF0000 +#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_HS_SHIFT 14 +#define SD4_EMMC_TOP_PRESETVAL2_DRVS_SEL_HS_MASK 0x0000C000 +#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_HS_SHIFT 10 +#define SD4_EMMC_TOP_PRESETVAL2_CLKGENSEL_HS_MASK 0x00000400 +#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_HS_SHIFT 0 +#define SD4_EMMC_TOP_PRESETVAL2_FREQ_SEL_HS_MASK 0x000003FF + +#define SD4_EMMC_TOP_PRESETVAL3_OFFSET 0x00000068 +#define SD4_EMMC_TOP_PRESETVAL3_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_PRESETVAL3_TYPE uint32_t +#define SD4_EMMC_TOP_PRESETVAL3_RESERVED_MASK 0x38003800 +#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR50_SHIFT 30 +#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR50_MASK 0xC0000000 +#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR50_SHIFT 26 +#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR50_MASK 0x04000000 +#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR50_SHIFT 16 +#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR50_MASK 0x03FF0000 +#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR25_SHIFT 14 +#define SD4_EMMC_TOP_PRESETVAL3_DRVS_SEL_SDR25_MASK 0x0000C000 +#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR25_SHIFT 10 +#define SD4_EMMC_TOP_PRESETVAL3_CLKGENSEL_SDR25_MASK 0x00000400 +#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR25_SHIFT 0 +#define SD4_EMMC_TOP_PRESETVAL3_FREQ_SEL_SDR25_MASK 0x000003FF + +#define SD4_EMMC_TOP_PRESETVAL4_OFFSET 0x0000006C +#define SD4_EMMC_TOP_PRESETVAL4_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_PRESETVAL4_TYPE uint32_t +#define SD4_EMMC_TOP_PRESETVAL4_RESERVED_MASK 0x38003800 +#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_DDR50_SHIFT 30 +#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_DDR50_MASK 0xC0000000 +#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_DDR50_SHIFT 26 +#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_DDR50_MASK 0x04000000 +#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_DDR50_SHIFT 16 +#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_DDR50_MASK 0x03FF0000 +#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_SDR104_SHIFT 14 +#define SD4_EMMC_TOP_PRESETVAL4_DRVS_SEL_SDR104_MASK 0x0000C000 +#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_SDR104_SHIFT 10 +#define SD4_EMMC_TOP_PRESETVAL4_CLKGENSEL_SDR104_MASK 0x00000400 +#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_SDR104_SHIFT 0 +#define SD4_EMMC_TOP_PRESETVAL4_FREQ_SEL_SDR104_MASK 0x000003FF + +#define SD4_EMMC_TOP_BOOTTIMEOUT_OFFSET 0x00000070 +#define SD4_EMMC_TOP_BOOTTIMEOUT_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_BOOTTIMEOUT_TYPE uint32_t +#define SD4_EMMC_TOP_BOOTTIMEOUT_RESERVED_MASK 0x00000000 +#define SD4_EMMC_TOP_BOOTTIMEOUT_BOOTDATATIMEOUTCTRVALUE_SHIFT 0 +#define SD4_EMMC_TOP_BOOTTIMEOUT_BOOTDATATIMEOUTCTRVALUE_MASK 0xFFFFFFFF + +#define SD4_EMMC_TOP_DBGSEL_OFFSET 0x00000074 +#define SD4_EMMC_TOP_DBGSEL_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_DBGSEL_TYPE uint32_t +#define SD4_EMMC_TOP_DBGSEL_RESERVED_MASK 0xFFFFFFFE +#define SD4_EMMC_TOP_DBGSEL_DBGSEL_SHIFT 0 +#define SD4_EMMC_TOP_DBGSEL_DBGSEL_MASK 0x00000001 + +#define SD4_EMMC_TOP_UHS2_PRESETVAL_OFFSET 0x00000074 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_DEFAULT 0x00000000 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_TYPE uint32_t +#define SD4_EMMC_TOP_UHS2_PRESETVAL_RESERVED_MASK 0xFFFF3800 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_DRVSTRVAL_SHIFT 14 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_DRVSTRVAL_MASK 0x0000C000 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_CLKGENSELVAL_SHIFT 10 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_CLKGENSELVAL_MASK 0x00000400 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_SDCLKFREQSELVAL_SHIFT 0 +#define SD4_EMMC_TOP_UHS2_PRESETVAL_SDCLKFREQSELVAL_MASK 0x000003FF + +#define SD4_EMMC_TOP_HCVERSIRQ_OFFSET 0x000000FC +#define SD4_EMMC_TOP_HCVERSIRQ_DEFAULT 0x10020000 +#define SD4_EMMC_TOP_HCVERSIRQ_TYPE uint32_t +#define SD4_EMMC_TOP_HCVERSIRQ_RESERVED_MASK 0x0000FF00 +#define SD4_EMMC_TOP_HCVERSIRQ_VENDVER_SHIFT 24 +#define SD4_EMMC_TOP_HCVERSIRQ_VENDVER_MASK 0xFF000000 +#define SD4_EMMC_TOP_HCVERSIRQ_SPECVER_SHIFT 16 +#define SD4_EMMC_TOP_HCVERSIRQ_SPECVER_MASK 0x00FF0000 +#define SD4_EMMC_TOP_HCVERSIRQ_SIRQ_SHIFT 0 +#define SD4_EMMC_TOP_HCVERSIRQ_SIRQ_MASK 0x000000FF + +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_OFFSET 0x000000FC +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_DEFAULT 0x01030000 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_TYPE uint32_t +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_RESERVED_MASK 0x0000FF00 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_VENDVER_SHIFT 24 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_VENDVER_MASK 0xFF000000 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SPECVER_SHIFT 16 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SPECVER_MASK 0x00FF0000 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SIRQ_SHIFT 0 +#define SD4_EMMC_TOP_HCVERSIRQ_SD4_SIRQ_MASK 0x000000FF + +#endif /* BRCM_RDB_SD4_EMMC_TOP_H */ diff --git a/include/drivers/brcm/emmc/emmc_chal_sd.h b/include/drivers/brcm/emmc/emmc_chal_sd.h new file mode 100644 index 000000000..8d223f9dd --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_chal_sd.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CHAL_SD_H +#define CHAL_SD_H + +#include <stddef.h> + +#define BASE_CLK_FREQ (200 * 1000 * 1000) +#define INIT_CLK_FREQ (400 * 1000) + +#define SD_ERROR_RECOVERABLE 0 +#define SD_ERROR_NON_RECOVERABLE 1 + +#define SD_OK 0 +#define SD_FAIL (-1) +#define SD_INVALID_HANDLE (-2) +#define SD_CEATA_INIT_ERROR (-3) +#define SD_RESET_ERROR (-4) +#define SD_CARD_INIT_ERROR (-5) +#define SD_INV_DATA_WIDTH (-6) +#define SD_SET_BUS_WIDTH_ERROR (-7) +#define SD_DMA_NOT_SUPPORT (-8) +#define SD_SDIO_READ_ERROR (-9) +#define SD_SDIO_WRITE_ERROR (-10) +#define SD_WRITE_ERROR (-11) +#define SD_READ_ERROR (-12) +#define SD_READ_SIZE_ERROR (-13) +#define SD_RW_ADDRESS_ERROR (-14) +#define SD_XFER_ADDRESS_ERROR (-15) +#define SD_DATA_XFER_ADDR_ERROR (-16) +#define SD_DATA_XFER_ERROR (-17) +#define SD_WRITE_SIZE_ERROR (-18) +#define SD_CMD_STATUS_UPDATE_ERR (-19) +#define SD_CMD12_ERROR (-20) +#define SD_CMD_DATA_ERROR (-21) +#define SD_CMD_TIMEOUT (-22) +#define SD_CMD_NO_RESPONSE (-22) +#define SD_CMD_ABORT_ERROR (-23) +#define SD_CMD_INVALID (-24) +#define SD_CMD_RESUME_ERROR (-25) +#define SD_CMD_ERR_INVALID_RESPONSE (-26) +#define SD_WAIT_TIMEOUT (-27) +#define SD_READ_TIMEOUT (-28) +#define SD_CEATA_REST_ERROR (-29) +#define SD_INIT_CAED_FAILED (-30) +#define SD_ERROR_CLOCK_OFFLIMIT (-31) +#define SD_INV_SLOT (-32) + +#define SD_NOR_INTERRUPTS 0x000000FF +#define SD_ERR_INTERRUPTS 0x03FF0000 +#define SD_CMD_ERROR_INT 0x010F0000 +#define SD_DAT_ERROR_INT 0x02F00000 +#define SD_DAT_TIMEOUT 0x00100000 + +/* Operation modes */ +#define SD_PIO_MODE 0 +#define SD_INT_MODE 1 + +/* Support both ADMA and SDMA (for version 2.0 and above) */ +#define SD_DMA_OFF 0 +#define SD_DMA_SDMA 1 +#define SD_DMA_ADMA 2 + +#define SD_NORMAL_SPEED 0 +#define SD_HIGH_SPEED 1 + +#define SD_XFER_CARD_TO_HOST 3 +#define SD_XFER_HOST_TO_CARD 4 + +#define SD_CARD_DETECT_AUTO 0 +#define SD_CARD_DETECT_SD 1 +#define SD_CARD_DETECT_SDIO 2 +#define SD_CARD_DETECT_MMC 3 +#define SD_CARD_DETECT_CEATA 4 + +#define SD_ABORT_SYNC_MODE 0 +#define SD_ABORT_ASYNC_MODE 1 + +#define SD_CMD_ERROR_FLAGS (0x18F << 16) +#define SD_DATA_ERROR_FLAGS (0x70 << 16) +#define SD_AUTO_CMD12_ERROR_FLAGS (0x9F) + +#define SD_CARD_STATUS_ERROR 0x10000000 +#define SD_CMD_MISSING 0x80000000 +#define SD_ERROR_INT 0x8000 + +#define SD_TRAN_HIGH_SPEED 0x32 +#define SD_CARD_HIGH_CAPACITY 0x40000000 +#define SD_CARD_POWER_UP_STATUS 0x80000000 + +#define SD_HOST_CORE_TIMEOUT 0x0E + +/* SD CARD and Host Controllers bus width */ +#define SD_BUS_DATA_WIDTH_1BIT 0x00 +#define SD_BUS_DATA_WIDTH_4BIT 0x02 +#define SD_BUS_DATA_WIDTH_8BIT 0x20 + +/* dma boundary settings */ +#define SD_DMA_BOUNDARY_4K 0 +#define SD_DMA_BOUNDARY_8K (1 << 12) +#define SD_DMA_BOUNDARY_16K (2 << 12) +#define SD_DMA_BOUNDARY_32K (3 << 12) +#define SD_DMA_BOUNDARY_64K (4 << 12) +#define SD_DMA_BOUNDARY_128K (5 << 12) +#define SD_DMA_BOUNDARY_256K (6 << 12) +#define SD_DMA_BOUNDARY_512K (7 << 12) + +#define SD_CMDR_CMD_NORMAL 0x00000000 +#define SD_CMDR_CMD_SUSPEND 0x00400000 +#define SD_CMDR_CMD_RESUME 0x00800000 +#define SD_CMDR_CMD_ABORT 0x00c00000 + +#define SD_CMDR_RSP_TYPE_NONE 0x0 +#define SD_CMDR_RSP_TYPE_R2 0x1 +#define SD_CMDR_RSP_TYPE_R3_4 0x2 +#define SD_CMDR_RSP_TYPE_R1_5_6 0x2 +#define SD_CMDR_RSP_TYPE_R1b_5b 0x3 +#define SD_CMDR_RSP_TYPE_S 16 + +struct sd_ctrl_info { + uint32_t blkReg; /* current block register cache value */ + uint32_t cmdReg; /* current command register cache value */ + uint32_t argReg; /* current argument register cache value */ + uint32_t cmdIndex; /* current command index */ + uint32_t cmdStatus; /* current command status, cmd/data compelete */ + uint16_t rca; /* relative card address */ + uint32_t ocr; /* operation codition */ + uint32_t eventList; /* events list */ + uint32_t blkGapEnable; + + uint32_t capability; /* controller's capbilities */ + uint32_t maxCurrent; /* maximum current supported */ + uint32_t present; /* if card is inserted or removed */ + uint32_t version; /* SD spec version 1.0 or 2.0 */ + uint32_t vendor; /* vendor number */ + + uintptr_t sdRegBaseAddr; /* sdio control registers */ + uintptr_t hostRegBaseAddr; /* SD Host control registers */ +}; + +struct sd_cfg { + uint32_t mode; /* interrupt or polling */ + uint32_t dma; /* dma enabled or disabled */ + uint32_t retryLimit; /* command retry limit */ + uint32_t speedMode; /* speed mode, 0 standard, 1 high speed */ + uint32_t voltage; /* voltage level */ + uint32_t blockSize; /* access block size (512 for HC card) */ + uint32_t dmaBoundary; /* dma address boundary */ + uint32_t detSignal; /* card det signal src, for test purpose only */ + uint32_t rdWaiting; + uint32_t wakeupOut; + uint32_t wakeupIn; + uint32_t wakeupInt; + uint32_t wfe_retry; + uint32_t gapInt; + uint32_t readWait; + uint32_t led; +}; + +struct sd_dev { + struct sd_cfg cfg; /* SD configuration */ + struct sd_ctrl_info ctrl; /* SD info */ +}; + +int32_t chal_sd_start(CHAL_HANDLE *sdHandle, uint32_t mode, + uint32_t sdBase, uint32_t hostBase); +int32_t chal_sd_config(CHAL_HANDLE *sdHandle, uint32_t speed, + uint32_t retry, uint32_t boundary, + uint32_t blkSize, uint32_t dma); +int32_t chal_sd_stop(void); +int32_t chal_sd_set_dma(CHAL_HANDLE *sdHandle, uint32_t mode); +uintptr_t chal_sd_get_dma_addr(CHAL_HANDLE *handle); +int32_t chal_sd_config_bus_width(CHAL_HANDLE *sdHandle, int32_t width); +int32_t chal_sd_send_cmd(CHAL_HANDLE *sdHandle, uint32_t cmdIndex, + uint32_t arg, uint32_t options); +int32_t chal_sd_set_dma_addr(CHAL_HANDLE *sdHandle, uintptr_t address); +int32_t chal_sd_set_clock(CHAL_HANDLE *sdHandle, + uint32_t div_ctrl_setting, uint32_t on); +uint32_t chal_sd_freq_2_div_ctrl_setting(uint32_t desired_freq); +int32_t chal_sd_setup_xfer(CHAL_HANDLE *sdHandle, uint8_t *data, + uint32_t length, int32_t dir); +int32_t chal_sd_write_buffer(CHAL_HANDLE *sdHandle, uint32_t length, + uint8_t *data); +int32_t chal_sd_read_buffer(CHAL_HANDLE *sdHandle, uint32_t length, + uint8_t *data); +int32_t chal_sd_reset_line(CHAL_HANDLE *sdHandle, uint32_t line); +int32_t chal_sd_get_response(CHAL_HANDLE *sdHandle, uint32_t *resp); +int32_t chal_sd_clear_pending_irq(CHAL_HANDLE *sdHandle); +int32_t chal_sd_get_irq_status(CHAL_HANDLE *sdHandle); +int32_t chal_sd_clear_irq(CHAL_HANDLE *sdHandle, uint32_t mask); +uint32_t chal_sd_get_present_status(CHAL_HANDLE *sdHandle); +int32_t chal_sd_get_atuo12_error(CHAL_HANDLE *sdHandle); +void chal_sd_set_speed(CHAL_HANDLE *sdHandle, uint32_t speed); +int32_t chal_sd_check_cap(CHAL_HANDLE *sdHandle, uint32_t cap); +void chal_sd_set_irq_signal(CHAL_HANDLE *sdHandle, uint32_t mask, + uint32_t state); +void chal_sd_dump_fifo(CHAL_HANDLE *sdHandle); +#endif /* CHAL_SD_H */ diff --git a/include/drivers/brcm/emmc/emmc_chal_types.h b/include/drivers/brcm/emmc/emmc_chal_types.h new file mode 100644 index 000000000..9563273ad --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_chal_types.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef CHAL_TYPES_H +#define CHAL_TYPES_H + +#include <stdint.h> + +// +// Generic cHAL handler +// +#ifndef CHAL_HANDLE + typedef void *CHAL_HANDLE; ///< void pointer (32 bits wide) +#endif + +#endif /* _CHAL_TYPES_H_ */ diff --git a/include/drivers/brcm/emmc/emmc_csl_sd.h b/include/drivers/brcm/emmc/emmc_csl_sd.h new file mode 100644 index 000000000..52b8bc84b --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_csl_sd.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CSL_SD_H +#define CSL_SD_H + +#define SD_CLOCK_BASE 104000000 +#define SD_CLOCK_52MHZ 52000000 +#define SD_CLOCK_26MHZ 26000000 +#define SD_CLOCK_17MHZ 17330000 +#define SD_CLOCK_13MHZ 13000000 +#define SD_CLOCK_10MHZ 10000000 +#define SD_CLOCK_9MHZ 9000000 +#define SD_CLOCK_7MHZ 7000000 +#define SD_CLOCK_5MHZ 5000000 +#define SD_CLOCK_1MHZ 1000000 +#define SD_CLOCK_400KHZ 400000 + +#define SD_DRIVE_STRENGTH_MASK 0x38000000 +#if defined(_BCM213x1_) || defined(_BCM21551_) || defined(_ATHENA_) +#define SD_DRIVE_STRENGTH 0x28000000 +#elif defined(_BCM2153_) +#define SD_DRIVE_STRENGTH 0x38000000 +#else +#define SD_DRIVE_STRENGTH 0x00000000 +#endif + +#define SD_NUM_HOST 2 + +#define SD_CARD_UNLOCK 0 +#define SD_CARD_LOCK 0x4 +#define SD_CARD_CLEAR_PWD 0x2 +#define SD_CARD_SET_PWD 0x1 +#define SD_CARD_ERASE_PWD 0x8 + +#define SD_CARD_LOCK_STATUS 0x02000000 +#define SD_CARD_UNLOCK_STATUS 0x01000000 + +#define SD_CMD_ERROR_FLAGS (0x18F << 16) +#define SD_DATA_ERROR_FLAGS (0x70 << 16) +#define SD_AUTO_CMD12_ERROR_FLAGS (0x9F) +#define SD_CARD_STATUS_ERROR 0x10000000 +#define SD_CMD_MISSING 0x80000000 + +#define SD_TRAN_HIGH_SPEED 0x32 +#define SD_CARD_HIGH_CAPACITY 0x40000000 +#define SD_CARD_POWER_UP_STATUS 0x80000000 + +struct sd_dev_info { + uint32_t mode; /* interrupt or polling */ + uint32_t dma; /* dma enabled or disabled */ + uint32_t voltage; /* voltage level */ + uint32_t slot; /* if the HC is locatd at slot 0 or slot 1 */ + uint32_t version; /* 1.0 or 2.0 */ + uint32_t curSystemAddr; /* system address */ + uint32_t dataWidth; /* data width for the controller */ + uint32_t clock; /* clock rate */ + uint32_t status; /* if device is active on transfer or not */ +}; + +void data_xfer_setup(struct sd_handle *handle, uint8_t *data, + uint32_t length, int dir); +int reset_card(struct sd_handle *handle); +int reset_host_ctrl(struct sd_handle *handle); +int init_card(struct sd_handle *handle, int detection); +int init_mmc_card(struct sd_handle *handle); +int write_buffer(struct sd_handle *handle, uint32_t len, uint8_t *buffer); +int read_buffer(struct sd_handle *handle, uint32_t len, uint8_t *buffer); +int select_blk_sz(struct sd_handle *handle, uint16_t size); +int check_error(struct sd_handle *handle, uint32_t ints); + +int process_data_xfer(struct sd_handle *handle, uint8_t *buffer, + uint32_t addr, uint32_t length, int dir); +int read_block(struct sd_handle *handle, uint8_t *dst, uint32_t addr, + uint32_t len); +#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE +int erase_card(struct sd_handle *handle, uint32_t addr, uint32_t blocks); +#endif +int write_block(struct sd_handle *handle, uint8_t *src, uint32_t addr, + uint32_t len); +int process_cmd_response(struct sd_handle *handle, uint32_t cmdIndex, + uint32_t rsp0, uint32_t rsp1, uint32_t rsp2, + uint32_t rsp3, struct sd_resp *resp); +int32_t set_config(struct sd_handle *handle, uint32_t speed, + uint32_t retry, uint32_t dma, uint32_t dmaBound, + uint32_t blkSize, uint32_t wfe_retry); + +uint32_t wait_for_event(struct sd_handle *handle, uint32_t mask, + uint32_t retry); +int set_boot_config(struct sd_handle *handle, uint32_t config); + +int mmc_cmd1(struct sd_handle *handle); +#endif /* CSL_SD_H */ diff --git a/include/drivers/brcm/emmc/emmc_csl_sdcmd.h b/include/drivers/brcm/emmc/emmc_csl_sdcmd.h new file mode 100644 index 000000000..425603f89 --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_csl_sdcmd.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CSL_SD_CMD_H +#define CSL_SD_CMD_H + +#define SD_CMD_OK 0 +#define SD_CMD_ERROR -1 + +#define SD_CMD_ERR_NO_IO_FUNC 5 +#define SD_CMD_ERR_INVALID_PARAMETER 6 +#define SD_CMD_ERR_R1_ILLEGAL_COMMAND 7 +#define SD_CMD_ERR_R1_COM_CRC_ERROR 8 +#define SD_CMD_ERR_R1_FUNC_NUM_ERROR 9 +#define SD_CMD_ERR_R1_ADDRESS_ERROR 10 +#define SD_CMD_ERR_R1_PARAMETER_ERROR 11 +#define SD_CMD_ERR_DATA_ERROR_TOKEN 12 +#define SD_CMD_ERR_DATA_NOT_ACCEPTED 13 +#define SD_CMD7_ARG_RCA_SHIFT 16 + +#define SD_CARD_STATUS_PENDING 0x01 +#define SD_CARD_STATUS_BUFFER_OVERFLOW 0x01 +#define SD_CARD_STATUS_DEVICE_BUSY 0x02 +#define SD_CARD_STATUS_UNSUCCESSFUL 0x03 +#define SD_CARD_STATUS_NOT_IMPLEMENTED 0x04 +#define SD_CARD_STATUS_ACCESS_VIOLATION 0x05 +#define SD_CARD_STATUS_INVALID_HANDLE 0x06 +#define SD_CARD_STATUS_INVALID_PARAMETER 0x07 +#define SD_CARD_STATUS_NO_SUCH_DEVICE 0x08 +#define SD_CARD_STATUS_INVALID_DEVICE_REQUEST 0x09 +#define SD_CARD_STATUS_NO_MEMORY 0x0A +#define SD_CARD_STATUS_BUS_DRIVER_NOT_READY 0x0B +#define SD_CARD_STATUS_DATA_ERROR 0x0C +#define SD_CARD_STATUS_CRC_ERROR 0x0D +#define SD_CARD_STATUS_INSUFFICIENT_RESOURCES 0x0E +#define SD_CARD_STATUS_DEVICE_NOT_CONNECTED 0x10 +#define SD_CARD_STATUS_DEVICE_REMOVED 0x11 +#define SD_CARD_STATUS_DEVICE_NOT_RESPONDING 0x12 +#define SD_CARD_STATUS_CANCELED 0x13 +#define SD_CARD_STATUS_RESPONSE_TIMEOUT 0x14 +#define SD_CARD_STATUS_DATA_TIMEOUT 0x15 +#define SD_CARD_STATUS_DEVICE_RESPONSE_ERROR 0x16 +#define SD_CARD_STATUS_DEVICE_UNSUPPORTED 0x17 + +/* Response structure */ +struct sd_r2_resp { + uint32_t rsp4; /* 127:96 */ + uint32_t rsp3; /* 95:64 */ + uint32_t rsp2; /* 63:32 */ + uint32_t rsp1; /* 31:0 */ +}; + +struct sd_r3_resp { + uint32_t ocr; +}; + +struct sd_r4_resp { + uint8_t cardReady; + uint8_t funcs; + uint8_t memPresent; + uint32_t ocr; +}; + +struct sd_r5_resp { + uint8_t data; +}; + +struct sd_r6_resp { + uint16_t rca; + uint16_t cardStatus; +}; + +struct sd_r7_resp { + uint16_t rca; +}; + +struct sd_resp { + uint8_t r1; + uint32_t cardStatus; + uint32_t rawData[4]; + union { + struct sd_r2_resp r2; + struct sd_r3_resp r3; + struct sd_r4_resp r4; + struct sd_r5_resp r5; + struct sd_r6_resp r6; + struct sd_r7_resp r7; + } data; +}; + +struct sd_card_info { + uint32_t type; /* card type SD, MMC or SDIO */ + uint64_t size; /* card size */ + uint32_t speed; /* card speed */ + uint32_t voltage; /* voltage supported */ + uint32_t mId; /* manufacturer ID */ + uint32_t oId; /* OEM ID */ + uint32_t classes; /* card class */ + uint32_t name1; /* product name part 1 */ + uint32_t name2; /* product name part 2 */ + uint32_t revision; /* revison */ + uint32_t sn; /* serial number */ + uint32_t numIoFuns; /* total I/O function number */ + uint32_t maxRdBlkLen; /* max read block length */ + uint32_t maxWtBlkLen; /* max write block length */ + uint32_t blkMode; /* sdio card block mode support */ + uint32_t f0Cis; /* sdio card block mode support */ + uint32_t f1Cis; /* sdio card block mode support */ + + uint8_t partRead; /* partial block read allowed */ + uint8_t partWrite; /* partial block write allowed */ + uint8_t dsr; /* card DSR */ + uint8_t rdCurMin; /* min current for read */ + uint8_t rdCurMax; /* max current for read */ + uint8_t wtCurMin; /* min current for write */ + uint8_t wtCurMax; /* max current for write */ + uint8_t erase; /* erase enable */ + uint8_t eraseSecSize; /* erase sector size */ + uint8_t proGrpSize; /* write protection group size */ + uint8_t protect; /* permanent write protection or not */ + uint8_t tmpProt; /* temp write protection or not */ + uint8_t wtSpeed; /* write speed relatively to read */ + uint8_t version; /* card version 0:1.0 - 1.01, 1:1.10, 2:2.0 */ + uint8_t eraseState; /* if the data will be 0 or 1 after erase */ + uint8_t bus; /* data with supported */ + uint8_t security; /* security support 0, 2:1.01 3:2.0 */ + uint8_t format; /* file format */ + uint8_t fileGrp; /* file group */ + char pwd[20]; /* password */ +}; + +struct sd_handle { + struct sd_dev *device; + struct sd_card_info *card; +}; + +int sd_cmd0(struct sd_handle *handle); +int sd_cmd1(struct sd_handle *handle, uint32_t initOcr, uint32_t *ocr); +int sd_cmd2(struct sd_handle *handle); +int sd_cmd3(struct sd_handle *handle); +int sd_cmd7(struct sd_handle *handle, uint32_t rca); +int sd_cmd9(struct sd_handle *handle, struct sd_card_data *card); +int sd_cmd13(struct sd_handle *handle, uint32_t *status); +int sd_cmd16(struct sd_handle *handle, uint32_t blockLen); +int sd_cmd17(struct sd_handle *handle, + uint32_t addr, uint32_t len, uint8_t *buffer); +int sd_cmd18(struct sd_handle *handle, + uint32_t addr, uint32_t len, uint8_t *buffer); +#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE +int sd_cmd24(struct sd_handle *handle, + uint32_t addr, uint32_t len, uint8_t *buffer); +int sd_cmd25(struct sd_handle *handle, + uint32_t addr, uint32_t len, uint8_t *buffer); +#endif +#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE +int sd_cmd35(struct sd_handle *handle, uint32_t start); +int sd_cmd36(struct sd_handle *handle, uint32_t end); +int sd_cmd38(struct sd_handle *handle); +#endif +int mmc_cmd6(struct sd_handle *handle, uint32_t argument); +int mmc_cmd8(struct sd_handle *handle, uint8_t *extCsdReg); + +int send_cmd(struct sd_handle *handle, uint32_t cmdIndex, + uint32_t argument, uint32_t options, struct sd_resp *resp); +#endif /* CSL_SD_CMD_H */ diff --git a/include/drivers/brcm/emmc/emmc_csl_sdprot.h b/include/drivers/brcm/emmc/emmc_csl_sdprot.h new file mode 100644 index 000000000..597e1e087 --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_csl_sdprot.h @@ -0,0 +1,435 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CSL_SD_PROT_H +#define CSL_SD_PROT_H + +#define SD_CARD_UNKNOWN 0 /* bad type or unrecognized */ +#define SD_CARD_SD 1 /* IO only card */ +#define SD_CARD_SDIO 2 /* memory only card */ +#define SD_CARD_COMBO 3 /* IO and memory combo card */ +#define SD_CARD_MMC 4 /* memory only card */ +#define SD_CARD_CEATA 5 /* IO and memory combo card */ + +#define SD_IO_FIXED_ADDRESS 0 /* fix Address */ +#define SD_IO_INCREMENT_ADDRESS 1 + +#define SD_HIGH_CAPACITY_CARD 0x40000000 + +#define MMC_CMD_IDLE_RESET_ARG 0xF0F0F0F0 + +/* Supported operating voltages are 3.2-3.3 and 3.3-3.4 */ +#define MMC_OCR_OP_VOLT 0x00300000 +/* Enable sector access mode */ +#define MMC_OCR_SECTOR_ACCESS_MODE 0x40000000 + +/* command index */ +#define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */ +#define SD_CMD_SEND_OPCOND 1 +#define SD_CMD_ALL_SEND_CID 2 +#define SD_CMD_MMC_SET_RCA 3 +#define SD_CMD_MMC_SET_DSR 4 +#define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */ +#define SD_ACMD_SET_BUS_WIDTH 6 +#define SD_CMD_SWITCH_FUNC 6 +#define SD_CMD_SELECT_DESELECT_CARD 7 +#define SD_CMD_READ_EXT_CSD 8 +#define SD_CMD_SEND_CSD 9 +#define SD_CMD_SEND_CID 10 +#define SD_CMD_STOP_TRANSMISSION 12 +#define SD_CMD_SEND_STATUS 13 +#define SD_ACMD_SD_STATUS 13 +#define SD_CMD_GO_INACTIVE_STATE 15 +#define SD_CMD_SET_BLOCKLEN 16 +#define SD_CMD_READ_SINGLE_BLOCK 17 +#define SD_CMD_READ_MULTIPLE_BLOCK 18 +#define SD_CMD_WRITE_BLOCK 24 +#define SD_CMD_WRITE_MULTIPLE_BLOCK 25 +#define SD_CMD_PROGRAM_CSD 27 +#define SD_CMD_SET_WRITE_PROT 28 +#define SD_CMD_CLR_WRITE_PROT 29 +#define SD_CMD_SEND_WRITE_PROT 30 +#define SD_CMD_ERASE_WR_BLK_START 32 +#define SD_CMD_ERASE_WR_BLK_END 33 +#define SD_CMD_ERASE_GROUP_START 35 +#define SD_CMD_ERASE_GROUP_END 36 +#define SD_CMD_ERASE 38 +#define SD_CMD_LOCK_UNLOCK 42 +#define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */ +#define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */ +#define SD_CMD_APP_CMD 55 +#define SD_CMD_GEN_CMD 56 +#define SD_CMD_READ_OCR 58 +#define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */ +#define SD_ACMD_SEND_NUM_WR_BLOCKS 22 +#define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23 +#define SD_ACMD_SD_SEND_OP_COND 41 +#define SD_ACMD_SET_CLR_CARD_DETECT 42 +#define SD_ACMD_SEND_SCR 51 + +/* response parameters */ +#define SD_RSP_NO_NONE 0 +#define SD_RSP_NO_1 1 +#define SD_RSP_NO_2 2 +#define SD_RSP_NO_3 3 +#define SD_RSP_NO_4 4 +#define SD_RSP_NO_5 5 +#define SD_RSP_NO_6 6 + +/* Modified R6 response (to CMD3) */ +#define SD_RSP_MR6_COM_CRC_ERROR 0x8000 +#define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000 +#define SD_RSP_MR6_ERROR 0x2000 + +/* Modified R1 in R4 Response (to CMD5) */ +#define SD_RSP_MR1_SBIT 0x80 +#define SD_RSP_MR1_PARAMETER_ERROR 0x40 +#define SD_RSP_MR1_RFU5 0x20 +#define SD_RSP_MR1_FUNC_NUM_ERROR 0x10 +#define SD_RSP_MR1_COM_CRC_ERROR 0x80 +#define SD_RSP_MR1_ILLEGAL_COMMAND 0x40 +#define SD_RSP_MR1_RFU1 0x20 +#define SD_RSP_MR1_IDLE_STATE 0x01 + +/* R5 response (to CMD52 and CMD53) */ +#define SD_RSP_R5_COM_CRC_ERROR 0x80 +#define SD_RSP_R5_ILLEGAL_COMMAND 0x40 +#define SD_RSP_R5_IO_CURRENTSTATE1 0x20 +#define SD_RSP_R5_IO_CURRENTSTATE0 0x10 +#define SD_RSP_R5_ERROR 0x80 +#define SD_RSP_R5_RFU 0x40 +#define SD_RSP_R5_FUNC_NUM_ERROR 0x20 +#define SD_RSP_R5_OUT_OF_RANGE 0x01 + +/* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */ +#define SD_OP_READ 0 /* Read_Write */ +#define SD_OP_WRITE 1 /* Read_Write */ + +#define SD_RW_NORMAL 0 /* no RAW */ +#define SD_RW_RAW 1 /* RAW */ + +#define SD_BYTE_MODE 0 /* Byte Mode */ +#define SD_BLOCK_MODE 1 /* BlockMode */ + +#define SD_FIXED_ADDRESS 0 /* fix Address */ +#define SD_INCREMENT_ADDRESS 1 /* IncrementAddress */ + +#define SD_CMD5_ARG_IO_OCR_MASK 0x00FFFFFF +#define SD_CMD5_ARG_IO_OCR_SHIFT 0 +#define SD_CMD55_ARG_RCA_SHIFT 16 +#define SD_CMD59_ARG_CRC_OPTION_MASK 0x01 +#define SD_CMD59_ARG_CRC_OPTION_SHIFT 0 + +/* SD_CMD_IO_RW_DIRECT Argument */ +#define SdioIoRWDirectArg(rw, raw, func, addr, data) \ + (((rw & 1) << 31) | ((func & 0x7) << 28) | \ + ((raw & 1) << 27) | ((addr & 0x1FFFF) << 9) | \ + (data & 0xFF)) + +/* build SD_CMD_IO_RW_EXTENDED Argument */ +#define SdioIoRWExtArg(rw, blk, func, addr, inc_addr, count) \ + (((rw & 1) << 31) | ((func & 0x7) << 28) | \ + ((blk & 1) << 27) | ((inc_addr & 1) << 26) | \ + ((addr & 0x1FFFF) << 9) | (count & 0x1FF)) + +/* + * The Common I/O area shall be implemented on all SDIO cards and + * is accessed the the host via I/O reads and writes to function 0, + * the registers within the CIA are provided to enable/disable + * the operationo fthe i/o funciton. + */ + +/* cccr_sdio_rev */ +#define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */ +#define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */ + +/* sd_rev */ +#define SDIO_REV_PHY_MASK 0x0f /* SD format version number */ +#define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */ +#define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */ +#define SDIO_INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */ +#define SDIO_INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */ +#define SDIO_INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */ +#define SDIO_IO_ABORT_RESET_ALL 0x08 /* I/O card reset */ +#define SDIO_IO_ABORT_FUNC_MASK 0x07 /* abort selection: function x */ +#define SDIO_BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */ +#define SDIO_BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */ +#define SDIO_BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */ +#define SDIO_BUS_DATA_WIDTH_MASK 0x03 /* bus width mask */ +#define SDIO_BUS_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */ +#define SDIO_BUS_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */ + +/* capability */ +#define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */ +#define SDIO_CAP_LSC 0x40 /* low speed card */ +#define SDIO_CAP_E4MI 0x20 /* enable int between block in 4-bit mode */ +#define SDIO_CAP_S4MI 0x10 /* support int between block in 4-bit mode */ +#define SDIO_CAP_SBS 0x08 /* support suspend/resume */ +#define SDIO_CAP_SRW 0x04 /* support read wait */ +#define SDIO_CAP_SMB 0x02 /* support multi-block transfer */ +#define SDIO_CAP_SDC 0x01 /* Support Direct cmd during multi-uint8 transfer */ + +/* CIA FBR1 registers */ +#define SDIO_FUNC1_INFO 0x100 /* basic info for function 1 */ +#define SDIO_FUNC1_EXT 0x101 /* extension of standard I/O device */ +#define SDIO_CIS_FUNC1_BASE_LOW 0x109 /* function 1 cis address bit 0-7 */ +#define SDIO_CIS_FUNC1_BASE_MID 0x10A /* function 1 cis address bit 8-15 */ +#define SDIO_CIS_FUNC1_BASE_HIGH 0x10B /* function 1 cis address bit 16 */ +#define SDIO_CSA_BASE_LOW 0x10C /* CSA base address uint8_t 0 */ +#define SDIO_CSA_BASE_MID 0x10D /* CSA base address uint8_t 1 */ +#define SDIO_CSA_BASE_HIGH 0x10E /* CSA base address uint8_t 2 */ +#define SDIO_CSA_DATA_OFFSET 0x10F /* CSA data register */ +#define SDIO_IO_BLK_SIZE_LOW 0x110 /* I/O block size uint8_t 0 */ +#define SDIO_IO_BLK_SIZE_HIGH 0x111 /* I/O block size uint8_t 1 */ + +/* SD_SDIO_FUNC1_INFO bits */ +#define SDIO_FUNC1_INFO_DIC 0x0f /* device interface code */ +#define SDIO_FUNC1_INFO_CSA 0x40 /* CSA support flag */ +#define SDIO_FUNC1_INFO_CSA_EN 0x80 /* CSA enabled */ + +/* SD_SDIO_FUNC1_EXT bits */ +#define SDIO_FUNC1_EXT_SHP 0x03 /* support high power */ +#define SDIO_FUNC1_EXT_EHP 0x04 /* enable high power */ + +/* devctr */ +/* I/O device interface code */ +#define SDIO_DEVCTR_DEVINTER 0x0f +/* support CSA */ +#define SDIO_DEVCTR_CSA_SUP 0x40 +/* enable CSA */ +#define SDIO_DEVCTR_CSA_EN 0x80 + +/* ext_dev */ +/* supports high-power mask */ +#define SDIO_HIGHPWR_SUPPORT_M 0x3 +/* enable high power */ +#define SDIO_HIGHPWR_EN 0x4 +/* standard power function(up to 200mA */ +#define SDIO_HP_STD 0 +/* need high power to operate */ +#define SDIO_HP_REQUIRED 0x2 +/* can work with standard power, but prefer high power */ +#define SDIO_HP_DESIRED 0x3 + +/* misc define */ +/* macro to calculate fbr register base */ +#define FBR_REG_BASE(n) (n*0x100) +#define SDIO_FUNC_0 0 +#define SDIO_FUNC_1 1 +#define SDIO_FUNC_2 2 +#define SDIO_FUNC_3 3 +#define SDIO_FUNC_4 4 +#define SDIO_FUNC_5 5 +#define SDIO_FUNC_6 6 +#define SDIO_FUNC_7 7 + +/* maximum block size for block mode operation */ +#define SDIO_MAX_BLOCK_SIZE 2048 +/* minimum block size for block mode operation */ +#define SDIO_MIN_BLOCK_SIZE 1 + +/* Card registers: status bit position */ +#define SDIO_STATUS_OUTOFRANGE 31 +#define SDIO_STATUS_COMCRCERROR 23 +#define SDIO_STATUS_ILLEGALCOMMAND 22 +#define SDIO_STATUS_ERROR 19 +#define SDIO_STATUS_IOCURRENTSTATE3 12 +#define SDIO_STATUS_IOCURRENTSTATE2 11 +#define SDIO_STATUS_IOCURRENTSTATE1 10 +#define SDIO_STATUS_IOCURRENTSTATE0 9 +#define SDIO_STATUS_FUN_NUM_ERROR 4 + +#define GET_SDIOCARD_STATUS(x) ((x >> 9) & 0x0f) +#define SDIO_STATUS_STATE_IDLE 0 +#define SDIO_STATUS_STATE_READY 1 +#define SDIO_STATUS_STATE_IDENT 2 +#define SDIO_STATUS_STATE_STBY 3 +#define SDIO_STATUS_STATE_TRAN 4 +#define SDIO_STATUS_STATE_DATA 5 +#define SDIO_STATUS_STATE_RCV 6 +#define SDIO_STATUS_STATE_PRG 7 +#define SDIO_STATUS_STATE_DIS 8 + +/* sprom */ +#define SBSDIO_SPROM_CS 0x10000 /* command and status */ +#define SBSDIO_SPROM_INFO 0x10001 /* info register */ +#define SBSDIO_SPROM_DATA_LOW 0x10002 /* indirect access data uint8_t 0 */ +#define SBSDIO_SPROM_DATA_HIGH 0x10003 /* indirect access data uint8_t 1 */ +#define SBSDIO_SPROM_ADDR_LOW 0x10004 /* indirect access addr uint8_t 0 */ +#define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* indirect access addr uint8_t 0 */ +#define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu data output */ +#define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu enable */ +#define SBSDIO_WATERMARK 0x10008 /* retired in rev 7 */ +#define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */ + +#define SBSDIO_SPROM_IDLE 0 +#define SBSDIO_SPROM_WRITE 1 +#define SBSDIO_SPROM_READ 2 +#define SBSDIO_SPROM_WEN 4 +#define SBSDIO_SPROM_WDS 7 +#define SBSDIO_SPROM_DONE 8 + +/* SBSDIO_SPROM_INFO */ +#define SBSDIO_SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */ +#define SBSDIO_SROM_BLANK 0x04 /* depreciated in corerev 6 */ +#define SBSDIO_SROM_OTP 0x80 /* OTP present */ + +/* SBSDIO_CHIP_CTRL */ +/* or'd with onchip xtal_pu, 1: power on oscillator */ +#define SBSDIO_CHIP_CTRL_XTAL 0x01 + +/* SBSDIO_WATERMARK */ +/* number of bytes minus 1 for sd device to wait before sending data to host */ +#define SBSDIO_WATERMARK_MASK 0x3f + +/* SBSDIO_DEVICE_CTL */ +/* 1: device will assert busy signal when receiving CMD53 */ +#define SBSDIO_DEVCTL_SETBUSY 0x01 +/* 1: assertion of sdio interrupt is synchronous to the sdio clock */ +#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 + +/* function 1 OCP space */ +/* sb offset addr is <= 15 bits, 32k */ +#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF +#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 +/* sdsdio function 1 OCP space has 16/32 bit section */ +#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 + +/* direct(mapped) cis space */ +/* MAPPED common CIS address */ +#define SBSDIO_CIS_BASE_COMMON 0x1000 +/* function 0(common) cis size in bytes */ +#define SBSDIO_CIS_FUNC0_LIMIT 0x020 +/* funciton 1 cis size in bytes */ +#define SBSDIO_CIS_SIZE_LIMIT 0x200 +/* cis offset addr is < 17 bits */ +#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF +/* manfid tuple length, include tuple, link bytes */ +#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 + +/* indirect cis access (in sprom) */ +/* 8 control bytes first, CIS starts from 8th uint8_t */ +#define SBSDIO_SPROM_CIS_OFFSET 0x8 +/* sdio uint8_t mode: maximum length of one data comamnd */ +#define SBSDIO_BYTEMODE_DATALEN_MAX 64 +/* 4317 supports less */ +#define SBSDIO_BYTEMODE_DATALEN_MAX_4317 52 +/* sdio core function one address mask */ +#define SBSDIO_CORE_ADDR_MASK 0x1FFFF + +/* CEATA defines */ +#define CEATA_EXT_CSDBLOCK_SIZE 512 +#define CEATA_FAST_IO 39 +#define CEATA_MULTIPLE_REGISTER_RW 60 +#define CEATA_MULTIPLE_BLOCK_RW 61 + +/* defines CE ATA task file registers */ +#define CEATA_SCT_CNT_EXP_REG 0x02 +#define CEATA_LBA_LOW_EXP_REG 0x03 +#define CEATA_LBA_MID_EXP_REG 0x04 +#define CEATA_LBA_HIGH_EXP_REG 0x05 +#define CEATA_CNTRL_REG 0x06 +#define CEATA_FEATURE_REG 0x09 /* write */ +#define CEATA_ERROR_REG 0x09 /* read */ +#define CEATA_SCT_CNT_REG 0x0A +#define CEATA_LBA_LOW_REG 0x0B +#define CEATA_LBA_MID_REG 0x0C +#define CEATA_LBA_HIGH_REG 0x0D +#define CEATA_DEV_HEAD_REG 0x0E +#define CEATA_STA_REG 0x0F /* read */ +#define CEATA_CMD_REG 0x0F /* write */ + +/* defines CEATA control and status registers for ce ata client driver */ +#define CEATA_SCR_TEMPC_REG 0x80 +#define CEATA_SCR_TEMPMAXP_REG 0x84 +#define CEATA_TEMPMINP_REG 0x88 +#define CEATA_SCR_STATUS_REG 0x8C +#define CEATA_SCR_REALLOCSA_REG 0x90 +#define CEATA_SCR_ERETRACTSA_REG 0x94 +#define CEATA_SCR_CAPABILITIES_REG 0x98 +#define CEATA_SCR_CONTROL_REG 0xC0 + +/* defines for SCR capabilities register bits for ce ata client driver */ +#define CEATA_SCR_CAP_512 0x00000001 +#define CEATA_SCR_CAP_1K 0x00000002 +#define CEATA_SCR_CAP_4K 0x00000004 + +/* defines CE ATA Control reg bits for ce ata client driver */ +#define CEATA_CNTRL_ENABLE_INTR 0x00 +#define CEATA_CNTRL_DISABLE_INTR 0x02 +#define CEATA_CNTRL_SRST 0x04 +#define CEATA_CNTRL_RSRST 0x00 + +/* define CE ATA Status reg bits for ce ata client driver */ +#define CEATA_STA_ERROR_BIT 0x01 +#define CEATA_STA_OVR_BIT 0x02 +#define CEATA_STA_SPT_BIT 0x04 +#define CEATA_STA_DRQ_BIT 0x08 +#define CEATA_STA_DRDY_BIT 0x40 +#define CEATA_STA_BSY_BIT 0x80 + +/* define CE ATA Error reg bits for ce ata client driver */ +#define CEATA_ERROR_ABORTED_BIT 0x04 +#define CEATA_ERROR_IDNF_BIT 0x10 +#define CEATA_ERROR_UNCORRECTABLE_BIT 0x40 +#define CEATA_ERROR_ICRC_BIT 0x80 + +/* define CE ATA Commands for ce ata client driver */ +#define CEATA_CMD_IDENTIFY_DEVICE 0xEC +#define CEATA_CMD_READ_DMA_EXT 0x25 +#define CEATA_CMD_WRITE_DMA_EXT 0x35 +#define CEATA_CMD_STANDBY_IMMEDIATE 0xE0 +#define CEATA_CMD_FLUSH_CACHE_EXT 0xEA + +struct csd_mmc { + uint32_t padding:8; + uint32_t structure:2; + uint32_t csdSpecVer:4; + uint32_t reserved1:2; + uint32_t taac:8; + uint32_t nsac:8; + uint32_t speed:8; + uint32_t classes:12; + uint32_t rdBlkLen:4; + uint32_t rdBlkPartial:1; + uint32_t wrBlkMisalign:1; + uint32_t rdBlkMisalign:1; + uint32_t dsr:1; + uint32_t reserved2:2; + uint32_t size:12; + uint32_t vddRdCurrMin:3; + uint32_t vddRdCurrMax:3; + uint32_t vddWrCurrMin:3; + uint32_t vddWrCurrMax:3; + uint32_t devSizeMulti:3; + uint32_t eraseGrpSize:5; + uint32_t eraseGrpSizeMulti:5; + uint32_t wrProtGroupSize:5; + uint32_t wrProtGroupEnable:1; + uint32_t manuDefEcc:2; + uint32_t wrSpeedFactor:3; + uint32_t wrBlkLen:4; + uint32_t wrBlkPartial:1; + uint32_t reserved5:4; + uint32_t protAppl:1; + uint32_t fileFormatGrp:1; + uint32_t copyFlag:1; + uint32_t permWrProt:1; + uint32_t tmpWrProt:1; + uint32_t fileFormat:2; + uint32_t eccCode:2; +}; + +/* CSD register*/ +union sd_csd { + uint32_t csd[4]; + struct csd_mmc mmc; +}; + +struct sd_card_data { + union sd_csd csd; +}; +#endif /* CSL_SD_PROT_H */ diff --git a/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h b/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h new file mode 100644 index 000000000..8e61b51c0 --- /dev/null +++ b/include/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PBOOT_HAL_MEMORY_EMMC_DRV_H +#define PBOOT_HAL_MEMORY_EMMC_DRV_H + +#include <drivers/delay_timer.h> + +#include "emmc_chal_types.h" +#include "emmc_chal_sd.h" +#include "emmc_csl_sdprot.h" +#include "emmc_csl_sdcmd.h" +#include "emmc_csl_sd.h" +#include "emmc_brcm_rdb_sd4_top.h" + +#define CLK_SDIO_DIV_52MHZ 0x0 +#define SYSCFG_IOCR4_PAD_10MA 0x38000000 + +#define SDCLK_CNT_PER_MS 52000 +#define BOOT_ACK_TIMEOUT (50 * SDCLK_CNT_PER_MS) +#define BOOT_DATA_TIMEOUT (1000 * SDCLK_CNT_PER_MS) + +#define EMMC_BOOT_OK 0 +#define EMMC_BOOT_ERROR 1 +#define EMMC_BOOT_TIMEOUT 2 +#define EMMC_BOOT_INVALIDIMAGE 3 +#define EMMC_BOOT_NO_CARD 4 + +#define EMMC_USER_AREA 0 +#define EMMC_BOOT_PARTITION1 1 +#define EMMC_BOOT_PARTITION2 2 +#define EMMC_USE_CURRENT_PARTITION 3 + +#define EMMC_BOOT_PARTITION_SIZE (128*1024) +#define EMMC_BLOCK_SIZE 512 +#define EMMC_DMA_SIZE (4*1024) + +/* + * EMMC4.3 definitions + * Table 6 EXT_CSD access mode + * Access + * Bits Access Name Operation + * 00 Command Set The command set is changed according to the Cmd Set field of + * the argument + * 01 Set Bits The bits in the pointed uint8_t are set, + * according to the 1 bits in the Value field. + * 10 Clear Bits The bits in the pointed uint8_t are cleared, + * according to the 1 bits in the Value field. + * 11 Write Byte The Value field is written into the pointed uint8_t. + */ + +#define SDIO_HW_EMMC_EXT_CSD_WRITE_BYTE 0X03000000 + +/* Boot bus width1 BOOT_BUS_WIDTH 1 R/W [177] */ +#define SDIO_HW_EMMC_EXT_CSD_BOOT_BUS_WIDTH_OFFSET 0X00B10000 + +/* Boot configuration BOOT_CONFIG 1 R/W [179] */ +#define SDIO_HW_EMMC_EXT_CSD_BOOT_CONFIG_OFFSET 0X00B30000 + +/* Bus width mode BUS_WIDTH 1 WO [183] */ +#define SDIO_HW_EMMC_EXT_CSD_BUS_WIDTH_OFFSET 0X00B70000 + +/* + * Bit 6: BOOT_ACK (non-volatile) + * 0x0 : No boot acknowledge sent (default) + * 0x1 : Boot acknowledge sent during boot operation + * Bit[5:3] : BOOT_PARTITION_ENABLE (non-volatile) + * User selects boot data that will be sent to master + * 0x0 : Device not boot enabled (default) + * 0x1 : Boot partition 1 enabled for boot + * 0x2 : Boot partition 2 enabled for boot + * 0x3-0x6 : Reserved + * 0x7 : User area enabled for boot + * Bit[2:0] : BOOT_PARTITION_ACCESS + * User selects boot partition for read and write operation + * 0x0 : No access to boot partition (default) + * 0x1 : R/W boot partition 1 + * 0x2 : R/W boot partition 2 + * 0x3-0x7 : Reserved + */ + +#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_BOOT1 0X00000100 +#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_BOOT2 0X00000200 +#define SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_USER 0X00000000 +#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_BOOT1 0X00004800 +#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_BOOT2 0X00005000 +#define SDIO_HW_EMMC_EXT_CSD_BOOT_EN_USER 0X00007800 + +#define SD_US_DELAY(x) udelay(x) + +#endif diff --git a/include/drivers/brcm/fru.h b/include/drivers/brcm/fru.h new file mode 100644 index 000000000..ee863b480 --- /dev/null +++ b/include/drivers/brcm/fru.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FRU_H +#define FRU_H + +#include <stdbool.h> +#include <stdint.h> + +/* max string length */ +#define FRU_MAX_STR_LEN 32 + +/* max number of DDR channels */ +#define BCM_MAX_NR_DDR 3 + +/* max supported FRU table size */ +#define BCM_MAX_FRU_LEN 512 + +/* FRU table starting offset */ +#define BCM_FRU_TBL_OFFSET 0x300000 + +/* FRU time constants */ +#define MINS_PER_DAY 1440 +#define MINS_PER_HOUR 60 +#define FRU_YEAR_START 1996 +#define FRU_MONTH_START 1 +#define FRU_DAY_START 1 +#define MONTHS_PER_YEAR 12 + +/* + * FRU areas based on the spec + */ +enum fru_area_name { + FRU_AREA_INTERNAL = 0, + FRU_AREA_CHASSIS_INFO, + FRU_AREA_BOARD_INFO, + FRU_AREA_PRODUCT_INFO, + FRU_AREA_MRECORD_INFO, + FRU_MAX_NR_AREAS +}; + +/* + * FRU area information + * + * @use: indicate this area is being used + * @version: format version + * @offset: offset of this area from the beginning of the FRU table + * @len: total length of the area + */ +struct fru_area_info { + bool use; + uint8_t version; + unsigned int offset; + unsigned int len; +}; + +/* + * DDR MCB information + * + * @idx: DDR channel index + * @size_mb: DDR size of this channel in MB + * @ref_id: DDR MCB reference ID + */ +struct ddr_mcb { + unsigned int idx; + unsigned int size_mb; + uint32_t ref_id; +}; + +/* + * DDR information + * + * @ddr_info: array that contains MCB related info for each channel + */ +struct ddr_info { + struct ddr_mcb mcb[BCM_MAX_NR_DDR]; +}; + +/* + * FRU board area information + * + * @lang: Language code + * @mfg_date: Manufacturing date + * @manufacturer: Manufacturer + * @product_name: Product name + * @serial_number: Serial number + * @part_number: Part number + * @file_id: FRU file ID + */ +struct fru_board_info { + unsigned char lang; + unsigned int mfg_date; + unsigned char manufacturer[FRU_MAX_STR_LEN]; + unsigned char product_name[FRU_MAX_STR_LEN]; + unsigned char serial_number[FRU_MAX_STR_LEN]; + unsigned char part_number[FRU_MAX_STR_LEN]; + unsigned char file_id[FRU_MAX_STR_LEN]; +}; + +/* + * FRU manufacture date in human readable format + */ +struct fru_time { + unsigned int min; + unsigned int hour; + unsigned int day; + unsigned int month; + unsigned int year; +}; + +#ifdef USE_FRU +int fru_validate(uint8_t *data, struct fru_area_info *fru_area); +int fru_parse_ddr(uint8_t *data, struct fru_area_info *area, + struct ddr_info *ddr); +int fru_parse_board(uint8_t *data, struct fru_area_info *area, + struct fru_board_info *board); +void fru_format_time(unsigned int min, struct fru_time *tm); +#else +static inline int fru_validate(uint8_t *data, struct fru_area_info *fru_area) +{ + return -1; +} + +static inline int fru_parse_ddr(uint8_t *data, struct fru_area_info *area, + struct ddr_info *ddr) +{ + return -1; +} + +static inline int fru_parse_board(uint8_t *data, struct fru_area_info *area, + struct fru_board_info *board) +{ + return -1; +} + +static inline void fru_format_time(unsigned int min, struct fru_time *tm) +{ +} +#endif /* USE_FRU */ + +#endif /* FRU_H */ diff --git a/include/drivers/brcm/iproc_gpio.h b/include/drivers/brcm/iproc_gpio.h new file mode 100644 index 000000000..be971f6f6 --- /dev/null +++ b/include/drivers/brcm/iproc_gpio.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IPROC_GPIO_H +#define IPROC_GPIO_H + +#ifdef USE_GPIO +void iproc_gpio_init(uintptr_t base, int nr_gpios, uintptr_t pinmux_base, + uintptr_t pinconf_base); +#else +static void iproc_gpio_init(uintptr_t base, int nr_gpios, uintptr_t pinmux_base, + uintptr_t pinconf_base) +{ +} +#endif /* IPROC_GPIO */ + +#endif /* IPROC_GPIO_H */ diff --git a/include/drivers/brcm/ocotp.h b/include/drivers/brcm/ocotp.h new file mode 100644 index 000000000..830b3e4cd --- /dev/null +++ b/include/drivers/brcm/ocotp.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef OCOTP_H +#define OCOTP_H + +#include <stdint.h> + +struct otpc_map { + /* in words. */ + uint32_t otpc_row_size; + /* 128 bit row / 4 words support. */ + uint16_t data_r_offset[4]; + /* 128 bit row / 4 words support. */ + uint16_t data_w_offset[4]; + int word_size; + int stride; +}; + +int bcm_otpc_init(struct otpc_map *map); +int bcm_otpc_read(unsigned int offset, void *val, uint32_t bytes, + uint32_t ecc_flag); + +#endif /* OCOTP_H */ diff --git a/include/drivers/brcm/scp.h b/include/drivers/brcm/scp.h new file mode 100644 index 000000000..7806314fa --- /dev/null +++ b/include/drivers/brcm/scp.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2017 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SCP_H +#define SCP_H + +#include <stdint.h> + +int download_scp_patch(void *image, unsigned int image_size); + +#endif /* SCP_H */ diff --git a/include/drivers/brcm/sf.h b/include/drivers/brcm/sf.h new file mode 100644 index 000000000..c32cbebf9 --- /dev/null +++ b/include/drivers/brcm/sf.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SF_H +#define SF_H + +#include <stdint.h> +#include <stddef.h> + +#ifdef SPI_DEBUG +#define SPI_DEBUG(fmt, ...) INFO(fmt, ##__VA_ARGS__) +#else +#define SPI_DEBUG(fmt, ...) +#endif + +#define SPI_FLASH_MAX_ID_LEN 6 + +#define CMD_WRSR 0x01 /* Write status register */ +#define CMD_PAGE_PROGRAM 0x02 +#define CMD_READ_NORMAL 0x03 +#define CMD_RDSR 0x05 +#define CMD_WRITE_ENABLE 0x06 +#define CMD_RDFSR 0x70 +#define CMD_READ_ID 0x9f +#define CMD_ERASE_4K 0x20 +#define CMD_ERASE_64K 0xd8 +#define ERASE_SIZE_64K (64 * 1024) + +/* Common status */ +#define STATUS_WIP BIT(0) + +struct spi_flash { + struct spi_slave *spi; + uint32_t size; + uint32_t page_size; + uint32_t sector_size; + uint32_t erase_size; + uint8_t erase_cmd; + uint8_t read_cmd; + uint8_t write_cmd; + uint8_t flags; +}; + +struct spi_flash_info { + const char *name; + + /* + * This array stores the ID bytes. + * The first three bytes are the JEDIC ID. + * JEDEC ID zero means "no ID" (mostly older chips). + */ + uint8_t id[SPI_FLASH_MAX_ID_LEN]; + uint8_t id_len; + + uint32_t sector_size; + uint32_t n_sectors; + uint16_t page_size; + + uint8_t flags; +}; + +/* Enum list - Full read commands */ +enum spi_read_cmds { + ARRAY_SLOW = BIT(0), + ARRAY_FAST = BIT(1), + DUAL_OUTPUT_FAST = BIT(2), + DUAL_IO_FAST = BIT(3), + QUAD_OUTPUT_FAST = BIT(4), + QUAD_IO_FAST = BIT(5), +}; + +/* sf param flags */ +enum spi_param_flag { + SECT_4K = BIT(0), + SECT_32K = BIT(1), + E_FSR = BIT(2), + SST_BP = BIT(3), + SST_WP = BIT(4), + WR_QPP = BIT(5), +}; + +int spi_flash_cmd_read(const uint8_t *cmd, size_t cmd_len, + void *data, size_t data_len); +int spi_flash_cmd(uint8_t cmd, void *response, size_t len); +int spi_flash_cmd_write(const uint8_t *cmd, size_t cmd_len, + const void *data, size_t data_len); +#endif diff --git a/include/drivers/brcm/sotp.h b/include/drivers/brcm/sotp.h new file mode 100644 index 000000000..a93d687f2 --- /dev/null +++ b/include/drivers/brcm/sotp.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2016-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOTP_H +#define SOTP_H + +#include <stddef.h> +#include <stdint.h> + +#include <platform_sotp.h> + +#define SOTP_ROW_NO_ECC 0 +#define SOTP_ROW_ECC 1 + +#define SOTP_STATUS_1 (SOTP_REGS_OTP_BASE + 0x001c) +#define SOTP_FAIL_BITS 0x18000000000 +#define SOTP_ECC_ERR_DETECT 0x8000000000000000 + +#define SOTP_REGS_SOTP_CHIP_STATES (SOTP_REGS_OTP_BASE + 0x0028) +#define SOTP_REGS_OTP_WR_LOCK (SOTP_REGS_OTP_BASE + 0x0038) + +#define SOTP_CHIP_STATES_MANU_DEBUG_MASK (1 << 8) +#define SOTP_DEVICE_SECURE_CFG0_OTP_ERASED_MASK (3 << 16) +#define SOTP_REGS_SOTP_CHIP_STATES_OTP_ERASED_MASK (1 << 16) + +#define SOTP_DEVICE_SECURE_CFG0_CID_MASK (3 << 2) +#define SOTP_DEVICE_SECURE_CFG0_AB_MASK (3 << 6) +#define SOTP_DEVICE_SECURE_CFG0_DEV_MASK (3 << 8) + +#define SOTP_BOOT_SOURCE_SHIFT 8 +/* bits 14 and 15 */ +#define SOTP_BOOT_SOURCE_ENABLE_MASK (0xC0 << SOTP_BOOT_SOURCE_SHIFT) +/* bits 8 to 13 */ +#define SOTP_BOOT_SOURCE_BITS0 (0x03 << SOTP_BOOT_SOURCE_SHIFT) +#define SOTP_BOOT_SOURCE_BITS1 (0x0C << SOTP_BOOT_SOURCE_SHIFT) +#define SOTP_BOOT_SOURCE_BITS2 (0x30 << SOTP_BOOT_SOURCE_SHIFT) +#define SOTP_BOOT_SOURCE_MASK (0x3F << SOTP_BOOT_SOURCE_SHIFT) + +#define SOTP_ATF_CFG_ROW_ID SOTP_DEVICE_SECURE_CFG2_ROW +/* bits 28 and 29 */ +#define SOTP_SBL_MASK (3 << 28) +/* bits 30 and 31 */ +#define SOTP_ATF_NVCOUNTER_ENABLE_MASK ((uint64_t)3 << 30) +/* bits 32 and 33 */ +#define SOTP_ATF_WATCHDOG_ENABLE_MASK ((uint64_t)3 << 32) +/* bits 34 and 35 */ +#define SOTP_ATF_PLL_ON ((uint64_t)3 << 34) +/* bits 36 and 37 */ +#define SOTP_ATF_RESET_RETRY ((uint64_t)3 << 36) +/* bits 38 to 40 */ +#define SOTP_ATF_LOG_LEVEL_SHIFT 38 +#define SOTP_ATF_LOG_LEVEL ((uint64_t)7 << SOTP_ATF_LOG_LEVEL_SHIFT) + +#define SOTP_ATF2_CFG_ROW_ID SOTP_DEVICE_SECURE_CFG3_ROW +/* bits 16 and 17 */ +#define SOTP_ROMKEY_MASK (3 << 16) +/* bits 18 and 19 */ +#define SOTP_EC_EN_MASK (3 << 18) + +#define SOTP_ENC_DEV_TYPE_AB_DEV ((uint64_t)0x19999800000) +#define SOTP_ENC_DEV_TYPE_MASK ((uint64_t)0x1ffff800000) + +uint64_t sotp_mem_read(uint32_t offset, uint32_t sotp_add_ecc); +void sotp_mem_write(uint32_t addr, uint32_t sotp_add_ecc, uint64_t wdata); +int sotp_read_key(uint8_t *key, size_t keysize, int start_row, int end_row); +int sotp_key_erased(void); +uint32_t sotp_redundancy_reduction(uint32_t sotp_row_data); +#endif diff --git a/include/drivers/brcm/spi.h b/include/drivers/brcm/spi.h new file mode 100644 index 000000000..9d92d8cfc --- /dev/null +++ b/include/drivers/brcm/spi.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2017 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPI_H +#define SPI_H + +#include <stdint.h> + +#define SPI_XFER_BEGIN (1 << 0) /* Assert CS before transfer */ +#define SPI_XFER_END (1 << 1) /* De-assert CS after transfer */ +#define SPI_XFER_QUAD (1 << 2) + +int spi_init(void); +int spi_claim_bus(void); +void spi_release_bus(void); +int spi_xfer(uint32_t bitlen, const void *dout, void *din, uint32_t flags); + +#endif /* _SPI_H_ */ diff --git a/include/drivers/brcm/spi_flash.h b/include/drivers/brcm/spi_flash.h new file mode 100644 index 000000000..bbaaa5088 --- /dev/null +++ b/include/drivers/brcm/spi_flash.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPI_FLASH_H +#define SPI_FLASH_H + +#include <sf.h> + +int spi_flash_probe(struct spi_flash *flash); +int spi_flash_erase(struct spi_flash *flash, uint32_t offset, uint32_t len); +int spi_flash_write(struct spi_flash *flash, uint32_t offset, + uint32_t len, void *buf); +int spi_flash_read(struct spi_flash *flash, uint32_t offset, + uint32_t len, void *data); +#endif /* _SPI_FLASH_H_ */ diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h index 64a062ca1..30ca910b9 100644 --- a/include/drivers/cadence/cdns_uart.h +++ b/include/drivers/cadence/cdns_uart.h @@ -21,21 +21,15 @@ #define R_UART_SR 0x2C #define UART_SR_INTR_REMPTY_BIT 1 #define UART_SR_INTR_TFUL_BIT 4 +#define UART_SR_INTR_TEMPTY_BIT 3 #define R_UART_TX 0x30 #define R_UART_RX 0x30 -#define CONSOLE_T_CDNS_BASE CONSOLE_T_DRVDATA - #ifndef __ASSEMBLER__ #include <stdint.h> -typedef struct { - console_t console; - uintptr_t base; -} console_cdns_t; - /* * Initialize a new Cadence console instance and register it with the console * framework. The |console| pointer must point to storage that will be valid @@ -43,7 +37,7 @@ typedef struct { * Its contents will be reinitialized from scratch. */ int console_cdns_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - console_cdns_t *console); + console_t *console); #endif /*__ASSEMBLER__*/ diff --git a/include/drivers/console.h b/include/drivers/console.h index a4859d80f..99bf96041 100644 --- a/include/drivers/console.h +++ b/include/drivers/console.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,7 +14,8 @@ #define CONSOLE_T_PUTC (U(2) * REGSZ) #define CONSOLE_T_GETC (U(3) * REGSZ) #define CONSOLE_T_FLUSH (U(4) * REGSZ) -#define CONSOLE_T_DRVDATA (U(5) * REGSZ) +#define CONSOLE_T_BASE (U(5) * REGSZ) +#define CONSOLE_T_DRVDATA (U(6) * REGSZ) #define CONSOLE_FLAG_BOOT (U(1) << 0) #define CONSOLE_FLAG_RUNTIME (U(1) << 1) @@ -42,7 +43,8 @@ typedef struct console { u_register_t flags; int (*const putc)(int character, struct console *console); int (*const getc)(struct console *console); - int (*const flush)(struct console *console); + void (*const flush)(struct console *console); + uintptr_t base; /* Additional private driver data may follow here. */ } console_t; @@ -74,7 +76,7 @@ int console_putc(int c); /* Read a character (blocking) from any console registered for current state. */ int console_getc(void); /* Flush all consoles registered for the current state. */ -int console_flush(void); +void console_flush(void); #endif /* __ASSEMBLER__ */ diff --git a/include/drivers/coreboot/cbmem_console.h b/include/drivers/coreboot/cbmem_console.h index 40c90e6bb..30b39f14d 100644 --- a/include/drivers/coreboot/cbmem_console.h +++ b/include/drivers/coreboot/cbmem_console.h @@ -9,14 +9,12 @@ #include <drivers/console.h> -#define CONSOLE_T_CBMC_BASE CONSOLE_T_DRVDATA -#define CONSOLE_T_CBMC_SIZE (CONSOLE_T_DRVDATA + REGSZ) +#define CONSOLE_T_CBMC_SIZE CONSOLE_T_DRVDATA #ifndef __ASSEMBLER__ typedef struct { console_t console; - uintptr_t base; uint32_t size; } console_cbmc_t; diff --git a/include/drivers/io/io_encrypted.h b/include/drivers/io/io_encrypted.h new file mode 100644 index 000000000..9dcf061b4 --- /dev/null +++ b/include/drivers/io/io_encrypted.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2020, Linaro Limited. All rights reserved. + * Author: Sumit Garg <sumit.garg@linaro.org> + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IO_ENCRYPTED_H +#define IO_ENCRYPTED_H + +struct io_dev_connector; + +int register_io_dev_enc(const struct io_dev_connector **dev_con); + +#endif /* IO_ENCRYPTED_H */ diff --git a/include/drivers/io/io_fip.h b/include/drivers/io/io_fip.h index e0b57463f..7e654361d 100644 --- a/include/drivers/io/io_fip.h +++ b/include/drivers/io/io_fip.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,5 +10,6 @@ struct io_dev_connector; int register_io_dev_fip(const struct io_dev_connector **dev_con); +int fip_dev_get_plat_toc_flag(io_dev_info_t *dev_info, uint16_t *plat_toc_flag); #endif /* IO_FIP_H */ diff --git a/include/drivers/io/io_storage.h b/include/drivers/io/io_storage.h index 0e6ffd619..f2d641c2d 100644 --- a/include/drivers/io/io_storage.h +++ b/include/drivers/io/io_storage.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,6 +25,7 @@ typedef enum { IO_TYPE_MTD, IO_TYPE_MMC, IO_TYPE_STM32IMAGE, + IO_TYPE_ENCRYPTED, IO_TYPE_MAX } io_type_t; @@ -53,7 +54,7 @@ typedef struct io_file_spec { /* UUID specification - used to refer to data accessed using UUIDs (i.e. FIP * images) */ typedef struct io_uuid_spec { - const uuid_t uuid; + uuid_t uuid; } io_uuid_spec_t; /* Block specification - used to refer to data on a device supporting diff --git a/include/drivers/marvell/aro.h b/include/drivers/marvell/aro.h index c16f62538..4d1094a65 100644 --- a/include/drivers/marvell/aro.h +++ b/include/drivers/marvell/aro.h @@ -21,11 +21,13 @@ enum hws_freq { DDR_FREQ_SAR }; +#include <mvebu_def.h> + enum cpu_clock_freq_mode { CPU_2000_DDR_1200_RCLK_1200 = 0x0, CPU_2000_DDR_1050_RCLK_1050 = 0x1, CPU_1600_DDR_800_RCLK_800 = 0x4, - CPU_1800_DDR_1200_RCLK_1200 = 0x6, + CPU_2200_DDR_1200_RCLK_1200 = 0x6, CPU_1800_DDR_1050_RCLK_1050 = 0x7, CPU_1600_DDR_900_RCLK_900 = 0x0B, CPU_1600_DDR_1050_RCLK_1050 = 0x0D, diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h index 85babb8d4..72111b374 100644 --- a/include/drivers/marvell/cache_llc.h +++ b/include/drivers/marvell/cache_llc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018 Marvell International Ltd. + * Copyright (C) 2018-2020 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -13,19 +13,35 @@ #define CACHE_LLC_H #define LLC_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x100) +#define LLC_SECURE_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x10C) #define LLC_SYNC(ap) (MVEBU_LLC_BASE(ap) + 0x700) -#define L2X0_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C) -#define L2X0_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC) -#define L2X0_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC) -#define LLC_TC0_LOCK(ap) (MVEBU_LLC_BASE(ap) + 0x920) +#define LLC_BANKED_MNT_AHR(ap) (MVEBU_LLC_BASE(ap) + 0x724) +#define LLC_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C) +#define LLC_BLK_ALOC(ap) (MVEBU_LLC_BASE(ap) + 0x78c) +#define LLC_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC) +#define LLC_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC) +#define LLC_TCN_LOCK(ap, tc) (MVEBU_LLC_BASE(ap) + 0x920 + 4 * (tc)) #define MASTER_LLC_CTRL LLC_CTRL(MVEBU_AP0) -#define MASTER_L2X0_INV_WAY L2X0_INV_WAY(MVEBU_AP0) -#define MASTER_LLC_TC0_LOCK LLC_TC0_LOCK(MVEBU_AP0) +#define MASTER_LLC_INV_WAY LLC_INV_WAY(MVEBU_AP0) +#define MASTER_LLC_TC0_LOCK LLC_TCN_LOCK(MVEBU_AP0, 0) #define LLC_CTRL_EN 1 #define LLC_EXCLUSIVE_EN 0x100 -#define LLC_WAY_MASK 0xFFFFFFFF +#define LLC_ALL_WAYS_MASK 0xFFFFFFFF + +/* AP806/AP807 - 1MB 8-ways LLC */ +#define LLC_WAYS 8 +#define LLC_WAY_MASK ((1 << LLC_WAYS) - 1) +#define LLC_SIZE (1024 * 1024) +#define LLC_WAY_SIZE (LLC_SIZE / LLC_WAYS) +#define LLC_TC_NUM 15 + +#define LLC_BLK_ALOC_WAY_ID(way) ((way) & 0x1f) +#define LLC_BLK_ALOC_WAY_DATA_DSBL (0x0 << 6) +#define LLC_BLK_ALOC_WAY_DATA_CLR (0x1 << 6) +#define LLC_BLK_ALOC_WAY_DATA_SET (0x3 << 6) +#define LLC_BLK_ALOC_BASE_ADDR(addr) ((addr) & ~(LLC_WAY_SIZE - 1)) #ifndef __ASSEMBLER__ void llc_cache_sync(int ap_index); @@ -36,6 +52,11 @@ void llc_disable(int ap_index); void llc_enable(int ap_index, int excl_mode); int llc_is_exclusive(int ap_index); void llc_runtime_enable(int ap_index); -#endif +#if LLC_SRAM +int llc_sram_enable(int ap_index, int size); +void llc_sram_disable(int ap_index); +int llc_sram_test(int ap_index, int size, char *msg); +#endif /* LLC_SRAM */ +#endif /* __ASSEMBLER__ */ #endif /* CACHE_LLC_H */ diff --git a/include/drivers/marvell/ccu.h b/include/drivers/marvell/ccu.h index b0d1ec984..f8f0adf67 100644 --- a/include/drivers/marvell/ccu.h +++ b/include/drivers/marvell/ccu.h @@ -46,6 +46,8 @@ void ccu_dram_win_config(int ap_index, struct addr_map_win *win); void ccu_dram_target_set(int ap_index, uint32_t target); void ccu_save_win_all(int ap_id); void ccu_restore_win_all(int ap_id); +int ccu_is_win_enabled(int ap_index, uint32_t win_id); +void errata_wa_init(void); #endif #endif /* CCU_H */ diff --git a/include/drivers/marvell/mci.h b/include/drivers/marvell/mci.h index 8ef023459..af5d62066 100644 --- a/include/drivers/marvell/mci.h +++ b/include/drivers/marvell/mci.h @@ -10,7 +10,7 @@ #ifndef MCI_H #define MCI_H -int mci_initialize(int mci_index); +int mci_link_tune(int mci_index); void mci_turn_link_down(void); void mci_turn_link_on(void); int mci_get_link_status(void); diff --git a/include/drivers/marvell/mochi/ap_setup.h b/include/drivers/marvell/mochi/ap_setup.h index eff447325..5b0e75f46 100644 --- a/include/drivers/marvell/mochi/ap_setup.h +++ b/include/drivers/marvell/mochi/ap_setup.h @@ -13,5 +13,6 @@ void ap_init(void); void ap_ble_init(void); int ap_get_count(void); +void update_cp110_default_win(int cp_id); #endif /* AP_SETUP_H */ diff --git a/include/drivers/marvell/mochi/cp110_setup.h b/include/drivers/marvell/mochi/cp110_setup.h index 3686257d3..11dc4e020 100644 --- a/include/drivers/marvell/mochi/cp110_setup.h +++ b/include/drivers/marvell/mochi/cp110_setup.h @@ -24,6 +24,7 @@ #define MVEBU_3900_DEV_ID (0x6025) #define MVEBU_80X0_DEV_ID (0x8040) #define MVEBU_80X0_CP115_DEV_ID (0x8045) +#define MVEBU_CN9130_DEV_ID (0x7025) #define MVEBU_CP110_SA_DEV_ID (0x110) #define MVEBU_CP110_REF_ID_A1 1 #define MVEBU_CP110_REF_ID_A2 2 @@ -51,5 +52,6 @@ static inline uint32_t cp110_rev_id_get(uintptr_t base) void cp110_init(uintptr_t cp110_base, uint32_t stream_id); void cp110_ble_init(uintptr_t cp110_base); +void cp110_amb_init(uintptr_t base); #endif /* CP110_SETUP_H */ diff --git a/include/drivers/marvell/uart/a3700_console.h b/include/drivers/marvell/uart/a3700_console.h index 517f01a8f..12d2cdc52 100644 --- a/include/drivers/marvell/uart/a3700_console.h +++ b/include/drivers/marvell/uart/a3700_console.h @@ -48,23 +48,17 @@ /* Line Status Register bits */ #define UARTLSR_TXFIFOFULL (1 << 11) /* Tx Fifo Full */ +#define UARTLSR_TXEMPTY (1 << 6) /* Tx Empty */ +#define UARTLSR_RXRDY (1 << 4) /* Rx Ready */ /* UART Control Register bits */ #define UART_CTRL_RXFIFO_RESET (1 << 14) #define UART_CTRL_TXFIFO_RESET (1 << 15) -#define UARTLSR_TXFIFOEMPTY (1 << 6) - -#define CONSOLE_T_A3700_BASE CONSOLE_T_DRVDATA #ifndef __ASSEMBLER__ #include <stdint.h> -typedef struct { - console_t console; - uintptr_t base; -} console_a3700_t; - /* * Initialize a new a3700 console instance and register it with the console * framework. The |console| pointer must point to storage that will be valid @@ -72,7 +66,7 @@ typedef struct { * Its contents will be reinitialized from scratch. */ int console_a3700_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - console_a3700_t *console); + console_t *console); #endif /*__ASSEMBLER__*/ diff --git a/include/drivers/measured_boot/event_log.h b/include/drivers/measured_boot/event_log.h new file mode 100644 index 000000000..efde11762 --- /dev/null +++ b/include/drivers/measured_boot/event_log.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EVENT_LOG_H +#define EVENT_LOG_H + +#include <stdint.h> + +#include <common/debug.h> +#include <drivers/measured_boot/tcg.h> + +/* + * Set Event Log debug level to one of: + * + * LOG_LEVEL_ERROR + * LOG_LEVEL_INFO + * LOG_LEVEL_WARNING + * LOG_LEVEL_VERBOSE + */ +#if EVENT_LOG_LEVEL == LOG_LEVEL_ERROR +#define LOG_EVENT ERROR +#elif EVENT_LOG_LEVEL == LOG_LEVEL_NOTICE +#define LOG_EVENT NOTICE +#elif EVENT_LOG_LEVEL == LOG_LEVEL_WARNING +#define LOG_EVENT WARN +#elif EVENT_LOG_LEVEL == LOG_LEVEL_INFO +#define LOG_EVENT INFO +#elif EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE +#define LOG_EVENT VERBOSE +#else +#error "Not supported EVENT_LOG_LEVEL" +#endif + +/* Number of hashing algorithms supported */ +#define HASH_ALG_COUNT 1U + +#define INVALID_ID MAX_NUMBER_IDS + +#define MEMBER_SIZE(type, member) sizeof(((type *)0)->member) + +#define BL2_STRING "BL_2" +#define BL31_STRING "BL_31" +#define BL32_STRING "BL_32" +#define BL32_EXTRA1_IMAGE_STRING "BL32_EXTRA1_IMAGE" +#define BL32_EXTRA2_IMAGE_STRING "BL32_EXTRA2_IMAGE" +#define BL33_STRING "BL_33" +#define GPT_IMAGE_STRING "GPT" +#define HW_CONFIG_STRING "HW_CONFIG" +#define NT_FW_CONFIG_STRING "NT_FW_CONFIG" +#define SCP_BL2_IMAGE_STRING "SCP_BL2_IMAGE" +#define SOC_FW_CONFIG_STRING "SOC_FW_CONFIG" +#define STM32_IMAGE_STRING "STM32" +#define TOS_FW_CONFIG_STRING "TOS_FW_CONFIG" + +typedef struct { + unsigned int id; + const char *name; + unsigned int pcr; +} image_data_t; + +typedef struct { + const image_data_t *images_data; + int (*set_nt_fw_info)(uintptr_t config_base, +#ifdef SPD_opteed + uintptr_t log_addr, +#endif + size_t log_size, uintptr_t *ns_log_addr); + int (*set_tos_fw_info)(uintptr_t config_base, uintptr_t log_addr, + size_t log_size); +} measured_boot_data_t; + +#define ID_EVENT_SIZE (sizeof(id_event_headers_t) + \ + (sizeof(id_event_algorithm_size_t) * HASH_ALG_COUNT) + \ + sizeof(id_event_struct_data_t)) + +#define LOC_EVENT_SIZE (sizeof(event2_header_t) + \ + sizeof(tpmt_ha) + TCG_DIGEST_SIZE + \ + sizeof(event2_data_t) + \ + sizeof(startup_locality_event_t)) + +#define LOG_MIN_SIZE (ID_EVENT_SIZE + LOC_EVENT_SIZE) + +#define EVENT2_HDR_SIZE (sizeof(event2_header_t) + \ + sizeof(tpmt_ha) + TCG_DIGEST_SIZE + \ + sizeof(event2_data_t)) + +/* Functions' declarations */ +void event_log_init(void); +int event_log_finalise(uint8_t **log_addr, size_t *log_size); +void dump_event_log(uint8_t *log_addr, size_t log_size); +const measured_boot_data_t *plat_get_measured_boot_data(void); +int tpm_record_measurement(uintptr_t data_base, uint32_t data_size, + uint32_t data_id); +#endif /* EVENT_LOG_H */ diff --git a/include/drivers/measured_boot/measured_boot.h b/include/drivers/measured_boot/measured_boot.h new file mode 100644 index 000000000..f8769ab43 --- /dev/null +++ b/include/drivers/measured_boot/measured_boot.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MEASURED_BOOT_H +#define MEASURED_BOOT_H + +#include <stdint.h> + +#include <drivers/measured_boot/event_log.h> + +/* Platform specific table of image IDs, names and PCRs */ +extern const image_data_t images_data[]; + +/* Functions' declarations */ +void measured_boot_init(void); +void measured_boot_finish(void); + +#endif /* MEASURED_BOOT_H */ diff --git a/include/drivers/measured_boot/tcg.h b/include/drivers/measured_boot/tcg.h new file mode 100644 index 000000000..ab27a0844 --- /dev/null +++ b/include/drivers/measured_boot/tcg.h @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TCG_H +#define TCG_H + +#include <stdint.h> + +#define TCG_ID_EVENT_SIGNATURE_03 "Spec ID Event03" +#define TCG_STARTUP_LOCALITY_SIGNATURE "StartupLocality" + +#define TCG_SPEC_VERSION_MAJOR_TPM2 2 +#define TCG_SPEC_VERSION_MINOR_TPM2 0 +#define TCG_SPEC_ERRATA_TPM2 2 + +/* + * Event types + * Ref. Table 9 Events + * TCG PC Client Platform Firmware Profile Specification. + */ +#define EV_PREBOOT_CERT U(0x00000000) +#define EV_POST_CODE U(0x00000001) +#define EV_UNUSED U(0x00000002) +#define EV_NO_ACTION U(0x00000003) +#define EV_SEPARATOR U(0x00000004) +#define EV_ACTION U(0x00000005) +#define EV_EVENT_TAG U(0x00000006) +#define EV_S_CRTM_CONTENTS U(0x00000007) +#define EV_S_CRTM_VERSION U(0x00000008) +#define EV_CPU_MICROCODE U(0x00000009) +#define EV_PLATFORM_CONFIG_FLAGS U(0x0000000A) +#define EV_TABLE_OF_DEVICES U(0x0000000B) +#define EV_COMPACT_HASH U(0x0000000C) +#define EV_IPL U(0x0000000D) +#define EV_IPL_PARTITION_DATA U(0x0000000E) +#define EV_NONHOST_CODE U(0x0000000F) +#define EV_NONHOST_CONFIG U(0x00000010) +#define EV_NONHOST_INFO U(0x00000011) +#define EV_OMIT_BOOT_DEVICE_EVENTS U(0x00000012) +#define EV_EFI_EVENT_BASE U(0x80000000) +#define EV_EFI_VARIABLE_DRIVER_CONFIG U(0x80000001) +#define EV_EFI_VARIABLE_BOOT U(0x80000002) +#define EV_EFI_BOOT_SERVICES_APPLICATION U(0x80000003) +#define EV_EFI_BOOT_SERVICES_DRIVER U(0x80000004) +#define EV_EFI_RUNTIME_SERVICES_DRIVER U(0x80000005) +#define EV_EFI_GPT_EVENT U(0x80000006) +#define EV_EFI_ACTION U(0x80000007) +#define EV_EFI_PLATFORM_FIRMWARE_BLOB U(0x80000008) +#define EV_EFI_HANDOFF_TABLES U(0x80000009) +#define EV_EFI_HCRTM_EVENT U(0x80000010) +#define EV_EFI_VARIABLE_AUTHORITY U(0x800000E0) + +/* + * TPM_ALG_ID constants. + * Ref. Table 9 - Definition of (UINT16) TPM_ALG_ID Constants + * Trusted Platform Module Library. Part 2: Structures + */ +#define TPM_ALG_SHA256 0x000B +#define TPM_ALG_SHA384 0x000C +#define TPM_ALG_SHA512 0x000D + +/* TCG Platform Type */ +#define PLATFORM_CLASS_CLIENT 0 +#define PLATFORM_CLASS_SERVER 1 + +/* SHA digest sizes in bytes */ +#define SHA1_DIGEST_SIZE 20 +#define SHA256_DIGEST_SIZE 32 +#define SHA384_DIGEST_SIZE 48 +#define SHA512_DIGEST_SIZE 64 + +enum { + /* + * SRTM, BIOS, Host Platform Extensions, Embedded + * Option ROMs and PI Drivers + */ + PCR_0 = 0, + /* Host Platform Configuration */ + PCR_1, + /* UEFI driver and application Code */ + PCR_2, + /* UEFI driver and application Configuration and Data */ + PCR_3, + /* UEFI Boot Manager Code (usually the MBR) and Boot Attempts */ + PCR_4, + /* + * Boot Manager Code Configuration and Data (for use + * by the Boot Manager Code) and GPT/Partition Table + */ + PCR_5, + /* Host Platform Manufacturer Specific */ + PCR_6, + /* Secure Boot Policy */ + PCR_7, + /* 8-15: Defined for use by the Static OS */ + PCR_8, + /* Debug */ + PCR_16 = 16 +}; + +#pragma pack(push, 1) + +/* + * PCR Event Header + * TCG EFI Protocol Specification + * 5.3 Event Log Header + */ +typedef struct { + /* PCRIndex: + * The PCR Index to which this event is extended + */ + uint32_t pcr_index; + + /* EventType: + * SHALL be an EV_NO_ACTION event + */ + uint32_t event_type; + + /* SHALL be 20 Bytes of 0x00 */ + uint8_t digest[SHA1_DIGEST_SIZE]; + + /* The size of the event */ + uint32_t event_size; + + /* SHALL be a TCG_EfiSpecIdEvent */ + uint8_t event[]; /* [event_data_size] */ +} tcg_pcr_event_t; + +/* + * Log Header Entry Data + * Ref. Table 14 TCG_EfiSpecIdEventAlgorithmSize + * TCG PC Client Platform Firmware Profile 9.4.5.1 + */ +typedef struct { + /* Algorithm ID (hashAlg) of the Hash used by BIOS */ + uint16_t algorithm_id; + + /* The size of the digest produced by the implemented Hash algorithm */ + uint16_t digest_size; +} id_event_algorithm_size_t; + +/* + * TCG_EfiSpecIdEvent structure + * Ref. Table 15 TCG_EfiSpecIdEvent + * TCG PC Client Platform Firmware Profile 9.4.5.1 + */ +typedef struct { + /* + * The NUL-terminated ASCII string "Spec ID Event03". + * SHALL be set to {0x53, 0x70, 0x65, 0x63, 0x20, 0x49, 0x44, + * 0x20, 0x45, 0x76, 0x65, 0x6e, 0x74, 0x30, 0x33, 0x00}. + */ + uint8_t signature[16]; + + /* + * The value for the Platform Class. + * The enumeration is defined in the TCG ACPI Specification Client + * Common Header. + */ + uint32_t platform_class; + + /* + * The PC Client Platform Profile Specification minor version number + * this BIOS supports. + * Any BIOS supporting this version (2.0) MUST set this value to 0x00. + */ + uint8_t spec_version_minor; + + /* + * The PC Client Platform Profile Specification major version number + * this BIOS supports. + * Any BIOS supporting this version (2.0) MUST set this value to 0x02. + */ + uint8_t spec_version_major; + + /* + * The PC Client Platform Profile Specification errata version number + * this BIOS supports. + * Any BIOS supporting this version (2.0) MUST set this value to 0x02. + */ + uint8_t spec_errata; + + /* + * Specifies the size of the UINTN fields used in various data + * structures used in this specification. + * 0x01 indicates UINT32 and 0x02 indicates UINT64. + */ + uint8_t uintn_size; + + /* + * The number of Hash algorithms in the digestSizes field. + * This field MUST be set to a value of 0x01 or greater. + */ + uint32_t number_of_algorithms; + + /* + * Each TCG_EfiSpecIdEventAlgorithmSize SHALL contain an algorithmId + * and digestSize for each hash algorithm used in the TCG_PCR_EVENT2 + * structure, the first of which is a Hash algorithmID and the second + * is the size of the respective digest. + */ + id_event_algorithm_size_t digest_size[]; /* number_of_algorithms */ +} id_event_struct_header_t; + +typedef struct { + /* + * Size in bytes of the VendorInfo field. + * Maximum value MUST be FFh bytes. + */ + uint8_t vendor_info_size; + + /* + * Provided for use by Platform Firmware implementer. The value might + * be used, for example, to provide more detailed information about the + * specific BIOS such as BIOS revision numbers, etc. The values within + * this field are not standardized and are implementer-specific. + * Platform-specific or -unique information MUST NOT be provided in + * this field. + * + */ + uint8_t vendor_info[]; /* [vendorInfoSize] */ +} id_event_struct_data_t; + +typedef struct { + id_event_struct_header_t struct_header; + id_event_struct_data_t struct_data; +} id_event_struct_t; + +typedef struct { + tcg_pcr_event_t header; + id_event_struct_header_t struct_header; +} id_event_headers_t; + +/* TPMT_HA Structure */ +typedef struct { + /* Selector of the hash contained in the digest that implies + * the size of the digest + */ + uint16_t algorithm_id; /* AlgorithmId */ + + /* Digest, depends on AlgorithmId */ + uint8_t digest[]; /* Digest[] */ +} tpmt_ha; + +/* + * TPML_DIGEST_VALUES Structure + */ +typedef struct { + /* The number of digests in the list */ + uint32_t count; /* Count */ + + /* The list of tagged digests, as sent to the TPM as part of a + * TPM2_PCR_Extend or as received from a TPM2_PCR_Event command + */ + tpmt_ha digests[]; /* Digests[Count] */ +} tpml_digest_values; + +/* + * TCG_PCR_EVENT2 header + */ +typedef struct { + /* The PCR Index to which this event was extended */ + uint32_t pcr_index; /* PCRIndex */ + + /* Type of event */ + uint32_t event_type; /* EventType */ + + /* Digests: + * A counted list of tagged digests, which contain the digest of + * the event data (or external data) for all active PCR banks + */ + tpml_digest_values digests; /* Digests */ +} event2_header_t; + +typedef struct event2_data { + /* The size of the event data */ + uint32_t event_size; /* EventSize */ + + /* The data of the event */ + uint8_t event[]; /* Event[EventSize] */ +} event2_data_t; + +/* + * Startup Locality Event + * Ref. TCG PC Client Platform Firmware Profile 9.4.5.3 + */ +typedef struct { + /* + * The NUL-terminated ASCII string "StartupLocality" SHALL be + * set to {0x53 0x74 0x61 0x72 0x74 0x75 0x70 0x4C 0x6F 0x63 + * 0x61 0x6C 0x69 0x74 0x79 0x00} + */ + uint8_t signature[16]; + + /* The Locality Indicator which sent the TPM2_Startup command */ + uint8_t startup_locality; +} startup_locality_event_t; + +#pragma pack(pop) + +#endif /* TCG_H */ diff --git a/include/drivers/raw_nand.h b/include/drivers/raw_nand.h index 18e4b73da..715230094 100644 --- a/include/drivers/raw_nand.h +++ b/include/drivers/raw_nand.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #ifndef DRIVERS_RAW_NAND_H #define DRIVERS_RAW_NAND_H +#include <cdefs.h> #include <stdint.h> #include <drivers/nand.h> @@ -168,7 +169,7 @@ struct rawnand_device { }; int nand_raw_init(unsigned long long *size, unsigned int *erase_size); -int nand_wait_ready(unsigned long delay); +int nand_wait_ready(unsigned int delay_ms); int nand_read_page_cmd(unsigned int page, unsigned int offset, uintptr_t buffer, unsigned int len); int nand_change_read_column_cmd(unsigned int offset, uintptr_t buffer, diff --git a/include/drivers/renesas/rcar/console/console.h b/include/drivers/renesas/rcar/console/console.h index 0e4ed8f35..7d5b5d3ce 100644 --- a/include/drivers/renesas/rcar/console/console.h +++ b/include/drivers/renesas/rcar/console/console.h @@ -7,17 +7,10 @@ #ifndef RCAR_PRINTF_H #define RCAR_PRINTF_H -#define CONSOLE_T_RCAR_BASE CONSOLE_T_DRVDATA - #ifndef __ASSEMBLER__ #include <stdint.h> -typedef struct { - console_t console; - uintptr_t base; -} console_rcar_t; - /* * Initialize a new rcar console instance and register it with the console * framework. The |console| pointer must point to storage that will be valid @@ -25,7 +18,7 @@ typedef struct { * Its contents will be reinitialized from scratch. */ int console_rcar_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - console_rcar_t *console); + console_t *console); #endif /*__ASSEMBLER__*/ diff --git a/include/drivers/rpi3/gpio/rpi3_gpio.h b/include/drivers/rpi3/gpio/rpi3_gpio.h index 159a2e08b..7bb3ee25b 100644 --- a/include/drivers/rpi3/gpio/rpi3_gpio.h +++ b/include/drivers/rpi3/gpio/rpi3_gpio.h @@ -11,11 +11,7 @@ #include <stdint.h> #include <drivers/gpio.h> -struct rpi3_gpio_params { - uintptr_t reg_base; -}; - -void rpi3_gpio_init(struct rpi3_gpio_params *params); +void rpi3_gpio_init(void); int rpi3_gpio_get_select(int gpio); void rpi3_gpio_set_select(int gpio, int fsel); diff --git a/include/drivers/scmi-msg.h b/include/drivers/scmi-msg.h new file mode 100644 index 000000000..a9a99cf52 --- /dev/null +++ b/include/drivers/scmi-msg.h @@ -0,0 +1,207 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Linaro Limited + */ + +#ifndef SCMI_MSG_H +#define SCMI_MSG_H + +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> + +/* Minimum size expected for SMT based shared memory message buffers */ +#define SMT_BUF_SLOT_SIZE 128U + +/* A channel abstract a communication path between agent and server */ +struct scmi_msg_channel; + +/* + * struct scmi_msg_channel - Shared memory buffer for a agent-to-server channel + * + * @shm_addr: Address of the shared memory for the SCMI channel + * @shm_size: Byte size of the shared memory for the SCMI channel + * @busy: True when channel is busy, flase when channel is free + * @agent_name: Agent name, SCMI protocol exposes 16 bytes max, or NULL + */ +struct scmi_msg_channel { + uintptr_t shm_addr; + size_t shm_size; + bool busy; + const char *agent_name; +}; + +/* + * Initialize SMT memory buffer, called by platform at init for each + * agent channel using the SMT header format. + * + * @chan: Pointer to the channel shared memory to be initialized + */ +void scmi_smt_init_agent_channel(struct scmi_msg_channel *chan); + +/* + * Process SMT formatted message in a fastcall SMC execution context. + * Called by platform on SMC entry. When returning, output message is + * available in shared memory for agent to read the response. + * + * @agent_id: SCMI agent ID the SMT belongs to + */ +void scmi_smt_fastcall_smc_entry(unsigned int agent_id); + +/* + * Process SMT formatted message in a secure interrupt execution context. + * Called by platform interrupt handler. When returning, output message is + * available in shared memory for agent to read the response. + * + * @agent_id: SCMI agent ID the SMT belongs to + */ +void scmi_smt_interrupt_entry(unsigned int agent_id); + +/* Platform callback functions */ + +/* + * Return the SCMI channel related to an agent + * @agent_id: SCMI agent ID + * Return a pointer to channel on success, NULL otherwise + */ +struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id); + +/* + * Return how many SCMI protocols supported by the platform + * According to the SCMI specification, this function does not target + * a specific agent ID and shall return all platform known capabilities. + */ +size_t plat_scmi_protocol_count(void); + +/* + * Get the count and list of SCMI protocols (but base) supported for an agent + * + * @agent_id: SCMI agent ID + * Return a pointer to a null terminated array supported protocol IDs. + */ +const uint8_t *plat_scmi_protocol_list(unsigned int agent_id); + +/* Get the name of the SCMI vendor for the platform */ +const char *plat_scmi_vendor_name(void); + +/* Get the name of the SCMI sub-vendor for the platform */ +const char *plat_scmi_sub_vendor_name(void); + +/* Handlers for SCMI Clock protocol services */ + +/* + * Return number of clock controllers for an agent + * @agent_id: SCMI agent ID + * Return number of clock controllers + */ +size_t plat_scmi_clock_count(unsigned int agent_id); + +/* + * Get clock controller string ID (aka name) + * @agent_id: SCMI agent ID + * @scmi_id: SCMI clock ID + * Return pointer to name or NULL + */ +const char *plat_scmi_clock_get_name(unsigned int agent_id, + unsigned int scmi_id); + +/* + * Get clock possible rate as an array of frequencies in Hertz. + * + * @agent_id: SCMI agent ID + * @scmi_id: SCMI clock ID + * @rates: If NULL, function returns, else output rates array + * @nb_elts: Array size of @rates. + * Return an SCMI compliant error code + */ +int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id, + unsigned long *rates, size_t *nb_elts); + +/* + * Get clock possible rate as range with regular steps in Hertz + * + * @agent_id: SCMI agent ID + * @scmi_id: SCMI clock ID + * @min_max_step: 3 cell array for min, max and step rate data + * Return an SCMI compliant error code + */ +int32_t plat_scmi_clock_rates_by_step(unsigned int agent_id, + unsigned int scmi_id, + unsigned long *min_max_step); + +/* + * Get clock rate in Hertz + * @agent_id: SCMI agent ID + * @scmi_id: SCMI clock ID + * Return clock rate or 0 if not supported + */ +unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, + unsigned int scmi_id); + +/* + * Set clock rate in Hertz + * @agent_id: SCMI agent ID + * @scmi_id: SCMI clock ID + * @rate: Target clock frequency in Hertz + * Return a compliant SCMI error code + */ +int32_t plat_scmi_clock_set_rate(unsigned int agent_id, unsigned int scmi_id, + unsigned long rate); + +/* + * Get clock state (enabled or disabled) + * @agent_id: SCMI agent ID + * @scmi_id: SCMI clock ID + * Return 1 if clock is enabled, 0 if disables, or a negative SCMI error code + */ +int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id); + +/* + * Get clock state (enabled or disabled) + * @agent_id: SCMI agent ID + * @scmi_id: SCMI clock ID + * @enable_not_disable: Enable clock if true, disable clock otherwise + * Return a compliant SCMI error code + */ +int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id, + bool enable_not_disable); + +/* Handlers for SCMI Reset Domain protocol services */ + +/* + * Return number of reset domains for the agent + * @agent_id: SCMI agent ID + * Return number of reset domains + */ +size_t plat_scmi_rstd_count(unsigned int agent_id); + +/* + * Get reset domain string ID (aka name) + * @agent_id: SCMI agent ID + * @scmi_id: SCMI reset domain ID + * Return pointer to name or NULL + */ +const char *plat_scmi_rstd_get_name(unsigned int agent_id, unsigned int scmi_id); + +/* + * Perform a reset cycle on a target reset domain + * @agent_id: SCMI agent ID + * @scmi_id: SCMI reset domain ID + * @state: Target reset state (see SCMI specification, 0 means context loss) + * Return a compliant SCMI error code + */ +int32_t plat_scmi_rstd_autonomous(unsigned int agent_id, unsigned int scmi_id, + unsigned int state); + +/* + * Assert or deassert target reset domain + * @agent_id: SCMI agent ID + * @scmi_id: SCMI reset domain ID + * @assert_not_deassert: Assert domain if true, otherwise deassert domain + * Return a compliant SCMI error code + */ +int32_t plat_scmi_rstd_set_state(unsigned int agent_id, unsigned int scmi_id, + bool assert_not_deassert); + +#endif /* SCMI_MSG_H */ diff --git a/include/drivers/scmi.h b/include/drivers/scmi.h new file mode 100644 index 000000000..ac5dc3871 --- /dev/null +++ b/include/drivers/scmi.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. + */ +#ifndef SCMI_MSG_SCMI_H +#define SCMI_MSG_SCMI_H + +#define SCMI_PROTOCOL_ID_BASE 0x10U +#define SCMI_PROTOCOL_ID_POWER_DOMAIN 0x11U +#define SCMI_PROTOCOL_ID_SYS_POWER 0x12U +#define SCMI_PROTOCOL_ID_PERF 0x13U +#define SCMI_PROTOCOL_ID_CLOCK 0x14U +#define SCMI_PROTOCOL_ID_SENSOR 0x15U +#define SCMI_PROTOCOL_ID_RESET_DOMAIN 0x16U + +/* SCMI error codes reported to agent through server-to-agent messages */ +#define SCMI_SUCCESS 0 +#define SCMI_NOT_SUPPORTED (-1) +#define SCMI_INVALID_PARAMETERS (-2) +#define SCMI_DENIED (-3) +#define SCMI_NOT_FOUND (-4) +#define SCMI_OUT_OF_RANGE (-5) +#define SCMI_BUSY (-6) +#define SCMI_COMMS_ERROR (-7) +#define SCMI_GENERIC_ERROR (-8) +#define SCMI_HARDWARE_ERROR (-9) +#define SCMI_PROTOCOL_ERROR (-10) + +#endif /* SCMI_MSG_SCMI_H */ diff --git a/include/drivers/st/etzpc.h b/include/drivers/st/etzpc.h new file mode 100644 index 000000000..4cd2b4e0b --- /dev/null +++ b/include/drivers/st/etzpc.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRIVERS_ST_ETZPC_H +#define DRIVERS_ST_ETZPC_H + +#include <stdbool.h> +#include <stdint.h> + +/* Define security level for each peripheral (DECPROT) */ +enum etzpc_decprot_attributes { + ETZPC_DECPROT_S_RW = 0, + ETZPC_DECPROT_NS_R_S_W = 1, + ETZPC_DECPROT_MCU_ISOLATION = 2, + ETZPC_DECPROT_NS_RW = 3, + ETZPC_DECPROT_MAX = 4, +}; + +void etzpc_configure_decprot(uint32_t decprot_id, + enum etzpc_decprot_attributes decprot_attr); +enum etzpc_decprot_attributes etzpc_get_decprot(uint32_t decprot_id); +void etzpc_lock_decprot(uint32_t decprot_id); + +void etzpc_configure_tzma(uint32_t tzma_id, uint16_t tzma_value); +uint16_t etzpc_get_tzma(uint32_t tzma_id); +void etzpc_lock_tzma(uint32_t tzma_id); +bool etzpc_get_lock_tzma(uint32_t tzma_id); + +uint8_t etzpc_get_num_per_sec(void); +uint8_t etzpc_get_revision(void); +uintptr_t etzpc_get_base_address(void); + +int etzpc_init(void); + +#endif /* DRIVERS_ST_ETZPC_H */ diff --git a/include/drivers/st/stm32_console.h b/include/drivers/st/stm32_console.h index a2ad87cb5..8d9187d2a 100644 --- a/include/drivers/st/stm32_console.h +++ b/include/drivers/st/stm32_console.h @@ -9,17 +9,10 @@ #include <drivers/console.h> -#define CONSOLE_T_STM32_BASE CONSOLE_T_DRVDATA - #ifndef __ASSEMBLER__ #include <stdint.h> -struct console_stm32 { - console_t console; - uintptr_t base; -}; - /* * Initialize a new STM32 console instance and register it with the console * framework. The |console| pointer must point to storage that will be valid @@ -27,7 +20,7 @@ struct console_stm32 { * Its contents will be reinitialized from scratch. */ int console_stm32_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - struct console_stm32 *console); + console_t *console); #endif /*__ASSEMBLER__*/ diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h index 1ebd39ff7..c46892b78 100644 --- a/include/drivers/st/stm32mp1_clk.h +++ b/include/drivers/st/stm32mp1_clk.h @@ -59,4 +59,7 @@ void stm32mp1_clk_rcc_regs_unlock(void); void stm32mp1_stgen_increment(unsigned long long offset_in_ms); +#ifdef STM32MP_SHARED_RESOURCES +void stm32mp1_register_clock_parents_secure(unsigned long id); +#endif #endif /* STM32MP1_CLK_H */ diff --git a/include/drivers/st/stm32mp1_ddr_regs.h b/include/drivers/st/stm32mp1_ddr_regs.h index 342239a52..01d663834 100644 --- a/include/drivers/st/stm32mp1_ddr_regs.h +++ b/include/drivers/st/stm32mp1_ddr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -284,7 +284,7 @@ struct stm32mp1_ddrphy { #define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) #define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) -#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(19, 12) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16) #define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16) #define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h index 4b4aac87d..2ffc3b2bc 100644 --- a/include/drivers/st/stm32mp1_rcc.h +++ b/include/drivers/st/stm32mp1_rcc.h @@ -250,6 +250,8 @@ #define RCC_MPCKSELR_HSE 0x00000001 #define RCC_MPCKSELR_PLL 0x00000002 #define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 +#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0) +#define RCC_MPCKSELR_MPUSRC_SHIFT 0 /* Values of RCC_ASSCKSELR register */ #define RCC_ASSCKSELR_HSI 0x00000000 @@ -266,6 +268,8 @@ #define RCC_CPERCKSELR_HSI 0x00000000 #define RCC_CPERCKSELR_CSI 0x00000001 #define RCC_CPERCKSELR_HSE 0x00000002 +#define RCC_CPERCKSELR_PERSRC_MASK GENMASK(1, 0) +#define RCC_CPERCKSELR_PERSRC_SHIFT 0 /* Used for most of DIVR register: max div for RTC */ #define RCC_DIVR_DIV_MASK GENMASK(5, 0) diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h index 076916730..c7e0b6e6f 100644 --- a/include/drivers/st/stm32mp_clkfunc.h +++ b/include/drivers/st/stm32mp_clkfunc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,14 +20,12 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id, uint32_t dflt_value); int fdt_get_rcc_node(void *fdt); -uint32_t fdt_rcc_read_addr(void); -int fdt_rcc_read_uint32_array(const char *prop_name, - uint32_t *array, uint32_t count); +int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count, + uint32_t *array); int fdt_rcc_subnode_offset(const char *name); const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp); bool fdt_get_rcc_secure_status(void); -uintptr_t fdt_get_stgen_base(void); int fdt_get_clock_id(int node); #endif /* STM32MP_CLKFUNC_H */ diff --git a/include/drivers/st/stm32mp_reset.h b/include/drivers/st/stm32mp_reset.h index 2da5adf44..84448050d 100644 --- a/include/drivers/st/stm32mp_reset.h +++ b/include/drivers/st/stm32mp_reset.h @@ -9,7 +9,42 @@ #include <stdint.h> -void stm32mp_reset_assert(uint32_t reset_id); -void stm32mp_reset_deassert(uint32_t reset_id); +/* + * Assert target reset, if @to_us non null, wait until reset is asserted + * + * @reset_id: Reset controller ID + * @to_us: Timeout in microsecond, or 0 if not waiting + * Return 0 on success and -ETIMEDOUT if waiting and timeout expired + */ +int stm32mp_reset_assert(uint32_t reset_id, unsigned int to_us); + +/* + * Enable reset control for target resource + * + * @reset_id: Reset controller ID + */ +static inline void stm32mp_reset_set(uint32_t reset_id) +{ + (void)stm32mp_reset_assert(reset_id, 0U); +} + +/* + * Deassert target reset, if @to_us non null, wait until reset is deasserted + * + * @reset_id: Reset controller ID + * @to_us: Timeout in microsecond, or 0 if not waiting + * Return 0 on success and -ETIMEDOUT if waiting and timeout expired + */ +int stm32mp_reset_deassert(uint32_t reset_id, unsigned int to_us); + +/* + * Release reset control for target resource + * + * @reset_id: Reset controller ID + */ +static inline void stm32mp_reset_release(uint32_t reset_id) +{ + (void)stm32mp_reset_deassert(reset_id, 0U); +} #endif /* STM32MP_RESET_H */ diff --git a/include/drivers/ti/uart/uart_16550.h b/include/drivers/ti/uart/uart_16550.h index 2b95fa33a..bddd9970c 100644 --- a/include/drivers/ti/uart/uart_16550.h +++ b/include/drivers/ti/uart/uart_16550.h @@ -71,17 +71,10 @@ #define UARTLSR_RDR_BIT (0) /* Rx Data Ready Bit */ #define UARTLSR_RDR (1 << UARTLSR_RDR_BIT) /* Rx Data Ready */ -#define CONSOLE_T_16550_BASE CONSOLE_T_DRVDATA - #ifndef __ASSEMBLER__ #include <stdint.h> -typedef struct { - console_t console; - uintptr_t base; -} console_16550_t; - /* * Initialize a new 16550 console instance and register it with the console * framework. The |console| pointer must point to storage that will be valid @@ -94,7 +87,7 @@ typedef struct { * case as well. */ int console_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, - console_16550_t *console); + console_t *console); #endif /*__ASSEMBLER__*/ diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 18bdb57f3..67e66b23f 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -248,4 +248,31 @@ #define STM32MP1_LAST_CLK 232 +/* SCMI clock identifiers */ +#define CK_SCMI0_HSE 0 +#define CK_SCMI0_HSI 1 +#define CK_SCMI0_CSI 2 +#define CK_SCMI0_LSE 3 +#define CK_SCMI0_LSI 4 +#define CK_SCMI0_PLL2_Q 5 +#define CK_SCMI0_PLL2_R 6 +#define CK_SCMI0_MPU 7 +#define CK_SCMI0_AXI 8 +#define CK_SCMI0_BSEC 9 +#define CK_SCMI0_CRYP1 10 +#define CK_SCMI0_GPIOZ 11 +#define CK_SCMI0_HASH1 12 +#define CK_SCMI0_I2C4 13 +#define CK_SCMI0_I2C6 14 +#define CK_SCMI0_IWDG1 15 +#define CK_SCMI0_RNG1 16 +#define CK_SCMI0_RTC 17 +#define CK_SCMI0_RTCAPB 18 +#define CK_SCMI0_SPI6 19 +#define CK_SCMI0_USART1 20 + +#define CK_SCMI1_PLL3_Q 0 +#define CK_SCMI1_PLL3_R 1 +#define CK_SCMI1_MCU 2 + #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index 7f6e4b94d..1bc2c40fc 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -26,6 +26,7 @@ #define AF14 0xf #define AF15 0x10 #define ANALOG 0x11 +#define RSVD 0x12 /* define Pins number*/ #define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) @@ -33,9 +34,9 @@ #define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) /* package information */ -#define STM32MP157CAA 0x1 -#define STM32MP157CAB 0x2 -#define STM32MP157CAC 0x4 -#define STM32MP157CAD 0x8 +#define STM32MP_PKG_AA 0x1 +#define STM32MP_PKG_AB 0x2 +#define STM32MP_PKG_AC 0x4 +#define STM32MP_PKG_AD 0x8 #endif /* _DT_BINDINGS_STM32_PINFUNC_H */ diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index f0c3aaef6..bc71924fa 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -105,4 +105,17 @@ #define GPIOJ_R 19785 #define GPIOK_R 19786 +/* SCMI reset domain identifiers */ +#define RST_SCMI0_SPI6 0 +#define RST_SCMI0_I2C4 1 +#define RST_SCMI0_I2C6 2 +#define RST_SCMI0_USART1 3 +#define RST_SCMI0_STGEN 4 +#define RST_SCMI0_GPIOZ 5 +#define RST_SCMI0_CRYP1 6 +#define RST_SCMI0_HASH1 7 +#define RST_SCMI0_RNG1 8 +#define RST_SCMI0_MDMA 9 +#define RST_SCMI0_MCU 10 + #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ diff --git a/include/dt-bindings/soc/st,stm32-etzpc.h b/include/dt-bindings/soc/st,stm32-etzpc.h new file mode 100644 index 000000000..3f9fb3b12 --- /dev/null +++ b/include/dt-bindings/soc/st,stm32-etzpc.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2017-2020, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef _DT_BINDINGS_STM32_ETZPC_H +#define _DT_BINDINGS_STM32_ETZPC_H + +/* DECPROT modes */ +#define DECPROT_S_RW 0x0 +#define DECPROT_NS_R_S_W 0x1 +#define DECPROT_MCU_ISOLATION 0x2 +#define DECPROT_NS_RW 0x3 + +/* DECPROT lock */ +#define DECPROT_UNLOCK 0x0 +#define DECPROT_LOCK 0x1 + +#endif /* _DT_BINDINGS_STM32_ETZPC_H */ diff --git a/include/export/common/ep_info_exp.h b/include/export/common/ep_info_exp.h index 4c703e6de..9d2969f3f 100644 --- a/include/export/common/ep_info_exp.h +++ b/include/export/common/ep_info_exp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,10 +25,10 @@ #endif /* Security state of the image. */ -#define EP_SECURITY_MASK U(0x1) -#define EP_SECURITY_SHIFT U(0) -#define EP_SECURE U(0x0) -#define EP_NON_SECURE U(0x1) +#define EP_SECURITY_MASK UL(0x1) +#define EP_SECURITY_SHIFT UL(0) +#define EP_SECURE UL(0x0) +#define EP_NON_SECURE UL(0x1) /* Endianness of the image. */ #define EP_EE_MASK U(0x2) diff --git a/include/export/common/tbbr/tbbr_img_def_exp.h b/include/export/common/tbbr/tbbr_img_def_exp.h index ff0d16c73..18f012513 100644 --- a/include/export/common/tbbr/tbbr_img_def_exp.h +++ b/include/export/common/tbbr/tbbr_img_def_exp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -85,7 +85,13 @@ /* Binary with STM32 header */ #define STM32_IMAGE_ID U(29) -/* Define size of the array */ -#define MAX_NUMBER_IDS U(30) +/* Encrypted image identifier */ +#define ENC_IMAGE_ID U(30) + +/* FW_CONFIG */ +#define FW_CONFIG_ID U(31) + +/* Max Images */ +#define MAX_IMAGE_IDS U(32) #endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H */ diff --git a/include/lib/coreboot.h b/include/lib/coreboot.h index 88212c315..0aa65791d 100644 --- a/include/lib/coreboot.h +++ b/include/lib/coreboot.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,27 @@ typedef struct { } coreboot_serial_t; extern coreboot_serial_t coreboot_serial; +#define COREBOOT_MAX_MEMRANGES 32 /* libpayload also uses this limit */ + +typedef struct __packed { + uint64_t start; + uint64_t size; + uint32_t type; +} coreboot_memrange_t; +extern coreboot_memrange_t coreboot_memranges[COREBOOT_MAX_MEMRANGES]; + +typedef enum { + CB_MEM_NONE = 0, /* coreboot will never report this */ + CB_MEM_RAM = 1, + CB_MEM_RESERVED = 2, + CB_MEM_ACPI = 3, + CB_MEM_NVS = 4, + CB_MEM_UNUSABLE = 5, + CB_MEM_VENDOR_RSVD = 6, + CB_MEM_TABLE = 16, +} coreboot_memory_t; + +coreboot_memory_t coreboot_get_memory_type(uintptr_t start, size_t size); void coreboot_table_setup(void *base); #endif /* COREBOOT_H */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index 102ff60c3..dc40e31ad 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -54,6 +55,7 @@ #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) #define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) +#define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24) #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index 7dc7e068a..a61825f1b 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -32,6 +32,8 @@ #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) + #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) #define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h index 0467ef3bb..0a42a5d77 100644 --- a/include/lib/cpus/aarch64/cortex_a77.h +++ b/include/lib/cpus/aarch64/cortex_a77.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,6 +16,7 @@ * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) /******************************************************************************* * CPU Power Control register specific definitions. @@ -23,4 +24,11 @@ #define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) +#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3 +#define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4 +#define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5 + #endif /* CORTEX_A77_H */ diff --git a/include/lib/cpus/aarch64/cortex_hercules.h b/include/lib/cpus/aarch64/cortex_a78.h index d5ca85ed2..caa512046 100644 --- a/include/lib/cpus/aarch64/cortex_hercules.h +++ b/include/lib/cpus/aarch64/cortex_a78.h @@ -1,44 +1,45 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2021, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_HERCULES_H -#define CORTEX_HERCULES_H +#ifndef CORTEX_A78_H +#define CORTEX_A78_H #include <lib/utils_def.h> -#define CORTEX_HERCULES_MIDR U(0x410FD410) +#define CORTEX_A78_MIDR U(0x410FD410) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CORTEX_HERCULES_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ -#define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) +#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30) +#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30) -#define CORTEX_HERCULES_ACTLR2_EL1 S3_0_C15_C1_1 -#define CORTEX_HERCULES_ACTLR2_EL1_BIT_1 (ULL(1) << 1) +#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1 +#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1) /******************************************************************************* * CPU Activity Monitor Unit register specific definitions. ******************************************************************************/ -#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4 -#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5 -#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0 -#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1 +#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4 +#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5 +#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0 +#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1 -#define CORTEX_HERCULES_AMU_GROUP0_MASK U(0xF) -#define CORTEX_HERCULES_AMU_GROUP1_MASK U(0x7) +#define CORTEX_A78_AMU_GROUP0_MASK U(0xF) +#define CORTEX_A78_AMU_GROUP1_MASK U(0x7) -#endif /* CORTEX_HERCULES_H */ +#endif /* CORTEX_A78_H */ diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h new file mode 100644 index 000000000..24ae7eeac --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a78_ae.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A78_AE_H +#define CORTEX_A78_AE_H + +#include <cortex_a78.h> + +#define CORTEX_A78_AE_MIDR U(0x410FD420) + +#endif /* CORTEX_A78_AE_H */ diff --git a/include/lib/cpus/aarch64/cortex_hercules_ae.h b/include/lib/cpus/aarch64/cortex_hercules_ae.h deleted file mode 100644 index 795563bc3..000000000 --- a/include/lib/cpus/aarch64/cortex_hercules_ae.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_HERCULES_AE_H -#define CORTEX_HERCULES_AE_H - -#include <cortex_hercules.h> - -#define CORTEX_HERCULES_AE_MIDR U(0x410FD420) - -#endif /* CORTEX_HERCULES_AE_H */ diff --git a/include/lib/cpus/aarch64/cortex_klein.h b/include/lib/cpus/aarch64/cortex_klein.h new file mode 100644 index 000000000..729b3bf0a --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_klein.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_KLEIN_H +#define CORTEX_KLEIN_H + +#define CORTEX_KLEIN_MIDR U(0x410FD460) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_KLEIN_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_KLEIN_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_KLEIN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_KLEIN_H */ diff --git a/include/lib/cpus/aarch64/cortex_matterhorn.h b/include/lib/cpus/aarch64/cortex_matterhorn.h new file mode 100644 index 000000000..018553359 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_matterhorn.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_MATTERHORN_H +#define CORTEX_MATTERHORN_H + +#define CORTEX_MATTERHORN_MIDR U(0x410FD470) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_MATTERHORN_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_MATTERHORN_H */ diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index c83824d77..92891ce38 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -25,10 +25,6 @@ /* Word size for 64-bit CPUs */ #define CPU_WORD_SIZE 8 -#if defined(IMAGE_BL1) || defined(IMAGE_BL31) ||(defined(IMAGE_BL2) && BL2_AT_EL3) -#define IMAGE_AT_EL3 -#endif - /* * Whether errata status needs reporting. Errata status is printed in debug * builds for both BL1 and BL31 images. diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h index 02657a0fb..24b6a870c 100644 --- a/include/lib/cpus/aarch64/denver.h +++ b/include/lib/cpus/aarch64/denver.h @@ -13,6 +13,11 @@ #define DENVER_MIDR_PN2 U(0x4E0F0020) #define DENVER_MIDR_PN3 U(0x4E0F0030) #define DENVER_MIDR_PN4 U(0x4E0F0040) +#define DENVER_MIDR_PN5 U(0x4E0F0050) +#define DENVER_MIDR_PN6 U(0x4E0F0060) +#define DENVER_MIDR_PN7 U(0x4E0F0070) +#define DENVER_MIDR_PN8 U(0x4E0F0080) +#define DENVER_MIDR_PN9 U(0x4E0F0090) /* Implementer code in the MIDR register */ #define DENVER_IMPL U(0x4E) @@ -34,6 +39,11 @@ #define DENVER_CPU_PMSTATE_C7 U(0x7) #define DENVER_CPU_PMSTATE_MASK U(0xF) +/* ACTRL_ELx bits to enable dual execution*/ +#define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9) +#define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9) +#define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4) + #ifndef __ASSEMBLER__ /* Disable Dynamic Code Optimisation */ diff --git a/include/lib/cpus/aarch64/generic.h b/include/lib/cpus/aarch64/generic.h new file mode 100644 index 000000000..53df58761 --- /dev/null +++ b/include/lib/cpus/aarch64/generic.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserverd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AARCH64_GENERIC_H +#define AARCH64_GENERIC_H + +#include <lib/utils_def.h> + +/* + * 0x0 value on the MIDR implementer value is reserved for software use, + * so use an MIDR value of 0 for a default CPU library. + */ +#define AARCH64_GENERIC_MIDR U(0) + +#endif /* AARCH64_GENERIC_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h new file mode 100644 index 000000000..7cbd8c17b --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_N2_H +#define NEOVERSE_N2_H + +/* Neoverse N2 ID register for revision r0p0 */ +#define NEOVERSE_N2_MIDR U(0x410FD490) + +/******************************************************************************* + * CPU Power control register + ******************************************************************************/ +#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) + +#endif /* NEOVERSE_N2_H */ diff --git a/include/lib/cpus/aarch64/neoverse_n_common.h b/include/lib/cpus/aarch64/neoverse_n_common.h new file mode 100644 index 000000000..7cb91cd05 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_n_common.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_N_COMMON_H +#define NEOVERSE_N_COMMON_H + +/****************************************************************************** + * Neoverse Nx CPU Configuration register definitions + *****************************************************************************/ +#define CPUCFR_EL1 S3_0_C15_C0_0 + +/* SCU bit of CPU Configuration Register, EL1 */ +#define SCU_SHIFT U(2) + +#endif /* NEOVERSE_N_COMMON_H */ diff --git a/include/lib/cpus/aarch64/neoverse_zeus.h b/include/lib/cpus/aarch64/neoverse_v1.h index f0947271d..650eb4d41 100644 --- a/include/lib/cpus/aarch64/neoverse_zeus.h +++ b/include/lib/cpus/aarch64/neoverse_v1.h @@ -1,23 +1,23 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef NEOVERSE_ZEUS_H -#define NEOVERSE_ZEUS_H +#ifndef NEOVERSE_V1_H +#define NEOVERSE_V1_H -#define NEOVERSE_ZEUS_MIDR U(0x410FD400) +#define NEOVERSE_V1_MIDR U(0x410FD400) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_ZEUS_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ -#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) -#endif /* NEOVERSE_ZEUS_H */ +#endif /* NEOVERSE_V1_H */ diff --git a/include/lib/cpus/aarch64/rainier.h b/include/lib/cpus/aarch64/rainier.h new file mode 100644 index 000000000..978661ff6 --- /dev/null +++ b/include/lib/cpus/aarch64/rainier.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RAINIER_H +#define RAINIER_H + +#include <lib/utils_def.h> + +/* RAINIER MIDR for revision 0 */ +#define RAINIER_MIDR U(0x3f0f4120) + +/* Exception Syndrome register EC code for IC Trap */ +#define RAINIER_EC_IC_TRAP U(0x1f) + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ +#define RAINIER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 + +/* Definitions of register field mask in RAINIER_CPUPWRCTLR_EL1 */ +#define RAINIER_CORE_PWRDN_EN_MASK U(0x1) + +#define RAINIER_ACTLR_AMEN_BIT (U(1) << 4) + +#define RAINIER_AMU_NR_COUNTERS U(5) +#define RAINIER_AMU_GROUP0_MASK U(0x1f) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define RAINIER_CPUECTLR_EL1 S3_0_C15_C1_4 + +#define RAINIER_WS_THR_L2_MASK (ULL(3) << 24) +#define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define RAINIER_CPUACTLR_EL1 S3_0_C15_C1_0 + +#define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) +#define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) + +#define RAINIER_CPUACTLR2_EL1 S3_0_C15_C1_1 + +#define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) +#define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) +#define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) +#define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) +#define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) + +#define RAINIER_CPUACTLR3_EL1 S3_0_C15_C1_2 + +#define RAINIER_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) + +/* Instruction patching registers */ +#define CPUPSELR_EL3 S3_6_C15_C8_0 +#define CPUPCR_EL3 S3_6_C15_C8_1 +#define CPUPOR_EL3 S3_6_C15_C8_2 +#define CPUPMR_EL3 S3_6_C15_C8_3 + +#endif /* RAINIER_H */ diff --git a/include/lib/cpus/errata_report.h b/include/lib/cpus/errata_report.h index 7cac77ebe..efdedf0aa 100644 --- a/include/lib/cpus/errata_report.h +++ b/include/lib/cpus/errata_report.h @@ -30,4 +30,7 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported); #define ERRATA_APPLIES 1 #define ERRATA_MISSING 2 +/* Macro to get CPU revision code for checking errata version compatibility. */ +#define CPU_REV(r, p) ((r << 4) | p) + #endif /* ERRATA_REPORT_H */ diff --git a/include/lib/el3_runtime/aarch32/context.h b/include/lib/el3_runtime/aarch32/context.h index c5567c974..5604c8e50 100644 --- a/include/lib/el3_runtime/aarch32/context.h +++ b/include/lib/el3_runtime/aarch32/context.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,7 +37,7 @@ #define WORD_SHIFT U(2) #define DEFINE_REG_STRUCT(name, num_regs) \ typedef struct name { \ - uint32_t _regs[num_regs]; \ + uint32_t ctx_regs[num_regs]; \ } __aligned(8) name##_t /* Constants to determine the size of individual context structures */ @@ -47,8 +47,8 @@ DEFINE_REG_STRUCT(regs, CTX_REG_ALL); #undef CTX_REG_ALL -#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> WORD_SHIFT]) -#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> WORD_SHIFT]) \ +#define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[offset >> WORD_SHIFT]) +#define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[offset >> WORD_SHIFT]) \ = val) typedef struct cpu_context { regs_t regs_ctx; diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index 7a1f3a3a8..3135fb45b 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -60,7 +60,8 @@ #define CTX_SPSR_EL3 U(0x18) #define CTX_ELR_EL3 U(0x20) #define CTX_PMCR_EL0 U(0x28) -#define CTX_EL3STATE_END U(0x30) +#define CTX_IS_IN_EL3 U(0x30) +#define CTX_EL3STATE_END U(0x40) /* Align to the next 16 byte boundary */ /******************************************************************************* * Constants that allow assembler code to access members of and the @@ -68,11 +69,11 @@ * registers are only 32-bits wide but are stored as 64-bit values for * convenience ******************************************************************************/ -#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) +#define CTX_EL1_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) #define CTX_SPSR_EL1 U(0x0) #define CTX_ELR_EL1 U(0x8) #define CTX_SCTLR_EL1 U(0x10) -#define CTX_ACTLR_EL1 U(0x18) +#define CTX_TCR_EL1 U(0x18) #define CTX_CPACR_EL1 U(0x20) #define CTX_CSSELR_EL1 U(0x28) #define CTX_SP_EL1 U(0x30) @@ -81,7 +82,7 @@ #define CTX_TTBR1_EL1 U(0x48) #define CTX_MAIR_EL1 U(0x50) #define CTX_AMAIR_EL1 U(0x58) -#define CTX_TCR_EL1 U(0x60) +#define CTX_ACTLR_EL1 U(0x60) #define CTX_TPIDR_EL1 U(0x68) #define CTX_TPIDR_EL0 U(0x70) #define CTX_TPIDRRO_EL0 U(0x78) @@ -138,13 +139,119 @@ /* * End of system registers. */ -#define CTX_SYSREGS_END CTX_MTE_REGS_END +#define CTX_EL1_SYSREGS_END CTX_MTE_REGS_END + +/* + * EL2 register set + */ + +#if CTX_INCLUDE_EL2_REGS +/* For later discussion + * ICH_AP0R<n>_EL2 + * ICH_AP1R<n>_EL2 + * AMEVCNTVOFF0<n>_EL2 + * AMEVCNTVOFF1<n>_EL2 + * ICH_LR<n>_EL2 + */ +#define CTX_EL2_SYSREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) + +#define CTX_ACTLR_EL2 U(0x0) +#define CTX_AFSR0_EL2 U(0x8) +#define CTX_AFSR1_EL2 U(0x10) +#define CTX_AMAIR_EL2 U(0x18) +#define CTX_CNTHCTL_EL2 U(0x20) +#define CTX_CNTHP_CTL_EL2 U(0x28) +#define CTX_CNTHP_CVAL_EL2 U(0x30) +#define CTX_CNTHP_TVAL_EL2 U(0x38) +#define CTX_CNTVOFF_EL2 U(0x40) +#define CTX_CPTR_EL2 U(0x48) +#define CTX_DBGVCR32_EL2 U(0x50) +#define CTX_ELR_EL2 U(0x58) +#define CTX_ESR_EL2 U(0x60) +#define CTX_FAR_EL2 U(0x68) +#define CTX_HACR_EL2 U(0x70) +#define CTX_HCR_EL2 U(0x78) +#define CTX_HPFAR_EL2 U(0x80) +#define CTX_HSTR_EL2 U(0x88) +#define CTX_ICC_SRE_EL2 U(0x90) +#define CTX_ICH_HCR_EL2 U(0x98) +#define CTX_ICH_VMCR_EL2 U(0xa0) +#define CTX_MAIR_EL2 U(0xa8) +#define CTX_MDCR_EL2 U(0xb0) +#define CTX_PMSCR_EL2 U(0xb8) +#define CTX_SCTLR_EL2 U(0xc0) +#define CTX_SPSR_EL2 U(0xc8) +#define CTX_SP_EL2 U(0xd0) +#define CTX_TCR_EL2 U(0xd8) +#define CTX_TPIDR_EL2 U(0xe0) +#define CTX_TTBR0_EL2 U(0xe8) +#define CTX_VBAR_EL2 U(0xf0) +#define CTX_VMPIDR_EL2 U(0xf8) +#define CTX_VPIDR_EL2 U(0x100) +#define CTX_VTCR_EL2 U(0x108) +#define CTX_VTTBR_EL2 U(0x110) + +// Only if MTE registers in use +#define CTX_TFSR_EL2 U(0x118) + +// Only if ENABLE_MPAM_FOR_LOWER_ELS==1 +#define CTX_MPAM2_EL2 U(0x120) +#define CTX_MPAMHCR_EL2 U(0x128) +#define CTX_MPAMVPM0_EL2 U(0x130) +#define CTX_MPAMVPM1_EL2 U(0x138) +#define CTX_MPAMVPM2_EL2 U(0x140) +#define CTX_MPAMVPM3_EL2 U(0x148) +#define CTX_MPAMVPM4_EL2 U(0x150) +#define CTX_MPAMVPM5_EL2 U(0x158) +#define CTX_MPAMVPM6_EL2 U(0x160) +#define CTX_MPAMVPM7_EL2 U(0x168) +#define CTX_MPAMVPMV_EL2 U(0x170) + +// Starting with Armv8.6 +#define CTX_HAFGRTR_EL2 U(0x178) +#define CTX_HDFGRTR_EL2 U(0x180) +#define CTX_HDFGWTR_EL2 U(0x188) +#define CTX_HFGITR_EL2 U(0x190) +#define CTX_HFGRTR_EL2 U(0x198) +#define CTX_HFGWTR_EL2 U(0x1a0) +#define CTX_CNTPOFF_EL2 U(0x1a8) + +// Starting with Armv8.4 +#define CTX_CNTHPS_CTL_EL2 U(0x1b0) +#define CTX_CNTHPS_CVAL_EL2 U(0x1b8) +#define CTX_CNTHPS_TVAL_EL2 U(0x1c0) +#define CTX_CNTHVS_CTL_EL2 U(0x1c8) +#define CTX_CNTHVS_CVAL_EL2 U(0x1d0) +#define CTX_CNTHVS_TVAL_EL2 U(0x1d8) +#define CTX_CNTHV_CTL_EL2 U(0x1e0) +#define CTX_CNTHV_CVAL_EL2 U(0x1e8) +#define CTX_CNTHV_TVAL_EL2 U(0x1f0) +#define CTX_CONTEXTIDR_EL2 U(0x1f8) +#define CTX_SDER32_EL2 U(0x200) +#define CTX_TTBR1_EL2 U(0x208) +#define CTX_VDISR_EL2 U(0x210) +#define CTX_VNCR_EL2 U(0x218) +#define CTX_VSESR_EL2 U(0x220) +#define CTX_VSTCR_EL2 U(0x228) +#define CTX_VSTTBR_EL2 U(0x230) +#define CTX_TRFCR_EL2 U(0x238) + +// Starting with Armv8.5 +#define CTX_SCXTNUM_EL2 U(0x240) +/* Align to the next 16 byte boundary */ +#define CTX_EL2_SYSREGS_END U(0x250) + +#endif /* CTX_INCLUDE_EL2_REGS */ /******************************************************************************* * Constants that allow assembler code to access members of and the 'fp_regs' * structure at their correct offsets. ******************************************************************************/ -#define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) +#if CTX_INCLUDE_EL2_REGS +# define CTX_FPREGS_OFFSET (CTX_EL2_SYSREGS_OFFSET + CTX_EL2_SYSREGS_END) +#else +# define CTX_FPREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) +#endif #if CTX_INCLUDE_FPREGS #define CTX_FP_Q0 U(0x0) #define CTX_FP_Q1 U(0x10) @@ -230,12 +337,15 @@ #define DWORD_SHIFT U(3) #define DEFINE_REG_STRUCT(name, num_regs) \ typedef struct name { \ - uint64_t _regs[num_regs]; \ + uint64_t ctx_regs[num_regs]; \ } __aligned(16) name##_t /* Constants to determine the size of individual context structures */ #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) -#define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) +#define CTX_EL1_SYSREGS_ALL (CTX_EL1_SYSREGS_END >> DWORD_SHIFT) +#if CTX_INCLUDE_EL2_REGS +# define CTX_EL2_SYSREGS_ALL (CTX_EL2_SYSREGS_END >> DWORD_SHIFT) +#endif #if CTX_INCLUDE_FPREGS # define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) #endif @@ -256,10 +366,18 @@ DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); /* * AArch64 EL1 system register context structure for preserving the - * architectural state during switches from one security state to - * another in EL1. + * architectural state during world switches. */ -DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL); +DEFINE_REG_STRUCT(el1_sysregs, CTX_EL1_SYSREGS_ALL); + + +/* + * AArch64 EL2 system register context structure for preserving the + * architectural state during world switches. + */ +#if CTX_INCLUDE_EL2_REGS +DEFINE_REG_STRUCT(el2_sysregs, CTX_EL2_SYSREGS_ALL); +#endif /* * AArch64 floating point register context structure for preserving @@ -288,8 +406,8 @@ DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); * Macros to access members of any of the above structures using their * offsets */ -#define read_ctx_reg(ctx, offset) ((ctx)->_regs[(offset) >> DWORD_SHIFT]) -#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[(offset) >> DWORD_SHIFT]) \ +#define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) +#define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ = (uint64_t) (val)) /* @@ -304,7 +422,10 @@ DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); typedef struct cpu_context { gp_regs_t gpregs_ctx; el3_state_t el3state_ctx; - el1_sys_regs_t sysregs_ctx; + el1_sysregs_t el1_sysregs_ctx; +#if CTX_INCLUDE_EL2_REGS + el2_sysregs_t el2_sysregs_ctx; +#endif #if CTX_INCLUDE_FPREGS fp_regs_t fpregs_ctx; #endif @@ -319,7 +440,10 @@ typedef struct cpu_context { #if CTX_INCLUDE_FPREGS # define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) #endif -#define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx) +#define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx) +#if CTX_INCLUDE_EL2_REGS +# define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx) +#endif #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) #if CTX_INCLUDE_PAUTH_REGS @@ -333,8 +457,12 @@ typedef struct cpu_context { */ CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ assert_core_context_gp_offset_mismatch); -CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \ - assert_core_context_sys_offset_mismatch); +CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), \ + assert_core_context_el1_sys_offset_mismatch); +#if CTX_INCLUDE_EL2_REGS +CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx), \ + assert_core_context_el2_sys_offset_mismatch); +#endif #if CTX_INCLUDE_FPREGS CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ assert_core_context_fp_offset_mismatch); @@ -387,8 +515,14 @@ CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), \ /******************************************************************************* * Function prototypes ******************************************************************************/ -void el1_sysregs_context_save(el1_sys_regs_t *regs); -void el1_sysregs_context_restore(el1_sys_regs_t *regs); +void el1_sysregs_context_save(el1_sysregs_t *regs); +void el1_sysregs_context_restore(el1_sysregs_t *regs); + +#if CTX_INCLUDE_EL2_REGS +void el2_sysregs_context_save(el2_sysregs_t *regs); +void el2_sysregs_context_restore(el2_sysregs_t *regs); +#endif + #if CTX_INCLUDE_FPREGS void fpregs_context_save(fp_regs_t *regs); void fpregs_context_restore(fp_regs_t *regs); diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h index 17955e3a8..2090687ee 100644 --- a/include/lib/el3_runtime/context_mgmt.h +++ b/include/lib/el3_runtime/context_mgmt.h @@ -32,10 +32,15 @@ void cm_set_context(void *context, uint32_t security_state); void cm_init_my_context(const struct entry_point_info *ep); void cm_init_context_by_index(unsigned int cpu_idx, const struct entry_point_info *ep); -void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep); +void cm_setup_context(cpu_context_t *ctx, const struct entry_point_info *ep); void cm_prepare_el3_exit(uint32_t security_state); #ifdef __aarch64__ +#if CTX_INCLUDE_EL2_REGS +void cm_el2_sysregs_context_save(uint32_t security_state); +void cm_el2_sysregs_context_restore(uint32_t security_state); +#endif + void cm_el1_sysregs_context_save(uint32_t security_state); void cm_el1_sysregs_context_restore(uint32_t security_state); void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint); diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h index 99ecfccbb..dcbdd5a67 100644 --- a/include/lib/extensions/amu.h +++ b/include/lib/extensions/amu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,13 +10,14 @@ #include <stdbool.h> #include <stdint.h> -#include <platform_def.h> - #include <lib/cassert.h> #include <lib/utils_def.h> +#include <platform_def.h> + /* All group 0 counters */ #define AMU_GROUP0_COUNTERS_MASK U(0xf) +#define AMU_GROUP0_NR_COUNTERS U(4) #ifdef PLAT_AMU_GROUP1_COUNTERS_MASK #define AMU_GROUP1_COUNTERS_MASK PLAT_AMU_GROUP1_COUNTERS_MASK @@ -24,25 +25,67 @@ #define AMU_GROUP1_COUNTERS_MASK U(0) #endif -#ifdef PLAT_AMU_GROUP1_NR_COUNTERS -#define AMU_GROUP1_NR_COUNTERS PLAT_AMU_GROUP1_NR_COUNTERS +/* Calculate number of group 1 counters */ +#if (AMU_GROUP1_COUNTERS_MASK & (1 << 15)) +#define AMU_GROUP1_NR_COUNTERS 16U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 14)) +#define AMU_GROUP1_NR_COUNTERS 15U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 13)) +#define AMU_GROUP1_NR_COUNTERS 14U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 12)) +#define AMU_GROUP1_NR_COUNTERS 13U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 11)) +#define AMU_GROUP1_NR_COUNTERS 12U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 10)) +#define AMU_GROUP1_NR_COUNTERS 11U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 9)) +#define AMU_GROUP1_NR_COUNTERS 10U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 8)) +#define AMU_GROUP1_NR_COUNTERS 9U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 7)) +#define AMU_GROUP1_NR_COUNTERS 8U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 6)) +#define AMU_GROUP1_NR_COUNTERS 7U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 5)) +#define AMU_GROUP1_NR_COUNTERS 6U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 4)) +#define AMU_GROUP1_NR_COUNTERS 5U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 3)) +#define AMU_GROUP1_NR_COUNTERS 4U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 2)) +#define AMU_GROUP1_NR_COUNTERS 3U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 1)) +#define AMU_GROUP1_NR_COUNTERS 2U +#elif (AMU_GROUP1_COUNTERS_MASK & (1 << 0)) +#define AMU_GROUP1_NR_COUNTERS 1U #else -#define AMU_GROUP1_NR_COUNTERS U(0) +#define AMU_GROUP1_NR_COUNTERS 0U #endif CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask); -CASSERT(AMU_GROUP1_NR_COUNTERS <= 16, invalid_amu_group1_nr_counters); + +struct amu_ctx { + uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS]; + +#if AMU_GROUP1_NR_COUNTERS + uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS]; +#endif +}; bool amu_supported(void); void amu_enable(bool el2_unused); /* Group 0 configuration helpers */ -uint64_t amu_group0_cnt_read(int idx); -void amu_group0_cnt_write(int idx, uint64_t val); +uint64_t amu_group0_cnt_read(unsigned int idx); +void amu_group0_cnt_write(unsigned int idx, uint64_t val); + +#if AMU_GROUP1_NR_COUNTERS +bool amu_group1_supported(void); /* Group 1 configuration helpers */ -uint64_t amu_group1_cnt_read(int idx); -void amu_group1_cnt_write(int idx, uint64_t val); -void amu_group1_set_evtype(int idx, unsigned int val); +uint64_t amu_group1_cnt_read(unsigned int idx); +void amu_group1_cnt_write(unsigned int idx, uint64_t val); +void amu_group1_set_evtype(unsigned int idx, unsigned int val); +#endif #endif /* AMU_H */ diff --git a/include/lib/extensions/amu_private.h b/include/lib/extensions/amu_private.h index ab4e6aaba..30ce59d3b 100644 --- a/include/lib/extensions/amu_private.h +++ b/include/lib/extensions/amu_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,11 +9,11 @@ #include <stdint.h> -uint64_t amu_group0_cnt_read_internal(int idx); -void amu_group0_cnt_write_internal(int idx, uint64_t val); +uint64_t amu_group0_cnt_read_internal(unsigned int idx); +void amu_group0_cnt_write_internal(unsigned int idx, uint64_t val); -uint64_t amu_group1_cnt_read_internal(int idx); -void amu_group1_cnt_write_internal(int idx, uint64_t val); -void amu_group1_set_evtype_internal(int idx, unsigned int val); +uint64_t amu_group1_cnt_read_internal(unsigned int idx); +void amu_group1_cnt_write_internal(unsigned int idx, uint64_t val); +void amu_group1_set_evtype_internal(unsigned int idx, unsigned int val); #endif /* AMU_PRIVATE_H */ diff --git a/include/lib/extensions/ras.h b/include/lib/extensions/ras.h index 4fc8f04b1..793ab9fac 100644 --- a/include/lib/extensions/ras.h +++ b/include/lib/extensions/ras.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -192,6 +193,7 @@ static inline int ras_err_ser_probe_sysreg(const struct err_record_info *info, probe_data); } +const char *ras_serr_to_str(unsigned int serr); int ras_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, void *handle, uint64_t flags); void ras_init(void); diff --git a/include/lib/extensions/ras_arch.h b/include/lib/extensions/ras_arch.h index 0c98c4a0e..55760b06b 100644 --- a/include/lib/extensions/ras_arch.h +++ b/include/lib/extensions/ras_arch.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -151,6 +152,9 @@ #define ERROR_STATUS_SET_UC 0x2 /* Uncontainable */ #define ERROR_STATUS_SET_CE 0x3 /* Corrected */ +/* Number of architecturally-defined primary error codes */ +#define ERROR_STATUS_NUM_SERR U(22) + /* Implementation Defined Syndrome bit in ESR */ #define SERROR_IDS_BIT U(24) diff --git a/include/lib/extensions/twed.h b/include/lib/extensions/twed.h new file mode 100644 index 000000000..eac4aa314 --- /dev/null +++ b/include/lib/extensions/twed.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TWED_H +#define TWED_H + +#include <stdint.h> + +#define TWED_DISABLED U(0xFFFFFFFF) + +uint32_t plat_arm_set_twedel_scr_el3(void); + +#endif /* TWEDE_H */ diff --git a/include/lib/fconf/fconf.h b/include/lib/fconf/fconf.h new file mode 100644 index 000000000..917e053bd --- /dev/null +++ b/include/lib/fconf/fconf.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_H +#define FCONF_H + +#include <stdint.h> + +/* Public API */ +#define FCONF_GET_PROPERTY(a, b, c) a##__##b##_getter(c) + +/* + * This macro takes three arguments: + * config: Configuration identifier + * name: property namespace + * callback: populate() function + */ +#define FCONF_REGISTER_POPULATOR(config, name, callback) \ + __attribute__((used, section(".fconf_populator"))) \ + const struct fconf_populator (name##__populator) = { \ + .config_type = (#config), \ + .info = (#name), \ + .populate = (callback) \ + }; + +/* + * Populator callback + * + * This structure are used by the fconf_populate function and should only be + * defined by the FCONF_REGISTER_POPULATOR macro. + */ +struct fconf_populator { + /* Description of the data loaded by the callback */ + const char *config_type; + const char *info; + + /* Callback used by fconf_populate function with a provided config dtb. + * Return 0 on success, err_code < 0 otherwise. + */ + int (*populate)(uintptr_t config); +}; + +/* This function supports to load tb_fw_config and fw_config dtb */ +int fconf_load_config(unsigned int image_id); + +/* Top level populate function + * + * This function takes a configuration dtb and calls all the registered + * populator callback with it. + * + * Panic on error. + */ +void fconf_populate(const char *config_type, uintptr_t config); + +/* FCONF specific getter */ +#define fconf__dtb_getter(prop) fconf_dtb_info.prop + +/* Structure used to locally keep a reference to the config dtb. */ +struct fconf_dtb_info_t { + uintptr_t base_addr; + size_t size; +}; + +extern struct fconf_dtb_info_t fconf_dtb_info; + +#endif /* FCONF_H */ diff --git a/include/lib/fconf/fconf_dyn_cfg_getter.h b/include/lib/fconf/fconf_dyn_cfg_getter.h new file mode 100644 index 000000000..6f8da0d78 --- /dev/null +++ b/include/lib/fconf/fconf_dyn_cfg_getter.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_DYN_CFG_GETTER_H +#define FCONF_DYN_CFG_GETTER_H + +#include <lib/fconf/fconf.h> + +/* Dynamic configuration related getter */ +#define dyn_cfg__dtb_getter(id) dyn_cfg_dtb_info_getter(id) + +struct dyn_cfg_dtb_info_t { + uintptr_t config_addr; + uint32_t config_max_size; + unsigned int config_id; +}; + +struct dyn_cfg_dtb_info_t *dyn_cfg_dtb_info_getter(unsigned int config_id); +int fconf_populate_dtb_registry(uintptr_t config); + +/* Set config information in global DTB array */ +void set_config_info(uintptr_t config_addr, uint32_t config_max_size, + unsigned int config_id); + +#endif /* FCONF_DYN_CFG_GETTER_H */ diff --git a/include/lib/fconf/fconf_tbbr_getter.h b/include/lib/fconf/fconf_tbbr_getter.h new file mode 100644 index 000000000..6066af6df --- /dev/null +++ b/include/lib/fconf/fconf_tbbr_getter.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_TBBR_GETTER_H +#define FCONF_TBBR_GETTER_H + +#include <assert.h> + +#include <lib/fconf/fconf.h> + +/* TBBR related getter */ +#define tbbr__cot_getter(id) __extension__ ({ \ + assert((id) < cot_desc_size); \ + cot_desc_ptr[id]; \ +}) + +#define tbbr__dyn_config_getter(id) tbbr_dyn_config.id + +struct tbbr_dyn_config_t { + uint32_t disable_auth; + void *mbedtls_heap_addr; + size_t mbedtls_heap_size; +#if MEASURED_BOOT + uint8_t bl2_hash_data[TCG_DIGEST_SIZE]; +#endif +}; + +extern struct tbbr_dyn_config_t tbbr_dyn_config; + +int fconf_populate_tbbr_dyn_config(uintptr_t config); + +#endif /* FCONF_TBBR_GETTER_H */ diff --git a/include/lib/libc/stdbool.h b/include/lib/libc/stdbool.h index e39aef7d3..b58334cd0 100644 --- a/include/lib/libc/stdbool.h +++ b/include/lib/libc/stdbool.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +9,8 @@ #define bool _Bool -#define true 1 -#define false 0 +#define true (0 < 1) +#define false (0 > 1) #define __bool_true_false_are_defined 1 diff --git a/include/lib/libc/stdio.h b/include/lib/libc/stdio.h index 2d9e6557b..ba13683e6 100644 --- a/include/lib/libc/stdio.h +++ b/include/lib/libc/stdio.h @@ -22,6 +22,7 @@ int snprintf(char *s, size_t n, const char *fmt, ...) __printflike(3, 4); #ifdef STDARG_H int vprintf(const char *fmt, va_list args); +int vsnprintf(char *s, size_t n, const char *fmt, va_list args); #endif int putchar(int c); diff --git a/include/lib/libc/stdlib.h b/include/lib/libc/stdlib.h index 24e7bae2f..4641e566e 100644 --- a/include/lib/libc/stdlib.h +++ b/include/lib/libc/stdlib.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2017 Roberto E. Vargas Caballero + * Copyright (c) 2012-2021 Roberto E. Vargas Caballero * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,8 +18,15 @@ #define _ATEXIT_MAX 1 +#define isspace(x) (((x) == ' ') || ((x) == '\r') || ((x) == '\n') || \ + ((x) == '\t') || ((x) == '\b')) + extern void abort(void); extern int atexit(void (*func)(void)); extern void exit(int status); +long strtol(const char *nptr, char **endptr, int base); +unsigned long strtoul(const char *nptr, char **endptr, int base); +long long strtoll(const char *nptr, char **endptr, int base); +unsigned long long strtoull(const char *nptr, char **endptr, int base); #endif /* STDLIB_H */ diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h index 71774b0c8..989448318 100644 --- a/include/lib/libc/string.h +++ b/include/lib/libc/string.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2019, ARM Limited and Contributors. + * Portions copyright (c) 2018-2020, ARM Limited and Contributors. * All rights reserved. */ @@ -26,5 +26,7 @@ size_t strlen(const char *s); size_t strnlen(const char *s, size_t maxlen); char *strrchr(const char *p, int ch); size_t strlcpy(char * dst, const char * src, size_t dsize); +size_t strlcat(char * dst, const char * src, size_t dsize); +char *strtok_r(char *s, const char *delim, char **last); #endif /* STRING_H */ diff --git a/include/lib/libfdt b/include/lib/libfdt new file mode 120000 index 000000000..b5668df60 --- /dev/null +++ b/include/lib/libfdt @@ -0,0 +1 @@ +../../../dtc/libfdt
\ No newline at end of file diff --git a/include/lib/libfdt/fdt.h b/include/lib/libfdt/fdt.h deleted file mode 100644 index ef7c86b6d..000000000 --- a/include/lib/libfdt/fdt.h +++ /dev/null @@ -1,111 +0,0 @@ -#ifndef FDT_H -#define FDT_H -/* - * libfdt - Flat Device Tree manipulation - * Copyright (C) 2006 David Gibson, IBM Corporation. - * Copyright 2012 Kim Phillips, Freescale Semiconductor. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ASSEMBLER__ - -struct fdt_header { - fdt32_t magic; /* magic word FDT_MAGIC */ - fdt32_t totalsize; /* total size of DT block */ - fdt32_t off_dt_struct; /* offset to structure */ - fdt32_t off_dt_strings; /* offset to strings */ - fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ - fdt32_t version; /* format version */ - fdt32_t last_comp_version; /* last compatible version */ - - /* version 2 fields below */ - fdt32_t boot_cpuid_phys; /* Which physical CPU id we're - booting on */ - /* version 3 fields below */ - fdt32_t size_dt_strings; /* size of the strings block */ - - /* version 17 fields below */ - fdt32_t size_dt_struct; /* size of the structure block */ -}; - -struct fdt_reserve_entry { - fdt64_t address; - fdt64_t size; -}; - -struct fdt_node_header { - fdt32_t tag; - char name[0]; -}; - -struct fdt_property { - fdt32_t tag; - fdt32_t len; - fdt32_t nameoff; - char data[0]; -}; - -#endif /* !__ASSEMBLER__ */ - -#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ -#define FDT_TAGSIZE sizeof(fdt32_t) - -#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ -#define FDT_END_NODE 0x2 /* End node */ -#define FDT_PROP 0x3 /* Property: name off, - size, content */ -#define FDT_NOP 0x4 /* nop */ -#define FDT_END 0x9 - -#define FDT_V1_SIZE (7*sizeof(fdt32_t)) -#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) -#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) -#define FDT_V16_SIZE FDT_V3_SIZE -#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) - -#endif /* FDT_H */ diff --git a/include/lib/libfdt/libfdt.h b/include/lib/libfdt/libfdt.h deleted file mode 100644 index c8c00fa86..000000000 --- a/include/lib/libfdt/libfdt.h +++ /dev/null @@ -1,1902 +0,0 @@ -#ifndef LIBFDT_H -#define LIBFDT_H -/* - * libfdt - Flat Device Tree manipulation - * Copyright (C) 2006 David Gibson, IBM Corporation. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <libfdt_env.h> -#include <fdt.h> - -#define FDT_FIRST_SUPPORTED_VERSION 0x02 -#define FDT_LAST_SUPPORTED_VERSION 0x11 - -/* Error codes: informative error codes */ -#define FDT_ERR_NOTFOUND 1 - /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ -#define FDT_ERR_EXISTS 2 - /* FDT_ERR_EXISTS: Attempted to create a node or property which - * already exists */ -#define FDT_ERR_NOSPACE 3 - /* FDT_ERR_NOSPACE: Operation needed to expand the device - * tree, but its buffer did not have sufficient space to - * contain the expanded tree. Use fdt_open_into() to move the - * device tree to a buffer with more space. */ - -/* Error codes: codes for bad parameters */ -#define FDT_ERR_BADOFFSET 4 - /* FDT_ERR_BADOFFSET: Function was passed a structure block - * offset which is out-of-bounds, or which points to an - * unsuitable part of the structure for the operation. */ -#define FDT_ERR_BADPATH 5 - /* FDT_ERR_BADPATH: Function was passed a badly formatted path - * (e.g. missing a leading / for a function which requires an - * absolute path) */ -#define FDT_ERR_BADPHANDLE 6 - /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle. - * This can be caused either by an invalid phandle property - * length, or the phandle value was either 0 or -1, which are - * not permitted. */ -#define FDT_ERR_BADSTATE 7 - /* FDT_ERR_BADSTATE: Function was passed an incomplete device - * tree created by the sequential-write functions, which is - * not sufficiently complete for the requested operation. */ - -/* Error codes: codes for bad device tree blobs */ -#define FDT_ERR_TRUNCATED 8 - /* FDT_ERR_TRUNCATED: Structure block of the given device tree - * ends without an FDT_END tag. */ -#define FDT_ERR_BADMAGIC 9 - /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a - * device tree at all - it is missing the flattened device - * tree magic number. */ -#define FDT_ERR_BADVERSION 10 - /* FDT_ERR_BADVERSION: Given device tree has a version which - * can't be handled by the requested operation. For - * read-write functions, this may mean that fdt_open_into() is - * required to convert the tree to the expected version. */ -#define FDT_ERR_BADSTRUCTURE 11 - /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt - * structure block or other serious error (e.g. misnested - * nodes, or subnodes preceding properties). */ -#define FDT_ERR_BADLAYOUT 12 - /* FDT_ERR_BADLAYOUT: For read-write functions, the given - * device tree has it's sub-blocks in an order that the - * function can't handle (memory reserve map, then structure, - * then strings). Use fdt_open_into() to reorganize the tree - * into a form suitable for the read-write operations. */ - -/* "Can't happen" error indicating a bug in libfdt */ -#define FDT_ERR_INTERNAL 13 - /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. - * Should never be returned, if it is, it indicates a bug in - * libfdt itself. */ - -/* Errors in device tree content */ -#define FDT_ERR_BADNCELLS 14 - /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells - * or similar property with a bad format or value */ - -#define FDT_ERR_BADVALUE 15 - /* FDT_ERR_BADVALUE: Device tree has a property with an unexpected - * value. For example: a property expected to contain a string list - * is not NUL-terminated within the length of its value. */ - -#define FDT_ERR_BADOVERLAY 16 - /* FDT_ERR_BADOVERLAY: The device tree overlay, while - * correctly structured, cannot be applied due to some - * unexpected or missing value, property or node. */ - -#define FDT_ERR_NOPHANDLES 17 - /* FDT_ERR_NOPHANDLES: The device tree doesn't have any - * phandle available anymore without causing an overflow */ - -#define FDT_ERR_MAX 17 - -/**********************************************************************/ -/* Low-level functions (you probably don't need these) */ -/**********************************************************************/ - -#ifndef SWIG /* This function is not useful in Python */ -const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); -#endif -static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) -{ - return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); -} - -uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); - -/**********************************************************************/ -/* Traversal functions */ -/**********************************************************************/ - -int fdt_next_node(const void *fdt, int offset, int *depth); - -/** - * fdt_first_subnode() - get offset of first direct subnode - * - * @fdt: FDT blob - * @offset: Offset of node to check - * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none - */ -int fdt_first_subnode(const void *fdt, int offset); - -/** - * fdt_next_subnode() - get offset of next direct subnode - * - * After first calling fdt_first_subnode(), call this function repeatedly to - * get direct subnodes of a parent node. - * - * @fdt: FDT blob - * @offset: Offset of previous subnode - * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more - * subnodes - */ -int fdt_next_subnode(const void *fdt, int offset); - -/** - * fdt_for_each_subnode - iterate over all subnodes of a parent - * - * @node: child node (int, lvalue) - * @fdt: FDT blob (const void *) - * @parent: parent node (int) - * - * This is actually a wrapper around a for loop and would be used like so: - * - * fdt_for_each_subnode(node, fdt, parent) { - * Use node - * ... - * } - * - * if ((node < 0) && (node != -FDT_ERR_NOT_FOUND)) { - * Error handling - * } - * - * Note that this is implemented as a macro and @node is used as - * iterator in the loop. The parent variable be constant or even a - * literal. - * - */ -#define fdt_for_each_subnode(node, fdt, parent) \ - for (node = fdt_first_subnode(fdt, parent); \ - node >= 0; \ - node = fdt_next_subnode(fdt, node)) - -/**********************************************************************/ -/* General functions */ -/**********************************************************************/ -#define fdt_get_header(fdt, field) \ - (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) -#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) -#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) -#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) -#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) -#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) -#define fdt_version(fdt) (fdt_get_header(fdt, version)) -#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) -#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) -#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) -#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) - -#define fdt_set_hdr_(name) \ - static inline void fdt_set_##name(void *fdt, uint32_t val) \ - { \ - struct fdt_header *fdth = (struct fdt_header *)fdt; \ - fdth->name = cpu_to_fdt32(val); \ - } -fdt_set_hdr_(magic); -fdt_set_hdr_(totalsize); -fdt_set_hdr_(off_dt_struct); -fdt_set_hdr_(off_dt_strings); -fdt_set_hdr_(off_mem_rsvmap); -fdt_set_hdr_(version); -fdt_set_hdr_(last_comp_version); -fdt_set_hdr_(boot_cpuid_phys); -fdt_set_hdr_(size_dt_strings); -fdt_set_hdr_(size_dt_struct); -#undef fdt_set_hdr_ - -/** - * fdt_check_header - sanity check a device tree or possible device tree - * @fdt: pointer to data which might be a flattened device tree - * - * fdt_check_header() checks that the given buffer contains what - * appears to be a flattened device tree with sane information in its - * header. - * - * returns: - * 0, if the buffer appears to contain a valid device tree - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings, as above - */ -int fdt_check_header(const void *fdt); - -/** - * fdt_move - move a device tree around in memory - * @fdt: pointer to the device tree to move - * @buf: pointer to memory where the device is to be moved - * @bufsize: size of the memory space at buf - * - * fdt_move() relocates, if possible, the device tree blob located at - * fdt to the buffer at buf of size bufsize. The buffer may overlap - * with the existing device tree blob at fdt. Therefore, - * fdt_move(fdt, fdt, fdt_totalsize(fdt)) - * should always succeed. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings - */ -int fdt_move(const void *fdt, void *buf, int bufsize); - -/**********************************************************************/ -/* Read-only functions */ -/**********************************************************************/ - -/** - * fdt_string - retrieve a string from the strings block of a device tree - * @fdt: pointer to the device tree blob - * @stroffset: offset of the string within the strings block (native endian) - * - * fdt_string() retrieves a pointer to a single string from the - * strings block of the device tree blob at fdt. - * - * returns: - * a pointer to the string, on success - * NULL, if stroffset is out of bounds - */ -const char *fdt_string(const void *fdt, int stroffset); - -/** - * fdt_get_max_phandle - retrieves the highest phandle in a tree - * @fdt: pointer to the device tree blob - * - * fdt_get_max_phandle retrieves the highest phandle in the given - * device tree. This will ignore badly formatted phandles, or phandles - * with a value of 0 or -1. - * - * returns: - * the highest phandle on success - * 0, if no phandle was found in the device tree - * -1, if an error occurred - */ -uint32_t fdt_get_max_phandle(const void *fdt); - -/** - * fdt_num_mem_rsv - retrieve the number of memory reserve map entries - * @fdt: pointer to the device tree blob - * - * Returns the number of entries in the device tree blob's memory - * reservation map. This does not include the terminating 0,0 entry - * or any other (0,0) entries reserved for expansion. - * - * returns: - * the number of entries - */ -int fdt_num_mem_rsv(const void *fdt); - -/** - * fdt_get_mem_rsv - retrieve one memory reserve map entry - * @fdt: pointer to the device tree blob - * @address, @size: pointers to 64-bit variables - * - * On success, *address and *size will contain the address and size of - * the n-th reserve map entry from the device tree blob, in - * native-endian format. - * - * returns: - * 0, on success - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings - */ -int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); - -/** - * fdt_subnode_offset_namelen - find a subnode based on substring - * @fdt: pointer to the device tree blob - * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate - * @namelen: number of characters of name to consider - * - * Identical to fdt_subnode_offset(), but only examine the first - * namelen characters of name for matching the subnode name. This is - * useful for finding subnodes based on a portion of a larger string, - * such as a full path. - */ -#ifndef SWIG /* Not available in Python */ -int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, - const char *name, int namelen); -#endif -/** - * fdt_subnode_offset - find a subnode of a given node - * @fdt: pointer to the device tree blob - * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate - * - * fdt_subnode_offset() finds a subnode of the node at structure block - * offset parentoffset with the given name. name may include a unit - * address, in which case fdt_subnode_offset() will find the subnode - * with that unit address, or the unit address may be omitted, in - * which case fdt_subnode_offset() will find an arbitrary subnode - * whose name excluding unit address matches the given name. - * - * returns: - * structure block offset of the requested subnode (>=0), on success - * -FDT_ERR_NOTFOUND, if the requested subnode does not exist - * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE - * tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); - -/** - * fdt_path_offset_namelen - find a tree node by its full path - * @fdt: pointer to the device tree blob - * @path: full path of the node to locate - * @namelen: number of characters of path to consider - * - * Identical to fdt_path_offset(), but only consider the first namelen - * characters of path as the path name. - */ -#ifndef SWIG /* Not available in Python */ -int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen); -#endif - -/** - * fdt_path_offset - find a tree node by its full path - * @fdt: pointer to the device tree blob - * @path: full path of the node to locate - * - * fdt_path_offset() finds a node of a given path in the device tree. - * Each path component may omit the unit address portion, but the - * results of this are undefined if any such path component is - * ambiguous (that is if there are multiple nodes at the relevant - * level matching the given component, differentiated only by unit - * address). - * - * returns: - * structure block offset of the node with the requested path (>=0), on - * success - * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid - * -FDT_ERR_NOTFOUND, if the requested node does not exist - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_path_offset(const void *fdt, const char *path); - -/** - * fdt_get_name - retrieve the name of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: structure block offset of the starting node - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_get_name() retrieves the name (including unit address) of the - * device tree node at structure block offset nodeoffset. If lenp is - * non-NULL, the length of this name is also returned, in the integer - * pointed to by lenp. - * - * returns: - * pointer to the node's name, on success - * If lenp is non-NULL, *lenp contains the length of that name - * (>=0) - * NULL, on error - * if lenp is non-NULL *lenp contains an error code (<0): - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE - * tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings - */ -const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); - -/** - * fdt_first_property_offset - find the offset of a node's first property - * @fdt: pointer to the device tree blob - * @nodeoffset: structure block offset of a node - * - * fdt_first_property_offset() finds the first property of the node at - * the given structure block offset. - * - * returns: - * structure block offset of the property (>=0), on success - * -FDT_ERR_NOTFOUND, if the requested node has no properties - * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_first_property_offset(const void *fdt, int nodeoffset); - -/** - * fdt_next_property_offset - step through a node's properties - * @fdt: pointer to the device tree blob - * @offset: structure block offset of a property - * - * fdt_next_property_offset() finds the property immediately after the - * one at the given structure block offset. This will be a property - * of the same node as the given property. - * - * returns: - * structure block offset of the next property (>=0), on success - * -FDT_ERR_NOTFOUND, if the given property is the last in its node - * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_next_property_offset(const void *fdt, int offset); - -/** - * fdt_for_each_property_offset - iterate over all properties of a node - * - * @property_offset: property offset (int, lvalue) - * @fdt: FDT blob (const void *) - * @node: node offset (int) - * - * This is actually a wrapper around a for loop and would be used like so: - * - * fdt_for_each_property_offset(property, fdt, node) { - * Use property - * ... - * } - * - * if ((property < 0) && (property != -FDT_ERR_NOT_FOUND)) { - * Error handling - * } - * - * Note that this is implemented as a macro and property is used as - * iterator in the loop. The node variable can be constant or even a - * literal. - */ -#define fdt_for_each_property_offset(property, fdt, node) \ - for (property = fdt_first_property_offset(fdt, node); \ - property >= 0; \ - property = fdt_next_property_offset(fdt, property)) - -/** - * fdt_get_property_by_offset - retrieve the property at a given offset - * @fdt: pointer to the device tree blob - * @offset: offset of the property to retrieve - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_get_property_by_offset() retrieves a pointer to the - * fdt_property structure within the device tree blob at the given - * offset. If lenp is non-NULL, the length of the property value is - * also returned, in the integer pointed to by lenp. - * - * Note that this code only works on device tree versions >= 16. fdt_getprop() - * works on all versions. - * - * returns: - * pointer to the structure representing the property - * if lenp is non-NULL, *lenp contains the length of the property - * value (>=0) - * NULL, on error - * if lenp is non-NULL, *lenp contains an error code (<0): - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -const struct fdt_property *fdt_get_property_by_offset(const void *fdt, - int offset, - int *lenp); - -/** - * fdt_get_property_namelen - find a property based on substring - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to find - * @name: name of the property to find - * @namelen: number of characters of name to consider - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * Identical to fdt_get_property(), but only examine the first namelen - * characters of name for matching the property name. - */ -#ifndef SWIG /* Not available in Python */ -const struct fdt_property *fdt_get_property_namelen(const void *fdt, - int nodeoffset, - const char *name, - int namelen, int *lenp); -#endif - -/** - * fdt_get_property - find a given property in a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to find - * @name: name of the property to find - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_get_property() retrieves a pointer to the fdt_property - * structure within the device tree blob corresponding to the property - * named 'name' of the node at offset nodeoffset. If lenp is - * non-NULL, the length of the property value is also returned, in the - * integer pointed to by lenp. - * - * returns: - * pointer to the structure representing the property - * if lenp is non-NULL, *lenp contains the length of the property - * value (>=0) - * NULL, on error - * if lenp is non-NULL, *lenp contains an error code (<0): - * -FDT_ERR_NOTFOUND, node does not have named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE - * tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, - const char *name, int *lenp); -static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, - const char *name, - int *lenp) -{ - return (struct fdt_property *)(uintptr_t) - fdt_get_property(fdt, nodeoffset, name, lenp); -} - -/** - * fdt_getprop_by_offset - retrieve the value of a property at a given offset - * @fdt: pointer to the device tree blob - * @ffset: offset of the property to read - * @namep: pointer to a string variable (will be overwritten) or NULL - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_getprop_by_offset() retrieves a pointer to the value of the - * property at structure block offset 'offset' (this will be a pointer - * to within the device blob itself, not a copy of the value). If - * lenp is non-NULL, the length of the property value is also - * returned, in the integer pointed to by lenp. If namep is non-NULL, - * the property's namne will also be returned in the char * pointed to - * by namep (this will be a pointer to within the device tree's string - * block, not a new copy of the name). - * - * returns: - * pointer to the property's value - * if lenp is non-NULL, *lenp contains the length of the property - * value (>=0) - * if namep is non-NULL *namep contiains a pointer to the property - * name. - * NULL, on error - * if lenp is non-NULL, *lenp contains an error code (<0): - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -#ifndef SWIG /* This function is not useful in Python */ -const void *fdt_getprop_by_offset(const void *fdt, int offset, - const char **namep, int *lenp); -#endif - -/** - * fdt_getprop_namelen - get property value based on substring - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to find - * @name: name of the property to find - * @namelen: number of characters of name to consider - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * Identical to fdt_getprop(), but only examine the first namelen - * characters of name for matching the property name. - */ -#ifndef SWIG /* Not available in Python */ -const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, - const char *name, int namelen, int *lenp); -static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset, - const char *name, int namelen, - int *lenp) -{ - return (void *)(uintptr_t)fdt_getprop_namelen(fdt, nodeoffset, name, - namelen, lenp); -} -#endif - -/** - * fdt_getprop - retrieve the value of a given property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to find - * @name: name of the property to find - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_getprop() retrieves a pointer to the value of the property - * named 'name' of the node at offset nodeoffset (this will be a - * pointer to within the device blob itself, not a copy of the value). - * If lenp is non-NULL, the length of the property value is also - * returned, in the integer pointed to by lenp. - * - * returns: - * pointer to the property's value - * if lenp is non-NULL, *lenp contains the length of the property - * value (>=0) - * NULL, on error - * if lenp is non-NULL, *lenp contains an error code (<0): - * -FDT_ERR_NOTFOUND, node does not have named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE - * tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -const void *fdt_getprop(const void *fdt, int nodeoffset, - const char *name, int *lenp); -static inline void *fdt_getprop_w(void *fdt, int nodeoffset, - const char *name, int *lenp) -{ - return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); -} - -/** - * fdt_get_phandle - retrieve the phandle of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: structure block offset of the node - * - * fdt_get_phandle() retrieves the phandle of the device tree node at - * structure block offset nodeoffset. - * - * returns: - * the phandle of the node at nodeoffset, on success (!= 0, != -1) - * 0, if the node has no phandle, or another error occurs - */ -uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); - -/** - * fdt_get_alias_namelen - get alias based on substring - * @fdt: pointer to the device tree blob - * @name: name of the alias th look up - * @namelen: number of characters of name to consider - * - * Identical to fdt_get_alias(), but only examine the first namelen - * characters of name for matching the alias name. - */ -#ifndef SWIG /* Not available in Python */ -const char *fdt_get_alias_namelen(const void *fdt, - const char *name, int namelen); -#endif - -/** - * fdt_get_alias - retrieve the path referenced by a given alias - * @fdt: pointer to the device tree blob - * @name: name of the alias th look up - * - * fdt_get_alias() retrieves the value of a given alias. That is, the - * value of the property named 'name' in the node /aliases. - * - * returns: - * a pointer to the expansion of the alias named 'name', if it exists - * NULL, if the given alias or the /aliases node does not exist - */ -const char *fdt_get_alias(const void *fdt, const char *name); - -/** - * fdt_get_path - determine the full path of a node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose path to find - * @buf: character buffer to contain the returned path (will be overwritten) - * @buflen: size of the character buffer at buf - * - * fdt_get_path() computes the full path of the node at offset - * nodeoffset, and records that path in the buffer at buf. - * - * NOTE: This function is expensive, as it must scan the device tree - * structure from the start to nodeoffset. - * - * returns: - * 0, on success - * buf contains the absolute path of the node at - * nodeoffset, as a NUL-terminated string. - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) - * characters and will not fit in the given buffer. - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); - -/** - * fdt_supernode_atdepth_offset - find a specific ancestor of a node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose parent to find - * @supernodedepth: depth of the ancestor to find - * @nodedepth: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_supernode_atdepth_offset() finds an ancestor of the given node - * at a specific depth from the root (where the root itself has depth - * 0, its immediate subnodes depth 1 and so forth). So - * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); - * will always return 0, the offset of the root node. If the node at - * nodeoffset has depth D, then: - * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); - * will return nodeoffset itself. - * - * NOTE: This function is expensive, as it must scan the device tree - * structure from the start to nodeoffset. - * - * returns: - * structure block offset of the node at node offset's ancestor - * of depth supernodedepth (>=0), on success - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of - * nodeoffset - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, - int supernodedepth, int *nodedepth); - -/** - * fdt_node_depth - find the depth of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose parent to find - * - * fdt_node_depth() finds the depth of a given node. The root node - * has depth 0, its immediate subnodes depth 1 and so forth. - * - * NOTE: This function is expensive, as it must scan the device tree - * structure from the start to nodeoffset. - * - * returns: - * depth of the node at nodeoffset (>=0), on success - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_depth(const void *fdt, int nodeoffset); - -/** - * fdt_parent_offset - find the parent of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose parent to find - * - * fdt_parent_offset() locates the parent node of a given node (that - * is, it finds the offset of the node which contains the node at - * nodeoffset as a subnode). - * - * NOTE: This function is expensive, as it must scan the device tree - * structure from the start to nodeoffset, *twice*. - * - * returns: - * structure block offset of the parent of the node at nodeoffset - * (>=0), on success - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_parent_offset(const void *fdt, int nodeoffset); - -/** - * fdt_node_offset_by_prop_value - find nodes with a given property value - * @fdt: pointer to the device tree blob - * @startoffset: only find nodes after this offset - * @propname: property name to check - * @propval: property value to search for - * @proplen: length of the value in propval - * - * fdt_node_offset_by_prop_value() returns the offset of the first - * node after startoffset, which has a property named propname whose - * value is of length proplen and has value equal to propval; or if - * startoffset is -1, the very first such node in the tree. - * - * To iterate through all nodes matching the criterion, the following - * idiom can be used: - * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, - * propval, proplen); - * while (offset != -FDT_ERR_NOTFOUND) { - * // other code here - * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, - * propval, proplen); - * } - * - * Note the -1 in the first call to the function, if 0 is used here - * instead, the function will never locate the root node, even if it - * matches the criterion. - * - * returns: - * structure block offset of the located node (>= 0, >startoffset), - * on success - * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the - * tree after startoffset - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, - const char *propname, - const void *propval, int proplen); - -/** - * fdt_node_offset_by_phandle - find the node with a given phandle - * @fdt: pointer to the device tree blob - * @phandle: phandle value - * - * fdt_node_offset_by_phandle() returns the offset of the node - * which has the given phandle value. If there is more than one node - * in the tree with the given phandle (an invalid tree), results are - * undefined. - * - * returns: - * structure block offset of the located node (>= 0), on success - * -FDT_ERR_NOTFOUND, no node with that phandle exists - * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); - -/** - * fdt_node_check_compatible: check a node's compatible property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of a tree node - * @compatible: string to match against - * - * - * fdt_node_check_compatible() returns 0 if the given node contains a - * 'compatible' property with the given string as one of its elements, - * it returns non-zero otherwise, or on error. - * - * returns: - * 0, if the node has a 'compatible' property listing the given string - * 1, if the node has a 'compatible' property, but it does not list - * the given string - * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property - * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_check_compatible(const void *fdt, int nodeoffset, - const char *compatible); - -/** - * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value - * @fdt: pointer to the device tree blob - * @startoffset: only find nodes after this offset - * @compatible: 'compatible' string to match against - * - * fdt_node_offset_by_compatible() returns the offset of the first - * node after startoffset, which has a 'compatible' property which - * lists the given compatible string; or if startoffset is -1, the - * very first such node in the tree. - * - * To iterate through all nodes matching the criterion, the following - * idiom can be used: - * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); - * while (offset != -FDT_ERR_NOTFOUND) { - * // other code here - * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); - * } - * - * Note the -1 in the first call to the function, if 0 is used here - * instead, the function will never locate the root node, even if it - * matches the criterion. - * - * returns: - * structure block offset of the located node (>= 0, >startoffset), - * on success - * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the - * tree after startoffset - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_offset_by_compatible(const void *fdt, int startoffset, - const char *compatible); - -/** - * fdt_stringlist_contains - check a string list property for a string - * @strlist: Property containing a list of strings to check - * @listlen: Length of property - * @str: String to search for - * - * This is a utility function provided for convenience. The list contains - * one or more strings, each terminated by \0, as is found in a device tree - * "compatible" property. - * - * @return: 1 if the string is found in the list, 0 not found, or invalid list - */ -int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); - -/** - * fdt_stringlist_count - count the number of strings in a string list - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of a tree node - * @property: name of the property containing the string list - * @return: - * the number of strings in the given property - * -FDT_ERR_BADVALUE if the property value is not NUL-terminated - * -FDT_ERR_NOTFOUND if the property does not exist - */ -int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property); - -/** - * fdt_stringlist_search - find a string in a string list and return its index - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of a tree node - * @property: name of the property containing the string list - * @string: string to look up in the string list - * - * Note that it is possible for this function to succeed on property values - * that are not NUL-terminated. That's because the function will stop after - * finding the first occurrence of @string. This can for example happen with - * small-valued cell properties, such as #address-cells, when searching for - * the empty string. - * - * @return: - * the index of the string in the list of strings - * -FDT_ERR_BADVALUE if the property value is not NUL-terminated - * -FDT_ERR_NOTFOUND if the property does not exist or does not contain - * the given string - */ -int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property, - const char *string); - -/** - * fdt_stringlist_get() - obtain the string at a given index in a string list - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of a tree node - * @property: name of the property containing the string list - * @index: index of the string to return - * @lenp: return location for the string length or an error code on failure - * - * Note that this will successfully extract strings from properties with - * non-NUL-terminated values. For example on small-valued cell properties - * this function will return the empty string. - * - * If non-NULL, the length of the string (on success) or a negative error-code - * (on failure) will be stored in the integer pointer to by lenp. - * - * @return: - * A pointer to the string at the given index in the string list or NULL on - * failure. On success the length of the string will be stored in the memory - * location pointed to by the lenp parameter, if non-NULL. On failure one of - * the following negative error codes will be returned in the lenp parameter - * (if non-NULL): - * -FDT_ERR_BADVALUE if the property value is not NUL-terminated - * -FDT_ERR_NOTFOUND if the property does not exist - */ -const char *fdt_stringlist_get(const void *fdt, int nodeoffset, - const char *property, int index, - int *lenp); - -/**********************************************************************/ -/* Read-only functions (addressing related) */ -/**********************************************************************/ - -/** - * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells - * - * This is the maximum value for #address-cells, #size-cells and - * similar properties that will be processed by libfdt. IEE1275 - * requires that OF implementations handle values up to 4. - * Implementations may support larger values, but in practice higher - * values aren't used. - */ -#define FDT_MAX_NCELLS 4 - -/** - * fdt_address_cells - retrieve address size for a bus represented in the tree - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node to find the address size for - * - * When the node has a valid #address-cells property, returns its value. - * - * returns: - * 0 <= n < FDT_MAX_NCELLS, on success - * 2, if the node has no #address-cells property - * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid - * #address-cells property - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_address_cells(const void *fdt, int nodeoffset); - -/** - * fdt_size_cells - retrieve address range size for a bus represented in the - * tree - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node to find the address range size for - * - * When the node has a valid #size-cells property, returns its value. - * - * returns: - * 0 <= n < FDT_MAX_NCELLS, on success - * 2, if the node has no #address-cells property - * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid - * #size-cells property - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_size_cells(const void *fdt, int nodeoffset); - - -/**********************************************************************/ -/* Write-in-place functions */ -/**********************************************************************/ - -/** - * fdt_setprop_inplace_namelen_partial - change a property's value, - * but not its size - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @namelen: number of characters of name to consider - * @idx: index of the property to change in the array - * @val: pointer to data to replace the property value with - * @len: length of the property value - * - * Identical to fdt_setprop_inplace(), but modifies the given property - * starting from the given index, and using only the first characters - * of the name. It is useful when you want to manipulate only one value of - * an array and you have a string that doesn't end with \0. - */ -#ifndef SWIG /* Not available in Python */ -int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, - const char *name, int namelen, - uint32_t idx, const void *val, - int len); -#endif - -/** - * fdt_setprop_inplace - change a property's value, but not its size - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: pointer to data to replace the property value with - * @len: length of the property value - * - * fdt_setprop_inplace() replaces the value of a given property with - * the data in val, of length len. This function cannot change the - * size of a property, and so will only work if len is equal to the - * current length of the property. - * - * This function will alter only the bytes in the blob which contain - * the given property value, and will not alter or move any other part - * of the tree. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, if len is not equal to the property's current length - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -#ifndef SWIG /* Not available in Python */ -int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, - const void *val, int len); -#endif - -/** - * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 32-bit integer value to replace the property with - * - * fdt_setprop_inplace_u32() replaces the value of a given property - * with the 32-bit integer value in val, converting val to big-endian - * if necessary. This function cannot change the size of a property, - * and so will only work if the property already exists and has length - * 4. - * - * This function will alter only the bytes in the blob which contain - * the given property value, and will not alter or move any other part - * of the tree. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, - const char *name, uint32_t val) -{ - fdt32_t tmp = cpu_to_fdt32(val); - return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 64-bit integer value to replace the property with - * - * fdt_setprop_inplace_u64() replaces the value of a given property - * with the 64-bit integer value in val, converting val to big-endian - * if necessary. This function cannot change the size of a property, - * and so will only work if the property already exists and has length - * 8. - * - * This function will alter only the bytes in the blob which contain - * the given property value, and will not alter or move any other part - * of the tree. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, - const char *name, uint64_t val) -{ - fdt64_t tmp = cpu_to_fdt64(val); - return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_setprop_inplace_cell - change the value of a single-cell property - * - * This is an alternative name for fdt_setprop_inplace_u32() - */ -static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, - const char *name, uint32_t val) -{ - return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); -} - -/** - * fdt_nop_property - replace a property with nop tags - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to nop - * @name: name of the property to nop - * - * fdt_nop_property() will replace a given property's representation - * in the blob with FDT_NOP tags, effectively removing it from the - * tree. - * - * This function will alter only the bytes in the blob which contain - * the property, and will not alter or move any other part of the - * tree. - * - * returns: - * 0, on success - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_nop_property(void *fdt, int nodeoffset, const char *name); - -/** - * fdt_nop_node - replace a node (subtree) with nop tags - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node to nop - * - * fdt_nop_node() will replace a given node's representation in the - * blob, including all its subnodes, if any, with FDT_NOP tags, - * effectively removing it from the tree. - * - * This function will alter only the bytes in the blob which contain - * the node and its properties and subnodes, and will not alter or - * move any other part of the tree. - * - * returns: - * 0, on success - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_nop_node(void *fdt, int nodeoffset); - -/**********************************************************************/ -/* Sequential write functions */ -/**********************************************************************/ - -int fdt_create(void *buf, int bufsize); -int fdt_resize(void *fdt, void *buf, int bufsize); -int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); -int fdt_finish_reservemap(void *fdt); -int fdt_begin_node(void *fdt, const char *name); -int fdt_property(void *fdt, const char *name, const void *val, int len); -static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) -{ - fdt32_t tmp = cpu_to_fdt32(val); - return fdt_property(fdt, name, &tmp, sizeof(tmp)); -} -static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) -{ - fdt64_t tmp = cpu_to_fdt64(val); - return fdt_property(fdt, name, &tmp, sizeof(tmp)); -} -static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) -{ - return fdt_property_u32(fdt, name, val); -} - -/** - * fdt_property_placeholder - add a new property and return a ptr to its value - * - * @fdt: pointer to the device tree blob - * @name: name of property to add - * @len: length of property value in bytes - * @valp: returns a pointer to where where the value should be placed - * - * returns: - * 0, on success - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_NOSPACE, standard meanings - */ -int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp); - -#define fdt_property_string(fdt, name, str) \ - fdt_property(fdt, name, str, strlen(str)+1) -int fdt_end_node(void *fdt); -int fdt_finish(void *fdt); - -/**********************************************************************/ -/* Read-write functions */ -/**********************************************************************/ - -int fdt_create_empty_tree(void *buf, int bufsize); -int fdt_open_into(const void *fdt, void *buf, int bufsize); -int fdt_pack(void *fdt); - -/** - * fdt_add_mem_rsv - add one memory reserve map entry - * @fdt: pointer to the device tree blob - * @address, @size: 64-bit values (native endian) - * - * Adds a reserve map entry to the given blob reserving a region at - * address address of length size. - * - * This function will insert data into the reserve map and will - * therefore change the indexes of some entries in the table. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new reservation entry - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); - -/** - * fdt_del_mem_rsv - remove a memory reserve map entry - * @fdt: pointer to the device tree blob - * @n: entry to remove - * - * fdt_del_mem_rsv() removes the n-th memory reserve map entry from - * the blob. - * - * This function will delete data from the reservation table and will - * therefore change the indexes of some entries in the table. - * - * returns: - * 0, on success - * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there - * are less than n+1 reserve map entries) - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_del_mem_rsv(void *fdt, int n); - -/** - * fdt_set_name - change the name of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: structure block offset of a node - * @name: name to give the node - * - * fdt_set_name() replaces the name (including unit address, if any) - * of the given node with the given string. NOTE: this function can't - * efficiently check if the new name is unique amongst the given - * node's siblings; results are undefined if this function is invoked - * with a name equal to one of the given node's siblings. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob - * to contain the new name - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings - */ -int fdt_set_name(void *fdt, int nodeoffset, const char *name); - -/** - * fdt_setprop - create or change a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: pointer to data to set the property value to - * @len: length of the property value - * - * fdt_setprop() sets the value of the named property in the given - * node to the given value and length, creating the property if it - * does not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_setprop(void *fdt, int nodeoffset, const char *name, - const void *val, int len); - -/** - * fdt_setprop_placeholder - allocate space for a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @len: length of the property value - * @prop_data: return pointer to property data - * - * fdt_setprop_placeholer() allocates the named property in the given node. - * If the property exists it is resized. In either case a pointer to the - * property data is returned. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name, - int len, void **prop_data); - -/** - * fdt_setprop_u32 - set a property to a 32-bit integer - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 32-bit integer value for the property (native endian) - * - * fdt_setprop_u32() sets the value of the named property in the given - * node to the given 32-bit integer value (converting to big-endian if - * necessary), or creates a new property with that value if it does - * not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, - uint32_t val) -{ - fdt32_t tmp = cpu_to_fdt32(val); - return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_setprop_u64 - set a property to a 64-bit integer - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 64-bit integer value for the property (native endian) - * - * fdt_setprop_u64() sets the value of the named property in the given - * node to the given 64-bit integer value (converting to big-endian if - * necessary), or creates a new property with that value if it does - * not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, - uint64_t val) -{ - fdt64_t tmp = cpu_to_fdt64(val); - return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_setprop_cell - set a property to a single cell value - * - * This is an alternative name for fdt_setprop_u32() - */ -static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, - uint32_t val) -{ - return fdt_setprop_u32(fdt, nodeoffset, name, val); -} - -/** - * fdt_setprop_string - set a property to a string value - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @str: string value for the property - * - * fdt_setprop_string() sets the value of the named property in the - * given node to the given string value (using the length of the - * string to determine the new length of the property), or creates a - * new property with that value if it does not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -#define fdt_setprop_string(fdt, nodeoffset, name, str) \ - fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) - - -/** - * fdt_setprop_empty - set a property to an empty value - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * - * fdt_setprop_empty() sets the value of the named property in the - * given node to an empty (zero length) value, or creates a new empty - * property if it does not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -#define fdt_setprop_empty(fdt, nodeoffset, name) \ - fdt_setprop((fdt), (nodeoffset), (name), NULL, 0) - -/** - * fdt_appendprop - append to or create a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to append to - * @val: pointer to data to append to the property value - * @len: length of the data to append to the property value - * - * fdt_appendprop() appends the value to the named property in the - * given node, creating the property if it does not already exist. - * - * This function may insert data into the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_appendprop(void *fdt, int nodeoffset, const char *name, - const void *val, int len); - -/** - * fdt_appendprop_u32 - append a 32-bit integer value to a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 32-bit integer value to append to the property (native endian) - * - * fdt_appendprop_u32() appends the given 32-bit integer value - * (converting to big-endian if necessary) to the value of the named - * property in the given node, or creates a new property with that - * value if it does not already exist. - * - * This function may insert data into the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, - const char *name, uint32_t val) -{ - fdt32_t tmp = cpu_to_fdt32(val); - return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_appendprop_u64 - append a 64-bit integer value to a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 64-bit integer value to append to the property (native endian) - * - * fdt_appendprop_u64() appends the given 64-bit integer value - * (converting to big-endian if necessary) to the value of the named - * property in the given node, or creates a new property with that - * value if it does not already exist. - * - * This function may insert data into the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, - const char *name, uint64_t val) -{ - fdt64_t tmp = cpu_to_fdt64(val); - return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_appendprop_cell - append a single cell value to a property - * - * This is an alternative name for fdt_appendprop_u32() - */ -static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, - const char *name, uint32_t val) -{ - return fdt_appendprop_u32(fdt, nodeoffset, name, val); -} - -/** - * fdt_appendprop_string - append a string to a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @str: string value to append to the property - * - * fdt_appendprop_string() appends the given string to the value of - * the named property in the given node, or creates a new property - * with that value if it does not already exist. - * - * This function may insert data into the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ - fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) - -/** - * fdt_delprop - delete a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to nop - * @name: name of the property to nop - * - * fdt_del_property() will delete the given property. - * - * This function will delete data from the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_delprop(void *fdt, int nodeoffset, const char *name); - -/** - * fdt_add_subnode_namelen - creates a new node based on substring - * @fdt: pointer to the device tree blob - * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate - * @namelen: number of characters of name to consider - * - * Identical to fdt_add_subnode(), but use only the first namelen - * characters of name as the name of the new node. This is useful for - * creating subnodes based on a portion of a larger string, such as a - * full path. - */ -#ifndef SWIG /* Not available in Python */ -int fdt_add_subnode_namelen(void *fdt, int parentoffset, - const char *name, int namelen); -#endif - -/** - * fdt_add_subnode - creates a new node - * @fdt: pointer to the device tree blob - * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate - * - * fdt_add_subnode() creates a new node as a subnode of the node at - * structure block offset parentoffset, with the given name (which - * should include the unit address, if any). - * - * This function will insert data into the blob, and will therefore - * change the offsets of some existing nodes. - - * returns: - * structure block offset of the created nodeequested subnode (>=0), on - * success - * -FDT_ERR_NOTFOUND, if the requested subnode does not exist - * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE - * tag - * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of - * the given name - * -FDT_ERR_NOSPACE, if there is insufficient free space in the - * blob to contain the new node - * -FDT_ERR_NOSPACE - * -FDT_ERR_BADLAYOUT - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_add_subnode(void *fdt, int parentoffset, const char *name); - -/** - * fdt_del_node - delete a node (subtree) - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node to nop - * - * fdt_del_node() will remove the given node, including all its - * subnodes if any, from the blob. - * - * This function will delete data from the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_del_node(void *fdt, int nodeoffset); - -/** - * fdt_overlay_apply - Applies a DT overlay on a base DT - * @fdt: pointer to the base device tree blob - * @fdto: pointer to the device tree overlay blob - * - * fdt_overlay_apply() will apply the given device tree overlay on the - * given base device tree. - * - * Expect the base device tree to be modified, even if the function - * returns an error. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there's not enough space in the base device tree - * -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or - * properties in the base DT - * -FDT_ERR_BADPHANDLE, - * -FDT_ERR_BADOVERLAY, - * -FDT_ERR_NOPHANDLES, - * -FDT_ERR_INTERNAL, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADOFFSET, - * -FDT_ERR_BADPATH, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_overlay_apply(void *fdt, void *fdto); - -/**********************************************************************/ -/* Debugging / informational functions */ -/**********************************************************************/ - -const char *fdt_strerror(int errval); - -#endif /* LIBFDT_H */ diff --git a/include/lib/libfdt/libfdt_env.h b/include/lib/libfdt/libfdt_env.h deleted file mode 100644 index bd2474628..000000000 --- a/include/lib/libfdt/libfdt_env.h +++ /dev/null @@ -1,139 +0,0 @@ -#ifndef LIBFDT_ENV_H -#define LIBFDT_ENV_H -/* - * libfdt - Flat Device Tree manipulation - * Copyright (C) 2006 David Gibson, IBM Corporation. - * Copyright 2012 Kim Phillips, Freescale Semiconductor. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <stddef.h> -#include <stdint.h> -#include <stdlib.h> -#include <string.h> - -#ifdef __CHECKER__ -#define FDT_FORCE __attribute__((force)) -#define FDT_BITWISE __attribute__((bitwise)) -#else -#define FDT_FORCE -#define FDT_BITWISE -#endif - -typedef uint16_t FDT_BITWISE fdt16_t; -typedef uint32_t FDT_BITWISE fdt32_t; -typedef uint64_t FDT_BITWISE fdt64_t; - -#define EXTRACT_BYTE(x, n) ((unsigned long long)((uint8_t *)&x)[n]) -#define CPU_TO_FDT16(x) ((EXTRACT_BYTE(x, 0) << 8) | EXTRACT_BYTE(x, 1)) -#define CPU_TO_FDT32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \ - (EXTRACT_BYTE(x, 2) << 8) | EXTRACT_BYTE(x, 3)) -#define CPU_TO_FDT64(x) ((EXTRACT_BYTE(x, 0) << 56) | (EXTRACT_BYTE(x, 1) << 48) | \ - (EXTRACT_BYTE(x, 2) << 40) | (EXTRACT_BYTE(x, 3) << 32) | \ - (EXTRACT_BYTE(x, 4) << 24) | (EXTRACT_BYTE(x, 5) << 16) | \ - (EXTRACT_BYTE(x, 6) << 8) | EXTRACT_BYTE(x, 7)) - -static inline uint16_t fdt16_to_cpu(fdt16_t x) -{ - return (FDT_FORCE uint16_t)CPU_TO_FDT16(x); -} -static inline fdt16_t cpu_to_fdt16(uint16_t x) -{ - return (FDT_FORCE fdt16_t)CPU_TO_FDT16(x); -} - -static inline uint32_t fdt32_to_cpu(fdt32_t x) -{ - return (FDT_FORCE uint32_t)CPU_TO_FDT32(x); -} -static inline fdt32_t cpu_to_fdt32(uint32_t x) -{ - return (FDT_FORCE fdt32_t)CPU_TO_FDT32(x); -} - -static inline uint64_t fdt64_to_cpu(fdt64_t x) -{ - return (FDT_FORCE uint64_t)CPU_TO_FDT64(x); -} -static inline fdt64_t cpu_to_fdt64(uint64_t x) -{ - return (FDT_FORCE fdt64_t)CPU_TO_FDT64(x); -} -#undef CPU_TO_FDT64 -#undef CPU_TO_FDT32 -#undef CPU_TO_FDT16 -#undef EXTRACT_BYTE - -#ifdef __APPLE__ -#include <AvailabilityMacros.h> - -/* strnlen() is not available on Mac OS < 10.7 */ -# if !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < \ - MAC_OS_X_VERSION_10_7) - -#define strnlen fdt_strnlen - -/* - * fdt_strnlen: returns the length of a string or max_count - which ever is - * smallest. - * Input 1 string: the string whose size is to be determined - * Input 2 max_count: the maximum value returned by this function - * Output: length of the string or max_count (the smallest of the two) - */ -static inline size_t fdt_strnlen(const char *string, size_t max_count) -{ - const char *p = memchr(string, 0, max_count); - return p ? p - string : max_count; -} - -#endif /* !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < - MAC_OS_X_VERSION_10_7) */ - -#endif /* __APPLE__ */ - -#endif /* LIBFDT_ENV_H */ diff --git a/include/lib/object_pool.h b/include/lib/object_pool.h index 0f85331a8..66e8c4780 100644 --- a/include/lib/object_pool.h +++ b/include/lib/object_pool.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -56,13 +56,13 @@ struct object_pool { */ static inline void *pool_alloc_n(struct object_pool *pool, size_t count) { - if (pool->used + count > pool->capacity) { + if ((pool->used + count) > pool->capacity) { ERROR("Cannot allocate %zu objects out of pool (%zu objects left).\n", count, pool->capacity - pool->used); panic(); } - void *obj = (char *)(pool->objects) + pool->obj_size * pool->used; + void *obj = (char *)(pool->objects) + (pool->obj_size * pool->used); pool->used += count; return obj; } diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h index 3fc8e3863..fa990d2e5 100644 --- a/include/lib/pmf/pmf.h +++ b/include/lib/pmf/pmf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,13 +14,13 @@ /* * Constants used for/by PMF services. */ -#define PMF_ARM_TIF_IMPL_ID U(0x41) +#define PMF_ARM_TIF_IMPL_ID UL(0x41) #define PMF_TID_SHIFT 0 -#define PMF_TID_MASK (U(0xFF) << PMF_TID_SHIFT) +#define PMF_TID_MASK (UL(0xFF) << PMF_TID_SHIFT) #define PMF_SVC_ID_SHIFT 10 -#define PMF_SVC_ID_MASK (U(0x3F) << PMF_SVC_ID_SHIFT) +#define PMF_SVC_ID_MASK (UL(0x3F) << PMF_SVC_ID_SHIFT) #define PMF_IMPL_ID_SHIFT 24 -#define PMF_IMPL_ID_MASK (U(0xFF) << PMF_IMPL_ID_SHIFT) +#define PMF_IMPL_ID_MASK (UL(0xFF) << PMF_IMPL_ID_SHIFT) /* * Flags passed to PMF_REGISTER_SERVICE diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h index db38e556a..b49c6da09 100644 --- a/include/lib/pmf/pmf_helpers.h +++ b/include/lib/pmf/pmf_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -173,25 +173,27 @@ typedef struct pmf_svc_desc { unsigned int tid, \ unsigned long long ts) \ { \ - CASSERT(_flags, select_proper_config); \ - PMF_VALIDATE_TID(_name, tid); \ + CASSERT(_flags != 0, select_proper_config); \ + PMF_VALIDATE_TID(_name, (uint64_t)tid); \ uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ if (((_flags) & PMF_STORE_ENABLE) != 0) \ - __pmf_store_timestamp(base_addr, tid, ts); \ + __pmf_store_timestamp(base_addr, \ + (uint64_t)tid, ts); \ if (((_flags) & PMF_DUMP_ENABLE) != 0) \ - __pmf_dump_timestamp(tid, ts); \ + __pmf_dump_timestamp((uint64_t)tid, ts); \ } \ void pmf_capture_timestamp_with_cache_maint_ ## _name( \ unsigned int tid, \ unsigned long long ts) \ { \ - CASSERT(_flags, select_proper_config); \ - PMF_VALIDATE_TID(_name, tid); \ + CASSERT(_flags != 0, select_proper_config); \ + PMF_VALIDATE_TID(_name, (uint64_t)tid); \ uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ if (((_flags) & PMF_STORE_ENABLE) != 0) \ - __pmf_store_timestamp_with_cache_maint(base_addr, tid, ts);\ + __pmf_store_timestamp_with_cache_maint( \ + base_addr, (uint64_t)tid, ts); \ if (((_flags) & PMF_DUMP_ENABLE) != 0) \ - __pmf_dump_timestamp(tid, ts); \ + __pmf_dump_timestamp((uint64_t)tid, ts); \ } /* diff --git a/include/lib/psci/psci_lib.h b/include/lib/psci/psci_lib.h index 76c1a8dcf..1ac45adf7 100644 --- a/include/lib/psci/psci_lib.h +++ b/include/lib/psci/psci_lib.h @@ -89,6 +89,8 @@ void psci_warmboot_entrypoint(void); void psci_register_spd_pm_hook(const spd_pm_ops_t *pm); void psci_prepare_next_non_secure_ctx( entry_point_info_t *next_image_info); +int psci_stop_other_cores(unsigned int wait_ms, + void (*stop_func)(u_register_t mpidr)); #endif /* __ASSEMBLER__ */ #endif /* PSCI_LIB_H */ diff --git a/include/lib/smccc.h b/include/lib/smccc.h index 5e13e6f0a..470317dd0 100644 --- a/include/lib/smccc.h +++ b/include/lib/smccc.h @@ -78,8 +78,8 @@ #define SMC_64 U(1) #define SMC_32 U(0) -#define SMC_TYPE_FAST ULL(1) -#define SMC_TYPE_YIELD ULL(0) +#define SMC_TYPE_FAST UL(1) +#define SMC_TYPE_YIELD UL(0) #define SMC_OK ULL(0) #define SMC_UNK -1 @@ -112,7 +112,8 @@ /* The macro below is used to identify a valid Fast SMC call */ #define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & U(0xff))) && \ - (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST)) + (GET_SMC_TYPE(_fid) \ + == (uint32_t)SMC_TYPE_FAST)) /* * Macro to define UUID for services. Apart from defining and initializing a @@ -122,18 +123,19 @@ */ #define DEFINE_SVC_UUID2(_name, _tl, _tm, _th, _cl, _ch, \ _n0, _n1, _n2, _n3, _n4, _n5) \ - CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\ + CASSERT((uint32_t)(_tl) != (uint32_t)SMC_UNK, \ + invalid_svc_uuid_##_name); \ static const uuid_t _name = { \ - {(_tl >> 24) & 0xFF, \ - (_tl >> 16) & 0xFF, \ - (_tl >> 8) & 0xFF, \ - (_tl & 0xFF)}, \ - {(_tm >> 8) & 0xFF, \ - (_tm & 0xFF)}, \ - {(_th >> 8) & 0xFF, \ - (_th & 0xFF)}, \ - _cl, _ch, \ - { _n0, _n1, _n2, _n3, _n4, _n5 } \ + {((_tl) >> 24) & 0xFF, \ + ((_tl) >> 16) & 0xFF, \ + ((_tl) >> 8) & 0xFF, \ + ((_tl) & 0xFF)}, \ + {((_tm) >> 8) & 0xFF, \ + ((_tm) & 0xFF)}, \ + {((_th) >> 8) & 0xFF, \ + ((_th) & 0xFF)}, \ + (_cl), (_ch), \ + { (_n0), (_n1), (_n2), (_n3), (_n4), (_n5) } \ } /* diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 23f59bdc3..2d0e9c08e 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,7 +17,7 @@ #define IS_POWER_OF_TWO(x) \ (((x) & ((x) - 1)) == 0) -#define SIZE_FROM_LOG2_WORDS(n) (4 << (n)) +#define SIZE_FROM_LOG2_WORDS(n) (U(4) << (n)) #define BIT_32(nr) (U(1) << (nr)) #define BIT_64(nr) (ULL(1) << (nr)) @@ -157,4 +158,9 @@ # define SPECULATION_SAFE_VALUE(var) var #endif +/* + * Ticks elapsed in one second with a signal of 1 MHz + */ +#define MHZ_TICKS_PER_SEC U(1000000) + #endif /* UTILS_DEF_H */ diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h index abdf1b6d0..269afd287 100644 --- a/include/lib/xlat_tables/xlat_mmu_helpers.h +++ b/include/lib/xlat_tables/xlat_mmu_helpers.h @@ -56,6 +56,8 @@ #include <stdint.h> #include <string.h> +#include <arch_helpers.h> + /* * Return the values that the MMU configuration registers must contain for the * specified translation context. `params` must be a pointer to array of size @@ -70,6 +72,7 @@ void setup_mmu_cfg(uint64_t *params, unsigned int flags, void enable_mmu_el1(unsigned int flags); void enable_mmu_el2(unsigned int flags); void enable_mmu_el3(unsigned int flags); +void enable_mmu(unsigned int flags); void enable_mmu_direct_el1(unsigned int flags); void enable_mmu_direct_el2(unsigned int flags); diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h index 76cfc0b34..579d8d89c 100644 --- a/include/lib/xlat_tables/xlat_tables_defs.h +++ b/include/lib/xlat_tables/xlat_tables_defs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -74,8 +74,8 @@ * 64KB. However, only 4KB are supported at the moment. */ #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT -#define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT) -#define PAGE_SIZE_MASK (PAGE_SIZE - U(1)) +#define PAGE_SIZE (UL(1) << PAGE_SIZE_SHIFT) +#define PAGE_SIZE_MASK (PAGE_SIZE - UL(1)) #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == U(0)) #if (ARM_ARCH_MAJOR == 7) && !ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h index 0e099987e..359b9839a 100644 --- a/include/lib/xlat_tables/xlat_tables_v2.h +++ b/include/lib/xlat_tables/xlat_tables_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -66,6 +66,11 @@ #define MT_EXECUTE_SHIFT U(5) /* In the EL1&0 translation regime, User (EL0) or Privileged (EL1). */ #define MT_USER_SHIFT U(6) + +/* Shareability attribute for the memory region */ +#define MT_SHAREABILITY_SHIFT U(7) +#define MT_SHAREABILITY_MASK (U(3) << MT_SHAREABILITY_SHIFT) +#define MT_SHAREABILITY(_attr) ((_attr) & MT_SHAREABILITY_MASK) /* All other bits are reserved */ /* @@ -106,6 +111,18 @@ #define MT_USER (U(1) << MT_USER_SHIFT) #define MT_PRIVILEGED (U(0) << MT_USER_SHIFT) +/* + * Shareability defines the visibility of any cache changes to + * all masters belonging to a shareable domain. + * + * MT_SHAREABILITY_ISH: For inner shareable domain + * MT_SHAREABILITY_OSH: For outer shareable domain + * MT_SHAREABILITY_NSH: For non shareable domain + */ +#define MT_SHAREABILITY_ISH (U(1) << MT_SHAREABILITY_SHIFT) +#define MT_SHAREABILITY_OSH (U(2) << MT_SHAREABILITY_SHIFT) +#define MT_SHAREABILITY_NSH (U(3) << MT_SHAREABILITY_SHIFT) + /* Compound attributes for most common usages */ #define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE) #define MT_RO_DATA (MT_MEMORY | MT_RO | MT_EXECUTE_NEVER) @@ -166,12 +183,13 @@ typedef struct xlat_ctx xlat_ctx_t; * BL image currently executing. */ #define REGISTER_XLAT_CONTEXT(_ctx_name, _mmap_count, _xlat_tables_count, \ - _virt_addr_space_size, _phy_addr_space_size) \ + _virt_addr_space_size, _phy_addr_space_size) \ REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, (_mmap_count), \ (_xlat_tables_count), \ (_virt_addr_space_size), \ (_phy_addr_space_size), \ - EL_REGIME_INVALID, "xlat_table") + EL_REGIME_INVALID, \ + "xlat_table", "base_xlat_table") /* * Same as REGISTER_XLAT_CONTEXT plus the additional parameters: @@ -183,15 +201,21 @@ typedef struct xlat_ctx xlat_ctx_t; * _section_name: * Specify the name of the section where the translation tables have to be * placed by the linker. + * + * _base_table_section_name: + * Specify the name of the section where the base translation tables have to + * be placed by the linker. */ #define REGISTER_XLAT_CONTEXT2(_ctx_name, _mmap_count, _xlat_tables_count, \ _virt_addr_space_size, _phy_addr_space_size, \ - _xlat_regime, _section_name) \ + _xlat_regime, _section_name, _base_table_section_name) \ REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, (_mmap_count), \ (_xlat_tables_count), \ (_virt_addr_space_size), \ (_phy_addr_space_size), \ - (_xlat_regime), (_section_name)) + (_xlat_regime), \ + (_section_name), (_base_table_section_name) \ +) /****************************************************************************** * Generic translation table APIs. @@ -345,6 +369,16 @@ int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va, size_t size, uint32_t attr); int xlat_change_mem_attributes(uintptr_t base_va, size_t size, uint32_t attr); +#if PLAT_RO_XLAT_TABLES +/* + * Change the memory attributes of the memory region encompassing the higher + * level translation tables to secure read-only data. + * + * Return 0 on success, a negative error code on error. + */ +int xlat_make_tables_readonly(void); +#endif + /* * Query the memory attributes of a memory page in a set of translation tables. * diff --git a/include/lib/xlat_tables/xlat_tables_v2_helpers.h b/include/lib/xlat_tables/xlat_tables_v2_helpers.h index b17b71a87..62f853d18 100644 --- a/include/lib/xlat_tables/xlat_tables_v2_helpers.h +++ b/include/lib/xlat_tables/xlat_tables_v2_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,6 +24,7 @@ #include <platform_def.h> #include <lib/cassert.h> +#include <lib/utils_def.h> #include <lib/xlat_tables/xlat_tables_arch.h> #include <lib/xlat_tables/xlat_tables_defs.h> @@ -70,6 +71,9 @@ struct xlat_ctx { */ uint64_t (*tables)[XLAT_TABLE_ENTRIES]; int tables_num; +#if PLAT_RO_XLAT_TABLES + bool readonly_tables; +#endif /* * Keep track of how many regions are mapped in each table. The base * table can't be unmapped so it isn't needed to keep track of it. @@ -122,9 +126,18 @@ struct xlat_ctx { /* do nothing */ #endif /* PLAT_XLAT_TABLES_DYNAMIC */ +#if PLAT_RO_XLAT_TABLES +#define XLAT_CTX_INIT_TABLE_ATTR() \ + .readonly_tables = false, +#else +#define XLAT_CTX_INIT_TABLE_ATTR() + /* do nothing */ +#endif + #define REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, _mmap_count, \ _xlat_tables_count, _virt_addr_space_size, \ - _phy_addr_space_size, _xlat_regime, _section_name)\ + _phy_addr_space_size, _xlat_regime, \ + _table_section, _base_table_section) \ CASSERT(CHECK_PHY_ADDR_SPACE_SIZE(_phy_addr_space_size), \ assert_invalid_physical_addr_space_sizefor_##_ctx_name);\ \ @@ -132,32 +145,34 @@ struct xlat_ctx { \ static uint64_t _ctx_name##_xlat_tables[_xlat_tables_count] \ [XLAT_TABLE_ENTRIES] \ - __aligned(XLAT_TABLE_SIZE) __section(_section_name); \ + __aligned(XLAT_TABLE_SIZE) __section(_table_section); \ \ static uint64_t _ctx_name##_base_xlat_table \ [GET_NUM_BASE_LEVEL_ENTRIES(_virt_addr_space_size)] \ __aligned(GET_NUM_BASE_LEVEL_ENTRIES(_virt_addr_space_size)\ - * sizeof(uint64_t)); \ + * sizeof(uint64_t)) \ + __section(_base_table_section); \ \ XLAT_ALLOC_DYNMAP_STRUCT(_ctx_name, _xlat_tables_count) \ \ static xlat_ctx_t _ctx_name##_xlat_ctx = { \ - .va_max_address = (_virt_addr_space_size) - 1UL, \ .pa_max_address = (_phy_addr_space_size) - 1ULL, \ + .va_max_address = (_virt_addr_space_size) - 1UL, \ .mmap = _ctx_name##_mmap, \ .mmap_num = (_mmap_count), \ - .base_level = GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_size),\ - .base_table = _ctx_name##_base_xlat_table, \ - .base_table_entries = \ - GET_NUM_BASE_LEVEL_ENTRIES(_virt_addr_space_size),\ .tables = _ctx_name##_xlat_tables, \ - .tables_num = _xlat_tables_count, \ + .tables_num = ARRAY_SIZE(_ctx_name##_xlat_tables), \ + XLAT_CTX_INIT_TABLE_ATTR() \ XLAT_REGISTER_DYNMAP_STRUCT(_ctx_name) \ - .xlat_regime = (_xlat_regime), \ + .next_table = 0, \ + .base_table = _ctx_name##_base_xlat_table, \ + .base_table_entries = \ + ARRAY_SIZE(_ctx_name##_base_xlat_table), \ .max_pa = 0U, \ .max_va = 0U, \ - .next_table = 0, \ + .base_level = GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_size),\ .initialized = false, \ + .xlat_regime = (_xlat_regime) \ } #endif /*__ASSEMBLER__*/ diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h index 4637b6785..b79e0d572 100644 --- a/include/plat/arm/board/common/board_css_def.h +++ b/include/plat/arm/board/common/board_css_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -50,13 +50,6 @@ #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) -/* - * Required platform porting definitions common to all ARM CSS-based - * development platforms - */ -#define PLAT_ARM_DRAM2_BASE ULL(0x880000000) -#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) - /* UART related constants */ #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index b419c853e..00746c6da 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,12 +12,19 @@ #include <drivers/arm/gic_common.h> #include <lib/utils_def.h> #include <lib/xlat_tables/xlat_tables_defs.h> +#include <plat/arm/common/smccc_def.h> #include <plat/common/common_def.h> /****************************************************************************** * Definitions common to all ARM standard platforms *****************************************************************************/ +/* + * Root of trust key hash lengths + */ +#define ARM_ROTPK_HEADER_LEN 19 +#define ARM_ROTPK_HASH_LEN 32 + /* Special value used to verify platform parameters from BL2 to BL31 */ #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) @@ -74,7 +81,7 @@ ARM_SCP_TZC_DRAM1_SIZE) #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ - ARM_SCP_TZC_DRAM1_SIZE - 1) + ARM_SCP_TZC_DRAM1_SIZE - 1U) /* * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime @@ -85,7 +92,7 @@ #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ - ARM_EL3_TZC_DRAM1_SIZE - 1) + ARM_EL3_TZC_DRAM1_SIZE - 1U) #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ ARM_DRAM1_SIZE - \ @@ -94,7 +101,7 @@ (ARM_SCP_TZC_DRAM1_SIZE + \ ARM_EL3_TZC_DRAM1_SIZE)) #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ - ARM_AP_TZC_DRAM1_SIZE - 1) + ARM_AP_TZC_DRAM1_SIZE - 1U) /* Define the Access permissions for Secure peripherals to NS_DRAM */ #if ARM_CRYPTOCELL_INTEG @@ -141,17 +148,17 @@ #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ ARM_TZC_DRAM1_SIZE) #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ - ARM_NS_DRAM1_SIZE - 1) + ARM_NS_DRAM1_SIZE - 1U) #define ARM_DRAM1_BASE ULL(0x80000000) #define ARM_DRAM1_SIZE ULL(0x80000000) #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ - ARM_DRAM1_SIZE - 1) + ARM_DRAM1_SIZE - 1U) #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ - ARM_DRAM2_SIZE - 1) + ARM_DRAM2_SIZE - 1U) #define ARM_IRQ_SEC_PHY_TIMER 29 @@ -223,6 +230,14 @@ ARM_EL3_TZC_DRAM1_SIZE, \ MT_MEMORY | MT_RW | MT_SECURE) +#if defined(SPD_spmd) +#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ + PLAT_ARM_TRUSTED_DRAM_BASE, \ + PLAT_ARM_TRUSTED_DRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif + + /* * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides @@ -279,12 +294,19 @@ #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ V2M_FLASH_BLOCK_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) +/* + * Map the region for device tree configuration with read and write permissions + */ +#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ + (ARM_FW_CONFIGS_LIMIT \ + - ARM_BL_RAM_BASE), \ + MT_MEMORY | MT_RW | MT_SECURE) /* * The max number of regions like RO(code), coherent and data required by * different BL stages which need to be mapped in the MMU. */ -#define ARM_BL_REGIONS 5 +#define ARM_BL_REGIONS 6 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ ARM_BL_REGIONS) @@ -331,24 +353,25 @@ #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) /* - * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base + * To enable FW_CONFIG to be loaded by BL1, define the corresponding base * and limit. Leave enough space of BL2 meminfo. */ -#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) -#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U)) +#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) +#define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ + + (PAGE_SIZE / 2U)) /* * Boot parameters passed from BL2 to BL31/BL32 are stored here */ -#define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT -#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE + \ - (PAGE_SIZE / 2U)) +#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) +#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ + + (PAGE_SIZE / 2U)) /* * Define limit of firmware configuration memory: - * ARM_TB_FW_CONFIG + ARM_BL2_MEM_DESC memory + * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory */ -#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) +#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) /******************************************************************************* * BL1 specific defines. @@ -395,13 +418,21 @@ /******************************************************************************* * BL31 specific defines. ******************************************************************************/ -#if ARM_BL31_IN_DRAM +#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION /* * Put BL31 at the bottom of TZC secured DRAM */ #define BL31_BASE ARM_AP_TZC_DRAM1_BASE #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ PLAT_ARM_MAX_BL31_SIZE) +/* + * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. + * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. + */ +#if SEPARATE_NOBITS_REGION +#define BL31_NOBITS_BASE BL2_BASE +#define BL31_NOBITS_LIMIT BL2_LIMIT +#endif /* SEPARATE_NOBITS_REGION */ #elif (RESET_TO_BL31) /* Ensure Position Independent support (PIE) is enabled for this config.*/ # if !ENABLE_PIE @@ -438,7 +469,7 @@ * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding * the page reserved for fw_configs) to BL32 */ -# define BL32_BASE ARM_FW_CONFIG_LIMIT +# define BL32_BASE ARM_FW_CONFIGS_LIMIT # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) # else /* Put BL32 below BL2 in the Trusted SRAM.*/ @@ -463,6 +494,12 @@ # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ ARM_AP_TZC_DRAM1_SIZE) +# elif defined(SPD_spmd) +# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) +# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) +# define BL32_BASE PLAT_ARM_SPMC_BASE +# define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ + PLAT_ARM_SPMC_SIZE) # elif ARM_BL31_IN_DRAM # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ PLAT_ARM_MAX_BL31_SIZE) @@ -476,7 +513,7 @@ # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE # define TSP_PROGBITS_LIMIT BL31_BASE -# define BL32_BASE ARM_FW_CONFIG_LIMIT +# define BL32_BASE ARM_FW_CONFIGS_LIMIT # define BL32_LIMIT BL31_BASE # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE @@ -497,12 +534,12 @@ /* * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no - * SPD and no SPM, as they are the only ones that can be used as BL32. + * SPD and no SPM-MM, as they are the only ones that can be used as BL32. */ #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME # if defined(SPD_none) && !SPM_MM # undef BL32_BASE -# endif /* defined(SPD_none) && !SPM_MM*/ +# endif /* defined(SPD_none) && !SPM_MM */ #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ /******************************************************************************* @@ -531,11 +568,18 @@ #define PLAT_SDEI_NORMAL_PRI 0x70 /* ARM platforms use 3 upper bits of secure interrupt priority */ -#define ARM_PRI_BITS 3 +#define PLAT_PRI_BITS 3 /* SGI used for SDEI signalling */ #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 +#if SDEI_IN_FCONF +/* ARM SDEI dynamic private event max count */ +#define ARM_SDEI_DP_EVENT_MAX_CNT 3 + +/* ARM SDEI dynamic shared event max count */ +#define ARM_SDEI_DS_EVENT_MAX_CNT 3 +#else /* ARM SDEI dynamic private event numbers */ #define ARM_SDEI_DP_EVENT_0 1000 #define ARM_SDEI_DP_EVENT_1 1001 @@ -556,5 +600,6 @@ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) +#endif /* SDEI_IN_FCONF */ #endif /* ARM_DEF_H */ diff --git a/include/plat/arm/common/arm_dyn_cfg_helpers.h b/include/plat/arm/common/arm_dyn_cfg_helpers.h index 3ad6d5468..34bf07c0d 100644 --- a/include/plat/arm/common/arm_dyn_cfg_helpers.h +++ b/include/plat/arm/common/arm_dyn_cfg_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,13 +10,12 @@ #include <stdint.h> /* Function declarations */ -int arm_dyn_get_config_load_info(void *dtb, int node, unsigned int config_id, - uint64_t *config_addr, uint32_t *config_size); int arm_dyn_tb_fw_cfg_init(void *dtb, int *node); -int arm_dyn_get_disable_auth(void *dtb, int node, uint32_t *disable_auth); -int arm_get_dtb_mbedtls_heap_info(void *dtb, void **heap_addr, - size_t *heap_size); int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr, size_t heap_size); +#if MEASURED_BOOT +int arm_set_bl2_hash_info(void *dtb, void *data); +#endif + #endif /* ARM_DYN_CFG_HELPERS_H */ diff --git a/include/plat/arm/common/arm_fconf_getter.h b/include/plat/arm/common/arm_fconf_getter.h new file mode 100644 index 000000000..8fd8c7ada --- /dev/null +++ b/include/plat/arm/common/arm_fconf_getter.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ARM_FCONF_GETTER +#define ARM_FCONF_GETTER + +#include <assert.h> + +#include <lib/fconf/fconf.h> + +/* ARM io policies */ +#define arm__io_policies_getter(id) __extension__ ({ \ + assert((id) < MAX_NUMBER_IDS); \ + &policies[id]; \ +}) + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int (*check)(const uintptr_t spec); +}; + +extern struct plat_io_policy policies[]; +int fconf_populate_arm_io_policies(uintptr_t config); + +#endif /* ARM_FCONF_GETTER */ diff --git a/include/plat/arm/common/arm_fconf_io_storage.h b/include/plat/arm/common/arm_fconf_io_storage.h new file mode 100644 index 000000000..02ee66c35 --- /dev/null +++ b/include/plat/arm/common/arm_fconf_io_storage.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef ARM_FCONF_IO_STORAGE_H +#define ARM_FCONF_IO_STORAGE_H + +#include <stdint.h> + +/* IO devices handle */ +extern uintptr_t memmap_dev_handle; +extern uintptr_t fip_dev_handle; + +/* Function declarations */ +int open_fip(const uintptr_t spec); +int open_memmap(const uintptr_t spec); + +#endif /* ARM_FCONF_IO_STORAGE_H */ diff --git a/include/plat/arm/common/arm_reclaim_init.ld.S b/include/plat/arm/common/arm_reclaim_init.ld.S index b5bf47365..717f65e2b 100644 --- a/include/plat/arm/common/arm_reclaim_init.ld.S +++ b/include/plat/arm/common/arm_reclaim_init.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,24 +12,32 @@ SECTIONS . = . + PLATFORM_STACK_SIZE; . = ALIGN(PAGE_SIZE); __INIT_CODE_START__ = .; - /* - * Exclude PSCI initialization functions to ensure the init section - * does not become larger than the overlaid stack region - */ - *(EXCLUDE_FILE (*psci_setup.o).text.init*) - __INIT_CODE_UNALIGNED__ = .; - . = ALIGN(PAGE_SIZE); + *(*text.init*); __INIT_CODE_END__ = .; + INIT_CODE_END_ALIGNED = ALIGN(PAGE_SIZE); } >RAM #ifdef BL31_PROGBITS_LIMIT ASSERT(__INIT_CODE_END__ <= BL31_PROGBITS_LIMIT, "BL31 init has exceeded progbits limit.") #endif +} - ASSERT(__INIT_CODE_END__ <= __STACKS_END__, - "Init code ends past the end of the stacks") +#define ABS ABSOLUTE -} +#define STACK_SECTION \ + stacks (NOLOAD) : { \ + __STACKS_START__ = .; \ + *(tzfw_normal_stacks) \ + __STACKS_END__ = .; \ + /* Allow room for the init section where necessary. */ \ + OFFSET = ABS(SIZEOF(.init) - (. - __STACKS_START__)); \ + /* Offset sign */ \ + SIGN = ABS(OFFSET) & (1 << 63); \ + /* Offset mask */ \ + MASK = ABS(SIGN >> 63) - 1; \ + . += ABS(OFFSET) & ABS(MASK); \ + . = ALIGN(PAGE_SIZE); \ + } #endif /* ARM_RECLAIM_INIT_LD_S */ diff --git a/include/plat/arm/common/fconf_arm_sp_getter.h b/include/plat/arm/common/fconf_arm_sp_getter.h new file mode 100644 index 000000000..aa628dfd3 --- /dev/null +++ b/include/plat/arm/common/fconf_arm_sp_getter.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_ARM_SP_GETTER_H +#define FCONF_ARM_SP_GETTER_H + +#include <lib/fconf/fconf.h> +#include <tools_share/uuid.h> + +/* arm_sp getter */ +#define arm__sp_getter(prop) arm_sp.prop + +#define ARM_SP_MAX_SIZE U(0xb0000) +#define ARM_SP_OWNER_NAME_LEN U(8) + +struct arm_sp_t { + unsigned int number_of_sp; + union uuid_helper_t uuids[MAX_SP_IDS]; + uintptr_t load_addr[MAX_SP_IDS]; + char owner[MAX_SP_IDS][ARM_SP_OWNER_NAME_LEN]; +}; + +int fconf_populate_arm_sp(uintptr_t config); + +extern struct arm_sp_t arm_sp; + +extern bl_mem_params_node_t sp_mem_params_descs[MAX_SP_IDS]; + +#endif /* FCONF_ARM_SP_GETTER_H */ diff --git a/include/plat/arm/common/fconf_nv_cntr_getter.h b/include/plat/arm/common/fconf_nv_cntr_getter.h new file mode 100644 index 000000000..80a600049 --- /dev/null +++ b/include/plat/arm/common/fconf_nv_cntr_getter.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_NV_CNTR_GETTER_H +#define FCONF_NV_CNTR_GETTER_H + +#include <common/nv_cntr_ids.h> +#include <lib/fconf/fconf.h> + +#define cot__nv_cntr_addr_getter(id) nv_cntr_base_addr[id] + +extern uintptr_t nv_cntr_base_addr[MAX_NV_CTR_IDS]; + +#endif /* FCONF_NV_CNTR_GETTER_H */ diff --git a/include/plat/arm/common/fconf_sdei_getter.h b/include/plat/arm/common/fconf_sdei_getter.h new file mode 100644 index 000000000..e0a97a6fb --- /dev/null +++ b/include/plat/arm/common/fconf_sdei_getter.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_SDEI_GETTER_H +#define FCONF_SDEI_GETTER_H + +#include <lib/fconf/fconf.h> + +#include <platform_def.h> + +#define sdei__dyn_config_getter(id) sdei_dyn_config.id + +struct sdei_dyn_config_t { + uint32_t private_ev_cnt; + int32_t private_ev_nums[PLAT_SDEI_DP_EVENT_MAX_CNT]; + unsigned int private_ev_intrs[PLAT_SDEI_DP_EVENT_MAX_CNT]; + unsigned int private_ev_flags[PLAT_SDEI_DP_EVENT_MAX_CNT]; + uint32_t shared_ev_cnt; + int32_t shared_ev_nums[PLAT_SDEI_DS_EVENT_MAX_CNT]; + unsigned int shared_ev_intrs[PLAT_SDEI_DS_EVENT_MAX_CNT]; + unsigned int shared_ev_flags[PLAT_SDEI_DS_EVENT_MAX_CNT]; +}; + +int fconf_populate_sdei_dyn_config(uintptr_t config); + +extern struct sdei_dyn_config_t sdei_dyn_config; + +#endif /* FCONF_SDEI_GETTER_H */ diff --git a/include/plat/arm/common/fconf_sec_intr_config.h b/include/plat/arm/common/fconf_sec_intr_config.h new file mode 100644 index 000000000..5d6b594a9 --- /dev/null +++ b/include/plat/arm/common/fconf_sec_intr_config.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_SEC_INTR_CONFIG_H +#define FCONF_SEC_INTR_CONFIG_H + +#include <lib/fconf/fconf.h> + +#include <platform_def.h> + +#define hw_config__sec_intr_prop_getter(id) sec_intr_prop.id + +#define SEC_INT_COUNT_MAX U(15) + +struct sec_intr_prop_t { + interrupt_prop_t descriptor[SEC_INT_COUNT_MAX]; + uint32_t count; +}; + +int fconf_populate_sec_intr_config(uintptr_t config); + +extern struct sec_intr_prop_t sec_intr_prop; + +#endif /* FCONF_SEC_INTR_CONFIG_H */ diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 02feec708..95fc18ed8 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -1,11 +1,12 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef PLAT_ARM_H #define PLAT_ARM_H +#include <stdbool.h> #include <stdint.h> #include <drivers/arm/tzc_common.h> @@ -142,11 +143,18 @@ void arm_setup_romlib(void); #define STATE_SW_E_PARAM (-2) #define STATE_SW_E_DENIED (-3) +/* plat_get_rotpk_info() flags */ +#define ARM_ROTPK_REGS_ID 1 +#define ARM_ROTPK_DEVEL_RSA_ID 2 +#define ARM_ROTPK_DEVEL_ECDSA_ID 3 + + /* IO storage utility functions */ -void arm_io_setup(void); +int arm_io_setup(void); /* Security utility functions */ -void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions); +void arm_tzc400_setup(uintptr_t tzc_base, + const arm_tzc_regions_info_t *tzc_regions); struct tzc_dmc500_driver_data; void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, const arm_tzc_regions_info_t *tzc_regions); @@ -182,7 +190,7 @@ void arm_bl1_platform_setup(void); void arm_bl1_plat_arch_setup(void); /* BL2 utility functions */ -void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout); +void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout); void arm_bl2_platform_setup(void); void arm_bl2_plat_arch_setup(void); uint32_t arm_get_spsr_for_bl32_entry(void); @@ -215,17 +223,33 @@ void arm_tsp_early_platform_setup(void); void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, uintptr_t hw_config, void *plat_params_from_bl2); void arm_sp_min_plat_runtime_setup(void); +void arm_sp_min_plat_arch_setup(void); /* FIP TOC validity check */ -int arm_io_is_toc_valid(void); +bool arm_io_is_toc_valid(void); /* Utility functions for Dynamic Config */ -void arm_load_tb_fw_config(void); -void arm_bl2_set_tb_cfg_addr(void *dtb); void arm_bl2_dyn_cfg_init(void); void arm_bl1_set_mbedtls_heap(void); int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); +#if MEASURED_BOOT +/* Measured boot related functions */ +void arm_bl1_set_bl2_hash(const image_desc_t *image_desc); +void arm_bl2_get_hash(void *data); +int arm_set_tos_fw_info(uintptr_t config_base, uintptr_t log_addr, + size_t log_size); +int arm_set_nt_fw_info(uintptr_t config_base, +/* + * Currently OP-TEE does not support reading DTBs from Secure memory + * and this option should be removed when feature is supported. + */ +#ifdef SPD_opteed + uintptr_t log_addr, +#endif + size_t log_size, uintptr_t *ns_log_addr); +#endif /* MEASURED_BOOT */ + /* * Free the memory storing initialization code only used during an images boot * time so it can be reclaimed for runtime data @@ -233,6 +257,11 @@ int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); void arm_free_init_memory(void); /* + * Make the higher level translation tables read-only + */ +void arm_xlat_make_tables_readonly(void); + +/* * Mandatory functions required in ARM standard platforms */ unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); @@ -251,13 +280,21 @@ void plat_arm_interconnect_init(void); void plat_arm_interconnect_enter_coherency(void); void plat_arm_interconnect_exit_coherency(void); void plat_arm_program_trusted_mailbox(uintptr_t address); -int plat_arm_bl1_fwu_needed(void); +bool plat_arm_bl1_fwu_needed(void); __dead2 void plat_arm_error_handler(int err); /* - * Optional function in ARM standard platforms + * Optional functions in ARM standard platforms */ void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); +int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags); +int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, + unsigned int *flags); +int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, + unsigned int *flags); +int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, + unsigned int *flags); #if ARM_PLAT_MT unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); @@ -304,4 +341,7 @@ extern const unsigned int arm_pm_idle_states[]; void plat_arm_secure_wdt_start(void); void plat_arm_secure_wdt_stop(void); +/* Get SOC-ID of ARM platform */ +uint32_t plat_arm_get_soc_id(void); + #endif /* PLAT_ARM_H */ diff --git a/include/plat/arm/common/smccc_def.h b/include/plat/arm/common/smccc_def.h new file mode 100644 index 000000000..6e698e5d2 --- /dev/null +++ b/include/plat/arm/common/smccc_def.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef SMCCC_DEF_H +#define SMCCC_DEF_H + +/* Defines used to retrieve ARM SOC revision */ +#define ARM_SOC_CONTINUATION_CODE U(0x4) +#define ARM_SOC_IDENTIFICATION_CODE U(0x3B) +#define ARM_SOC_CONTINUATION_SHIFT U(24) +#define ARM_SOC_IDENTIFICATION_SHIFT U(16) + +#endif /* SMCCC_DEF_H */ diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index 2adf11d66..d59935266 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,6 +29,10 @@ #define SID_REG_BASE 0x2a4a0000 #define SID_SYSTEM_ID_OFFSET 0x40 #define SID_SYSTEM_CFG_OFFSET 0x70 +#define SID_NODE_ID_OFFSET 0x60 +#define SID_CHIP_ID_MASK 0xFF +#define SID_MULTI_CHIP_MODE_MASK 0x100 +#define SID_MULTI_CHIP_MODE_SHIFT 8 /* The slave_bootsecure controls access to GPU, DMC and CS. */ #define CSS_NIC400_SLAVE_BOOTSECURE 8 @@ -185,9 +189,6 @@ /* Load address of Non-Secure Image for CSS platform ports */ #define PLAT_ARM_NS_IMAGE_BASE U(0xE0000000) -/* TZC related constants */ -#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL - /* * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP * command diff --git a/include/plat/arm/css/common/css_pm.h b/include/plat/arm/css/common/css_pm.h index 93f86162e..e5357f50b 100644 --- a/include/plat/arm/css/common/css_pm.h +++ b/include/plat/arm/css/common/css_pm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,4 +44,15 @@ int css_node_hw_state(u_register_t mpidr, unsigned int power_level); */ extern const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[]; +#define SCMI_DOMAIN_ID_MASK U(0xFFFF) +#define SCMI_CHANNEL_ID_MASK U(0xFFFF) +#define SCMI_CHANNEL_ID_SHIFT U(16) + +#define SET_SCMI_CHANNEL_ID(n) (((n) & SCMI_CHANNEL_ID_MASK) << \ + SCMI_CHANNEL_ID_SHIFT) +#define SET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) +#define GET_SCMI_CHANNEL_ID(n) (((n) >> SCMI_CHANNEL_ID_SHIFT) & \ + SCMI_CHANNEL_ID_MASK) +#define GET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) + #endif /* CSS_PM_H */ diff --git a/include/plat/brcm/common/bcm_console.h b/include/plat/brcm/common/bcm_console.h new file mode 100644 index 000000000..7b653d802 --- /dev/null +++ b/include/plat/brcm/common/bcm_console.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2018-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BCM_CONSOLE_H +#define BCM_CONSOLE_H + +void bcm_console_boot_init(void); +void bcm_console_boot_end(void); +void bcm_console_runtime_init(void); +void bcm_console_runtime_end(void); + +#endif /* BCM_CONSOLE_H */ diff --git a/include/plat/brcm/common/bcm_elog.h b/include/plat/brcm/common/bcm_elog.h new file mode 100644 index 000000000..ea4b1692d --- /dev/null +++ b/include/plat/brcm/common/bcm_elog.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2018 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BCM_ELOG_H +#define BCM_ELOG_H + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + +#if defined(BCM_ELOG) && (defined(IMAGE_BL2) || defined(IMAGE_BL31)) +int bcm_elog_init(void *base, uint32_t size, unsigned int level); +void bcm_elog_exit(void); +int bcm_elog_copy_log(void *dst, uint32_t max_size); +void bcm_elog(const char *fmt, ...); +#else +static inline int bcm_elog_init(void *base, uint32_t size, + unsigned int level) +{ + return 0; +} +static inline void bcm_elog_exit(void) +{ +} +static inline int bcm_elog_copy_log(void *dst, uint32_t max_size) +{ + return 0; +} +static inline void bcm_elog(const char *fmt, ...) +{ +} +#endif /* BCM_ELOG */ + +#endif /* __ASSEMBLER__ */ +#endif /* BCM_ELOG_H */ diff --git a/include/plat/brcm/common/brcm_def.h b/include/plat/brcm/common/brcm_def.h new file mode 100644 index 000000000..c9137bca9 --- /dev/null +++ b/include/plat/brcm/common/brcm_def.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BRCM_DEF_H +#define BRCM_DEF_H + +#include <arch.h> +#include <common/tbbr/tbbr_img_def.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables.h> +#include <plat/common/common_def.h> + +#include <platform_def.h> + +#define PLAT_PHY_ADDR_SPACE_SIZE BIT_64(32) +#define PLAT_VIRT_ADDR_SPACE_SIZE BIT_64(32) + +#define BL11_DAUTH_ID 0x796C51ab +#define BL11_DAUTH_BASE BL11_RW_BASE + +/* We keep a table at the end of ROM for function pointers */ +#define ROM_TABLE_SIZE 32 +#define BL1_ROM_TABLE (BL1_RO_LIMIT - ROM_TABLE_SIZE) + +/* + * The top 16MB of DRAM1 is configured as secure access only using the TZC + * - SCP TZC DRAM: If present, DRAM reserved for SCP use + * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use + */ +#define BRCM_TZC_DRAM1_SIZE ULL(0x01000000) + +#define BRCM_SCP_TZC_DRAM1_BASE (BRCM_DRAM1_BASE + \ + BRCM_DRAM1_SIZE - \ + BRCM_SCP_TZC_DRAM1_SIZE) +#define BRCM_SCP_TZC_DRAM1_SIZE PLAT_BRCM_SCP_TZC_DRAM1_SIZE + +#define BRCM_AP_TZC_DRAM1_BASE (BRCM_DRAM1_BASE + \ + BRCM_DRAM1_SIZE - \ + BRCM_TZC_DRAM1_SIZE) +#define BRCM_AP_TZC_DRAM1_SIZE (BRCM_TZC_DRAM1_SIZE - \ + BRCM_SCP_TZC_DRAM1_SIZE) + +#define BRCM_NS_DRAM1_BASE BRCM_DRAM1_BASE +#define BRCM_NS_DRAM1_SIZE (BRCM_DRAM1_SIZE - \ + BRCM_TZC_DRAM1_SIZE) + +#ifdef BRCM_SHARED_DRAM_BASE +#define BRCM_NS_SHARED_DRAM_BASE BRCM_SHARED_DRAM_BASE +#define BRCM_NS_SHARED_DRAM_SIZE BRCM_SHARED_DRAM_SIZE +#endif + +#define BRCM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + BRCM_SHARED_RAM_BASE, \ + BRCM_SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define BRCM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + BRCM_NS_DRAM1_BASE, \ + BRCM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#ifdef BRCM_SHARED_DRAM_BASE +#define BRCM_MAP_NS_SHARED_DRAM MAP_REGION_FLAT( \ + BRCM_NS_SHARED_DRAM_BASE, \ + BRCM_NS_SHARED_DRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) +#endif + +#ifdef BRCM_EXT_SRAM_BASE +#define BRCM_MAP_EXT_SRAM MAP_REGION_FLAT( \ + BRCM_EXT_SRAM_BASE, \ + BRCM_EXT_SRAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#define BRCM_MAP_NAND_RO MAP_REGION_FLAT(NAND_BASE_ADDR,\ + NAND_SIZE, \ + MT_MEMORY | MT_RO | MT_SECURE) + +#define BRCM_MAP_QSPI_RO MAP_REGION_FLAT(QSPI_BASE_ADDR,\ + QSPI_SIZE, \ + MT_MEMORY | MT_RO | MT_SECURE) + +#define HSLS_REGION MAP_REGION_FLAT(HSLS_BASE_ADDR, \ + HSLS_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define CCN_REGION MAP_REGION_FLAT(PLAT_BRCM_CCN_BASE, \ + CCN_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define GIC500_REGION MAP_REGION_FLAT(GIC500_BASE, \ + GIC500_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#ifdef PERIPH0_BASE +#define PERIPH0_REGION MAP_REGION_FLAT(PERIPH0_BASE, \ + PERIPH0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#ifdef PERIPH1_BASE +#define PERIPH1_REGION MAP_REGION_FLAT(PERIPH1_BASE, \ + PERIPH1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#ifdef PERIPH2_BASE +#define PERIPH2_REGION MAP_REGION_FLAT(PERIPH2_BASE, \ + PERIPH2_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#if BRCM_BL31_IN_DRAM +#if IMAGE_BL2 +#define BRCM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ + BL31_BASE, \ + PLAT_BRCM_MAX_BL31_SIZE,\ + MT_DEVICE | MT_RW | MT_SECURE) +#else +#define BRCM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ + BL31_BASE, \ + PLAT_BRCM_MAX_BL31_SIZE,\ + MT_MEMORY | MT_RW | MT_SECURE) +#endif +#endif + +#if defined(USB_BASE) && defined(DRIVER_USB_ENABLE) +#define USB_REGION MAP_REGION_FLAT( \ + USB_BASE, \ + USB_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#ifdef USE_CRMU_SRAM +#define CRMU_SRAM_REGION MAP_REGION_FLAT( \ + CRMU_SRAM_BASE, \ + CRMU_SRAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif +/* + * The number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#if USE_COHERENT_MEM +#define BRCM_BL_REGIONS 3 +#else +#define BRCM_BL_REGIONS 2 +#endif + +#endif /* BRCM_DEF_H */ diff --git a/include/plat/brcm/common/plat_brcm.h b/include/plat/brcm/common/plat_brcm.h new file mode 100644 index 000000000..66ed2cbaf --- /dev/null +++ b/include/plat/brcm/common/plat_brcm.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_BRCM_H +#define PLAT_BRCM_H + +#include <stdint.h> + +#include <lib/cassert.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables.h> + +#include <platform_def.h> + +struct image_info; + +/* Global variables */ +extern const mmap_region_t plat_brcm_mmap[]; + +uint32_t brcm_get_spsr_for_bl32_entry(void); +uint32_t brcm_get_spsr_for_bl33_entry(void); +const mmap_region_t *plat_brcm_get_mmap(void); +int bcm_bl2_handle_scp_bl2(struct image_info *image_info); +unsigned int plat_brcm_calc_core_pos(u_register_t mpidr); +void plat_brcm_gic_driver_init(void); +void plat_brcm_gic_init(void); +void plat_brcm_gic_cpuif_enable(void); +void plat_brcm_gic_cpuif_disable(void); +void plat_brcm_gic_pcpu_init(void); +void plat_brcm_gic_redistif_on(void); +void plat_brcm_gic_redistif_off(void); +void plat_brcm_interconnect_init(void); +void plat_brcm_interconnect_enter_coherency(void); +void plat_brcm_interconnect_exit_coherency(void); +void plat_brcm_io_setup(void); +void plat_brcm_process_flags(uint16_t plat_toc_flags); + +#endif /* PLAT_BRCM_H */ diff --git a/include/plat/common/plat_trng.h b/include/plat/common/plat_trng.h new file mode 100644 index 000000000..a9f73b679 --- /dev/null +++ b/include/plat/common/plat_trng.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_TRNG_H +#define PLAT_TRNG_H + +#include <tools_share/uuid.h> + +/* TRNG platform functions */ + +extern uuid_t plat_trng_uuid; +void plat_entropy_setup(void); +bool plat_get_entropy(uint64_t *out); + +#endif /* PLAT_TRNG_H */ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index 332cfca8d..1def86ea7 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,12 @@ #include <stdint.h> #include <lib/psci/psci.h> +#if defined(SPD_spmd) + #include <services/spm_core_manifest.h> +#endif +#if TRNG_SUPPORT +#include "plat_trng.h" +#endif /******************************************************************************* * Forward declarations @@ -24,6 +30,7 @@ struct bl_params; struct mmap_region; struct spm_mm_boot_info; struct sp_res_desc; +enum fw_enc_status_t; /******************************************************************************* * plat_get_rotpk_info() flags @@ -34,6 +41,15 @@ struct sp_res_desc; #define ROTPK_NOT_DEPLOYED (1 << 1) /******************************************************************************* + * plat_get_enc_key_info() flags + ******************************************************************************/ +/* + * Flag used to notify caller that information provided in key buffer is an + * identifier rather than an actual key. + */ +#define ENC_KEY_IS_IDENTIFIER (1 << 0) + +/******************************************************************************* * Function declarations ******************************************************************************/ /******************************************************************************* @@ -98,7 +114,7 @@ uintptr_t plat_get_my_stack(void); void plat_report_exception(unsigned int exception_type); int plat_crash_console_init(void); int plat_crash_console_putc(int c); -int plat_crash_console_flush(void); +void plat_crash_console_flush(void); void plat_error_handler(int err) __dead2; void plat_panic_handler(void) __dead2; const char *plat_log_get_prefix(unsigned int log_level); @@ -119,6 +135,7 @@ struct meminfo *bl1_plat_sec_mem_layout(void); /* SDEI platform functions */ #if SDEI_SUPPORT +void plat_sdei_setup(void); int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode); void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr); #endif @@ -161,6 +178,14 @@ __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved); int bl1_plat_handle_pre_image_load(unsigned int image_id); int bl1_plat_handle_post_image_load(unsigned int image_id); +#if MEASURED_BOOT +/* + * Calculates and writes BL2 hash data to the platform's defined location. + * For ARM platforms the data are written to TB_FW_CONFIG DTB. + */ +void bl1_plat_set_bl2_hash(const image_desc_t *image_desc); +#endif + /******************************************************************************* * Mandatory BL2 functions ******************************************************************************/ @@ -176,11 +201,13 @@ struct meminfo *bl2_plat_sec_mem_layout(void); int bl2_plat_handle_pre_image_load(unsigned int image_id); int bl2_plat_handle_post_image_load(unsigned int image_id); - /******************************************************************************* * Optional BL2 functions (may be overridden) ******************************************************************************/ - +#if MEASURED_BOOT +/* Read TCG_DIGEST_SIZE bytes of BL2 hash data */ +void bl2_plat_get_hash(void *data); +#endif /******************************************************************************* * Mandatory BL2 at EL3 functions: Must be implemented if BL2_AT_EL3 image is @@ -190,7 +217,6 @@ void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3); void bl2_el3_plat_arch_setup(void); - /******************************************************************************* * Optional BL2 at EL3 functions (may be overridden) ******************************************************************************/ @@ -262,6 +288,9 @@ int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr); int plat_set_nv_ctr2(void *cookie, const struct auth_img_desc_s *img_desc, unsigned int nv_ctr); int get_mbedtls_heap_helper(void **heap_addr, size_t *heap_size); +int plat_get_enc_key_info(enum fw_enc_status_t fw_enc_status, uint8_t *key, + size_t *key_len, unsigned int *flags, + const uint8_t *img_id, size_t img_id_len); /******************************************************************************* * Secure Partitions functions @@ -272,7 +301,10 @@ const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( int plat_spm_sp_rd_load(struct sp_res_desc *rd, const void *ptr, size_t size); int plat_spm_sp_get_next_address(void **sp_base, size_t *sp_size, void **rd_base, size_t *rd_size); - +#if defined(SPD_spmd) +int plat_spm_core_manifest_load(spmc_manifest_attribute_t *manifest, + const void *pm_addr); +#endif /******************************************************************************* * Mandatory BL image load functions(may be overridden). ******************************************************************************/ @@ -302,4 +334,19 @@ void plat_flush_next_bl_params(void); */ unsigned int platform_core_pos_helper(unsigned long mpidr); +/* + * Optional function to get SOC version + */ +int32_t plat_get_soc_version(void); + +/* + * Optional function to get SOC revision + */ +int32_t plat_get_soc_revision(void); + +/* + * Optional function to check for SMCCC function availability for platform + */ +int32_t plat_is_smccc_feature_available(u_register_t fid); + #endif /* PLATFORM_H */ diff --git a/include/plat/marvell/a3700/common/armada_common.h b/include/plat/marvell/armada/a3k/common/armada_common.h index c6953fb71..c6953fb71 100644 --- a/include/plat/marvell/a3700/common/armada_common.h +++ b/include/plat/marvell/armada/a3k/common/armada_common.h diff --git a/include/plat/marvell/a3700/common/board_marvell_def.h b/include/plat/marvell/armada/a3k/common/board_marvell_def.h index 178259662..bc3e04f00 100644 --- a/include/plat/marvell/a3700/common/board_marvell_def.h +++ b/include/plat/marvell/armada/a3k/common/board_marvell_def.h @@ -71,6 +71,4 @@ #define MAX_IO_DEVICES 3 #define MAX_IO_HANDLES 4 -#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */ - #endif /* BOARD_MARVELL_DEF_H */ diff --git a/include/plat/marvell/a3700/common/marvell_def.h b/include/plat/marvell/armada/a3k/common/marvell_def.h index eb13ba8af..1394c05ab 100644 --- a/include/plat/marvell/a3700/common/marvell_def.h +++ b/include/plat/marvell/armada/a3k/common/marvell_def.h @@ -49,15 +49,17 @@ */ #define MARVELL_LOCAL_STATE_OFF 2 +/* This leaves a gap between end of DRAM and start of ROM block */ +#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */ + /* The first 4KB of Trusted SRAM are used as shared memory */ -#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE -#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE +#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE #define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ /* The remaining Trusted SRAM is used to load the BL images */ #define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \ MARVELL_SHARED_RAM_SIZE) -#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \ +#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \ MARVELL_SHARED_RAM_SIZE) #define MARVELL_DRAM_BASE ULL(0x0) @@ -65,7 +67,7 @@ #define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \ MARVELL_DRAM_SIZE - 1) -#define MARVELL_IRQ_SEC_PHY_TIMER 29 +#define MARVELL_IRQ_SEC_PHY_TIMER 29 #define MARVELL_IRQ_SEC_SGI_0 8 #define MARVELL_IRQ_SEC_SGI_1 9 @@ -86,7 +88,6 @@ MARVELL_DRAM_SIZE, \ MT_MEMORY | MT_RW | MT_NS) - /* * The number of regions like RO(code), coherent and data required by * different BL stages which need to be mapped in the MMU. @@ -173,5 +174,15 @@ #define BL31_LIMIT (MARVELL_BL_RAM_BASE + \ MARVELL_BL_RAM_SIZE) +/***************************************************************************** + * BL32 specific defines. + ***************************************************************************** + */ +#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE +#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE) + +#ifdef SPD_none +#undef BL32_BASE +#endif /* SPD_none */ #endif /* MARVELL_DEF_H */ diff --git a/include/plat/marvell/a3700/common/plat_marvell.h b/include/plat/marvell/armada/a3k/common/plat_marvell.h index ea7cdcd4c..ea7cdcd4c 100644 --- a/include/plat/marvell/a3700/common/plat_marvell.h +++ b/include/plat/marvell/armada/a3k/common/plat_marvell.h diff --git a/include/plat/marvell/a8k/common/armada_common.h b/include/plat/marvell/armada/a8k/common/armada_common.h index 709d009c2..709d009c2 100644 --- a/include/plat/marvell/a8k/common/armada_common.h +++ b/include/plat/marvell/armada/a8k/common/armada_common.h diff --git a/include/plat/marvell/a8k/common/board_marvell_def.h b/include/plat/marvell/armada/a8k/common/board_marvell_def.h index 0da56e7af..7e90f5f19 100644 --- a/include/plat/marvell/a8k/common/board_marvell_def.h +++ b/include/plat/marvell/armada/a8k/common/board_marvell_def.h @@ -71,7 +71,4 @@ #define MAX_IO_DEVICES 3 #define MAX_IO_HANDLES 4 -#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */ - - #endif /* BOARD_MARVELL_DEF_H */ diff --git a/include/plat/marvell/a8k/common/marvell_def.h b/include/plat/marvell/armada/a8k/common/marvell_def.h index 4eda01f1e..1245b88a2 100644 --- a/include/plat/marvell/a8k/common/marvell_def.h +++ b/include/plat/marvell/armada/a8k/common/marvell_def.h @@ -47,15 +47,17 @@ */ #define MARVELL_LOCAL_STATE_OFF 2 +/* This leaves a gap between end of DRAM and start of ROM block */ +#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */ + /* The first 4KB of Trusted SRAM are used as shared memory */ -#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE -#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE +#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE #define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ /* The remaining Trusted SRAM is used to load the BL images */ #define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \ MARVELL_SHARED_RAM_SIZE) -#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \ +#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \ MARVELL_SHARED_RAM_SIZE) /* Non-shared DRAM */ #define MARVELL_DRAM_BASE ULL(0x0) @@ -75,9 +77,40 @@ #define MARVELL_IRQ_SEC_SGI_6 14 #define MARVELL_IRQ_SEC_SGI_7 15 -#define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \ - MARVELL_SHARED_RAM_BASE,\ - MARVELL_SHARED_RAM_SIZE,\ +#ifdef SPD_opteed +/* + * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to + * load/authenticate the trusted os extra image. The first 512KB of + * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading + * for OPTEE is paged image which only include the paging part using + * virtual memory but without "init" data. OPTEE will copy the "init" data + * (from pager image) to the first 512KB of TZC_DRAM, and then copy the + * extra image behind the "init" data. + */ +#define MARVELL_OPTEE_PAGEABLE_LOAD_BASE \ + (PLAT_MARVELL_TRUSTED_RAM_BASE + \ + PLAT_MARVELL_TRUSTED_RAM_SIZE - \ + MARVELL_OPTEE_PAGEABLE_LOAD_SIZE) +#define MARVELL_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 +#define MARVELL_OPTEE_PAGEABLE_LOAD_MEM \ + MAP_REGION_FLAT( \ + MARVELL_OPTEE_PAGEABLE_LOAD_BASE, \ + MARVELL_OPTEE_PAGEABLE_LOAD_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +/* + * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging + * support is enabled). + */ +#define MARVELL_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ + BL32_BASE, \ + BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* SPD_opteed */ + +#define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \ + MARVELL_SHARED_RAM_BASE, \ + MARVELL_SHARED_RAM_SIZE, \ MT_MEMORY | MT_RW | MT_SECURE) #define MARVELL_MAP_DRAM MAP_REGION_FLAT( \ @@ -85,7 +118,6 @@ MARVELL_DRAM_SIZE, \ MT_MEMORY | MT_RW | MT_NS) - /* * The number of regions like RO(code), coherent and data required by * different BL stages which need to be mapped in the MMU. @@ -177,5 +209,14 @@ #define BL31_LIMIT (MARVELL_BL_RAM_BASE + \ MARVELL_BL_RAM_SIZE) +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE +#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE) + +#ifdef SPD_none +#undef BL32_BASE +#endif /* SPD_none */ #endif /* MARVELL_DEF_H */ diff --git a/include/plat/marvell/a8k/common/plat_marvell.h b/include/plat/marvell/armada/a8k/common/plat_marvell.h index 5d805a7f1..5d805a7f1 100644 --- a/include/plat/marvell/a8k/common/plat_marvell.h +++ b/include/plat/marvell/armada/a8k/common/plat_marvell.h diff --git a/include/plat/marvell/a8k/common/plat_pm_trace.h b/include/plat/marvell/armada/a8k/common/plat_pm_trace.h index a9549147d..a9549147d 100644 --- a/include/plat/marvell/a8k/common/plat_pm_trace.h +++ b/include/plat/marvell/armada/a8k/common/plat_pm_trace.h diff --git a/include/plat/marvell/common/aarch64/cci_macros.S b/include/plat/marvell/armada/common/aarch64/cci_macros.S index b0a909bb6..b0a909bb6 100644 --- a/include/plat/marvell/common/aarch64/cci_macros.S +++ b/include/plat/marvell/armada/common/aarch64/cci_macros.S diff --git a/include/plat/marvell/common/aarch64/marvell_macros.S b/include/plat/marvell/armada/common/aarch64/marvell_macros.S index bfe2d4127..bfe2d4127 100644 --- a/include/plat/marvell/common/aarch64/marvell_macros.S +++ b/include/plat/marvell/armada/common/aarch64/marvell_macros.S diff --git a/include/plat/marvell/common/marvell_plat_priv.h b/include/plat/marvell/armada/common/marvell_plat_priv.h index 78b5331e4..78b5331e4 100644 --- a/include/plat/marvell/common/marvell_plat_priv.h +++ b/include/plat/marvell/armada/common/marvell_plat_priv.h diff --git a/include/plat/marvell/common/marvell_pm.h b/include/plat/marvell/armada/common/marvell_pm.h index 8f1660755..8f1660755 100644 --- a/include/plat/marvell/common/marvell_pm.h +++ b/include/plat/marvell/armada/common/marvell_pm.h diff --git a/include/plat/marvell/common/mvebu.h b/include/plat/marvell/armada/common/mvebu.h index 35a0200ad..35a0200ad 100644 --- a/include/plat/marvell/common/mvebu.h +++ b/include/plat/marvell/armada/common/mvebu.h diff --git a/include/services/arm_arch_svc.h b/include/services/arm_arch_svc.h index 23c6f5660..5bbd8bb6c 100644 --- a/include/services/arm_arch_svc.h +++ b/include/services/arm_arch_svc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,9 +9,11 @@ #define SMCCC_VERSION U(0x80000000) #define SMCCC_ARCH_FEATURES U(0x80000001) +#define SMCCC_ARCH_SOC_ID U(0x80000002) #define SMCCC_ARCH_WORKAROUND_1 U(0x80008000) #define SMCCC_ARCH_WORKAROUND_2 U(0x80007FFF) -#define SMCCC_ARCH_NOT_REQUIRED -2 +#define SMCCC_GET_SOC_VERSION U(0) +#define SMCCC_GET_SOC_REVISION U(1) #endif /* ARM_ARCH_SVC_H */ diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h new file mode 100644 index 000000000..0513eab5e --- /dev/null +++ b/include/services/ffa_svc.h @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FFA_SVC_H +#define FFA_SVC_H + +#include <lib/smccc.h> +#include <lib/utils_def.h> +#include <tools_share/uuid.h> + +/* FFA error codes. */ +#define FFA_ERROR_NOT_SUPPORTED -1 +#define FFA_ERROR_INVALID_PARAMETER -2 +#define FFA_ERROR_NO_MEMORY -3 +#define FFA_ERROR_BUSY -4 +#define FFA_ERROR_INTERRUPTED -5 +#define FFA_ERROR_DENIED -6 +#define FFA_ERROR_RETRY -7 + +/* The macros below are used to identify FFA calls from the SMC function ID */ +#define FFA_FNUM_MIN_VALUE U(0x60) +#define FFA_FNUM_MAX_VALUE U(0x7f) +#define is_ffa_fid(fid) __extension__ ({ \ + __typeof__(fid) _fid = (fid); \ + ((GET_SMC_NUM(_fid) >= FFA_FNUM_MIN_VALUE) && \ + (GET_SMC_NUM(_fid) <= FFA_FNUM_MAX_VALUE)); }) + +/* FFA_VERSION helpers */ +#define FFA_VERSION_MAJOR U(1) +#define FFA_VERSION_MAJOR_SHIFT 16 +#define FFA_VERSION_MAJOR_MASK U(0x7FFF) +#define FFA_VERSION_MINOR U(0) +#define FFA_VERSION_MINOR_SHIFT 0 +#define FFA_VERSION_MINOR_MASK U(0xFFFF) +#define FFA_VERSION_BIT31_MASK U(0x1u << 31) + + +#define MAKE_FFA_VERSION(major, minor) \ + ((((major) & FFA_VERSION_MAJOR_MASK) << FFA_VERSION_MAJOR_SHIFT) | \ + (((minor) & FFA_VERSION_MINOR_MASK) << FFA_VERSION_MINOR_SHIFT)) +#define FFA_VERSION_COMPILED MAKE_FFA_VERSION(FFA_VERSION_MAJOR, \ + FFA_VERSION_MINOR) + +/* FFA_MSG_SEND helpers */ +#define FFA_MSG_SEND_ATTRS_BLK_SHIFT U(0) +#define FFA_MSG_SEND_ATTRS_BLK_MASK U(0x1) +#define FFA_MSG_SEND_ATTRS_BLK U(0) +#define FFA_MSG_SEND_ATTRS_BLK_NOT U(1) +#define FFA_MSG_SEND_ATTRS(blk) \ + (((blk) & FFA_MSG_SEND_ATTRS_BLK_MASK) \ + << FFA_MSG_SEND_ATTRS_BLK_SHIFT) + +/* Get FFA fastcall std FID from function number */ +#define FFA_FID(smc_cc, func_num) \ + ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ + ((smc_cc) << FUNCID_CC_SHIFT) | \ + (OEN_STD_START << FUNCID_OEN_SHIFT) | \ + ((func_num) << FUNCID_NUM_SHIFT)) + +/* FFA function numbers */ +#define FFA_FNUM_ERROR U(0x60) +#define FFA_FNUM_SUCCESS U(0x61) +#define FFA_FNUM_INTERRUPT U(0x62) +#define FFA_FNUM_VERSION U(0x63) +#define FFA_FNUM_FEATURES U(0x64) +#define FFA_FNUM_RX_RELEASE U(0x65) +#define FFA_FNUM_RXTX_MAP U(0x66) +#define FFA_FNUM_RXTX_UNMAP U(0x67) +#define FFA_FNUM_PARTITION_INFO_GET U(0x68) +#define FFA_FNUM_ID_GET U(0x69) +#define FFA_FNUM_MSG_POLL U(0x6A) +#define FFA_FNUM_MSG_WAIT U(0x6B) +#define FFA_FNUM_MSG_YIELD U(0x6C) +#define FFA_FNUM_MSG_RUN U(0x6D) +#define FFA_FNUM_MSG_SEND U(0x6E) +#define FFA_FNUM_MSG_SEND_DIRECT_REQ U(0x6F) +#define FFA_FNUM_MSG_SEND_DIRECT_RESP U(0x70) +#define FFA_FNUM_MEM_DONATE U(0x71) +#define FFA_FNUM_MEM_LEND U(0x72) +#define FFA_FNUM_MEM_SHARE U(0x73) +#define FFA_FNUM_MEM_RETRIEVE_REQ U(0x74) +#define FFA_FNUM_MEM_RETRIEVE_RESP U(0x75) +#define FFA_FNUM_MEM_RELINQUISH U(0x76) +#define FFA_FNUM_MEM_RECLAIM U(0x77) + +/* FFA SMC32 FIDs */ +#define FFA_ERROR FFA_FID(SMC_32, FFA_FNUM_ERROR) +#define FFA_SUCCESS_SMC32 FFA_FID(SMC_32, FFA_FNUM_SUCCESS) +#define FFA_INTERRUPT FFA_FID(SMC_32, FFA_FNUM_INTERRUPT) +#define FFA_VERSION FFA_FID(SMC_32, FFA_FNUM_VERSION) +#define FFA_FEATURES FFA_FID(SMC_32, FFA_FNUM_FEATURES) +#define FFA_RX_RELEASE FFA_FID(SMC_32, FFA_FNUM_RX_RELEASE) +#define FFA_RXTX_MAP_SMC32 FFA_FID(SMC_32, FFA_FNUM_RXTX_MAP) +#define FFA_RXTX_UNMAP FFA_FID(SMC_32, FFA_FNUM_RXTX_UNMAP) +#define FFA_PARTITION_INFO_GET FFA_FID(SMC_32, FFA_FNUM_PARTITION_INFO_GET) +#define FFA_ID_GET FFA_FID(SMC_32, FFA_FNUM_ID_GET) +#define FFA_MSG_POLL FFA_FID(SMC_32, FFA_FNUM_MSG_POLL) +#define FFA_MSG_WAIT FFA_FID(SMC_32, FFA_FNUM_MSG_WAIT) +#define FFA_MSG_YIELD FFA_FID(SMC_32, FFA_FNUM_MSG_YIELD) +#define FFA_MSG_RUN FFA_FID(SMC_32, FFA_FNUM_MSG_RUN) +#define FFA_MSG_SEND FFA_FID(SMC_32, FFA_FNUM_MSG_SEND) +#define FFA_MSG_SEND_DIRECT_REQ_SMC32 \ + FFA_FID(SMC_32, FFA_FNUM_MSG_SEND_DIRECT_REQ) +#define FFA_MSG_SEND_DIRECT_RESP_SMC32 \ + FFA_FID(SMC_32, FFA_FNUM_MSG_SEND_DIRECT_RESP) +#define FFA_MEM_DONATE_SMC32 FFA_FID(SMC_32, FFA_FNUM_MEM_DONATE) +#define FFA_MEM_LEND_SMC32 FFA_FID(SMC_32, FFA_FNUM_MEM_LEND) +#define FFA_MEM_SHARE_SMC32 FFA_FID(SMC_32, FFA_FNUM_MEM_SHARE) +#define FFA_MEM_RETRIEVE_REQ_SMC32 \ + FFA_FID(SMC_32, FFA_FNUM_MEM_RETRIEVE_REQ) +#define FFA_MEM_RETRIEVE_RESP FFA_FID(SMC_32, FFA_FNUM_MEM_RETRIEVE_RESP) +#define FFA_MEM_RELINQUISH FFA_FID(SMC_32, FFA_FNUM_MEM_RELINQUISH) +#define FFA_MEM_RECLAIM FFA_FID(SMC_32, FFA_FNUM_MEM_RECLAIM) + +/* FFA SMC64 FIDs */ +#define FFA_SUCCESS_SMC64 FFA_FID(SMC_64, FFA_FNUM_SUCCESS) +#define FFA_RXTX_MAP_SMC64 FFA_FID(SMC_64, FFA_FNUM_RXTX_MAP) +#define FFA_MSG_SEND_DIRECT_REQ_SMC64 \ + FFA_FID(SMC_64, FFA_FNUM_MSG_SEND_DIRECT_REQ) +#define FFA_MSG_SEND_DIRECT_RESP_SMC64 \ + FFA_FID(SMC_64, FFA_FNUM_MSG_SEND_DIRECT_RESP) +#define FFA_MEM_DONATE_SMC64 FFA_FID(SMC_64, FFA_FNUM_MEM_DONATE) +#define FFA_MEM_LEND_SMC64 FFA_FID(SMC_64, FFA_FNUM_MEM_LEND) +#define FFA_MEM_SHARE_SMC64 FFA_FID(SMC_64, FFA_FNUM_MEM_SHARE) +#define FFA_MEM_RETRIEVE_REQ_SMC64 \ + FFA_FID(SMC_64, FFA_FNUM_MEM_RETRIEVE_REQ) + +/* + * Reserve a special value for traffic targeted to the Hypervisor or SPM. + */ +#define FFA_TARGET_INFO_MBZ U(0x0) + +/* + * Reserve a special value for MBZ parameters. + */ +#define FFA_PARAM_MBZ U(0x0) + +/* + * Maximum FF-A endpoint id value + */ +#define FFA_ENDPOINT_ID_MAX U(1 << 16) + +/* + * Mask for source and destination endpoint id in + * a direct message request/response. + */ +#define FFA_DIRECT_MSG_ENDPOINT_ID_MASK U(0xffff) + +/* + * Bit shift for destination endpoint id in a direct message request/response. + */ +#define FFA_DIRECT_MSG_DESTINATION_SHIFT U(0) + +/* + * Bit shift for source endpoint id in a direct message request/response. + */ +#define FFA_DIRECT_MSG_SOURCE_SHIFT U(16) + +/****************************************************************************** + * ffa_endpoint_destination + *****************************************************************************/ +static inline uint16_t ffa_endpoint_destination(unsigned int ep) +{ + return (ep >> FFA_DIRECT_MSG_DESTINATION_SHIFT) & + FFA_DIRECT_MSG_ENDPOINT_ID_MASK; +} + +/****************************************************************************** + * ffa_endpoint_source + *****************************************************************************/ +static inline uint16_t ffa_endpoint_source(unsigned int ep) +{ + return (ep >> FFA_DIRECT_MSG_SOURCE_SHIFT) & + FFA_DIRECT_MSG_ENDPOINT_ID_MASK; +} + +#endif /* FFA_SVC_H */ diff --git a/include/services/sdei.h b/include/services/sdei.h index ae8c7e42f..063ed6f28 100644 --- a/include/services/sdei.h +++ b/include/services/sdei.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include <lib/spinlock.h> #include <lib/utils_def.h> +#include <services/sdei_flags.h> /* Range 0xC4000020 - 0xC400003F reserved for SDE 64bit smc calls */ #define SDEI_VERSION 0xC4000020U @@ -41,50 +42,6 @@ #define SDEI_EV_HANDLED 0U #define SDEI_EV_FAILED 1U -/* Internal: SDEI flag bit positions */ -#define SDEI_MAPF_DYNAMIC_SHIFT_ 1U -#define SDEI_MAPF_BOUND_SHIFT_ 2U -#define SDEI_MAPF_SIGNALABLE_SHIFT_ 3U -#define SDEI_MAPF_PRIVATE_SHIFT_ 4U -#define SDEI_MAPF_CRITICAL_SHIFT_ 5U -#define SDEI_MAPF_EXPLICIT_SHIFT_ 6U - -/* SDEI event 0 */ -#define SDEI_EVENT_0 0 - -/* Placeholder interrupt for dynamic mapping */ -#define SDEI_DYN_IRQ 0U - -/* SDEI flags */ - -/* - * These flags determine whether or not an event can be associated with an - * interrupt. Static events are permanently associated with an interrupt, and - * can't be changed at runtime. Association of dynamic events with interrupts - * can be changed at run time using the SDEI_INTERRUPT_BIND and - * SDEI_INTERRUPT_RELEASE calls. - * - * SDEI_MAPF_DYNAMIC only indicates run time configurability, where as - * SDEI_MAPF_BOUND indicates interrupt association. For example: - * - * - Calling SDEI_INTERRUPT_BIND on a dynamic event will have both - * SDEI_MAPF_DYNAMIC and SDEI_MAPF_BOUND set. - * - * - Statically-bound events will always have SDEI_MAPF_BOUND set, and neither - * SDEI_INTERRUPT_BIND nor SDEI_INTERRUPT_RELEASE can be called on them. - * - * See also the is_map_bound() macro. - */ -#define SDEI_MAPF_DYNAMIC BIT(SDEI_MAPF_DYNAMIC_SHIFT_) -#define SDEI_MAPF_BOUND BIT(SDEI_MAPF_BOUND_SHIFT_) -#define SDEI_MAPF_EXPLICIT BIT(SDEI_MAPF_EXPLICIT_SHIFT_) - -#define SDEI_MAPF_SIGNALABLE BIT(SDEI_MAPF_SIGNALABLE_SHIFT_) -#define SDEI_MAPF_PRIVATE BIT(SDEI_MAPF_PRIVATE_SHIFT_) - -#define SDEI_MAPF_NORMAL 0 -#define SDEI_MAPF_CRITICAL BIT(SDEI_MAPF_CRITICAL_SHIFT_) - /* Indices of private and shared mappings */ #define SDEI_MAP_IDX_PRIV_ 0U #define SDEI_MAP_IDX_SHRD_ 1U diff --git a/include/services/sdei_flags.h b/include/services/sdei_flags.h new file mode 100644 index 000000000..d1308f82a --- /dev/null +++ b/include/services/sdei_flags.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SDEI_FLAGS_H +#define SDEI_FLAGS_H + +#include <lib/utils_def.h> + +/* Internal: SDEI flag bit positions */ +#define SDEI_MAPF_DYNAMIC_SHIFT_ 1U +#define SDEI_MAPF_BOUND_SHIFT_ 2U +#define SDEI_MAPF_SIGNALABLE_SHIFT_ 3U +#define SDEI_MAPF_PRIVATE_SHIFT_ 4U +#define SDEI_MAPF_CRITICAL_SHIFT_ 5U +#define SDEI_MAPF_EXPLICIT_SHIFT_ 6U + +/* SDEI event 0 */ +#define SDEI_EVENT_0 0 + +/* Placeholder interrupt for dynamic mapping */ +#define SDEI_DYN_IRQ 0U + +/* SDEI flags */ + +/* + * These flags determine whether or not an event can be associated with an + * interrupt. Static events are permanently associated with an interrupt, and + * can't be changed at runtime. Association of dynamic events with interrupts + * can be changed at run time using the SDEI_INTERRUPT_BIND and + * SDEI_INTERRUPT_RELEASE calls. + * + * SDEI_MAPF_DYNAMIC only indicates run time configurability, where as + * SDEI_MAPF_BOUND indicates interrupt association. For example: + * + * - Calling SDEI_INTERRUPT_BIND on a dynamic event will have both + * SDEI_MAPF_DYNAMIC and SDEI_MAPF_BOUND set. + * + * - Statically-bound events will always have SDEI_MAPF_BOUND set, and neither + * SDEI_INTERRUPT_BIND nor SDEI_INTERRUPT_RELEASE can be called on them. + * + * See also the is_map_bound() macro. + */ +#define SDEI_MAPF_DYNAMIC BIT(SDEI_MAPF_DYNAMIC_SHIFT_) +#define SDEI_MAPF_BOUND BIT(SDEI_MAPF_BOUND_SHIFT_) +#define SDEI_MAPF_EXPLICIT BIT(SDEI_MAPF_EXPLICIT_SHIFT_) + +#define SDEI_MAPF_SIGNALABLE BIT(SDEI_MAPF_SIGNALABLE_SHIFT_) +#define SDEI_MAPF_PRIVATE BIT(SDEI_MAPF_PRIVATE_SHIFT_) + +#define SDEI_MAPF_NORMAL 0 +#define SDEI_MAPF_CRITICAL BIT(SDEI_MAPF_CRITICAL_SHIFT_) + +#endif /* SDEI_FLAGS_H */ diff --git a/include/services/spm_core_manifest.h b/include/services/spm_core_manifest.h new file mode 100644 index 000000000..453b21c0b --- /dev/null +++ b/include/services/spm_core_manifest.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPM_CORE_MANIFEST_H +#define SPM_CORE_MANIFEST_H + +#include <stdint.h> + +/******************************************************************************* + * Attribute Section + ******************************************************************************/ + +typedef struct spm_core_manifest_sect_attribute { + /* + * FFA version (mandatory). + */ + uint32_t major_version; + uint32_t minor_version; + + /* + * Run-Time Execution state (optional): + * - 0: AArch64 (default) + * - 1: AArch32 + */ + uint32_t exec_state; + + /* + * Address of binary image containing SPM Core (optional). + */ + uint64_t load_address; + + /* + * Offset from the base of the partition's binary image to the entry + * point of the partition (optional). + */ + uint64_t entrypoint; + + /* + * Size of binary image containing SPM Core in bytes (mandatory). + */ + uint32_t binary_size; + + /* + * ID of the SPMC (mandatory) + */ + uint16_t spmc_id; + +} spmc_manifest_attribute_t; + +#endif /* SPM_CORE_MANIFEST_H */ diff --git a/include/services/spmd_svc.h b/include/services/spmd_svc.h new file mode 100644 index 000000000..1e7e6aa87 --- /dev/null +++ b/include/services/spmd_svc.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SPMD_SVC_H +#define SPMD_SVC_H + +#ifndef __ASSEMBLER__ +#include <services/ffa_svc.h> +#include <stdint.h> + +int spmd_setup(void); +uint64_t spmd_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); +#endif /* __ASSEMBLER__ */ + +#endif /* SPMD_SVC_H */ diff --git a/include/services/trng_svc.h b/include/services/trng_svc.h new file mode 100644 index 000000000..ed4d557ca --- /dev/null +++ b/include/services/trng_svc.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TRNG_SVC_H +#define TRNG_SVC_H + +#include <stdbool.h> +#include <stdint.h> + +#include <lib/smccc.h> + +/* SMC function IDs for TRNG queries */ +#define ARM_TRNG_VERSION U(0x84000050) +#define ARM_TRNG_FEATURES U(0x84000051) +#define ARM_TRNG_GET_UUID U(0x84000052) +#define ARM_TRNG_RND32 U(0x84000053) +#define ARM_TRNG_RND64 U(0xc4000053) + +/* TRNG version numbers */ +#define TRNG_VERSION_MAJOR (0x1) +#define TRNG_VERSION_MINOR (0x0) + +/* TRNG Error Numbers */ +#define TRNG_E_SUCCESS (0) +#define TRNG_E_NOT_SUPPORTED (-1) +#define TRNG_E_INVALID_PARAMS (-2) +#define TRNG_E_NO_ENTROPY (-3) +#define TRNG_E_NOT_IMPLEMENTED (-4) + +#if TRNG_SUPPORT +void trng_setup(void); +bool is_trng_fid(uint32_t smc_fid); +#else +static inline void trng_setup(void) +{ +} + +static inline bool is_trng_fid(uint32_t smc_fid) +{ + return false; +} +#endif +uintptr_t trng_smc_handler( + uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags +); + +#endif /* TRNG_SVC_H */ diff --git a/include/tools_share/dualroot_oid.h b/include/tools_share/dualroot_oid.h new file mode 100644 index 000000000..3e88a6d22 --- /dev/null +++ b/include/tools_share/dualroot_oid.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DUALROOT_OID_H +#define DUALROOT_OID_H + +/* Reuse the Object IDs defined by TBBR for certificate extensions. */ +#include "tbbr_oid.h" + +/* + * Platform root-of-trust public key. + * Arbitrary value that does not conflict with any of the TBBR reserved OIDs. + */ +#define PROT_PK_OID "1.3.6.1.4.1.4128.2100.1102" + +#endif /* DUALROOT_OID_H */ diff --git a/include/tools_share/firmware_encrypted.h b/include/tools_share/firmware_encrypted.h new file mode 100644 index 000000000..7ca634f5e --- /dev/null +++ b/include/tools_share/firmware_encrypted.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020, Linaro Limited. All rights reserved. + * Author: Sumit Garg <sumit.garg@linaro.org> + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FIRMWARE_ENCRYPTED_H +#define FIRMWARE_ENCRYPTED_H + +#include <stdint.h> + +/* This is used as a signature to validate the encryption header */ +#define ENC_HEADER_MAGIC 0xAA640001U + +/* Firmware encryption status flag mask */ +#define FW_ENC_STATUS_FLAG_MASK 0x1 + +/* + * SSK: Secret Symmetric Key + * BSSK: Binding Secret Symmetric Key + */ +enum fw_enc_status_t { + FW_ENC_WITH_SSK = 0, + FW_ENC_WITH_BSSK = 1, +}; + +#define ENC_MAX_IV_SIZE 16U +#define ENC_MAX_TAG_SIZE 16U +#define ENC_MAX_KEY_SIZE 32U + +struct fw_enc_hdr { + uint32_t magic; + uint16_t dec_algo; + uint16_t flags; + uint16_t iv_len; + uint16_t tag_len; + uint8_t iv[ENC_MAX_IV_SIZE]; + uint8_t tag[ENC_MAX_TAG_SIZE]; +}; + +#endif /* FIRMWARE_ENCRYPTED_H */ diff --git a/include/tools_share/firmware_image_package.h b/include/tools_share/firmware_image_package.h index 598d5c258..bcde04fd1 100644 --- a/include/tools_share/firmware_image_package.h +++ b/include/tools_share/firmware_image_package.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -64,6 +64,10 @@ {{0xa4, 0x9f, 0x44, 0x11}, {0x5e, 0x63}, {0xe4, 0x11}, 0x87, 0x28, {0x3f, 0x05, 0x72, 0x2a, 0xf3, 0x3d} } #define UUID_NON_TRUSTED_FW_CONTENT_CERT \ {{0x8e, 0xc4, 0xc1, 0xf3}, {0x5d, 0x63}, {0xe4, 0x11}, 0xa7, 0xa9, {0x87, 0xee, 0x40, 0xb2, 0x3f, 0xa7} } +#define UUID_SIP_SECURE_PARTITION_CONTENT_CERT \ + {{0x77, 0x6d, 0xfd, 0x44}, {0x86, 0x97}, {0x4c, 0x3b}, 0x91, 0xeb, {0xc1, 0x3e, 0x02, 0x5a, 0x2a, 0x6f} } +#define UUID_PLAT_SECURE_PARTITION_CONTENT_CERT \ + {{0xdd, 0xcb, 0xbf, 0x4a}, {0xca, 0xd6}, {0x11, 0xea}, 0x87, 0xd0, {0x02, 0x42, 0xac, 0x13, 0x00, 0x03} } /* Dynamic configs */ #define UUID_HW_CONFIG \ {{0x08, 0xb8, 0xf1, 0xd9}, {0xc9, 0xcf}, {0x93, 0x49}, 0xa9, 0x62, {0x6f, 0xbc, 0x6b, 0x72, 0x65, 0xcc} } @@ -75,6 +79,8 @@ {{0x26, 0x25, 0x7c, 0x1a}, {0xdb, 0xc6}, {0x7f, 0x47}, 0x8d, 0x96, {0xc4, 0xc4, 0xb0, 0x24, 0x80, 0x21} } #define UUID_NT_FW_CONFIG \ {{0x28, 0xda, 0x98, 0x15}, {0x93, 0xe8}, {0x7e, 0x44}, 0xac, 0x66, {0x1a, 0xaf, 0x80, 0x15, 0x50, 0xf9} } +#define UUID_FW_CONFIG \ + {{0x58, 0x07, 0xe1, 0x6a}, {0x84, 0x59}, {0x47, 0xbe}, 0x8e, 0xd5, {0x64, 0x8e, 0x8d, 0xdd, 0xab, 0x0e} } typedef struct fip_toc_header { uint32_t name; diff --git a/include/tools_share/sptool.h b/include/tools_share/sptool.h index 67a2cf093..53668e09c 100644 --- a/include/tools_share/sptool.h +++ b/include/tools_share/sptool.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Arm Limited. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,21 +9,17 @@ #include <stdint.h> -/* Header for a secure partition package. There is one per package. */ -struct sp_pkg_header { - uint64_t version; - uint64_t number_of_sp; -}; +/* 4 Byte magic name "SPKG" */ +#define SECURE_PARTITION_MAGIC 0x474B5053 -/* - * Entry descriptor in a secure partition package. Each entry comprises a - * secure partition and its resource description. - */ -struct sp_pkg_entry { - uint64_t sp_offset; - uint64_t sp_size; - uint64_t rd_offset; - uint64_t rd_size; +/* Header for a secure partition package. */ +struct sp_pkg_header { + uint32_t magic; + uint32_t version; + uint32_t pm_offset; + uint32_t pm_size; + uint32_t img_offset; + uint32_t img_size; }; #endif /* SPTOOL_H */ diff --git a/include/tools_share/tbbr_oid.h b/include/tools_share/tbbr_oid.h index 6bccfdd1e..c789f790f 100644 --- a/include/tools_share/tbbr_oid.h +++ b/include/tools_share/tbbr_oid.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,8 @@ #ifndef TBBR_OID_H #define TBBR_OID_H +#define MAX_OID_NAME_LEN 30 + /* * The following is a list of OID values defined and reserved by ARM, which * are used to define the extension fields of the certificate structure, as @@ -43,6 +45,7 @@ #define TRUSTED_BOOT_FW_HASH_OID "1.3.6.1.4.1.4128.2100.201" #define TRUSTED_BOOT_FW_CONFIG_HASH_OID "1.3.6.1.4.1.4128.2100.202" #define HW_CONFIG_HASH_OID "1.3.6.1.4.1.4128.2100.203" +#define FW_CONFIG_HASH_OID "1.3.6.1.4.1.4128.2100.204" /* * Trusted Key Certificate @@ -145,4 +148,16 @@ /* NonTrustedFirmwareConfigHash - NT_FW_CONFIG */ #define NON_TRUSTED_FW_CONFIG_HASH_OID "1.3.6.1.4.1.4128.2100.1202" +/* + * Secure Partitions Content Certificate + */ +#define SP_PKG1_HASH_OID "1.3.6.1.4.1.4128.2100.1301" +#define SP_PKG2_HASH_OID "1.3.6.1.4.1.4128.2100.1302" +#define SP_PKG3_HASH_OID "1.3.6.1.4.1.4128.2100.1303" +#define SP_PKG4_HASH_OID "1.3.6.1.4.1.4128.2100.1304" +#define SP_PKG5_HASH_OID "1.3.6.1.4.1.4128.2100.1305" +#define SP_PKG6_HASH_OID "1.3.6.1.4.1.4128.2100.1306" +#define SP_PKG7_HASH_OID "1.3.6.1.4.1.4128.2100.1307" +#define SP_PKG8_HASH_OID "1.3.6.1.4.1.4128.2100.1308" + #endif /* TBBR_OID_H */ diff --git a/include/tools_share/uuid.h b/include/tools_share/uuid.h index 7d0043206..36be9ed37 100644 --- a/include/tools_share/uuid.h +++ b/include/tools_share/uuid.h @@ -27,7 +27,7 @@ */ /* - * Portions copyright (c) 2014, ARM Limited and Contributors. + * Portions copyright (c) 2014-2020, ARM Limited and Contributors. * All rights reserved. */ @@ -56,6 +56,11 @@ struct uuid { uint8_t node[_UUID_NODE_LEN]; }; +union uuid_helper_t { + struct uuid uuid_struct; + uint32_t word[4]; +}; + /* XXX namespace pollution? */ typedef struct uuid uuid_t; |