diff options
Diffstat (limited to 'drivers/marvell/mochi/apn806_setup.c')
| -rw-r--r-- | drivers/marvell/mochi/apn806_setup.c | 63 |
1 files changed, 37 insertions, 26 deletions
diff --git a/drivers/marvell/mochi/apn806_setup.c b/drivers/marvell/mochi/apn806_setup.c index 1e91c4317..8c3ba9296 100644 --- a/drivers/marvell/mochi/apn806_setup.c +++ b/drivers/marvell/mochi/apn806_setup.c @@ -28,9 +28,6 @@ 0x200) #define CCU_SET_POC_OFFSET 5 -#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \ - 0x90 + 4 * (win)) - #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) #define DVM_48BIT_VA_ENABLE (1 << 21) @@ -44,6 +41,14 @@ SEC_MOCHI_IN_ACC_IHB1_EN | \ SEC_MOCHI_IN_ACC_IHB2_EN | \ SEC_MOCHI_IN_ACC_PIDI_EN) +#define MOCHI_IN_ACC_LEVEL_FORCE_NONSEC (0) +#define MOCHI_IN_ACC_LEVEL_FORCE_SEC (1) +#define MOCHI_IN_ACC_LEVEL_LEAVE_ORIG (2) +#define MOCHI_IN_ACC_LEVEL_MASK_ALL (3) +#define SEC_MOCHI_IN_ACC_IHB0_LEVEL(l) ((l) << 1) +#define SEC_MOCHI_IN_ACC_IHB1_LEVEL(l) ((l) << 4) +#define SEC_MOCHI_IN_ACC_PIDI_LEVEL(l) ((l) << 10) + /* SYSRST_OUTn Config definitions */ #define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4) @@ -70,19 +75,36 @@ enum axi_attr { static void apn_sec_masters_access_en(uint32_t enable) { - uint32_t reg; - /* Open/Close incoming access for all masters. * The access is disabled in trusted boot mode * Could only be done in EL3 */ - reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG); - if (enable) - mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | + if (enable != 0) { + mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */ SEC_IN_ACCESS_ENA_ALL_MASTERS); - else - mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg & - ~SEC_IN_ACCESS_ENA_ALL_MASTERS); +#if LLC_SRAM + /* Do not change access security level + * for PIDI masters + */ + mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, + SEC_MOCHI_IN_ACC_PIDI_LEVEL( + MOCHI_IN_ACC_LEVEL_MASK_ALL), + SEC_MOCHI_IN_ACC_PIDI_LEVEL( + MOCHI_IN_ACC_LEVEL_LEAVE_ORIG)); +#endif + } else { + mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, + SEC_IN_ACCESS_ENA_ALL_MASTERS, + 0x0U /* no set */); +#if LLC_SRAM + /* Return PIDI access level to the default */ + mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, + SEC_MOCHI_IN_ACC_PIDI_LEVEL( + MOCHI_IN_ACC_LEVEL_MASK_ALL), + SEC_MOCHI_IN_ACC_PIDI_LEVEL( + MOCHI_IN_ACC_LEVEL_FORCE_NONSEC)); +#endif + } } static void setup_smmu(void) @@ -95,20 +117,6 @@ static void setup_smmu(void) mmio_write_32(SMMU_sACR, reg); } -static void apn806_errata_wa_init(void) -{ - /* - * ERRATA ID: RES-3033912 - Internal Address Space Init state causes - * a hang upon accesses to [0xf070_0000, 0xf07f_ffff] - * Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to - * split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and - * [0x80_0000, 0xff_ffff] that cause accesses to the - * segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI. - */ - mmio_write_32(CCU_RGF(4), 0x37f9b809); - mmio_write_32(CCU_RGF(5), 0x7ffa0009); -} - static void init_aurora2(void) { uint32_t reg; @@ -131,7 +139,7 @@ static void init_aurora2(void) mmio_write_32(CCU_HTC_CR, reg); #endif /* LLC_ENABLE */ - apn806_errata_wa_init(); + errata_wa_init(); } @@ -250,3 +258,6 @@ int ap_get_count(void) return 1; } +void update_cp110_default_win(int cp_id) +{ +} |