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-rw-r--r--drivers/marvell/mochi/ap807_setup.c85
-rw-r--r--drivers/marvell/mochi/apn806_setup.c63
-rw-r--r--drivers/marvell/mochi/cp110_setup.c10
3 files changed, 118 insertions, 40 deletions
diff --git a/drivers/marvell/mochi/ap807_setup.c b/drivers/marvell/mochi/ap807_setup.c
index 864c9230a..1069f8cef 100644
--- a/drivers/marvell/mochi/ap807_setup.c
+++ b/drivers/marvell/mochi/ap807_setup.c
@@ -11,6 +11,7 @@
#include <drivers/marvell/cache_llc.h>
#include <drivers/marvell/ccu.h>
#include <drivers/marvell/io_win.h>
+#include <drivers/marvell/iob.h>
#include <drivers/marvell/mci.h>
#include <drivers/marvell/mochi/ap_setup.h>
#include <lib/mmio.h>
@@ -31,6 +32,11 @@
#define DSS_CR0 (MVEBU_RFU_BASE + 0x100)
#define DVM_48BIT_VA_ENABLE (1 << 21)
+
+/* SoC RFU / IHBx4 Control */
+#define MCIX4_807_REG_START_ADDR_REG(unit_id) (MVEBU_RFU_BASE + \
+ 0x4258 + (unit_id * 0x4))
+
/* Secure MoChi incoming access */
#define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738)
#define SEC_MOCHI_IN_ACC_IHB0_EN (1)
@@ -41,6 +47,14 @@
SEC_MOCHI_IN_ACC_IHB1_EN | \
SEC_MOCHI_IN_ACC_IHB2_EN | \
SEC_MOCHI_IN_ACC_PIDI_EN)
+#define MOCHI_IN_ACC_LEVEL_FORCE_NONSEC (0)
+#define MOCHI_IN_ACC_LEVEL_FORCE_SEC (1)
+#define MOCHI_IN_ACC_LEVEL_LEAVE_ORIG (2)
+#define MOCHI_IN_ACC_LEVEL_MASK_ALL (3)
+#define SEC_MOCHI_IN_ACC_IHB0_LEVEL(l) ((l) << 1)
+#define SEC_MOCHI_IN_ACC_IHB1_LEVEL(l) ((l) << 4)
+#define SEC_MOCHI_IN_ACC_PIDI_LEVEL(l) ((l) << 10)
+
/* SYSRST_OUTn Config definitions */
#define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4)
@@ -65,19 +79,36 @@ enum axi_attr {
static void ap_sec_masters_access_en(uint32_t enable)
{
- uint32_t reg;
-
/* Open/Close incoming access for all masters.
* The access is disabled in trusted boot mode
* Could only be done in EL3
*/
- reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG);
- if (enable)
- mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg |
- SEC_IN_ACCESS_ENA_ALL_MASTERS);
- else
- mmio_write_32(SEC_MOCHI_IN_ACC_REG,
- reg & ~SEC_IN_ACCESS_ENA_ALL_MASTERS);
+ if (enable != 0) {
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */
+ SEC_IN_ACCESS_ENA_ALL_MASTERS);
+#if LLC_SRAM
+ /* Do not change access security level
+ * for PIDI masters
+ */
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_MASK_ALL),
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_LEAVE_ORIG));
+#endif
+ } else {
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
+ SEC_IN_ACCESS_ENA_ALL_MASTERS,
+ 0x0U /* no set */);
+#if LLC_SRAM
+ /* Return PIDI access level to the default */
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_MASK_ALL),
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_FORCE_NONSEC));
+#endif
+ }
}
static void setup_smmu(void)
@@ -111,6 +142,8 @@ static void init_aurora2(void)
reg |= (0x1 << CCU_SET_POC_OFFSET);
mmio_write_32(CCU_HTC_CR, reg);
#endif /* LLC_ENABLE */
+
+ errata_wa_init();
}
@@ -124,7 +157,7 @@ static void mci_remap_indirect_access_base(void)
uint32_t mci;
for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++)
- mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci),
+ mmio_write_32(MCIX4_807_REG_START_ADDR_REG(mci),
MVEBU_MCI_REG_BASE_REMAP(mci) >>
MCI_REMAP_OFF_SHIFT);
}
@@ -186,6 +219,38 @@ static void misc_soc_configurations(void)
mmio_write_32(MVEBU_SYSRST_OUT_CONFIG_REG, reg);
}
+/*
+ * By default all external CPs start with configuration address space set to
+ * 0xf200_0000. To overcome this issue, go in the loop and initialize the
+ * CP one by one, using temporary window configuration which allows to access
+ * each CP and update its configuration space according to decoding
+ * windows scheme defined for each platform.
+ */
+void update_cp110_default_win(int cp_id)
+{
+ int mci_id = cp_id - 1;
+ uintptr_t cp110_base, cp110_temp_base;
+
+ /* CP110 default configuration address space */
+ cp110_temp_base = MVEBU_AP_IO_BASE(MVEBU_AP0);
+
+ struct addr_map_win iowin_temp_win = {
+ .base_addr = cp110_temp_base,
+ .win_size = MVEBU_CP_OFFSET,
+ };
+
+ iowin_temp_win.target_id = mci_id;
+ iow_temp_win_insert(0, &iowin_temp_win, 1);
+
+ /* Calculate the new CP110 - base address */
+ cp110_base = MVEBU_CP_REGS_BASE(cp_id);
+ /* Go and update the CP110 configuration address space */
+ iob_cfg_space_update(0, cp_id, cp110_temp_base, cp110_base);
+
+ /* Remove the temporary IO-WIN window */
+ iow_temp_win_remove(0, &iowin_temp_win, 1);
+}
+
void ap_init(void)
{
/* Setup Aurora2. */
diff --git a/drivers/marvell/mochi/apn806_setup.c b/drivers/marvell/mochi/apn806_setup.c
index 1e91c4317..8c3ba9296 100644
--- a/drivers/marvell/mochi/apn806_setup.c
+++ b/drivers/marvell/mochi/apn806_setup.c
@@ -28,9 +28,6 @@
0x200)
#define CCU_SET_POC_OFFSET 5
-#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \
- 0x90 + 4 * (win))
-
#define DSS_CR0 (MVEBU_RFU_BASE + 0x100)
#define DVM_48BIT_VA_ENABLE (1 << 21)
@@ -44,6 +41,14 @@
SEC_MOCHI_IN_ACC_IHB1_EN | \
SEC_MOCHI_IN_ACC_IHB2_EN | \
SEC_MOCHI_IN_ACC_PIDI_EN)
+#define MOCHI_IN_ACC_LEVEL_FORCE_NONSEC (0)
+#define MOCHI_IN_ACC_LEVEL_FORCE_SEC (1)
+#define MOCHI_IN_ACC_LEVEL_LEAVE_ORIG (2)
+#define MOCHI_IN_ACC_LEVEL_MASK_ALL (3)
+#define SEC_MOCHI_IN_ACC_IHB0_LEVEL(l) ((l) << 1)
+#define SEC_MOCHI_IN_ACC_IHB1_LEVEL(l) ((l) << 4)
+#define SEC_MOCHI_IN_ACC_PIDI_LEVEL(l) ((l) << 10)
+
/* SYSRST_OUTn Config definitions */
#define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4)
@@ -70,19 +75,36 @@ enum axi_attr {
static void apn_sec_masters_access_en(uint32_t enable)
{
- uint32_t reg;
-
/* Open/Close incoming access for all masters.
* The access is disabled in trusted boot mode
* Could only be done in EL3
*/
- reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG);
- if (enable)
- mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg |
+ if (enable != 0) {
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */
SEC_IN_ACCESS_ENA_ALL_MASTERS);
- else
- mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg &
- ~SEC_IN_ACCESS_ENA_ALL_MASTERS);
+#if LLC_SRAM
+ /* Do not change access security level
+ * for PIDI masters
+ */
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_MASK_ALL),
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_LEAVE_ORIG));
+#endif
+ } else {
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
+ SEC_IN_ACCESS_ENA_ALL_MASTERS,
+ 0x0U /* no set */);
+#if LLC_SRAM
+ /* Return PIDI access level to the default */
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_MASK_ALL),
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_FORCE_NONSEC));
+#endif
+ }
}
static void setup_smmu(void)
@@ -95,20 +117,6 @@ static void setup_smmu(void)
mmio_write_32(SMMU_sACR, reg);
}
-static void apn806_errata_wa_init(void)
-{
- /*
- * ERRATA ID: RES-3033912 - Internal Address Space Init state causes
- * a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
- * Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to
- * split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and
- * [0x80_0000, 0xff_ffff] that cause accesses to the
- * segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI.
- */
- mmio_write_32(CCU_RGF(4), 0x37f9b809);
- mmio_write_32(CCU_RGF(5), 0x7ffa0009);
-}
-
static void init_aurora2(void)
{
uint32_t reg;
@@ -131,7 +139,7 @@ static void init_aurora2(void)
mmio_write_32(CCU_HTC_CR, reg);
#endif /* LLC_ENABLE */
- apn806_errata_wa_init();
+ errata_wa_init();
}
@@ -250,3 +258,6 @@ int ap_get_count(void)
return 1;
}
+void update_cp110_default_win(int cp_id)
+{
+}
diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c
index b4b4e0c82..0fa049764 100644
--- a/drivers/marvell/mochi/cp110_setup.c
+++ b/drivers/marvell/mochi/cp110_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2020 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -130,6 +130,7 @@ enum axi_attr {
#define USB3H_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x10)
#define SATA_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x14)
#define SATA_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x18)
+#define SDIO_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x28)
#define CP_DMA_0_STREAM_ID_REG (0x6B0010)
#define CP_DMA_1_STREAM_ID_REG (0x6D0010)
@@ -144,6 +145,7 @@ uintptr_t stream_id_reg[] = {
CP_DMA_1_STREAM_ID_REG,
SATA_0_STREAM_ID_REG,
SATA_1_STREAM_ID_REG,
+ SDIO_0_STREAM_ID_REG,
0
};
@@ -303,7 +305,7 @@ static void cp110_axi_attr_init(uintptr_t base)
DOMAIN_SYSTEM_SHAREABLE);
}
-static void amb_bridge_init(uintptr_t base)
+void cp110_amb_init(uintptr_t base)
{
uint32_t reg;
@@ -399,7 +401,7 @@ void cp110_init(uintptr_t cp110_base, uint32_t stream_id)
cp110_stream_id_init(cp110_base, stream_id);
/* Open AMB bridge for comphy for CP0 & CP1*/
- amb_bridge_init(cp110_base);
+ cp110_amb_init(cp110_base);
/* Reset RTC if needed */
cp110_rtc_init(cp110_base);
@@ -411,7 +413,7 @@ void cp110_ble_init(uintptr_t cp110_base)
#if PCI_EP_SUPPORT
INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
- amb_bridge_init(cp110_base);
+ cp110_amb_init(cp110_base);
/* Configure PCIe clock */
cp110_pcie_clk_cfg(cp110_base);
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-15 04:17:58 +0000