diff options
Diffstat (limited to 'bl32/tsp/aarch64')
| -rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 49 | ||||
| -rw-r--r-- | bl32/tsp/aarch64/tsp_exceptions.S | 50 |
2 files changed, 49 insertions, 50 deletions
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 9732ff2cd..d183dff9f 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -177,7 +177,7 @@ func tsp_vector_table b tsp_cpu_off_entry b tsp_cpu_resume_entry b tsp_cpu_suspend_entry - b tsp_fiq_entry + b tsp_sel1_intr_entry b tsp_system_off_entry b tsp_system_reset_entry endfunc tsp_vector_table @@ -325,13 +325,13 @@ func tsp_cpu_suspend_entry restore_args_call_smc endfunc tsp_cpu_suspend_entry - /*--------------------------------------------- + /*------------------------------------------------- * This entrypoint is used by the TSPD to pass - * control for handling a pending S-EL1 FIQ. + * control for handling a pending S-EL1 Interrupt. * 'x0' contains a magic number which indicates * this. TSPD expects control to be handed back - * at the end of FIQ processing. This is done - * through an SMC. The handover agreement is: + * at the end of interrupt processing. This is + * done through an SMC. The handover agreement is: * * 1. PSTATE.DAIF are set upon entry. 'x1' has * the ELR_EL3 from the non-secure state. @@ -343,40 +343,41 @@ endfunc tsp_cpu_suspend_entry * 4. TSP can use 'x0-x18' to enable its C * runtime. * 5. TSP returns to TSPD using an SMC with - * 'x0' = TSP_HANDLED_S_EL1_FIQ - * --------------------------------------------- + * 'x0' = TSP_HANDLED_S_EL1_INTR + * ------------------------------------------------ */ -func tsp_fiq_entry +func tsp_sel1_intr_entry #if DEBUG - mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff) - movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff) + mov x2, #(TSP_HANDLE_SEL1_INTR_AND_RETURN & ~0xffff) + movk x2, #(TSP_HANDLE_SEL1_INTR_AND_RETURN & 0xffff) cmp x0, x2 - b.ne tsp_fiq_entry_panic + b.ne tsp_sel1_int_entry_panic #endif - /*--------------------------------------------- + /*------------------------------------------------- * Save any previous context needed to perform * an exception return from S-EL1 e.g. context - * from a previous IRQ. Update statistics and - * handle the FIQ before returning to the TSPD. + * from a previous Non secure Interrupt. + * Update statistics and handle the S-EL1 + * interrupt before returning to the TSPD. * IRQ/FIQs are not enabled since that will * complicate the implementation. Execution * will be transferred back to the normal world * in any case. A non-zero return value from the - * fiq handler is an error. - * --------------------------------------------- + * interrupt handler is an error. + * ------------------------------------------------ */ save_eret_context x2 x3 - bl tsp_update_sync_fiq_stats - bl tsp_fiq_handler - cbnz x0, tsp_fiq_entry_panic + bl tsp_update_sync_sel1_intr_stats + bl tsp_common_int_handler + cbnz x0, tsp_sel1_int_entry_panic restore_eret_context x2 x3 - mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff) - movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff) + mov x0, #(TSP_HANDLED_S_EL1_INTR & ~0xffff) + movk x0, #(TSP_HANDLED_S_EL1_INTR & 0xffff) smc #0 -tsp_fiq_entry_panic: - b tsp_fiq_entry_panic -endfunc tsp_fiq_entry +tsp_sel1_int_entry_panic: + b tsp_sel1_int_entry_panic +endfunc tsp_sel1_intr_entry /*--------------------------------------------- * This entrypoint is used by the TSPD when this diff --git a/bl32/tsp/aarch64/tsp_exceptions.S b/bl32/tsp/aarch64/tsp_exceptions.S index 272d94b7b..d5e089f6e 100644 --- a/bl32/tsp/aarch64/tsp_exceptions.S +++ b/bl32/tsp/aarch64/tsp_exceptions.S @@ -70,6 +70,28 @@ add sp, sp, SCRATCH_REG_SIZE .endm + /* ---------------------------------------------------- + * Common TSP interrupt handling routine + * ---------------------------------------------------- + */ + .macro handle_tsp_interrupt label + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + save_caller_regs_and_lr + bl tsp_common_int_handler + cbz x0, interrupt_exit_\label + + /* + * This interrupt was not targetted to S-EL1 so send it to + * the monitor and wait for execution to resume. + */ + smc #0 +interrupt_exit_\label: + restore_caller_regs_and_lr + eret + .endm + .globl tsp_exceptions /* ----------------------------------------------------- @@ -120,36 +142,12 @@ sync_exception_sp_elx: .align 7 irq_sp_elx: - /* Enable the SError interrupt */ - msr daifclr, #DAIF_ABT_BIT - - save_caller_regs_and_lr - /* We just update some statistics in the handler */ - bl tsp_handle_preemption - /* Hand over control to the normal world to handle the IRQ */ - smc #0 - /* The resume std smc starts from here */ - restore_caller_regs_and_lr - eret + handle_tsp_interrupt irq_sp_elx check_vector_size irq_sp_elx .align 7 fiq_sp_elx: - /* Enable the SError interrupt */ - msr daifclr, #DAIF_ABT_BIT - - save_caller_regs_and_lr - bl tsp_fiq_handler - cbz x0, fiq_sp_elx_done - - /* - * This FIQ was not targetted to S-EL1 so send it to - * the monitor and wait for execution to resume. - */ - smc #0 -fiq_sp_elx_done: - restore_caller_regs_and_lr - eret + handle_tsp_interrupt fiq_sp_elx check_vector_size fiq_sp_elx .align 7 |