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authorKalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>2019-10-02 13:57:23 -0700
committerVarun Wadekar <vwadekar@nvidia.com>2020-08-27 20:12:34 -0700
commit22e4f948bccd53a8b63013ceeed956fc22f9d1ac (patch)
treed7fbf765547f21bdf137b5ff6bc5fa548ec72268 /plat/nvidia/tegra/include
parent50eee85e044a77ad59f4903a5dad91b266770a1d (diff)
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Tegra194: verify firewall settings before resource use
The firewall settings for the hardware resources are present in the Security Configuration Registers. The firewall settings are programmed by other software components and so must be verified for correctness before touching the hardware resources they protect. This patch reads the firewall settings during early boot and asserts if the settings mismatch. Change-Id: I53cc9aeadad32e54e460db0fa2c38e46bcc92066 Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/include')
-rw-r--r--plat/nvidia/tegra/include/t194/tegra_def.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index e39f9cad6..6f44da619 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -294,4 +294,26 @@
#define TEGRA_SID_XUSB_VF2 U(0x5f)
#define TEGRA_SID_XUSB_VF3 U(0x60)
+/*******************************************************************************
+ * SCR addresses and expected settings
+ ******************************************************************************/
+#define SCRATCH_RSV68_SCR U(0x0C398110)
+#define SCRATCH_RSV68_SCR_VAL U(0x38000101)
+#define SCRATCH_RSV71_SCR U(0x0C39811C)
+#define SCRATCH_RSV71_SCR_VAL U(0x38000101)
+#define SCRATCH_RSV72_SCR U(0x0C398120)
+#define SCRATCH_RSV72_SCR_VAL U(0x38000101)
+#define SCRATCH_RSV75_SCR U(0x0C39812C)
+#define SCRATCH_RSV75_SCR_VAL U(0x3A000005)
+#define SCRATCH_RSV81_SCR U(0x0C398144)
+#define SCRATCH_RSV81_SCR_VAL U(0x3A000105)
+#define SCRATCH_RSV97_SCR U(0x0C398184)
+#define SCRATCH_RSV97_SCR_VAL U(0x38000101)
+#define SCRATCH_RSV99_SCR U(0x0C39818C)
+#define SCRATCH_RSV99_SCR_VAL U(0x38000101)
+#define SCRATCH_RSV109_SCR U(0x0C3981B4)
+#define SCRATCH_RSV109_SCR_VAL U(0x38000101)
+#define MISCREG_SCR_SCRTZWELCK U(0x00109000)
+#define MISCREG_SCR_SCRTZWELCK_VAL U(0x30000100)
+
#endif /* TEGRA_DEF_H */