diff options
| author | Antonio Niño Díaz <antonio.ninodiaz@arm.com> | 2019-04-23 12:32:06 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-04-23 12:32:06 +0000 |
| commit | 217a3edd70b6146dc893f6b2d9062f1007b85ea6 (patch) | |
| tree | e8fb2789e63fbd6556a48671768d8a428cf7a178 /include | |
| parent | 932d02961645f09e31028381783713d3f51c57ff (diff) | |
| parent | 632ab3eb26fcef5561cc3d0314886fd9b2793c1f (diff) | |
| download | platform_external_arm-trusted-firmware-217a3edd70b6146dc893f6b2d9062f1007b85ea6.tar.gz platform_external_arm-trusted-firmware-217a3edd70b6146dc893f6b2d9062f1007b85ea6.tar.bz2 platform_external_arm-trusted-firmware-217a3edd70b6146dc893f6b2d9062f1007b85ea6.zip | |
Merge "Neoverse N1: Forces cacheable atomic to near" into integration
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 908993e45..ed5f136dd 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -13,10 +13,9 @@ #define NEOVERSE_N1_MIDR U(0x410fd0c0) /******************************************************************************* - * CPU Extended Control register specific definitions. + * CPU Power Control register specific definitions. ******************************************************************************/ #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) @@ -26,6 +25,18 @@ #define NEOVERSE_N1_AMU_NR_COUNTERS U(5) #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 + +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) + /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0 #define CPUPCR_EL3 S3_6_C15_C8_1 |