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| author | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-04-18 14:34:11 +0100 |
|---|---|---|
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-04-18 14:55:46 +0100 |
| commit | 632ab3eb26fcef5561cc3d0314886fd9b2793c1f (patch) | |
| tree | 805b16e71e3a7155ad8e55b0251c08d4e6cf1b16 /include | |
| parent | 0e985d708e8f429c1fa1f557d3eea90e32de5228 (diff) | |
| download | platform_external_arm-trusted-firmware-632ab3eb26fcef5561cc3d0314886fd9b2793c1f.tar.gz platform_external_arm-trusted-firmware-632ab3eb26fcef5561cc3d0314886fd9b2793c1f.tar.bz2 platform_external_arm-trusted-firmware-632ab3eb26fcef5561cc3d0314886fd9b2793c1f.zip | |
Neoverse N1: Forces cacheable atomic to near
This patch forces all cacheable atomic instructions to be near, which
improves performance in highly contended parallelized use-cases.
Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index 908993e45..ed5f136dd 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -13,10 +13,9 @@ #define NEOVERSE_N1_MIDR U(0x410fd0c0) /******************************************************************************* - * CPU Extended Control register specific definitions. + * CPU Power Control register specific definitions. ******************************************************************************/ #define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */ #define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1) @@ -26,6 +25,18 @@ #define NEOVERSE_N1_AMU_NR_COUNTERS U(5) #define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f) +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1 + +#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) + /* Instruction patching registers */ #define CPUPSELR_EL3 S3_6_C15_C8_0 #define CPUPCR_EL3 S3_6_C15_C8_1 |