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| author | Alexei Fedorov <Alexei.Fedorov@arm.com> | 2020-07-14 08:17:56 +0100 |
|---|---|---|
| committer | Alexei Fedorov <Alexei.Fedorov@arm.com> | 2020-08-10 10:40:53 +0000 |
| commit | f3ccf036ecb1ae16287817833ebb07a26dcc0230 (patch) | |
| tree | 8a734bf075457fe60cae995eb9ee3a2964113498 /include/arch/aarch64/arch.h | |
| parent | 8ae3a91c39d8a22acf845f134cb7a093be0ab918 (diff) | |
| download | platform_external_arm-trusted-firmware-f3ccf036ecb1ae16287817833ebb07a26dcc0230.tar.gz platform_external_arm-trusted-firmware-f3ccf036ecb1ae16287817833ebb07a26dcc0230.tar.bz2 platform_external_arm-trusted-firmware-f3ccf036ecb1ae16287817833ebb07a26dcc0230.zip | |
TF-A AMU extension: fix detection of group 1 counters.
This patch fixes the bug when AMUv1 group1 counters was
always assumed being implemented without checking for its
presence which was causing exception otherwise.
The AMU extension code was also modified as listed below:
- Added detection of AMUv1 for ARMv8.6
- 'PLAT_AMU_GROUP1_NR_COUNTERS' build option is removed and
number of group1 counters 'AMU_GROUP1_NR_COUNTERS' is now
calculated based on 'AMU_GROUP1_COUNTERS_MASK' value
- Added bit fields definitions and access functions for
AMCFGR_EL0/AMCFGR and AMCGCR_EL0/AMCGCR registers
- Unification of amu.c Aarch64 and Aarch32 source files
- Bug fixes and TF-A coding style compliant changes.
Change-Id: I14e407be62c3026ebc674ec7045e240ccb71e1fb
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Diffstat (limited to 'include/arch/aarch64/arch.h')
| -rw-r--r-- | include/arch/aarch64/arch.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 90569c3cf..ebe1a244a 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -898,9 +898,14 @@ #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 +/* AMCFGR_EL0 definitions */ +#define AMCFGR_EL0_NCG_SHIFT U(28) +#define AMCFGR_EL0_NCG_MASK U(0xf) +#define AMCFGR_EL0_N_SHIFT U(0) +#define AMCFGR_EL0_N_MASK U(0xff) + /* AMCGCR_EL0 definitions */ #define AMCGCR_EL0_CG1NC_SHIFT U(8) -#define AMCGCR_EL0_CG1NC_LENGTH U(8) #define AMCGCR_EL0_CG1NC_MASK U(0xff) /* MPAM register definitions */ |