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authorAntonio Niño Díaz <antonio.ninodiaz@arm.com>2019-04-12 10:40:35 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2019-04-12 10:40:35 +0000
commit6cf7b2184b0b547f35aa8464c07b290f5f3922e5 (patch)
tree6b7aaa7ae75490c8bd3f7b2e0165a3c5dbf80c81 /docs
parent72db70ca184c0db10d920923288bc2f1e009e19f (diff)
parentdd4cf2c74566c18adbb04944e6bf7a974276ec16 (diff)
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Merge "Cortex A9:errata 794073 workaround" into integration
Diffstat (limited to 'docs')
-rw-r--r--docs/cpu-specific-build-macros.rst7
1 files changed, 6 insertions, 1 deletions
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index ca3366dc5..222c6a7fd 100644
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -71,6 +71,11 @@ for it to specify which errata workarounds should be enabled or not.
The value of the build flags is 0 by default, that is, disabled. A value of 1
will enable it.
+For Cortex-A9, the following errata build flags are defined :
+
+- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A15
+ CPU. This needs to be enabled for all revisions of the CPU.
+
For Cortex-A15, the following errata build flags are defined :
- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
@@ -260,7 +265,7 @@ architecture that can be enabled by the platform as desired.
--------------
-*Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639