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authorJoel Hutton <Joel.Hutton@arm.com>2019-04-10 12:52:52 +0100
committerJoel Hutton <Joel.Hutton@arm.com>2019-04-12 10:10:32 +0000
commitdd4cf2c74566c18adbb04944e6bf7a974276ec16 (patch)
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parentc554e1ad82b0cf874a76e4685a4da61da14da1fe (diff)
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Cortex A9:errata 794073 workaround
On Cortex A9 an errata can cause the processor to violate the rules for speculative fetches when the MMU is off but branch prediction has not been disabled. The workaround for this is to execute an Invalidate Entire Branch Prediction Array (BPIALL) followed by a DSB. see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf for more details. Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93 Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>
Diffstat (limited to 'docs')
-rw-r--r--docs/cpu-specific-build-macros.rst7
1 files changed, 6 insertions, 1 deletions
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index ca3366dc5..222c6a7fd 100644
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -71,6 +71,11 @@ for it to specify which errata workarounds should be enabled or not.
The value of the build flags is 0 by default, that is, disabled. A value of 1
will enable it.
+For Cortex-A9, the following errata build flags are defined :
+
+- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A15
+ CPU. This needs to be enabled for all revisions of the CPU.
+
For Cortex-A15, the following errata build flags are defined :
- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
@@ -260,7 +265,7 @@ architecture that can be enabled by the platform as desired.
--------------
-*Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639