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author | Antonio Niño Díaz <antonio.ninodiaz@arm.com> | 2019-02-06 10:20:25 +0000 |
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committer | GitHub <noreply@github.com> | 2019-02-06 10:20:25 +0000 |
commit | 30490b15fef50900acac0f23a528651c24759e7d (patch) | |
tree | ff3f53537201d7f7324a1db26982ca7a438472bd /docs | |
parent | d636f67e60d65a0eaa5f7d5588ace3f6f3d66563 (diff) | |
parent | a474d3d700bcf4ff2c19694521e41c960b6cc091 (diff) | |
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Merge pull request #1785 from vwadekar/tf2.0-tegra-downstream-rebase-1.25.19
Tf2.0 tegra downstream rebase 1.25.19
Diffstat (limited to 'docs')
-rw-r--r-- | docs/plat/nvidia-tegra.rst | 40 | ||||
-rw-r--r-- | docs/user-guide.rst | 4 |
2 files changed, 38 insertions, 6 deletions
diff --git a/docs/plat/nvidia-tegra.rst b/docs/plat/nvidia-tegra.rst index 90d2ae132..7ed0f2c82 100644 --- a/docs/plat/nvidia-tegra.rst +++ b/docs/plat/nvidia-tegra.rst @@ -1,6 +1,23 @@ Tegra SoCs - Overview ===================== +- .. rubric:: T186 + :name: t186 + +The NVIDIA® Parker (T186) series system-on-chip (SoC) delivers a heterogeneous +multi-processing (HMP) solution designed to optimize performance and +efficiency. + +T186 has Dual NVIDIA Denver 2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores, +in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores +support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code +including legacy ARMv7 applications. The Denver 2 processors each have 128 KB +Instruction and 64 KB Data Level 1 caches; and have a 2MB shared Level 2 +unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB +Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A +high speed coherency fabric connects these two processor complexes and allows +heterogeneous multi-processing with all six cores if required. + - .. rubric:: T210 :name: t210 @@ -49,11 +66,21 @@ Directory structure Trusted OS dispatcher ===================== -Tegra supports multiple Trusted OS', Trusted Little Kernel (TLK) being one of -them. In order to include the 'tlkd' dispatcher in the image, pass 'SPD=tlkd' -on the command line while preparing a bl31 image. This allows other Trusted OS -vendors to use the upstream code and include their dispatchers in the image -without changing any makefiles. +Tegra supports multiple Trusted OS'. + +- Trusted Little Kernel (TLK): In order to include the 'tlkd' dispatcher in + the image, pass 'SPD=tlkd' on the command line while preparing a bl31 image. +- Trusty: In order to include the 'trusty' dispatcher in the image, pass + 'SPD=trusty' on the command line while preparing a bl31 image. + +This allows other Trusted OS vendors to use the upstream code and include +their dispatchers in the image without changing any makefiles. + +These are the supported Trusted OS' by Tegra platforms. + +Tegra132: TLK +Tegra210: TLK and Trusty +Tegra186: Trusty Preparing the BL31 image to run on Tegra SoCs ============================================= @@ -61,7 +88,8 @@ Preparing the BL31 image to run on Tegra SoCs .. code:: shell CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \ - TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> bl31 + TARGET_SOC=<target-soc e.g. t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd> + bl31 Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>`` to the build command line. diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 320bb1dc7..35d44ca3c 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -575,6 +575,10 @@ Common build options 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it wants the timer registers to be saved and restored. +- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc + for the BL image. It can be either 0 (include) or 1 (remove). The default + value is 0. + - ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that the underlying hardware is not a full PL011 UART but a minimally compliant generic UART, which is a subset of the PL011. The driver will not access |