From 77f1f7a11738cece09d3e399e30f6106dc0f909a Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 31 Jan 2019 09:22:30 -0800 Subject: Introduce build option to override libc This patch introduces a build option 'OVERRIDE_LIBC' that platforms can set to override libc from the BL image. The default value is '0' to keep the library. Change-Id: I10a0b247f6a782eeea4a0359e30a8d79b1e9e4e1 Signed-off-by: Varun Wadekar --- docs/user-guide.rst | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'docs') diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 3828eaff1..63b0f36ea 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -581,6 +581,10 @@ Common build options 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it wants the timer registers to be saved and restored. +- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc + for the BL image. It can be either 0 (include) or 1 (remove). The default + value is 0. + - ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that the underlying hardware is not a full PL011 UART but a minimally compliant generic UART, which is a subset of the PL011. The driver will not access -- cgit v1.2.3 From a474d3d700bcf4ff2c19694521e41c960b6cc091 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 3 Jan 2019 15:09:44 -0800 Subject: docs: add Tegra186 information to nvidia-tegra.rst This patch adds information about the Tegra186 platforms to the docs. Change-Id: I69525c60a0126030dc15505ec7f02ccf8250be6f Signed-off-by: Varun Wadekar --- docs/plat/nvidia-tegra.rst | 40 ++++++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 6 deletions(-) (limited to 'docs') diff --git a/docs/plat/nvidia-tegra.rst b/docs/plat/nvidia-tegra.rst index 90d2ae132..7ed0f2c82 100644 --- a/docs/plat/nvidia-tegra.rst +++ b/docs/plat/nvidia-tegra.rst @@ -1,6 +1,23 @@ Tegra SoCs - Overview ===================== +- .. rubric:: T186 + :name: t186 + +The NVIDIA® Parker (T186) series system-on-chip (SoC) delivers a heterogeneous +multi-processing (HMP) solution designed to optimize performance and +efficiency. + +T186 has Dual NVIDIA Denver 2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores, +in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores +support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code +including legacy ARMv7 applications. The Denver 2 processors each have 128 KB +Instruction and 64 KB Data Level 1 caches; and have a 2MB shared Level 2 +unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB +Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A +high speed coherency fabric connects these two processor complexes and allows +heterogeneous multi-processing with all six cores if required. + - .. rubric:: T210 :name: t210 @@ -49,11 +66,21 @@ Directory structure Trusted OS dispatcher ===================== -Tegra supports multiple Trusted OS', Trusted Little Kernel (TLK) being one of -them. In order to include the 'tlkd' dispatcher in the image, pass 'SPD=tlkd' -on the command line while preparing a bl31 image. This allows other Trusted OS -vendors to use the upstream code and include their dispatchers in the image -without changing any makefiles. +Tegra supports multiple Trusted OS'. + +- Trusted Little Kernel (TLK): In order to include the 'tlkd' dispatcher in + the image, pass 'SPD=tlkd' on the command line while preparing a bl31 image. +- Trusty: In order to include the 'trusty' dispatcher in the image, pass + 'SPD=trusty' on the command line while preparing a bl31 image. + +This allows other Trusted OS vendors to use the upstream code and include +their dispatchers in the image without changing any makefiles. + +These are the supported Trusted OS' by Tegra platforms. + +Tegra132: TLK +Tegra210: TLK and Trusty +Tegra186: Trusty Preparing the BL31 image to run on Tegra SoCs ============================================= @@ -61,7 +88,8 @@ Preparing the BL31 image to run on Tegra SoCs .. code:: shell CROSS_COMPILE=/bin/aarch64-none-elf- make PLAT=tegra \ - TARGET_SOC= SPD= bl31 + TARGET_SOC= SPD= + bl31 Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=`` to the build command line. -- cgit v1.2.3