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| author | Soby Mathew <soby.mathew@arm.com> | 2018-10-03 11:18:30 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-03 11:18:30 +0100 |
| commit | 034a8155f03b5e2168327cac6802755aa5ec24f8 (patch) | |
| tree | c6dc647172dbb792b1bdf4835533bfda9a179c33 /docs | |
| parent | dbc8d9496ead9ecdd7c2a276b542a4fbbbf64027 (diff) | |
| parent | c0740e4fa6e2bb9595270444cbccd23afda22c88 (diff) | |
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Merge pull request #1597 from antonio-nino-diaz-arm/an/optimise
plat/arm: Remove option ARM_BOARD_OPTIMISE_MEM
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/user-guide.rst | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 47a04a315..2632329a2 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -707,14 +707,6 @@ Arm development platform specific build options sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build flag. -- ``ARM_BOARD_OPTIMISE_MEM``: Boolean option to enable or disable optimisation - of the memory reserved for each image. This affects the maximum size of each - BL image as well as the number of allocated memory regions and translation - tables. By default this flag is 0, which means it uses the default - unoptimised values for these macros. Arm development platforms that wish to - optimise memory usage need to set this flag to 1 and must override the - related macros. - - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>`` frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should |