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| author | Soby Mathew <soby.mathew@arm.com> | 2014-05-09 20:49:17 +0100 |
|---|---|---|
| committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-05-23 08:46:21 +0100 |
| commit | 239b04fa31647100c537852b4a3fc8bd47e33aa6 (patch) | |
| tree | 3b2c73b2d39ed0a460375b42f1f3143703646fbc /bl32/tsp/aarch64 | |
| parent | a20a81e5b4a19969673f672523b946647f5d545d (diff) | |
| download | platform_external_arm-trusted-firmware-239b04fa31647100c537852b4a3fc8bd47e33aa6.tar.gz platform_external_arm-trusted-firmware-239b04fa31647100c537852b4a3fc8bd47e33aa6.tar.bz2 platform_external_arm-trusted-firmware-239b04fa31647100c537852b4a3fc8bd47e33aa6.zip | |
Non-Secure Interrupt support during Standard SMC processing in TSP
Implements support for Non Secure Interrupts preempting the
Standard SMC call in EL1. Whenever an IRQ is trapped in the
Secure world we securely handover to the Normal world
to process the interrupt. The normal world then issues
"resume" smc call to resume the previous interrupted SMC call.
Fixes ARM-software/tf-issues#105
Change-Id: I72b760617dee27438754cdfc9fe9bcf4cc024858
Diffstat (limited to 'bl32/tsp/aarch64')
| -rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 19 | ||||
| -rw-r--r-- | bl32/tsp/aarch64/tsp_exceptions.S | 9 |
2 files changed, 26 insertions, 2 deletions
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 54276f2c6..9999c432b 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -39,8 +39,11 @@ .globl tsp_cpu_suspend_entry .globl tsp_cpu_resume_entry .globl tsp_fast_smc_entry + .globl tsp_std_smc_entry .globl tsp_fiq_entry + + /* --------------------------------------------- * Populate the params in x0-x7 from the pointer * to the smc args structure in x0. @@ -317,8 +320,22 @@ tsp_cpu_resume_panic: * --------------------------------------------- */ func tsp_fast_smc_entry - bl tsp_fast_smc_handler + bl tsp_smc_handler restore_args_call_smc tsp_fast_smc_entry_panic: b tsp_fast_smc_entry_panic + /*--------------------------------------------- + * This entrypoint is used by the TSPD to ask + * the TSP to service a std smc request. + * We will enable preemption during execution + * of tsp_smc_handler. + * --------------------------------------------- + */ +func tsp_std_smc_entry + msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT + bl tsp_smc_handler + msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT + restore_args_call_smc +tsp_std_smc_entry_panic: + b tsp_std_smc_entry_panic diff --git a/bl32/tsp/aarch64/tsp_exceptions.S b/bl32/tsp/aarch64/tsp_exceptions.S index ccb4cdddd..f84b5e099 100644 --- a/bl32/tsp/aarch64/tsp_exceptions.S +++ b/bl32/tsp/aarch64/tsp_exceptions.S @@ -120,7 +120,14 @@ sync_exception_sp_elx: .align 7 irq_sp_elx: - b irq_sp_elx + save_caller_regs_and_lr + /* We just update some statistics in the handler */ + bl tsp_irq_received + /* Hand over control to the normal world to handle the IRQ */ + smc #0 + /* The resume std smc starts from here */ + restore_caller_regs_and_lr + eret check_vector_size irq_sp_elx .align 7 |