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Backport from trunk
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Refactor aarch64_address_costs.
gcc/
* config/aarch64/aarch64-protos.h (scale_addr_mode_cost): New.
(cpu_addrcost_table): Use it.
* config/aarch64/aarch64.c (generic_addrcost_table): Initialize it.
(aarch64_address_cost): Rewrite using aarch64_classify_address,
move it.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210493 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Add cost tables for Cortex-A57
gcc/
* config/aarch64/aarch64.c (cortexa57_addrcost_table): New.
(cortexa57_vector_cost): Likewise.
(cortexa57_tunings): Use them.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210494 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Better estimate cost of building a constant
gcc/
* config/aarch64/aarch64.c (aarch64_build_constant): Conditionally
emit instructions, return number of instructions which would
be emitted.
(aarch64_add_constant): Update call to aarch64_build_constant.
(aarch64_output_mi_thunk): Likewise.
(aarch64_rtx_costs): Estimate cost of a CONST_INT, cost
a CONST_DOUBLE.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210496 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Add cost tables for Cortex-A57
gcc/
* config/aarch64/aarch64.c (cortexa57_addrcost_table): New.
(cortexa57_vector_cost): Likewise.
(cortexa57_tunings): Use them.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Wrap aarch64_rtx_costs to dump verbose output
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs_wrapper): New.
(TARGET_RTX_COSTS): Call it.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Better estimate cost of building a constant
gcc/
* config/aarch64/aarch64.c (aarch64_build_constant): Conditionally
emit instructions, return number of instructions which would
be emitted.
(aarch64_add_constant): Update call to aarch64_build_constant.
(aarch64_output_mi_thunk): Likewise.
(aarch64_rtx_costs): Estimate cost of a CONST_INT, cost
a CONST_DOUBLE.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Factor out common MULT cases
gcc/
* config/aarch64/aarch64.c (aarch64_strip_shift_or_extend): Rename
to...
(aarch64_strip_extend): ...this, don't strip shifts, check RTX is
well formed.
(aarch64_rtx_mult_cost): New.
(aarch64_rtx_costs): Use it, refactor as appropriate.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210497 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Set default costs and handle vector modes.
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Set default costs.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210498 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philip Tomsich <philipp.tomsich@theobroma-systems.com>
Improve SET cost.
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costing
for SET RTX.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210499 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philip Tomsich <philipp.tomsich@theobroma-systems.com>
Cost memory accesses using address costs
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Use address
costs when costing loads and stores to memory.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210500 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philip Tomsich <philipp.tomsich@theobroma-systems.com>
Better cost logical operations
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve cost for
logical operations.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210501 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philip Tomsich <philipp.tomsich@theobroma-systems.com>
Improve costs for sign/zero extend operations
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost
ZERO_EXTEND and SIGN_EXTEND better.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210502 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philip Tomsich <philipp.tomsich@theobroma-systems.com>
Improve costs for rotate and shift operations.
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for
rotates and shifts.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210503 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philip Tomsich <philipp.tomsich@theobroma-systems.com>
Improve costs for sign/zero extracts
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for
SIGN/ZERO_EXTRACT.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210504 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Improve costs for div/mod
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for
DIV/MOD.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210505 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cost comparisons, flag setting operators and IF_THEN_ELSE
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost comparison
operators.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210506 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cost more Floating point RTX.
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost FMA,
FLOAT_EXTEND, FLOAT_TRUNCATE, ABS, SMAX, and SMIN.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210507 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cost TRUNCATE
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost TRUNCATE.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210508 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Cost for SYMBOL_REF, HIGH and LO_SUM
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost SYMBOL_REF,
HIGH, LO_SUM.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210509 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Dump a message if we are unable to cost an insn.
gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle the case
where we were unable to cost an RTX.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210510 138bc75d-0d04-0410-961f-82ee72b054a4
2014-08-26 Evandro Menezes <e.menezes@samsung.com>
Fix typos in cost data structure.
* config/arm/aarch64/aarch64.c (generic_addrcost_table): Delete
qi cost; add di cost.
(cortexa57_addrcost_table): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@214503 138bc75d-0d04-0410-961f-82ee72b054a4
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* changes:
PR tree-optimization/48052
PR tree-optimization/52563, tree-optimization/62173
Cherry-pick: PR tree-optimization/65447
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commit 05032b10839cf0498c992c819bf2358e86c22bb0
Author: amker <amker@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Tue Jun 2 10:19:18 2015 +0000
PR tree-optimization/48052
* cfgloop.h (struct control_iv): New.
(struct loop): New field control_ivs.
* tree-ssa-loop-niter.c : Include "stor-layout.h".
(number_of_iterations_lt): Set no_overflow information.
(number_of_iterations_exit): Init control iv in niter struct.
(record_control_iv): New.
(estimate_numbers_of_iterations_loop): Call record_control_iv.
(loop_exits_before_overflow): New. Interface factored out of
scev_probably_wraps_p.
(scev_probably_wraps_p): Factor loop niter related code into
loop_exits_before_overflow.
(free_numbers_of_iterations_estimates_loop): Free control ivs.
* tree-ssa-loop-niter.h (free_loop_control_ivs): New.
gcc/testsuite/ChangeLog
PR tree-optimization/48052
* gcc.dg/tree-ssa/scev-8.c: New.
* gcc.dg/tree-ssa/scev-9.c: New.
* gcc.dg/tree-ssa/scev-10.c: New.
* gcc.dg/vect/pr48052.c: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@224020 138bc75d-0d04-0410-961f-82ee72b054a4
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commit 5fe66b3cf99994fd9c8c68cea43aa1cf42eaa76d
Author: amker <amker@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Tue Jun 2 03:33:35 2015 +0000
PR tree-optimization/52563
PR tree-optimization/62173
* tree-ssa-loop-ivopts.c (struct iv): New field. Reorder fields.
(alloc_iv, set_iv): New parameter.
(determine_biv_step): Delete.
(find_bivs): Inline original determine_biv_step. Pass new
argument to set_iv.
(idx_find_step): Use no_overflow information for conversion.
* tree-scalar-evolution.c (analyze_scalar_evolution_in_loop): Let
resolve_mixers handle folded_casts.
(instantiate_scev_name): Change bool parameter to bool pointer.
(instantiate_scev_poly, instantiate_scev_binary): Ditto.
(instantiate_array_ref, instantiate_scev_not): Ditto.
(instantiate_scev_3, instantiate_scev_2): Ditto.
(instantiate_scev_1, instantiate_scev_r): Ditto.
(instantiate_scev_convert, ): Change parameter. Pass argument
to chrec_convert_aggressive.
(instantiate_scev): Change argument.
(resolve_mixers): New parameter and set it.
(scev_const_prop): New argument.
* tree-scalar-evolution.h (resolve_mixers): New parameter.
* tree-chrec.c (convert_affine_scev): Call chrec_convert instead
of chrec_conert_1.
(chrec_convert): New parameter. Move definition below.
(chrec_convert_aggressive): New parameter and set it. Call
convert_affine_scev.
* tree-chrec.h (chrec_convert): New parameter.
(chrec_convert_aggressive): Ditto.
gcc/testsuite/ChangeLog
PR tree-optimization/52563
PR tree-optimization/62173
* gcc.dg/tree-ssa/scev-3.c: Remove xfail.
* gcc.dg/tree-ssa/scev-4.c: Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@224009 138bc75d-0d04-0410-961f-82ee72b054a4
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commit ad478851f7dd45438a9b33ecd7f30a4e6ab00388
Author: amker <amker@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Wed May 20 05:15:56 2015 +0000
PR tree-optimization/65447
* tree-ssa-loop-ivopts.c (struct iv_use): New fields.
(dump_use, dump_uses): Support to dump sub use.
(record_use): New parameters to support sub use. Remove call to
dump_use.
(record_sub_use, record_group_use): New functions.
(compute_max_addr_offset, split_all_small_groups): New functions.
(group_address_uses, rewrite_use_address): New functions.
(strip_offset): New declaration.
(find_interesting_uses_address): Call record_group_use.
(add_candidate): New assertion.
(infinite_cost_p): Move definition forward.
(add_costs): Check INFTY cost and return immediately.
(get_computation_cost_at): Clear setup cost and dependent bitmap
for sub uses.
(determine_use_iv_cost_address): Compute cost for sub uses.
(rewrite_use_address_1): Rename from old rewrite_use_address.
(free_loop_data): Free sub uses.
(tree_ssa_iv_optimize_loop): Call group_address_uses.
gcc/testsuite
PR tree-optimization/65447
* gcc.dg/tree-ssa/pr65447.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@223433 138bc75d-0d04-0410-961f-82ee72b054a4
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1) Add missing _GCOV_fopen if !__KERNEL__
2) Use _fullpath
Change-Id: Id10cedf85e9a3409c284b77321675f61d37e76c2
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Change-Id: Ic2549845a10d16620d492cbf91a8cfc4cb2e6c61
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This patch ensure that the generated library is called libgnustl_shared.so
instead of libstdc++.so.3 (or some similar number-versioned name).
Change-Id: I63fb5be818115c6d0c7e96b937ba39f225b475cf
(cherry picked from commit 62268d3b73073a061628595f226989bc17c2c622)
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For NDK toolchains, always enable the fix of cortex-a53 erratum 843419.
Use -mno-fix-cortex-a53-843419 to disable this workaround.
Change-Id: I69b8a71113abb172138bf0986697a94e42a5117e
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With this change, -fexceptions and -frtti become default options
when compiling C++ sources.
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BUG=23157315
This reverts commit 659b5199aa009008a003062ff828f44b6bd70b65.
Change-Id: I3564560d3aa57c039c6bc78e0cd630cea3a4bb8b
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2014-11-19 Wilco Dijkstra <wdijkstr@arm.com>
PR target/61915
* config/aarch64/aarch64.c (generic_regmove_cost): Increase FP move cost.
Change-Id: Ifaa0c2d1a72955e42f3882c68d1e52acf5a790e7
Signed-off-by: Junmo Park <junmoz.park@samsung.com>
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2015-03-11 Junmo Park <junmoz.park@samsung.com>
* config/arm/cortex-a57.md (cortex_a57_crypto_simple): Add
crypto_sha256_fast.
(cortex_a57_crypto_complex): Add crypto_sha256_slow.
2015-01-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/cortex-a57.md: Remove duplicate of file accidentally
introduced in revision 219724.
2015-01-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/cortex-a57.md: New.
* config/aarch64/aarch64.md: Include it.
* config/aarch64/aarch64-cores.def (cortex-a57): Tune for it.
* config/aarch64/aarch64-tune.md: Regenerate.
Change-Id: Id089f9d746c222a7ffe224b69e3249f083bbaf3b
Signed-off-by: Junmo Park <junmoz.park@samsung.com>
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BUG=23157315
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[AArch64 costs 5/18] Factor out common MULT cases
gcc/
* config/aarch64/aarch64.c (aarch64_strip_shift_or_extend): Rename
to...
(aarch64_strip_extend): ...this, don't strip shifts, check RTX is
well formed.
(aarch64_rtx_mult_cost): New.
(aarch64_rtx_costs): Use it, refactor as appropriate.
Change-Id: I298e5af1b4006f37d873b113c8d05643e897f6f1
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After call to pointer_map_insert, the caller need to write the value.
This fixes the following regression,
gfortran.dg/array_constructor_6.f90
gfortran.dg/subref_array_pointer_2.f90
Change-Id: Ic7aec96c24d17c527291aefe30e726989ecd9a8f
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support them."
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does not support them.
Change-Id: I0b36e48a9dd0317b65442291752500880b549fb6
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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This change is re-based and modified to work with the older context, as the
context code is changed a lot in GCC trunk.
It is about to insert some barriers on stack-pointer register, so that the
adjust-stack-pointer code does not get scheduled before any code in the
fuction epilogue, which may access some stack space without explicit use of
stack pointer.
Examples are a load from an auto array and some access to an area of alloca.
Anyway, the barriers would make all such alias dependences not violated.
For more details, please refer to GCC bug 63293.
(Personally I think there may be a bit too many barriers generated.)
Change-Id: I61ea54e500b6965feab69a62165d10b6c3a21c20
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Change-Id: I3d6f06fc613c8f8b6a82143dc44b7338483aac5d
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The update is necessary so that LRA is able to detect the conflict
between these regisers and LRA registers.
The change is a back-port from GCC 5.0 r217783, and please refer to
gcc bug 63762 for some details. That bug report has an example, which
is about VFP register file, but the issue applies to ARM integer
register file too, with the same mechanism. The change is mainly about
Thumb, although theoretically not limitted to.
Change-Id: I1fedb410ae5ca39f168dab874f310d7337ab9bcc
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Change-Id: I54a6469aa140e7b24853237ac51398f8e8f4ea95
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BUG=19872411
2014-07-01 Jan Hubicka <hubicka@ucw.cz>
* ipa-utils.h (method_class_type, vtable_pointer_value_to_binfo,
vtable_pointer_value_to_vtable): Constify.
(contains_polymorphic_type_p): Declare.
* ipa-devirt.c (method_class_type, vtable_pointer_value_to_binfo,
vtable_pointer_value_to_vtable): Constify.
(contains_polymorphic_type_p): New predicate.
* ipa-prop.c (ipa_set_jf_known_type): Allow types containing
polymorphic types.
(ipa_set_ancestor_jf): Likewise.
(detect_type_change): Return false in easy cases.
(compute_complex_assign_jump_func): Require type to contain
polymorphic type.
(compute_known_type_jump_func): Likewise.
Change-Id: If4b1a919f00fb1b23c6ebce84141c04120e0e2b6
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Change-Id: Id19630f78848dc3ccfa564e2e925f892b8ea4433
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Fix builtin vector types for 64 bit mode.
Change-Id: I0641798eb23646dcd3fc4d5ee623ad4d8dcbd142
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2014-06-30 Joseph Myers <joseph@codesourcery.com>
* var-tracking.c (add_stores): Return instead of asserting if old
and new values for conditional store are the same.
Change-Id: Ibb5775a3ad90e57bd6882a86a6b4c7a5262c09d0
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("O0")
In google/google-4_9 branch
------------------------------------------------------------------------
r221700 | wmi | 2015-03-26 11:11:16 -0700 (Thu, 26 Mar 2015) | 13 lines
Fix the problem in b/19277289 by avoiding calling walk_aliased_vdefs in O0 function.
gcc/
2015-03-26 Carrot Wei <carrot@google.com>
* ipa-inline-analysis.c: Early return.
gcc/testsuite
2015-03-26 Carrot Wei <carrot@google.com>
* testsuite/gcc.dg/19277289.c: New test.
Change-Id: I6bd7353b65fb918f9651dd737cbe3112fca1fa17
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Change-Id: Id87035be4552719dc05096bb98b49d4bed91a07a
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2014-11-21 Evgeny Stupachenko <evstupac@gmail.com>
PR target/60451
* config/i386/i386.c (expand_vec_perm_even_odd_pack): New.
(expand_vec_perm_even_odd_1): Add new expand for V8HI mode,
replace for V16QI, V16HI and V32QI modes.
(ix86_expand_vec_perm_const_1): Add new expand.
2014-06-11 Evgeny Stupachenko <evstupac@gmail.com>
* tree-vect-data-refs.c (vect_grouped_store_supported): New
check for stores group of length 3.
(vect_permute_store_chain): New permutations for stores group of
length 3.
* tree-vect-stmts.c (vect_model_store_cost): Change cost
of vec_perm_shuffle for the new permutations.
2014-11-28 Evgeny Stupachenko <evstupac@gmail.com>
* tree-vect-data-refs.c (vect_transform_grouped_load): Limit shift
permutations to loads group of size 3.
2014-12-18 Bin Cheng <bin.cheng@arm.com>
PR tree-optimization/62178
* tree-ssa-loop-ivopts.c (cheaper_cost_with_cand): New function.
(iv_ca_replace): New function.
(try_improve_iv_set): New parameter try_replace_p.
Break local optimal fixed-point by calling iv_ca_replace.
(find_optimal_iv_set_1): Pass new argument to try_improve_iv_set.
Change-Id: I5dca8236d3807cedc5e09d7eda65f0ccec9f5cb2
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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2014-11-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/55334
* function.h (struct function): Add last_clique member.
* tree-inline.c (remap_dependence_clique): New function.
(remap_gimple_op_r): Remap dependence cliques in MEM_REFs.
(copy_tree_body_r): Likewise.
(copy_cfg_body): Free dependence map.
(copy_gimple_seq_and_replace_locals): Likewise.
* tree-pretty-print.c (dump_generic_node): Dump
dependence info.
* tree-ssa-alias.c (refs_may_alias_p_1): Use dependence info
to answer alias query.
* tree-ssa-structalias.c: Include tree-phinodes.h, ssa-iterators.h,
tree-pretty-print.h and gimple-walk.h.
(struct variable_info): Add is_restrict_var flag and ruid
member.
(new_var_info): Initialize is_restrict_var.
(make_constraint_from_restrict): Likewise.
(create_variable_info_for): Exclude restricts from global vars
from new handling.
(intra_create_variable_infos): But not those from parameters.
(visit_loadstore): New function.
(maybe_set_dependence_info): Likewise.
(compute_dependence_clique): Likewise.
(compute_may_aliases): Call compute_dependence_clique.
* tree-data-ref.c (dr_analyze_indices): Copy dependence info
to fake MEM_REF.
(dr_may_alias_p): Use recorded dependence info to answer
alias query.
* tree-core.h (struct tree_base): Add clique, base struct in
union.
* tree.h (MR_DEPENDENCE_CLIQUE): New macro.
(MR_DEPENDENCE_BASE): Likewise.
* tree-inline.h (dependence_hasher): New hash-map kind.
(struct copy_body_data): Add dependence_map pointer.
* tree-streamer-in.c (unpack_value_fields): Stream dependence info.
* tree-streamer-out.c (streamer_pack_tree_bitfields): Likewise.
* gcc.dg/tree-ssa/restrict-5.c: New testcase.
Change-Id: I45c8d5eac758aea881a884c131f627cc916cbaf3
Signed-off-by: Andrew Senkevich <andrew.senkevich@intel.com>
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is costly"
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Author: uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Sat Nov 22 19:02:12 2014 +0000
* params.def (PARAM_MAX_COMPLETELY_PEELED_INSNS): Increase to 200.
* config/i386/i386.c (ix86_option_override_internal): Do not increase
PARAM_MAX_COMPLETELY_PEELED_INSNS.
Change-Id: I202e14a29f2436872910301efec863afdd4127e7
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false positive array bound warnings due to an issue in complete unroll. This patch disables this warning so we can switch the ARM build to 4.9. Will re-enable the warning once the issue is fixed.""
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positive array bound warnings due to an issue in complete unroll. This patch disables this warning so we can switch the ARM build to 4.9. Will re-enable the warning once the issue is fixed."
This reverts commit 407a2d5c2c63bdc0c842ffcd57a139ef8a4f33e2, because https://android-review.googlesource.com/#/c/125800 provides fixes to root cause.
Change-Id: I3ceda349beca8e558ccfac5602de942b9be4d31d
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2015-01-28 Ilya Enkovich <ilya.enkovich@intel.com>
PR tree-optimization/64277
* tree-ssa-loop-niter.c (record_nonwrapping_iv): Use base
range info when possible to refine estimation.
2015-01-27 Richard Biener <rguenther@suse.de>
PR tree-optimization/56273
PR tree-optimization/59124
PR tree-optimization/64277
* tree-vrp.c (vrp_finalize): Emit array-bound warnings only
from the first VRP pass.
* g++.dg/warn/Warray-bounds-6.C: New testcase.
* gcc.dg/Warray-bounds-12.c: Likewise.
* gcc.dg/Warray-bounds-13.c: Likewise.
Change-Id: I175b420a4c8150ecf986d477e4c51cbbff276c82
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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Issue happens only when gcc is configured with "--disable-tls".
Backport from trunk for fixing PR42616
2014-12-09 Varvara Rainchik <varvara.rainchik@intel.com>
* config.h.in: Regenerate.
* configure: Regenerate.
* configure.ac: Add GCC_CHECK_EMUTLS.
* libgomp.h: Add check for USE_EMUTLS: this case
is equal to HAVE_TLS.
* team.c: Likewise.
Change-Id: Iee574d1a7888b3bcbd01718669eac34fdd116abb
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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2014-11-21 Evgeny Stupachenko <evstupac@gmail.com>
* config/i386/i386.c (ix86_option_override_internal): Increase
PARAM_MAX_COMPLETELY_PEELED_INSNS.
Change-Id: I529a9297cb8d230a5821d73d5b462d433a8c2108
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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We are seeing some false positive array bound warnings due to an
issue in complete unroll. This patch disables this warning
so we can switch the ARM build to 4.9. Will re-enable the
warning once the issue is fixed.
Change-Id: Ifefe470b9e9146665e9096e5ac6f2f5fec7b9627
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2014-10-13 Evgeny Stupachenko <evstupac@gmail.com>
* config/i386/x86-tune.def (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY):
Remove m_SILVERMONT and m_INTEL from the tune.
Change-Id: I5d793525c43015f10f15cd46505e326039dd4b7e
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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This patch backports svn r216853 from upsteam gcc-4.9 branch that
fixed a bug introduced in fixing cortex a53 erratum 835769.
Change-Id: Iccc6fd04ede28c2deba51be3f8e348ce374c8b4f
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Android does not use the LINK_SPEC in aarch64-linux.h.
Rather, it picks up LINUX_TARGET_LINK_SPEC. Move the SPEC
change in r216979 to LINUX_TRAGET_LINK_SPEC.
Change-Id: I6c39522efcfe067a8a66397954b386f5d104dc02
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Backport 3 patches from upstream gcc that fixed some vectorization
issues: r215585 fixed PR63341
r216508 fixed PR63563
r216770 fixed PR63530
Change-Id: I650bf25ef0843b1ff01911b567fb26e069fd4550
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This is proted from upstream gcc-4_9 branch: svn r216979.
Change-Id: I1cee530fb4f50843a9832aa678c1630f51564fa6
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r216292 from google/gcc-4_9 branch: Move update_ssa after vpt transformation. BUG=17997360"
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Backport r216292 from google/gcc-4_9 branch: Move update_ssa
after vpt transformation.
BUG=17997360
Change-Id: Iae9e15be6ff5655b1514e349c55f05647388df36
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google/gcc-4_9 branches which makes ifunc support available for BIONIC (still controlled by configure)."
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