diff options
Diffstat (limited to 'gcc-4.9/gcc/config/stormy16')
| -rw-r--r-- | gcc-4.9/gcc/config/stormy16/constraints.md | 119 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/stormy16/predicates.md | 178 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/stormy16/stormy-abi | 174 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/stormy16/stormy16-protos.h | 69 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/stormy16/stormy16.c | 2703 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/stormy16/stormy16.h | 504 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/stormy16/stormy16.md | 1250 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/stormy16/stormy16.opt | 24 |
8 files changed, 5021 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/config/stormy16/constraints.md b/gcc-4.9/gcc/config/stormy16/constraints.md new file mode 100644 index 000000000..6eafe53d2 --- /dev/null +++ b/gcc-4.9/gcc/config/stormy16/constraints.md @@ -0,0 +1,119 @@ +;; Constraint definitions for XSTORMY16. +;; Copyright (C) 2011-2014 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +;; Register constraints. +(define_register_constraint "a" "R0_REGS" + "@internal") + +(define_register_constraint "b" "R1_REGS" + "@internal") + +(define_register_constraint "c" "R2_REGS" + "@internal") + +(define_register_constraint "d" "R8_REGS" + "@internal") + +(define_register_constraint "e" "EIGHT_REGS" + "@internal") + +(define_register_constraint "t" "TWO_REGS" + "@internal") + +(define_register_constraint "z" "ICALL_REGS" + "@internal") + +;; Integer constraints. +(define_constraint "I" + "An integer between 0 and 3." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, 0, 3)"))) + +(define_constraint "J" + "A power of two." + (and (match_code "const_int") + (match_test "exact_log2 (ival) != -1"))) + +(define_constraint "K" + "A power of two when inverted." + (and (match_code "const_int") + (match_test "exact_log2 (~ival) != -1"))) + +(define_constraint "L" + "An 8-bit unsigned integer." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, 0, 255)"))) + +(define_constraint "M" + "An integer between -255 and 0." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -255, 0)"))) + +(define_constraint "N" + "An integer between -3 and 0." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -3, 0)"))) + +(define_constraint "O" + "An integer between 1 and 4." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, 1, 4)"))) + +(define_constraint "P" + "An integer between -4 and -1." + (and (match_code "const_int") + (match_test "IN_RANGE (ival, -4, -1)"))) + +;; Extra constraints. +(define_constraint "Q" + "A register push operation." + (and (match_code "mem") + (match_code "post_inc" "0") + (match_test "XEXP (XEXP (op, 0), 0) == stack_pointer_rtx"))) + +(define_constraint "R" + "A register pop operation." + (and (match_code "mem") + (match_code "pre_dec" "0") + (match_test "XEXP (XEXP (op, 0), 0) == stack_pointer_rtx"))) + +(define_constraint "S" + "An immediate memory address." + (and (match_code "mem") + (match_code "const_int" "0") + (match_test "xstormy16_legitimate_address_p (VOIDmode, XEXP (op, 0), false)"))) + +(define_constraint "T" + "@internal" + ;; For Rx; not implemented yet. + (match_test "0")) + +(define_constraint "U" + "An integer not between 2 and 15." + (and (match_code "const_int") + (match_test "!IN_RANGE (ival, 2, 15)"))) + +(define_constraint "W" + "@internal" + (match_operand 0 "xstormy16_below100_operand")) + +(define_constraint "Z" + "Zero." + (and (match_code "const_int") + (match_test "ival == 0")))
\ No newline at end of file diff --git a/gcc-4.9/gcc/config/stormy16/predicates.md b/gcc-4.9/gcc/config/stormy16/predicates.md new file mode 100644 index 000000000..fc4797390 --- /dev/null +++ b/gcc-4.9/gcc/config/stormy16/predicates.md @@ -0,0 +1,178 @@ +;; Predicate definitions for XSTORMY16. +;; Copyright (C) 2005-2014 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +;; Return 1 if OP is a shift operator. + +(define_predicate "shift_operator" + (match_code "ashift,ashiftrt,lshiftrt") +{ + enum rtx_code code = GET_CODE (op); + + return (code == ASHIFT + || code == ASHIFTRT + || code == LSHIFTRT); +}) + +;; Return 1 if this is an EQ or NE operator. + +(define_predicate "equality_operator" + (match_code "eq,ne") +{ + return ((mode == VOIDmode || GET_MODE (op) == mode) + && (GET_CODE (op) == EQ || GET_CODE (op) == NE)); +}) + +;; Return 1 if this is a comparison operator but not an EQ or NE +;; operator. + +(define_predicate "inequality_operator" + (match_code "ge,gt,le,lt,geu,gtu,leu,ltu") +{ + return comparison_operator (op, mode) && ! equality_operator (op, mode); +}) + +;; Return 1 if this is a LT, GE, LTU, or GEU operator. + +(define_predicate "xstormy16_ineqsi_operator" + (match_code "lt,ge,ltu,geu") +{ + enum rtx_code code = GET_CODE (op); + + return ((mode == VOIDmode || GET_MODE (op) == mode) + && (code == LT || code == GE || code == LTU || code == GEU)); +}) + +;; Predicate for MEMs that can use special 8-bit addressing. + +(define_predicate "xstormy16_below100_operand" + (match_code "mem") +{ + if (GET_MODE (op) != mode) + return 0; + if (GET_CODE (op) == MEM) + op = XEXP (op, 0); + else if (GET_CODE (op) == SUBREG + && GET_CODE (XEXP (op, 0)) == MEM + && !MEM_VOLATILE_P (XEXP (op, 0))) + op = XEXP (XEXP (op, 0), 0); + else + return 0; + if (GET_CODE (op) == CONST_INT) + { + HOST_WIDE_INT i = INTVAL (op); + return (i >= 0x7f00 && i < 0x7fff); + } + return xstormy16_below100_symbol (op, HImode); +}) + +;; TODO: Add a comment here. + +(define_predicate "xstormy16_below100_or_register" + (match_code "mem,reg,subreg") +{ + return (xstormy16_below100_operand (op, mode) + || register_operand (op, mode)); +}) + +;; TODO: Add a comment here. + +(define_predicate "xstormy16_splittable_below100_or_register" + (match_code "mem,reg,subreg") +{ + if (GET_CODE (op) == MEM && MEM_VOLATILE_P (op)) + return 0; + return (xstormy16_below100_operand (op, mode) + || register_operand (op, mode)); +}) + +;; Predicate for constants with exactly one bit not set. + +(define_predicate "xstormy16_onebit_clr_operand" + (match_code "const_int") +{ + HOST_WIDE_INT i; + if (GET_CODE (op) != CONST_INT) + return 0; + i = ~ INTVAL (op); + if (mode == QImode) + i &= 0xff; + if (mode == HImode) + i &= 0xffff; + return exact_log2 (i) != -1; +}) + +;; Predicate for constants with exactly one bit set. + +(define_predicate "xstormy16_onebit_set_operand" + (match_code "const_int") +{ + HOST_WIDE_INT i; + if (GET_CODE (op) != CONST_INT) + return 0; + i = INTVAL (op); + if (mode == QImode) + i &= 0xff; + if (mode == HImode) + i &= 0xffff; + return exact_log2 (i) != -1; +}) + +;; TODO: Add a comment here. + +(define_predicate "nonimmediate_nonstack_operand" + (match_code "reg,mem,subreg") +{ + /* 'Q' is for pushes, 'R' for pops. */ + return (nonimmediate_operand (op, mode) + && ! satisfies_constraint_Q (op) + && ! satisfies_constraint_R (op)); +}) + +(define_predicate "xstormy16_carry_plus_operand" + (match_code "plus") +{ + return (GET_CODE (XEXP (op, 1)) == CONST_INT + && (INTVAL (XEXP (op, 1)) < -4 || INTVAL (XEXP (op, 1)) > 4)); +}) + +(define_predicate "xs_hi_general_operand" + (match_code "const_int,reg,subreg,mem,symbol_ref,label_ref,const") +{ + if ((GET_CODE (op) == CONST_INT) + && ((INTVAL (op) >= 32768) || (INTVAL (op) < -32768))) + { + error ("constant halfword load operand out of range"); + return false; + } + + return general_operand (op, mode); +}) + +(define_predicate "xs_hi_nonmemory_operand" + (match_code "const_int,reg,subreg,const") +{ + if ((GET_CODE (op) == CONST_INT) + && ((INTVAL (op) >= 32768) || (INTVAL (op) < -32768))) + { + error ("constant arithmetic operand out of range"); + return false; + } + + return nonmemory_operand (op, mode); +}) diff --git a/gcc-4.9/gcc/config/stormy16/stormy-abi b/gcc-4.9/gcc/config/stormy16/stormy-abi new file mode 100644 index 000000000..a9ceb3197 --- /dev/null +++ b/gcc-4.9/gcc/config/stormy16/stormy-abi @@ -0,0 +1,174 @@ +xStormy16 ABI +************ + +!!!!! NOTE !!!!! +This document is a draft and is subject to change. +!!!!! NOTE !!!!! + +This part of the file describes the conventions required to write +ELF object files that are link-compatible with the ones produced +by the GNU toolchains. + +Bit and Byte Ordering +===================== + +This implementation is little-endian. Bits are numbered starting +from 0 being the LSB. + +In this document, 'word' means 16 bits. + +Calling Sequence +================ + +The registers are allocated as follows: + +Register Purpose +------------------------------------------------------------------- +r0, r1 Call-volatile. May be changed during the execution + of a call instruction. +r2 through r7 Argument passing; call-clobbered. +r8, r9 Call-volatile. May be changed during the execution + of a call instruction. +r10 through r13 Call-saved. +r14 Program status word. +r15 Stack pointer. + + +Scalar values are returned in register r2-r7 if the value fits. +Otherwise, a pointer is passed as a 'hidden' first argument and +the return value is placed there. + +Arguments are passed in registers starting in r2, then on the stack. +Arguments of size not a multiple of a word are padded to whole words. +If an argument would otherwise be passed partially in registers, and +partially on the stack, the whole of it is passed on the stack. The +last argument is pushed on the stack first. + +After a procedure's arguments are pushed on the stack, +the return address is pushed on the stack, as if by the call +instruction. The return address is on the top of the stack when +a procedure is called. + +Objects whose size is a multiple of 16 bits are aligned to a 16-bit +boundary. + +Pointers are 16 bits, referencing addresses between 0 and 0xFFFF. + +Procedure pointers are also implemented as 16-bit pointers. + +Variable Argument Functions +=========================== + +The C type 'va_list' is implemented as a structure, as follows: + +struct { + char *base; + unsigned count; +} + +Both fields are 16 bits. An argument of size N bytes +(N will be even) is accessed as if by the following code: + +char *result; +/* count = #bytes non-variable arguments */ +/* 12 = #bytes for register arguments */ +if (count + N > 12) + { + if (count < 12) + count = 12; + result = base - (count + N - 12 + 4); + } +else + { + result = base + count; + } +count += N; +/* The argument is at `*result'. */ + + +One implementation of this is if a variadic function first +pushes registers 2 through 7 in sequence at entry, and +sets 'base' to the address of the first word pushed, +producing a stack that appears like: + +SP -> + [other data] + r7 + r6 + r5 + r4 + r3 +count-> r2 + Return address (two words) + 7th procedure parameter word + 8th procedure parameter word + ... + last procedure parameter word + +and initializes 'count' to be the number of bytes of non-variable +arguments to the function. + +ELF File Format +=============== + +ELF file header +--------------- + +xStormy16 ELF files are distinguished by the value EM_XSTORMY16 in +the e_machine field of the ELF file header: + +#define EM_XSTORMY16 0xad45 + +DWARF Register Number Mapping +----------------------------- + +Registers r0 through r15 are mapped to numbers 0 through 15. + +Relocations +----------- + +RELA relocs are used exclusively. The relocation types defined are: + +Name Value Field Calculation Overflow +---------------------------------------------------------------- +R_XSTORMY16_NONE 0 none none none +R_XSTORMY16_32 1 32 S + A none +R_XSTORMY16_16 2 16 S + A either +R_XSTORMY16_8 3 8 S + A unsigned +R_XSTORMY16_PC32 4 32 S + A - P none +R_XSTORMY16_PC16 5 16 S + A - P signed +R_XSTORMY16_PC8 6 8 S + A - P signed +R_XSTORMY16_REL_12 7 16:12:0 S + A - P signed +R_XSTORMY16_24 8 32:23:1 (S + A) >> 1 unsigned +R_XSTORMY16_FPTR16 9 16 S + A either +R_XSTORMY16_LO16 10 16 S + A none +R_XSTORMY16_HI16 11 32:16:16 S + A none +R_XSTORMY16_12 12 16:12:0 S + A signed +R_XSTORMY16_GNU_VTINHERIT 128 n/a n/a n/a +R_XSTORMY16_GNU_VTENTRY 129 n/a n/a n/a + +In the 'Field' column, the first number indicates whether the +relocation refers to a byte, word or doubleword. The second number, +if any, indicates the size of the bit-field into which the relocation +is to occur (and also the size for overflow checking). The third +number indicates the first bit of the bit-field in the word or +doubleword, counting the LSB as bit 0. + +In the 'Calculation' column, 'S' is the value of the symbol to which +the reloc refers, 'A' is the addend, and 'P' represents the place of +the storage unit being relocated. + +In the 'Overflow' column, 'none' means that any overflow of the +computation performed in the 'Calculation' column is ignored. +'signed' means that the overflow is only reported if it happens when +the values are treated as signed quantities. 'unsigned' is the same, +except that the values are treated as unsigned quantities. 'either' +means that overflow is reported for either signed or unsigned +overflow. + + +Copyright (C) 2001-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. diff --git a/gcc-4.9/gcc/config/stormy16/stormy16-protos.h b/gcc-4.9/gcc/config/stormy16/stormy16-protos.h new file mode 100644 index 000000000..2085eb45f --- /dev/null +++ b/gcc-4.9/gcc/config/stormy16/stormy16-protos.h @@ -0,0 +1,69 @@ +/* Prototypes for exported functions defined in xstormy16.c + Copyright (C) 2000-2014 Free Software Foundation, Inc. + Contributed by Red Hat, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + + + +extern struct xstormy16_stack_layout xstormy16_compute_stack_layout (void); +extern void xstormy16_expand_prologue (void); +extern void xstormy16_expand_epilogue (void); +extern int xstormy16_initial_elimination_offset (int, int); +extern int direct_return (void); +extern int xstormy16_interrupt_function_p (void); +extern int xstormy16_epilogue_uses (int); +extern void xstormy16_function_profiler (void); + +#if defined (TREE_CODE) +extern void xstormy16_asm_output_aligned_common (FILE *, tree, const char *, + int, int, int); +#endif + +#if defined (TREE_CODE) && defined (RTX_CODE) +extern void xstormy16_initialize_trampoline (rtx, rtx, rtx); +#endif + +#ifdef RTX_CODE +extern void xstormy16_emit_cbranch (enum rtx_code, rtx, rtx, rtx); +extern char *xstormy16_output_cbranch_hi (rtx, const char *, int, rtx); +extern char *xstormy16_output_cbranch_si (rtx, const char *, int, rtx); + +extern void xstormy16_expand_casesi (rtx, rtx, rtx, rtx, rtx); +extern void xstormy16_output_addr_vec (FILE *, rtx, rtx); +extern void xstormy16_expand_call (rtx, rtx, rtx); +extern void xstormy16_expand_iorqi3 (rtx *); +extern void xstormy16_expand_andqi3 (rtx *); +#endif + +#if defined (HAVE_MACHINE_MODES) && defined (RTX_CODE) +extern void xstormy16_split_cbranch (enum machine_mode, rtx, rtx, rtx); +extern int short_memory_operand (rtx, enum machine_mode); +extern int nonimmediate_nonstack_operand (rtx, enum machine_mode); +extern enum reg_class xstormy16_secondary_reload_class + (enum reg_class, enum machine_mode, rtx); +extern void xstormy16_split_move (enum machine_mode, rtx, rtx); +extern void xstormy16_expand_move (enum machine_mode, rtx, rtx); +extern void xstormy16_expand_arith (enum machine_mode, enum rtx_code, + rtx, rtx, rtx); +extern const char * xstormy16_output_shift (enum machine_mode, enum rtx_code, + rtx, rtx, rtx); +extern int xstormy16_below100_symbol (rtx, enum machine_mode); +extern int xstormy16_splittable_below100_operand (rtx, enum machine_mode); +extern bool xstormy16_legitimate_address_p (enum machine_mode, rtx, bool); +#endif + diff --git a/gcc-4.9/gcc/config/stormy16/stormy16.c b/gcc-4.9/gcc/config/stormy16/stormy16.c new file mode 100644 index 000000000..6a64fccbe --- /dev/null +++ b/gcc-4.9/gcc/config/stormy16/stormy16.c @@ -0,0 +1,2703 @@ +/* Xstormy16 target functions. + Copyright (C) 1997-2014 Free Software Foundation, Inc. + Contributed by Red Hat, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + <http://www.gnu.org/licenses/>. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "insn-config.h" +#include "conditions.h" +#include "insn-flags.h" +#include "output.h" +#include "insn-attr.h" +#include "flags.h" +#include "recog.h" +#include "diagnostic-core.h" +#include "obstack.h" +#include "tree.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" +#include "expr.h" +#include "optabs.h" +#include "except.h" +#include "function.h" +#include "target.h" +#include "target-def.h" +#include "tm_p.h" +#include "langhooks.h" +#include "pointer-set.h" +#include "hash-table.h" +#include "vec.h" +#include "ggc.h" +#include "basic-block.h" +#include "tree-ssa-alias.h" +#include "internal-fn.h" +#include "gimple-fold.h" +#include "tree-eh.h" +#include "gimple-expr.h" +#include "is-a.h" +#include "gimple.h" +#include "gimplify.h" +#include "df.h" +#include "reload.h" + +static rtx emit_addhi3_postreload (rtx, rtx, rtx); +static void xstormy16_asm_out_constructor (rtx, int); +static void xstormy16_asm_out_destructor (rtx, int); +static void xstormy16_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, + HOST_WIDE_INT, tree); + +static void xstormy16_init_builtins (void); +static rtx xstormy16_expand_builtin (tree, rtx, rtx, enum machine_mode, int); +static bool xstormy16_rtx_costs (rtx, int, int, int, int *, bool); +static int xstormy16_address_cost (rtx, enum machine_mode, addr_space_t, bool); +static bool xstormy16_return_in_memory (const_tree, const_tree); + +static GTY(()) section *bss100_section; + +/* Compute a (partial) cost for rtx X. Return true if the complete + cost has been computed, and false if subexpressions should be + scanned. In either case, *TOTAL contains the cost result. */ + +static bool +xstormy16_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, + int opno ATTRIBUTE_UNUSED, int *total, + bool speed ATTRIBUTE_UNUSED) +{ + switch (code) + { + case CONST_INT: + if (INTVAL (x) < 16 && INTVAL (x) >= 0) + *total = COSTS_N_INSNS (1) / 2; + else if (INTVAL (x) < 256 && INTVAL (x) >= 0) + *total = COSTS_N_INSNS (1); + else + *total = COSTS_N_INSNS (2); + return true; + + case CONST_DOUBLE: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + *total = COSTS_N_INSNS (2); + return true; + + case MULT: + *total = COSTS_N_INSNS (35 + 6); + return true; + case DIV: + *total = COSTS_N_INSNS (51 - 6); + return true; + + default: + return false; + } +} + +static int +xstormy16_address_cost (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED, + addr_space_t as ATTRIBUTE_UNUSED, + bool speed ATTRIBUTE_UNUSED) +{ + return (CONST_INT_P (x) ? 2 + : GET_CODE (x) == PLUS ? 7 + : 5); +} + +/* Worker function for TARGET_MEMORY_MOVE_COST. */ + +static int +xstormy16_memory_move_cost (enum machine_mode mode, reg_class_t rclass, + bool in) +{ + return (5 + memory_move_secondary_cost (mode, rclass, in)); +} + +/* Branches are handled as follows: + + 1. HImode compare-and-branches. The machine supports these + natively, so the appropriate pattern is emitted directly. + + 2. SImode EQ and NE. These are emitted as pairs of HImode + compare-and-branches. + + 3. SImode LT, GE, LTU and GEU. These are emitted as a sequence + of a SImode subtract followed by a branch (not a compare-and-branch), + like this: + sub + sbc + blt + + 4. SImode GT, LE, GTU, LEU. These are emitted as a sequence like: + sub + sbc + blt + or + bne. */ + +/* Emit a branch of kind CODE to location LOC. */ + +void +xstormy16_emit_cbranch (enum rtx_code code, rtx op0, rtx op1, rtx loc) +{ + rtx condition_rtx, loc_ref, branch, cy_clobber; + rtvec vec; + enum machine_mode mode; + + mode = GET_MODE (op0); + gcc_assert (mode == HImode || mode == SImode); + + if (mode == SImode + && (code == GT || code == LE || code == GTU || code == LEU)) + { + int unsigned_p = (code == GTU || code == LEU); + int gt_p = (code == GT || code == GTU); + rtx lab = NULL_RTX; + + if (gt_p) + lab = gen_label_rtx (); + xstormy16_emit_cbranch (unsigned_p ? LTU : LT, op0, op1, gt_p ? lab : loc); + /* This should be generated as a comparison against the temporary + created by the previous insn, but reload can't handle that. */ + xstormy16_emit_cbranch (gt_p ? NE : EQ, op0, op1, loc); + if (gt_p) + emit_label (lab); + return; + } + else if (mode == SImode + && (code == NE || code == EQ) + && op1 != const0_rtx) + { + rtx op0_word, op1_word; + rtx lab = NULL_RTX; + int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; + int i; + + if (code == EQ) + lab = gen_label_rtx (); + + for (i = 0; i < num_words - 1; i++) + { + op0_word = simplify_gen_subreg (word_mode, op0, mode, + i * UNITS_PER_WORD); + op1_word = simplify_gen_subreg (word_mode, op1, mode, + i * UNITS_PER_WORD); + xstormy16_emit_cbranch (NE, op0_word, op1_word, code == EQ ? lab : loc); + } + op0_word = simplify_gen_subreg (word_mode, op0, mode, + i * UNITS_PER_WORD); + op1_word = simplify_gen_subreg (word_mode, op1, mode, + i * UNITS_PER_WORD); + xstormy16_emit_cbranch (code, op0_word, op1_word, loc); + + if (code == EQ) + emit_label (lab); + return; + } + + /* We can't allow reload to try to generate any reload after a branch, + so when some register must match we must make the temporary ourselves. */ + if (mode != HImode) + { + rtx tmp; + tmp = gen_reg_rtx (mode); + emit_move_insn (tmp, op0); + op0 = tmp; + } + + condition_rtx = gen_rtx_fmt_ee (code, mode, op0, op1); + loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); + branch = gen_rtx_SET (VOIDmode, pc_rtx, + gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, + loc_ref, pc_rtx)); + + cy_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); + + if (mode == HImode) + vec = gen_rtvec (2, branch, cy_clobber); + else if (code == NE || code == EQ) + vec = gen_rtvec (2, branch, gen_rtx_CLOBBER (VOIDmode, op0)); + else + { + rtx sub; +#if 0 + sub = gen_rtx_SET (VOIDmode, op0, gen_rtx_MINUS (SImode, op0, op1)); +#else + sub = gen_rtx_CLOBBER (SImode, op0); +#endif + vec = gen_rtvec (3, branch, sub, cy_clobber); + } + + emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec)); +} + +/* Take a SImode conditional branch, one of GT/LE/GTU/LEU, and split + the arithmetic operation. Most of the work is done by + xstormy16_expand_arith. */ + +void +xstormy16_split_cbranch (enum machine_mode mode, rtx label, rtx comparison, + rtx dest) +{ + rtx op0 = XEXP (comparison, 0); + rtx op1 = XEXP (comparison, 1); + rtx seq, last_insn; + rtx compare; + + start_sequence (); + xstormy16_expand_arith (mode, COMPARE, dest, op0, op1); + seq = get_insns (); + end_sequence (); + + gcc_assert (INSN_P (seq)); + + last_insn = seq; + while (NEXT_INSN (last_insn) != NULL_RTX) + last_insn = NEXT_INSN (last_insn); + + compare = SET_SRC (XVECEXP (PATTERN (last_insn), 0, 0)); + PUT_CODE (XEXP (compare, 0), GET_CODE (comparison)); + XEXP (compare, 1) = gen_rtx_LABEL_REF (VOIDmode, label); + emit_insn (seq); +} + + +/* Return the string to output a conditional branch to LABEL, which is + the operand number of the label. + + OP is the conditional expression, or NULL for branch-always. + + REVERSED is nonzero if we should reverse the sense of the comparison. + + INSN is the insn. */ + +char * +xstormy16_output_cbranch_hi (rtx op, const char *label, int reversed, rtx insn) +{ + static char string[64]; + int need_longbranch = (op != NULL_RTX + ? get_attr_length (insn) == 8 + : get_attr_length (insn) == 4); + int really_reversed = reversed ^ need_longbranch; + const char *ccode; + const char *templ; + const char *operands; + enum rtx_code code; + + if (! op) + { + if (need_longbranch) + ccode = "jmpf"; + else + ccode = "br"; + sprintf (string, "%s %s", ccode, label); + return string; + } + + code = GET_CODE (op); + + if (! REG_P (XEXP (op, 0))) + { + code = swap_condition (code); + operands = "%3,%2"; + } + else + operands = "%2,%3"; + + /* Work out which way this really branches. */ + if (really_reversed) + code = reverse_condition (code); + + switch (code) + { + case EQ: ccode = "z"; break; + case NE: ccode = "nz"; break; + case GE: ccode = "ge"; break; + case LT: ccode = "lt"; break; + case GT: ccode = "gt"; break; + case LE: ccode = "le"; break; + case GEU: ccode = "nc"; break; + case LTU: ccode = "c"; break; + case GTU: ccode = "hi"; break; + case LEU: ccode = "ls"; break; + + default: + gcc_unreachable (); + } + + if (need_longbranch) + templ = "b%s %s,.+8 | jmpf %s"; + else + templ = "b%s %s,%s"; + sprintf (string, templ, ccode, operands, label); + + return string; +} + +/* Return the string to output a conditional branch to LABEL, which is + the operand number of the label, but suitable for the tail of a + SImode branch. + + OP is the conditional expression (OP is never NULL_RTX). + + REVERSED is nonzero if we should reverse the sense of the comparison. + + INSN is the insn. */ + +char * +xstormy16_output_cbranch_si (rtx op, const char *label, int reversed, rtx insn) +{ + static char string[64]; + int need_longbranch = get_attr_length (insn) >= 8; + int really_reversed = reversed ^ need_longbranch; + const char *ccode; + const char *templ; + char prevop[16]; + enum rtx_code code; + + code = GET_CODE (op); + + /* Work out which way this really branches. */ + if (really_reversed) + code = reverse_condition (code); + + switch (code) + { + case EQ: ccode = "z"; break; + case NE: ccode = "nz"; break; + case GE: ccode = "ge"; break; + case LT: ccode = "lt"; break; + case GEU: ccode = "nc"; break; + case LTU: ccode = "c"; break; + + /* The missing codes above should never be generated. */ + default: + gcc_unreachable (); + } + + switch (code) + { + case EQ: case NE: + { + int regnum; + + gcc_assert (REG_P (XEXP (op, 0))); + + regnum = REGNO (XEXP (op, 0)); + sprintf (prevop, "or %s,%s", reg_names[regnum], reg_names[regnum+1]); + } + break; + + case GE: case LT: case GEU: case LTU: + strcpy (prevop, "sbc %2,%3"); + break; + + default: + gcc_unreachable (); + } + + if (need_longbranch) + templ = "%s | b%s .+6 | jmpf %s"; + else + templ = "%s | b%s %s"; + sprintf (string, templ, prevop, ccode, label); + + return string; +} + +/* Many machines have some registers that cannot be copied directly to or from + memory or even from other types of registers. An example is the `MQ' + register, which on most machines, can only be copied to or from general + registers, but not memory. Some machines allow copying all registers to and + from memory, but require a scratch register for stores to some memory + locations (e.g., those with symbolic address on the RT, and those with + certain symbolic address on the SPARC when compiling PIC). In some cases, + both an intermediate and a scratch register are required. + + You should define these macros to indicate to the reload phase that it may + need to allocate at least one register for a reload in addition to the + register to contain the data. Specifically, if copying X to a register + RCLASS in MODE requires an intermediate register, you should define + `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of + whose registers can be used as intermediate registers or scratch registers. + + If copying a register RCLASS in MODE to X requires an intermediate or scratch + register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the + largest register class required. If the requirements for input and output + reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used + instead of defining both macros identically. + + The values returned by these macros are often `GENERAL_REGS'. Return + `NO_REGS' if no spare register is needed; i.e., if X can be directly copied + to or from a register of RCLASS in MODE without requiring a scratch register. + Do not define this macro if it would always return `NO_REGS'. + + If a scratch register is required (either with or without an intermediate + register), you should define patterns for `reload_inM' or `reload_outM', as + required.. These patterns, which will normally be implemented with a + `define_expand', should be similar to the `movM' patterns, except that + operand 2 is the scratch register. + + Define constraints for the reload register and scratch register that contain + a single register class. If the original reload register (whose class is + RCLASS) can meet the constraint given in the pattern, the value returned by + these macros is used for the class of the scratch register. Otherwise, two + additional reload registers are required. Their classes are obtained from + the constraints in the insn pattern. + + X might be a pseudo-register or a `subreg' of a pseudo-register, which could + either be in a hard register or in memory. Use `true_regnum' to find out; + it will return -1 if the pseudo is in memory and the hard register number if + it is in a register. + + These macros should not be used in the case where a particular class of + registers can only be copied to memory and not to another class of + registers. In that case, secondary reload registers are not needed and + would not be helpful. Instead, a stack location must be used to perform the + copy and the `movM' pattern should use memory as an intermediate storage. + This case often occurs between floating-point and general registers. */ + +enum reg_class +xstormy16_secondary_reload_class (enum reg_class rclass, + enum machine_mode mode ATTRIBUTE_UNUSED, + rtx x) +{ + /* This chip has the interesting property that only the first eight + registers can be moved to/from memory. */ + if ((MEM_P (x) + || ((GET_CODE (x) == SUBREG || REG_P (x)) + && (true_regnum (x) == -1 + || true_regnum (x) >= FIRST_PSEUDO_REGISTER))) + && ! reg_class_subset_p (rclass, EIGHT_REGS)) + return EIGHT_REGS; + + return NO_REGS; +} + +/* Worker function for TARGET_PREFERRED_RELOAD_CLASS + and TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */ + +static reg_class_t +xstormy16_preferred_reload_class (rtx x, reg_class_t rclass) +{ + if (rclass == GENERAL_REGS && MEM_P (x)) + return EIGHT_REGS; + + return rclass; +} + +/* Predicate for symbols and addresses that reflect special 8-bit + addressing. */ + +int +xstormy16_below100_symbol (rtx x, + enum machine_mode mode ATTRIBUTE_UNUSED) +{ + if (GET_CODE (x) == CONST) + x = XEXP (x, 0); + if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) + x = XEXP (x, 0); + + if (GET_CODE (x) == SYMBOL_REF) + return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_XSTORMY16_BELOW100) != 0; + + if (CONST_INT_P (x)) + { + HOST_WIDE_INT i = INTVAL (x); + + if ((i >= 0x0000 && i <= 0x00ff) + || (i >= 0x7f00 && i <= 0x7fff)) + return 1; + } + return 0; +} + +/* Likewise, but only for non-volatile MEMs, for patterns where the + MEM will get split into smaller sized accesses. */ + +int +xstormy16_splittable_below100_operand (rtx x, enum machine_mode mode) +{ + if (MEM_P (x) && MEM_VOLATILE_P (x)) + return 0; + return xstormy16_below100_operand (x, mode); +} + +/* Expand an 8-bit IOR. This either detects the one case we can + actually do, or uses a 16-bit IOR. */ + +void +xstormy16_expand_iorqi3 (rtx *operands) +{ + rtx in, out, outsub, val; + + out = operands[0]; + in = operands[1]; + val = operands[2]; + + if (xstormy16_onebit_set_operand (val, QImode)) + { + if (!xstormy16_below100_or_register (in, QImode)) + in = copy_to_mode_reg (QImode, in); + if (!xstormy16_below100_or_register (out, QImode)) + out = gen_reg_rtx (QImode); + emit_insn (gen_iorqi3_internal (out, in, val)); + if (out != operands[0]) + emit_move_insn (operands[0], out); + return; + } + + if (! REG_P (in)) + in = copy_to_mode_reg (QImode, in); + + if (! REG_P (val) && ! CONST_INT_P (val)) + val = copy_to_mode_reg (QImode, val); + + if (! REG_P (out)) + out = gen_reg_rtx (QImode); + + in = simplify_gen_subreg (HImode, in, QImode, 0); + outsub = simplify_gen_subreg (HImode, out, QImode, 0); + + if (! CONST_INT_P (val)) + val = simplify_gen_subreg (HImode, val, QImode, 0); + + emit_insn (gen_iorhi3 (outsub, in, val)); + + if (out != operands[0]) + emit_move_insn (operands[0], out); +} + +/* Expand an 8-bit AND. This either detects the one case we can + actually do, or uses a 16-bit AND. */ + +void +xstormy16_expand_andqi3 (rtx *operands) +{ + rtx in, out, outsub, val; + + out = operands[0]; + in = operands[1]; + val = operands[2]; + + if (xstormy16_onebit_clr_operand (val, QImode)) + { + if (!xstormy16_below100_or_register (in, QImode)) + in = copy_to_mode_reg (QImode, in); + if (!xstormy16_below100_or_register (out, QImode)) + out = gen_reg_rtx (QImode); + emit_insn (gen_andqi3_internal (out, in, val)); + if (out != operands[0]) + emit_move_insn (operands[0], out); + return; + } + + if (! REG_P (in)) + in = copy_to_mode_reg (QImode, in); + + if (! REG_P (val) && ! CONST_INT_P (val)) + val = copy_to_mode_reg (QImode, val); + + if (! REG_P (out)) + out = gen_reg_rtx (QImode); + + in = simplify_gen_subreg (HImode, in, QImode, 0); + outsub = simplify_gen_subreg (HImode, out, QImode, 0); + + if (! CONST_INT_P (val)) + val = simplify_gen_subreg (HImode, val, QImode, 0); + + emit_insn (gen_andhi3 (outsub, in, val)); + + if (out != operands[0]) + emit_move_insn (operands[0], out); +} + +#define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \ + (CONST_INT_P (X) \ + && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 2048) < 4096) + +#define LEGITIMATE_ADDRESS_CONST_INT_P(X, OFFSET) \ + (CONST_INT_P (X) \ + && INTVAL (X) + (OFFSET) >= 0 \ + && INTVAL (X) + (OFFSET) < 0x8000 \ + && (INTVAL (X) + (OFFSET) < 0x100 || INTVAL (X) + (OFFSET) >= 0x7F00)) + +bool +xstormy16_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, + rtx x, bool strict) +{ + if (LEGITIMATE_ADDRESS_CONST_INT_P (x, 0)) + return true; + + if (GET_CODE (x) == PLUS + && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 0)) + { + x = XEXP (x, 0); + /* PR 31232: Do not allow INT+INT as an address. */ + if (CONST_INT_P (x)) + return false; + } + + if ((GET_CODE (x) == PRE_MODIFY && CONST_INT_P (XEXP (XEXP (x, 1), 1))) + || GET_CODE (x) == POST_INC + || GET_CODE (x) == PRE_DEC) + x = XEXP (x, 0); + + if (REG_P (x) + && REGNO_OK_FOR_BASE_P (REGNO (x)) + && (! strict || REGNO (x) < FIRST_PSEUDO_REGISTER)) + return true; + + if (xstormy16_below100_symbol (x, mode)) + return true; + + return false; +} + +/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. + + On this chip, this is true if the address is valid with an offset + of 0 but not of 6, because in that case it cannot be used as an + address for DImode or DFmode, or if the address is a post-increment + or pre-decrement address. */ + +static bool +xstormy16_mode_dependent_address_p (const_rtx x, + addr_space_t as ATTRIBUTE_UNUSED) +{ + if (LEGITIMATE_ADDRESS_CONST_INT_P (x, 0) + && ! LEGITIMATE_ADDRESS_CONST_INT_P (x, 6)) + return true; + + if (GET_CODE (x) == PLUS + && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 0) + && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (x, 1), 6)) + return true; + + /* Auto-increment addresses are now treated generically in recog.c. */ + return false; +} + +int +short_memory_operand (rtx x, enum machine_mode mode) +{ + if (! memory_operand (x, mode)) + return 0; + return (GET_CODE (XEXP (x, 0)) != PLUS); +} + +/* Splitter for the 'move' patterns, for modes not directly implemented + by hardware. Emit insns to copy a value of mode MODE from SRC to + DEST. + + This function is only called when reload_completed. */ + +void +xstormy16_split_move (enum machine_mode mode, rtx dest, rtx src) +{ + int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; + int direction, end, i; + int src_modifies = 0; + int dest_modifies = 0; + int src_volatile = 0; + int dest_volatile = 0; + rtx mem_operand; + rtx auto_inc_reg_rtx = NULL_RTX; + + /* Check initial conditions. */ + gcc_assert (reload_completed + && mode != QImode && mode != HImode + && nonimmediate_operand (dest, mode) + && general_operand (src, mode)); + + /* This case is not supported below, and shouldn't be generated. */ + gcc_assert (! MEM_P (dest) || ! MEM_P (src)); + + /* This case is very very bad after reload, so trap it now. */ + gcc_assert (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG); + + /* The general idea is to copy by words, offsetting the source and + destination. Normally the least-significant word will be copied + first, but for pre-dec operations it's better to copy the + most-significant word first. Only one operand can be a pre-dec + or post-inc operand. + + It's also possible that the copy overlaps so that the direction + must be reversed. */ + direction = 1; + + if (MEM_P (dest)) + { + mem_operand = XEXP (dest, 0); + dest_modifies = side_effects_p (mem_operand); + if (auto_inc_p (mem_operand)) + auto_inc_reg_rtx = XEXP (mem_operand, 0); + dest_volatile = MEM_VOLATILE_P (dest); + if (dest_volatile) + { + dest = copy_rtx (dest); + MEM_VOLATILE_P (dest) = 0; + } + } + else if (MEM_P (src)) + { + mem_operand = XEXP (src, 0); + src_modifies = side_effects_p (mem_operand); + if (auto_inc_p (mem_operand)) + auto_inc_reg_rtx = XEXP (mem_operand, 0); + src_volatile = MEM_VOLATILE_P (src); + if (src_volatile) + { + src = copy_rtx (src); + MEM_VOLATILE_P (src) = 0; + } + } + else + mem_operand = NULL_RTX; + + if (mem_operand == NULL_RTX) + { + if (REG_P (src) + && REG_P (dest) + && reg_overlap_mentioned_p (dest, src) + && REGNO (dest) > REGNO (src)) + direction = -1; + } + else if (GET_CODE (mem_operand) == PRE_DEC + || (GET_CODE (mem_operand) == PLUS + && GET_CODE (XEXP (mem_operand, 0)) == PRE_DEC)) + direction = -1; + else if (MEM_P (src) && reg_overlap_mentioned_p (dest, src)) + { + int regno; + + gcc_assert (REG_P (dest)); + regno = REGNO (dest); + + gcc_assert (refers_to_regno_p (regno, regno + num_words, + mem_operand, 0)); + + if (refers_to_regno_p (regno, regno + 1, mem_operand, 0)) + direction = -1; + else if (refers_to_regno_p (regno + num_words - 1, regno + num_words, + mem_operand, 0)) + direction = 1; + else + /* This means something like + (set (reg:DI r0) (mem:DI (reg:HI r1))) + which we'd need to support by doing the set of the second word + last. */ + gcc_unreachable (); + } + + end = direction < 0 ? -1 : num_words; + for (i = direction < 0 ? num_words - 1 : 0; i != end; i += direction) + { + rtx w_src, w_dest, insn; + + if (src_modifies) + w_src = gen_rtx_MEM (word_mode, mem_operand); + else + w_src = simplify_gen_subreg (word_mode, src, mode, i * UNITS_PER_WORD); + if (src_volatile) + MEM_VOLATILE_P (w_src) = 1; + if (dest_modifies) + w_dest = gen_rtx_MEM (word_mode, mem_operand); + else + w_dest = simplify_gen_subreg (word_mode, dest, mode, + i * UNITS_PER_WORD); + if (dest_volatile) + MEM_VOLATILE_P (w_dest) = 1; + + /* The simplify_subreg calls must always be able to simplify. */ + gcc_assert (GET_CODE (w_src) != SUBREG + && GET_CODE (w_dest) != SUBREG); + + insn = emit_insn (gen_rtx_SET (VOIDmode, w_dest, w_src)); + if (auto_inc_reg_rtx) + REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, + auto_inc_reg_rtx, + REG_NOTES (insn)); + } +} + +/* Expander for the 'move' patterns. Emit insns to copy a value of + mode MODE from SRC to DEST. */ + +void +xstormy16_expand_move (enum machine_mode mode, rtx dest, rtx src) +{ + if (MEM_P (dest) && (GET_CODE (XEXP (dest, 0)) == PRE_MODIFY)) + { + rtx pmv = XEXP (dest, 0); + rtx dest_reg = XEXP (pmv, 0); + rtx dest_mod = XEXP (pmv, 1); + rtx set = gen_rtx_SET (Pmode, dest_reg, dest_mod); + rtx clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); + + dest = gen_rtx_MEM (mode, dest_reg); + emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); + } + else if (MEM_P (src) && (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)) + { + rtx pmv = XEXP (src, 0); + rtx src_reg = XEXP (pmv, 0); + rtx src_mod = XEXP (pmv, 1); + rtx set = gen_rtx_SET (Pmode, src_reg, src_mod); + rtx clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); + + src = gen_rtx_MEM (mode, src_reg); + emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); + } + + /* There are only limited immediate-to-memory move instructions. */ + if (! reload_in_progress + && ! reload_completed + && MEM_P (dest) + && (! CONST_INT_P (XEXP (dest, 0)) + || ! xstormy16_legitimate_address_p (mode, XEXP (dest, 0), 0)) + && ! xstormy16_below100_operand (dest, mode) + && ! REG_P (src) + && GET_CODE (src) != SUBREG) + src = copy_to_mode_reg (mode, src); + + /* Don't emit something we would immediately split. */ + if (reload_completed + && mode != HImode && mode != QImode) + { + xstormy16_split_move (mode, dest, src); + return; + } + + emit_insn (gen_rtx_SET (VOIDmode, dest, src)); +} + +/* Stack Layout: + + The stack is laid out as follows: + +SP-> +FP-> Local variables + Register save area (up to 4 words) + Argument register save area for stdarg (NUM_ARGUMENT_REGISTERS words) + +AP-> Return address (two words) + 9th procedure parameter word + 10th procedure parameter word + ... + last procedure parameter word + + The frame pointer location is tuned to make it most likely that all + parameters and local variables can be accessed using a load-indexed + instruction. */ + +/* A structure to describe the layout. */ +struct xstormy16_stack_layout +{ + /* Size of the topmost three items on the stack. */ + int locals_size; + int register_save_size; + int stdarg_save_size; + /* Sum of the above items. */ + int frame_size; + /* Various offsets. */ + int first_local_minus_ap; + int sp_minus_fp; + int fp_minus_ap; +}; + +/* Does REGNO need to be saved? */ +#define REG_NEEDS_SAVE(REGNUM, IFUN) \ + ((df_regs_ever_live_p (REGNUM) && ! call_used_regs[REGNUM]) \ + || (IFUN && ! fixed_regs[REGNUM] && call_used_regs[REGNUM] \ + && (REGNUM != CARRY_REGNUM) \ + && (df_regs_ever_live_p (REGNUM) || ! crtl->is_leaf))) + +/* Compute the stack layout. */ + +struct xstormy16_stack_layout +xstormy16_compute_stack_layout (void) +{ + struct xstormy16_stack_layout layout; + int regno; + const int ifun = xstormy16_interrupt_function_p (); + + layout.locals_size = get_frame_size (); + + layout.register_save_size = 0; + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (REG_NEEDS_SAVE (regno, ifun)) + layout.register_save_size += UNITS_PER_WORD; + + if (cfun->stdarg) + layout.stdarg_save_size = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD; + else + layout.stdarg_save_size = 0; + + layout.frame_size = (layout.locals_size + + layout.register_save_size + + layout.stdarg_save_size); + + if (crtl->args.size <= 2048 && crtl->args.size != -1) + { + if (layout.frame_size - INCOMING_FRAME_SP_OFFSET + + crtl->args.size <= 2048) + layout.fp_minus_ap = layout.frame_size - INCOMING_FRAME_SP_OFFSET; + else + layout.fp_minus_ap = 2048 - crtl->args.size; + } + else + layout.fp_minus_ap = (layout.stdarg_save_size + + layout.register_save_size + - INCOMING_FRAME_SP_OFFSET); + layout.sp_minus_fp = (layout.frame_size - INCOMING_FRAME_SP_OFFSET + - layout.fp_minus_ap); + layout.first_local_minus_ap = layout.sp_minus_fp - layout.locals_size; + return layout; +} + +/* Worker function for TARGET_CAN_ELIMINATE. */ + +static bool +xstormy16_can_eliminate (const int from, const int to) +{ + return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM + ? ! frame_pointer_needed + : true); +} + +/* Determine how all the special registers get eliminated. */ + +int +xstormy16_initial_elimination_offset (int from, int to) +{ + struct xstormy16_stack_layout layout; + int result; + + layout = xstormy16_compute_stack_layout (); + + if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) + result = layout.sp_minus_fp - layout.locals_size; + else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) + result = - layout.locals_size; + else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) + result = - layout.fp_minus_ap; + else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) + result = - (layout.sp_minus_fp + layout.fp_minus_ap); + else + gcc_unreachable (); + + return result; +} + +static rtx +emit_addhi3_postreload (rtx dest, rtx src0, rtx src1) +{ + rtx set, clobber, insn; + + set = gen_rtx_SET (VOIDmode, dest, gen_rtx_PLUS (HImode, src0, src1)); + clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); + insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); + return insn; +} + +/* Called after register allocation to add any instructions needed for + the prologue. Using a prologue insn is favored compared to putting + all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro, + since it allows the scheduler to intermix instructions with the + saves of the caller saved registers. In some cases, it might be + necessary to emit a barrier instruction as the last insn to prevent + such scheduling. + + Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 + so that the debug info generation code can handle them properly. */ + +void +xstormy16_expand_prologue (void) +{ + struct xstormy16_stack_layout layout; + int regno; + rtx insn; + rtx mem_push_rtx; + const int ifun = xstormy16_interrupt_function_p (); + + mem_push_rtx = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); + mem_push_rtx = gen_rtx_MEM (HImode, mem_push_rtx); + + layout = xstormy16_compute_stack_layout (); + + if (layout.locals_size >= 32768) + error ("local variable memory requirements exceed capacity"); + + if (flag_stack_usage_info) + current_function_static_stack_size = layout.frame_size; + + /* Save the argument registers if necessary. */ + if (layout.stdarg_save_size) + for (regno = FIRST_ARGUMENT_REGISTER; + regno < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS; + regno++) + { + rtx dwarf; + rtx reg = gen_rtx_REG (HImode, regno); + + insn = emit_move_insn (mem_push_rtx, reg); + RTX_FRAME_RELATED_P (insn) = 1; + + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2)); + + XVECEXP (dwarf, 0, 0) = gen_rtx_SET (VOIDmode, + gen_rtx_MEM (Pmode, stack_pointer_rtx), + reg); + XVECEXP (dwarf, 0, 1) = gen_rtx_SET (Pmode, stack_pointer_rtx, + plus_constant (Pmode, + stack_pointer_rtx, + GET_MODE_SIZE (Pmode))); + add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); + RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 0)) = 1; + RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 1)) = 1; + } + + /* Push each of the registers to save. */ + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (REG_NEEDS_SAVE (regno, ifun)) + { + rtx dwarf; + rtx reg = gen_rtx_REG (HImode, regno); + + insn = emit_move_insn (mem_push_rtx, reg); + RTX_FRAME_RELATED_P (insn) = 1; + + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (2)); + + XVECEXP (dwarf, 0, 0) = gen_rtx_SET (VOIDmode, + gen_rtx_MEM (Pmode, stack_pointer_rtx), + reg); + XVECEXP (dwarf, 0, 1) = gen_rtx_SET (Pmode, stack_pointer_rtx, + plus_constant (Pmode, + stack_pointer_rtx, + GET_MODE_SIZE (Pmode))); + add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); + RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 0)) = 1; + RTX_FRAME_RELATED_P (XVECEXP (dwarf, 0, 1)) = 1; + } + + /* It's just possible that the SP here might be what we need for + the new FP... */ + if (frame_pointer_needed && layout.sp_minus_fp == layout.locals_size) + { + insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } + + /* Allocate space for local variables. */ + if (layout.locals_size) + { + insn = emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (layout.locals_size)); + RTX_FRAME_RELATED_P (insn) = 1; + } + + /* Set up the frame pointer, if required. */ + if (frame_pointer_needed && layout.sp_minus_fp != layout.locals_size) + { + insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + + if (layout.sp_minus_fp) + { + insn = emit_addhi3_postreload (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + GEN_INT (- layout.sp_minus_fp)); + RTX_FRAME_RELATED_P (insn) = 1; + } + } +} + +/* Do we need an epilogue at all? */ + +int +direct_return (void) +{ + return (reload_completed + && xstormy16_compute_stack_layout ().frame_size == 0 + && ! xstormy16_interrupt_function_p ()); +} + +/* Called after register allocation to add any instructions needed for + the epilogue. Using an epilogue insn is favored compared to putting + all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro, + since it allows the scheduler to intermix instructions with the + saves of the caller saved registers. In some cases, it might be + necessary to emit a barrier instruction as the last insn to prevent + such scheduling. */ + +void +xstormy16_expand_epilogue (void) +{ + struct xstormy16_stack_layout layout; + rtx mem_pop_rtx; + int regno; + const int ifun = xstormy16_interrupt_function_p (); + + mem_pop_rtx = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); + mem_pop_rtx = gen_rtx_MEM (HImode, mem_pop_rtx); + + layout = xstormy16_compute_stack_layout (); + + /* Pop the stack for the locals. */ + if (layout.locals_size) + { + if (frame_pointer_needed && layout.sp_minus_fp == layout.locals_size) + emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); + else + emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (- layout.locals_size)); + } + + /* Restore any call-saved registers. */ + for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--) + if (REG_NEEDS_SAVE (regno, ifun)) + emit_move_insn (gen_rtx_REG (HImode, regno), mem_pop_rtx); + + /* Pop the stack for the stdarg save area. */ + if (layout.stdarg_save_size) + emit_addhi3_postreload (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (- layout.stdarg_save_size)); + + /* Return. */ + if (ifun) + emit_jump_insn (gen_return_internal_interrupt ()); + else + emit_jump_insn (gen_return_internal ()); +} + +int +xstormy16_epilogue_uses (int regno) +{ + if (reload_completed && call_used_regs[regno]) + { + const int ifun = xstormy16_interrupt_function_p (); + return REG_NEEDS_SAVE (regno, ifun); + } + return 0; +} + +void +xstormy16_function_profiler (void) +{ + sorry ("function_profiler support"); +} + +/* Update CUM to advance past an argument in the argument list. The + values MODE, TYPE and NAMED describe that argument. Once this is + done, the variable CUM is suitable for analyzing the *following* + argument with `TARGET_FUNCTION_ARG', etc. + + This function need not do anything if the argument in question was + passed on the stack. The compiler knows how to track the amount of + stack space used for arguments without any special help. However, + it makes life easier for xstormy16_build_va_list if it does update + the word count. */ + +static void +xstormy16_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, + const_tree type, bool named ATTRIBUTE_UNUSED) +{ + CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); + + /* If an argument would otherwise be passed partially in registers, + and partially on the stack, the whole of it is passed on the + stack. */ + if (*cum < NUM_ARGUMENT_REGISTERS + && *cum + XSTORMY16_WORD_SIZE (type, mode) > NUM_ARGUMENT_REGISTERS) + *cum = NUM_ARGUMENT_REGISTERS; + + *cum += XSTORMY16_WORD_SIZE (type, mode); +} + +static rtx +xstormy16_function_arg (cumulative_args_t cum_v, enum machine_mode mode, + const_tree type, bool named ATTRIBUTE_UNUSED) +{ + CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); + + if (mode == VOIDmode) + return const0_rtx; + if (targetm.calls.must_pass_in_stack (mode, type) + || *cum + XSTORMY16_WORD_SIZE (type, mode) > NUM_ARGUMENT_REGISTERS) + return NULL_RTX; + return gen_rtx_REG (mode, *cum + FIRST_ARGUMENT_REGISTER); +} + +/* Build the va_list type. + + For this chip, va_list is a record containing a counter and a pointer. + The counter is of type 'int' and indicates how many bytes + have been used to date. The pointer indicates the stack position + for arguments that have not been passed in registers. + To keep the layout nice, the pointer is first in the structure. */ + +static tree +xstormy16_build_builtin_va_list (void) +{ + tree f_1, f_2, record, type_decl; + + record = (*lang_hooks.types.make_type) (RECORD_TYPE); + type_decl = build_decl (BUILTINS_LOCATION, + TYPE_DECL, get_identifier ("__va_list_tag"), record); + + f_1 = build_decl (BUILTINS_LOCATION, + FIELD_DECL, get_identifier ("base"), + ptr_type_node); + f_2 = build_decl (BUILTINS_LOCATION, + FIELD_DECL, get_identifier ("count"), + unsigned_type_node); + + DECL_FIELD_CONTEXT (f_1) = record; + DECL_FIELD_CONTEXT (f_2) = record; + + TYPE_STUB_DECL (record) = type_decl; + TYPE_NAME (record) = type_decl; + TYPE_FIELDS (record) = f_1; + DECL_CHAIN (f_1) = f_2; + + layout_type (record); + + return record; +} + +/* Implement the stdarg/varargs va_start macro. STDARG_P is nonzero if this + is stdarg.h instead of varargs.h. VALIST is the tree of the va_list + variable to initialize. NEXTARG is the machine independent notion of the + 'next' argument after the variable arguments. */ + +static void +xstormy16_expand_builtin_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) +{ + tree f_base, f_count; + tree base, count; + tree t,u; + + if (xstormy16_interrupt_function_p ()) + error ("cannot use va_start in interrupt function"); + + f_base = TYPE_FIELDS (va_list_type_node); + f_count = DECL_CHAIN (f_base); + + base = build3 (COMPONENT_REF, TREE_TYPE (f_base), valist, f_base, NULL_TREE); + count = build3 (COMPONENT_REF, TREE_TYPE (f_count), valist, f_count, + NULL_TREE); + + t = make_tree (TREE_TYPE (base), virtual_incoming_args_rtx); + u = build_int_cst (NULL_TREE, - INCOMING_FRAME_SP_OFFSET); + u = fold_convert (TREE_TYPE (count), u); + t = fold_build_pointer_plus (t, u); + t = build2 (MODIFY_EXPR, TREE_TYPE (base), base, t); + TREE_SIDE_EFFECTS (t) = 1; + expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); + + t = build2 (MODIFY_EXPR, TREE_TYPE (count), count, + build_int_cst (NULL_TREE, + crtl->args.info * UNITS_PER_WORD)); + TREE_SIDE_EFFECTS (t) = 1; + expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); +} + +/* Implement the stdarg/varargs va_arg macro. VALIST is the variable + of type va_list as a tree, TYPE is the type passed to va_arg. + Note: This algorithm is documented in stormy-abi. */ + +static tree +xstormy16_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, + gimple_seq *post_p ATTRIBUTE_UNUSED) +{ + tree f_base, f_count; + tree base, count; + tree count_tmp, addr, t; + tree lab_gotaddr, lab_fromstack; + int size, size_of_reg_args, must_stack; + tree size_tree; + + f_base = TYPE_FIELDS (va_list_type_node); + f_count = DECL_CHAIN (f_base); + + base = build3 (COMPONENT_REF, TREE_TYPE (f_base), valist, f_base, NULL_TREE); + count = build3 (COMPONENT_REF, TREE_TYPE (f_count), valist, f_count, + NULL_TREE); + + must_stack = targetm.calls.must_pass_in_stack (TYPE_MODE (type), type); + size_tree = round_up (size_in_bytes (type), UNITS_PER_WORD); + gimplify_expr (&size_tree, pre_p, NULL, is_gimple_val, fb_rvalue); + + size_of_reg_args = NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD; + + count_tmp = get_initialized_tmp_var (count, pre_p, NULL); + lab_gotaddr = create_artificial_label (UNKNOWN_LOCATION); + lab_fromstack = create_artificial_label (UNKNOWN_LOCATION); + addr = create_tmp_var (ptr_type_node, NULL); + + if (!must_stack) + { + tree r; + + t = fold_convert (TREE_TYPE (count), size_tree); + t = build2 (PLUS_EXPR, TREE_TYPE (count), count_tmp, t); + r = fold_convert (TREE_TYPE (count), size_int (size_of_reg_args)); + t = build2 (GT_EXPR, boolean_type_node, t, r); + t = build3 (COND_EXPR, void_type_node, t, + build1 (GOTO_EXPR, void_type_node, lab_fromstack), + NULL_TREE); + gimplify_and_add (t, pre_p); + + t = fold_build_pointer_plus (base, count_tmp); + gimplify_assign (addr, t, pre_p); + + t = build1 (GOTO_EXPR, void_type_node, lab_gotaddr); + gimplify_and_add (t, pre_p); + + t = build1 (LABEL_EXPR, void_type_node, lab_fromstack); + gimplify_and_add (t, pre_p); + } + + /* Arguments larger than a word might need to skip over some + registers, since arguments are either passed entirely in + registers or entirely on the stack. */ + size = PUSH_ROUNDING (int_size_in_bytes (type)); + if (size > 2 || size < 0 || must_stack) + { + tree r, u; + + r = size_int (NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD); + u = build2 (MODIFY_EXPR, TREE_TYPE (count_tmp), count_tmp, r); + + t = fold_convert (TREE_TYPE (count), r); + t = build2 (GE_EXPR, boolean_type_node, count_tmp, t); + t = build3 (COND_EXPR, void_type_node, t, NULL_TREE, u); + gimplify_and_add (t, pre_p); + } + + t = size_int (NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD + + INCOMING_FRAME_SP_OFFSET); + t = fold_convert (TREE_TYPE (count), t); + t = build2 (MINUS_EXPR, TREE_TYPE (count), count_tmp, t); + t = build2 (PLUS_EXPR, TREE_TYPE (count), t, + fold_convert (TREE_TYPE (count), size_tree)); + t = fold_convert (TREE_TYPE (t), fold (t)); + t = fold_build1 (NEGATE_EXPR, TREE_TYPE (t), t); + t = fold_build_pointer_plus (base, t); + gimplify_assign (addr, t, pre_p); + + t = build1 (LABEL_EXPR, void_type_node, lab_gotaddr); + gimplify_and_add (t, pre_p); + + t = fold_convert (TREE_TYPE (count), size_tree); + t = build2 (PLUS_EXPR, TREE_TYPE (count), count_tmp, t); + gimplify_assign (count, t, pre_p); + + addr = fold_convert (build_pointer_type (type), addr); + return build_va_arg_indirect_ref (addr); +} + +/* Worker function for TARGET_TRAMPOLINE_INIT. */ + +static void +xstormy16_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain) +{ + rtx temp = gen_reg_rtx (HImode); + rtx reg_fnaddr = gen_reg_rtx (HImode); + rtx reg_addr, reg_addr_mem; + + reg_addr = copy_to_reg (XEXP (m_tramp, 0)); + reg_addr_mem = adjust_automodify_address (m_tramp, HImode, reg_addr, 0); + + emit_move_insn (temp, GEN_INT (0x3130 | STATIC_CHAIN_REGNUM)); + emit_move_insn (reg_addr_mem, temp); + emit_insn (gen_addhi3 (reg_addr, reg_addr, const2_rtx)); + reg_addr_mem = adjust_automodify_address (reg_addr_mem, VOIDmode, NULL, 2); + + emit_move_insn (temp, static_chain); + emit_move_insn (reg_addr_mem, temp); + emit_insn (gen_addhi3 (reg_addr, reg_addr, const2_rtx)); + reg_addr_mem = adjust_automodify_address (reg_addr_mem, VOIDmode, NULL, 2); + + emit_move_insn (reg_fnaddr, XEXP (DECL_RTL (fndecl), 0)); + emit_move_insn (temp, reg_fnaddr); + emit_insn (gen_andhi3 (temp, temp, GEN_INT (0xFF))); + emit_insn (gen_iorhi3 (temp, temp, GEN_INT (0x0200))); + emit_move_insn (reg_addr_mem, temp); + emit_insn (gen_addhi3 (reg_addr, reg_addr, const2_rtx)); + reg_addr_mem = adjust_automodify_address (reg_addr_mem, VOIDmode, NULL, 2); + + emit_insn (gen_lshrhi3 (reg_fnaddr, reg_fnaddr, GEN_INT (8))); + emit_move_insn (reg_addr_mem, reg_fnaddr); +} + +/* Worker function for TARGET_FUNCTION_VALUE. */ + +static rtx +xstormy16_function_value (const_tree valtype, + const_tree func ATTRIBUTE_UNUSED, + bool outgoing ATTRIBUTE_UNUSED) +{ + enum machine_mode mode; + mode = TYPE_MODE (valtype); + PROMOTE_MODE (mode, 0, valtype); + return gen_rtx_REG (mode, RETURN_VALUE_REGNUM); +} + +/* Worker function for TARGET_LIBCALL_VALUE. */ + +static rtx +xstormy16_libcall_value (enum machine_mode mode, + const_rtx fun ATTRIBUTE_UNUSED) +{ + return gen_rtx_REG (mode, RETURN_VALUE_REGNUM); +} + +/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. */ + +static bool +xstormy16_function_value_regno_p (const unsigned int regno) +{ + return (regno == RETURN_VALUE_REGNUM); +} + +/* A C compound statement that outputs the assembler code for a thunk function, + used to implement C++ virtual function calls with multiple inheritance. The + thunk acts as a wrapper around a virtual function, adjusting the implicit + object parameter before handing control off to the real function. + + First, emit code to add the integer DELTA to the location that contains the + incoming first argument. Assume that this argument contains a pointer, and + is the one used to pass the `this' pointer in C++. This is the incoming + argument *before* the function prologue, e.g. `%o0' on a sparc. The + addition must preserve the values of all other incoming arguments. + + After the addition, emit code to jump to FUNCTION, which is a + `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch + the return address. Hence returning from FUNCTION will return to whoever + called the current `thunk'. + + The effect must be as if @var{function} had been called directly + with the adjusted first argument. This macro is responsible for + emitting all of the code for a thunk function; + TARGET_ASM_FUNCTION_PROLOGUE and TARGET_ASM_FUNCTION_EPILOGUE are + not invoked. + + The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been + extracted from it.) It might possibly be useful on some targets, but + probably not. */ + +static void +xstormy16_asm_output_mi_thunk (FILE *file, + tree thunk_fndecl ATTRIBUTE_UNUSED, + HOST_WIDE_INT delta, + HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, + tree function) +{ + int regnum = FIRST_ARGUMENT_REGISTER; + + /* There might be a hidden first argument for a returned structure. */ + if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) + regnum += 1; + + fprintf (file, "\tadd %s,#0x%x\n", reg_names[regnum], (int) delta & 0xFFFF); + fputs ("\tjmpf ", file); + assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); + putc ('\n', file); +} + +/* The purpose of this function is to override the default behavior of + BSS objects. Normally, they go into .bss or .sbss via ".common" + directives, but we need to override that and put them in + .bss_below100. We can't just use a section override (like we do + for .data_below100), because that makes them initialized rather + than uninitialized. */ + +void +xstormy16_asm_output_aligned_common (FILE *stream, + tree decl, + const char *name, + int size, + int align, + int global) +{ + rtx mem = decl == NULL_TREE ? NULL_RTX : DECL_RTL (decl); + rtx symbol; + + if (mem != NULL_RTX + && MEM_P (mem) + && GET_CODE (symbol = XEXP (mem, 0)) == SYMBOL_REF + && SYMBOL_REF_FLAGS (symbol) & SYMBOL_FLAG_XSTORMY16_BELOW100) + { + const char *name2; + int p2align = 0; + + switch_to_section (bss100_section); + + while (align > 8) + { + align /= 2; + p2align ++; + } + + name2 = default_strip_name_encoding (name); + if (global) + fprintf (stream, "\t.globl\t%s\n", name2); + if (p2align) + fprintf (stream, "\t.p2align %d\n", p2align); + fprintf (stream, "\t.type\t%s, @object\n", name2); + fprintf (stream, "\t.size\t%s, %d\n", name2, size); + fprintf (stream, "%s:\n\t.space\t%d\n", name2, size); + return; + } + + if (!global) + { + fprintf (stream, "\t.local\t"); + assemble_name (stream, name); + fprintf (stream, "\n"); + } + fprintf (stream, "\t.comm\t"); + assemble_name (stream, name); + fprintf (stream, ",%u,%u\n", size, align / BITS_PER_UNIT); +} + +/* Implement TARGET_ASM_INIT_SECTIONS. */ + +static void +xstormy16_asm_init_sections (void) +{ + bss100_section + = get_unnamed_section (SECTION_WRITE | SECTION_BSS, + output_section_asm_op, + "\t.section \".bss_below100\",\"aw\",@nobits"); +} + +/* Mark symbols with the "below100" attribute so that we can use the + special addressing modes for them. */ + +static void +xstormy16_encode_section_info (tree decl, rtx r, int first) +{ + default_encode_section_info (decl, r, first); + + if (TREE_CODE (decl) == VAR_DECL + && (lookup_attribute ("below100", DECL_ATTRIBUTES (decl)) + || lookup_attribute ("BELOW100", DECL_ATTRIBUTES (decl)))) + { + rtx symbol = XEXP (r, 0); + + gcc_assert (GET_CODE (symbol) == SYMBOL_REF); + SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_XSTORMY16_BELOW100; + } +} + +#undef TARGET_ASM_CONSTRUCTOR +#define TARGET_ASM_CONSTRUCTOR xstormy16_asm_out_constructor +#undef TARGET_ASM_DESTRUCTOR +#define TARGET_ASM_DESTRUCTOR xstormy16_asm_out_destructor + +/* Output constructors and destructors. Just like + default_named_section_asm_out_* but don't set the sections writable. */ + +static void +xstormy16_asm_out_destructor (rtx symbol, int priority) +{ + const char *section = ".dtors"; + char buf[16]; + + /* ??? This only works reliably with the GNU linker. */ + if (priority != DEFAULT_INIT_PRIORITY) + { + sprintf (buf, ".dtors.%.5u", + /* Invert the numbering so the linker puts us in the proper + order; constructors are run from right to left, and the + linker sorts in increasing order. */ + MAX_INIT_PRIORITY - priority); + section = buf; + } + + switch_to_section (get_section (section, 0, NULL)); + assemble_align (POINTER_SIZE); + assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); +} + +static void +xstormy16_asm_out_constructor (rtx symbol, int priority) +{ + const char *section = ".ctors"; + char buf[16]; + + /* ??? This only works reliably with the GNU linker. */ + if (priority != DEFAULT_INIT_PRIORITY) + { + sprintf (buf, ".ctors.%.5u", + /* Invert the numbering so the linker puts us in the proper + order; constructors are run from right to left, and the + linker sorts in increasing order. */ + MAX_INIT_PRIORITY - priority); + section = buf; + } + + switch_to_section (get_section (section, 0, NULL)); + assemble_align (POINTER_SIZE); + assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); +} + +/* Worker function for TARGET_PRINT_OPERAND_ADDRESS. + + Print a memory address as an operand to reference that memory location. */ + +static void +xstormy16_print_operand_address (FILE *file, rtx address) +{ + HOST_WIDE_INT offset; + int pre_dec, post_inc; + + /* There are a few easy cases. */ + if (CONST_INT_P (address)) + { + fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (address) & 0xFFFF); + return; + } + + if (CONSTANT_P (address) || LABEL_P (address)) + { + output_addr_const (file, address); + return; + } + + /* Otherwise, it's hopefully something of the form + (plus:HI (pre_dec:HI (reg:HI ...)) (const_int ...)). */ + if (GET_CODE (address) == PLUS) + { + gcc_assert (CONST_INT_P (XEXP (address, 1))); + offset = INTVAL (XEXP (address, 1)); + address = XEXP (address, 0); + } + else + offset = 0; + + pre_dec = (GET_CODE (address) == PRE_DEC); + post_inc = (GET_CODE (address) == POST_INC); + if (pre_dec || post_inc) + address = XEXP (address, 0); + + gcc_assert (REG_P (address)); + + fputc ('(', file); + if (pre_dec) + fputs ("--", file); + fputs (reg_names [REGNO (address)], file); + if (post_inc) + fputs ("++", file); + if (offset != 0) + fprintf (file, "," HOST_WIDE_INT_PRINT_DEC, offset); + fputc (')', file); +} + +/* Worker function for TARGET_PRINT_OPERAND. + + Print an operand to an assembler instruction. */ + +static void +xstormy16_print_operand (FILE *file, rtx x, int code) +{ + switch (code) + { + case 'B': + /* There is either one bit set, or one bit clear, in X. + Print it preceded by '#'. */ + { + static int bits_set[8] = { 0, 1, 1, 2, 1, 2, 2, 3 }; + HOST_WIDE_INT xx = 1; + HOST_WIDE_INT l; + + if (CONST_INT_P (x)) + xx = INTVAL (x); + else + output_operand_lossage ("'B' operand is not constant"); + + /* GCC sign-extends masks with the MSB set, so we have to + detect all the cases that differ only in sign extension + beyond the bits we care about. Normally, the predicates + and constraints ensure that we have the right values. This + works correctly for valid masks. */ + if (bits_set[xx & 7] <= 1) + { + /* Remove sign extension bits. */ + if ((~xx & ~(HOST_WIDE_INT)0xff) == 0) + xx &= 0xff; + else if ((~xx & ~(HOST_WIDE_INT)0xffff) == 0) + xx &= 0xffff; + l = exact_log2 (xx); + } + else + { + /* Add sign extension bits. */ + if ((xx & ~(HOST_WIDE_INT)0xff) == 0) + xx |= ~(HOST_WIDE_INT)0xff; + else if ((xx & ~(HOST_WIDE_INT)0xffff) == 0) + xx |= ~(HOST_WIDE_INT)0xffff; + l = exact_log2 (~xx); + } + + if (l == -1) + output_operand_lossage ("'B' operand has multiple bits set"); + + fprintf (file, IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC, l); + return; + } + + case 'C': + /* Print the symbol without a surrounding @fptr(). */ + if (GET_CODE (x) == SYMBOL_REF) + assemble_name (file, XSTR (x, 0)); + else if (LABEL_P (x)) + output_asm_label (x); + else + xstormy16_print_operand_address (file, x); + return; + + case 'o': + case 'O': + /* Print the immediate operand less one, preceded by '#'. + For 'O', negate it first. */ + { + HOST_WIDE_INT xx = 0; + + if (CONST_INT_P (x)) + xx = INTVAL (x); + else + output_operand_lossage ("'o' operand is not constant"); + + if (code == 'O') + xx = -xx; + + fprintf (file, IMMEDIATE_PREFIX HOST_WIDE_INT_PRINT_DEC, xx - 1); + return; + } + + case 'b': + /* Print the shift mask for bp/bn. */ + { + HOST_WIDE_INT xx = 1; + HOST_WIDE_INT l; + + if (CONST_INT_P (x)) + xx = INTVAL (x); + else + output_operand_lossage ("'B' operand is not constant"); + + l = 7 - xx; + + fputs (IMMEDIATE_PREFIX, file); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, l); + return; + } + + case 0: + /* Handled below. */ + break; + + default: + output_operand_lossage ("xstormy16_print_operand: unknown code"); + return; + } + + switch (GET_CODE (x)) + { + case REG: + fputs (reg_names [REGNO (x)], file); + break; + + case MEM: + xstormy16_print_operand_address (file, XEXP (x, 0)); + break; + + default: + /* Some kind of constant or label; an immediate operand, + so prefix it with '#' for the assembler. */ + fputs (IMMEDIATE_PREFIX, file); + output_addr_const (file, x); + break; + } + + return; +} + +/* Expander for the `casesi' pattern. + INDEX is the index of the switch statement. + LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding + to the first table entry. + RANGE is the number of table entries. + TABLE is an ADDR_VEC that is the jump table. + DEFAULT_LABEL is the address to branch to if INDEX is outside the + range LOWER_BOUND to LOWER_BOUND + RANGE - 1. */ + +void +xstormy16_expand_casesi (rtx index, rtx lower_bound, rtx range, + rtx table, rtx default_label) +{ + HOST_WIDE_INT range_i = INTVAL (range); + rtx int_index; + + /* This code uses 'br', so it can deal only with tables of size up to + 8192 entries. */ + if (range_i >= 8192) + sorry ("switch statement of size %lu entries too large", + (unsigned long) range_i); + + index = expand_binop (SImode, sub_optab, index, lower_bound, NULL_RTX, 0, + OPTAB_LIB_WIDEN); + emit_cmp_and_jump_insns (index, range, GTU, NULL_RTX, SImode, 1, + default_label); + int_index = gen_lowpart_common (HImode, index); + emit_insn (gen_ashlhi3 (int_index, int_index, const2_rtx)); + emit_jump_insn (gen_tablejump_pcrel (int_index, table)); +} + +/* Output an ADDR_VEC. It is output as a sequence of 'jmpf' + instructions, without label or alignment or any other special + constructs. We know that the previous instruction will be the + `tablejump_pcrel' output above. + + TODO: it might be nice to output 'br' instructions if they could + all reach. */ + +void +xstormy16_output_addr_vec (FILE *file, rtx label ATTRIBUTE_UNUSED, rtx table) +{ + int vlen, idx; + + switch_to_section (current_function_section ()); + + vlen = XVECLEN (table, 0); + for (idx = 0; idx < vlen; idx++) + { + fputs ("\tjmpf ", file); + output_asm_label (XEXP (XVECEXP (table, 0, idx), 0)); + fputc ('\n', file); + } +} + +/* Expander for the `call' patterns. + RETVAL is the RTL for the return register or NULL for void functions. + DEST is the function to call, expressed as a MEM. + COUNTER is ignored. */ + +void +xstormy16_expand_call (rtx retval, rtx dest, rtx counter) +{ + rtx call, temp; + enum machine_mode mode; + + gcc_assert (MEM_P (dest)); + dest = XEXP (dest, 0); + + if (! CONSTANT_P (dest) && ! REG_P (dest)) + dest = force_reg (Pmode, dest); + + if (retval == NULL) + mode = VOIDmode; + else + mode = GET_MODE (retval); + + call = gen_rtx_CALL (mode, gen_rtx_MEM (FUNCTION_MODE, dest), + counter); + if (retval) + call = gen_rtx_SET (VOIDmode, retval, call); + + if (! CONSTANT_P (dest)) + { + temp = gen_reg_rtx (HImode); + emit_move_insn (temp, const0_rtx); + } + else + temp = const0_rtx; + + call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, + gen_rtx_USE (VOIDmode, temp))); + emit_call_insn (call); +} + +/* Expanders for multiword computational operations. */ + +/* Expander for arithmetic operations; emit insns to compute + + (set DEST (CODE:MODE SRC0 SRC1)) + + When CODE is COMPARE, a branch template is generated + (this saves duplicating code in xstormy16_split_cbranch). */ + +void +xstormy16_expand_arith (enum machine_mode mode, enum rtx_code code, + rtx dest, rtx src0, rtx src1) +{ + int num_words = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; + int i; + int firstloop = 1; + + if (code == NEG) + emit_move_insn (src0, const0_rtx); + + for (i = 0; i < num_words; i++) + { + rtx w_src0, w_src1, w_dest; + rtx insn; + + w_src0 = simplify_gen_subreg (word_mode, src0, mode, + i * UNITS_PER_WORD); + w_src1 = simplify_gen_subreg (word_mode, src1, mode, i * UNITS_PER_WORD); + w_dest = simplify_gen_subreg (word_mode, dest, mode, i * UNITS_PER_WORD); + + switch (code) + { + case PLUS: + if (firstloop + && CONST_INT_P (w_src1) + && INTVAL (w_src1) == 0) + continue; + + if (firstloop) + insn = gen_addchi4 (w_dest, w_src0, w_src1); + else + insn = gen_addchi5 (w_dest, w_src0, w_src1); + break; + + case NEG: + case MINUS: + case COMPARE: + if (code == COMPARE && i == num_words - 1) + { + rtx branch, sub, clobber, sub_1; + + sub_1 = gen_rtx_MINUS (HImode, w_src0, + gen_rtx_ZERO_EXTEND (HImode, gen_rtx_REG (BImode, CARRY_REGNUM))); + sub = gen_rtx_SET (VOIDmode, w_dest, + gen_rtx_MINUS (HImode, sub_1, w_src1)); + clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (BImode, CARRY_REGNUM)); + branch = gen_rtx_SET (VOIDmode, pc_rtx, + gen_rtx_IF_THEN_ELSE (VOIDmode, + gen_rtx_EQ (HImode, + sub_1, + w_src1), + pc_rtx, + pc_rtx)); + insn = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (3, branch, sub, clobber)); + } + else if (firstloop + && code != COMPARE + && CONST_INT_P (w_src1) + && INTVAL (w_src1) == 0) + continue; + else if (firstloop) + insn = gen_subchi4 (w_dest, w_src0, w_src1); + else + insn = gen_subchi5 (w_dest, w_src0, w_src1); + break; + + case IOR: + case XOR: + case AND: + if (CONST_INT_P (w_src1) + && INTVAL (w_src1) == -(code == AND)) + continue; + + insn = gen_rtx_SET (VOIDmode, w_dest, gen_rtx_fmt_ee (code, mode, + w_src0, w_src1)); + break; + + case NOT: + insn = gen_rtx_SET (VOIDmode, w_dest, gen_rtx_NOT (mode, w_src0)); + break; + + default: + gcc_unreachable (); + } + + firstloop = 0; + emit (insn); + } + + /* If we emit nothing, try_split() will think we failed. So emit + something that does nothing and can be optimized away. */ + if (firstloop) + emit (gen_nop ()); +} + +/* The shift operations are split at output time for constant values; + variable-width shifts get handed off to a library routine. + + Generate an output string to do (set X (CODE:MODE X SIZE_R)) + SIZE_R will be a CONST_INT, X will be a hard register. */ + +const char * +xstormy16_output_shift (enum machine_mode mode, enum rtx_code code, + rtx x, rtx size_r, rtx temp) +{ + HOST_WIDE_INT size; + const char *r0, *r1, *rt; + static char r[64]; + + gcc_assert (CONST_INT_P (size_r) + && REG_P (x) + && mode == SImode); + + size = INTVAL (size_r) & (GET_MODE_BITSIZE (mode) - 1); + + if (size == 0) + return ""; + + r0 = reg_names [REGNO (x)]; + r1 = reg_names [REGNO (x) + 1]; + + /* For shifts of size 1, we can use the rotate instructions. */ + if (size == 1) + { + switch (code) + { + case ASHIFT: + sprintf (r, "shl %s,#1 | rlc %s,#1", r0, r1); + break; + case ASHIFTRT: + sprintf (r, "asr %s,#1 | rrc %s,#1", r1, r0); + break; + case LSHIFTRT: + sprintf (r, "shr %s,#1 | rrc %s,#1", r1, r0); + break; + default: + gcc_unreachable (); + } + return r; + } + + /* For large shifts, there are easy special cases. */ + if (size == 16) + { + switch (code) + { + case ASHIFT: + sprintf (r, "mov %s,%s | mov %s,#0", r1, r0, r0); + break; + case ASHIFTRT: + sprintf (r, "mov %s,%s | asr %s,#15", r0, r1, r1); + break; + case LSHIFTRT: + sprintf (r, "mov %s,%s | mov %s,#0", r0, r1, r1); + break; + default: + gcc_unreachable (); + } + return r; + } + if (size > 16) + { + switch (code) + { + case ASHIFT: + sprintf (r, "mov %s,%s | mov %s,#0 | shl %s,#%d", + r1, r0, r0, r1, (int) size - 16); + break; + case ASHIFTRT: + sprintf (r, "mov %s,%s | asr %s,#15 | asr %s,#%d", + r0, r1, r1, r0, (int) size - 16); + break; + case LSHIFTRT: + sprintf (r, "mov %s,%s | mov %s,#0 | shr %s,#%d", + r0, r1, r1, r0, (int) size - 16); + break; + default: + gcc_unreachable (); + } + return r; + } + + /* For the rest, we have to do more work. In particular, we + need a temporary. */ + rt = reg_names [REGNO (temp)]; + switch (code) + { + case ASHIFT: + sprintf (r, + "mov %s,%s | shl %s,#%d | shl %s,#%d | shr %s,#%d | or %s,%s", + rt, r0, r0, (int) size, r1, (int) size, rt, (int) (16 - size), + r1, rt); + break; + case ASHIFTRT: + sprintf (r, + "mov %s,%s | asr %s,#%d | shr %s,#%d | shl %s,#%d | or %s,%s", + rt, r1, r1, (int) size, r0, (int) size, rt, (int) (16 - size), + r0, rt); + break; + case LSHIFTRT: + sprintf (r, + "mov %s,%s | shr %s,#%d | shr %s,#%d | shl %s,#%d | or %s,%s", + rt, r1, r1, (int) size, r0, (int) size, rt, (int) (16 - size), + r0, rt); + break; + default: + gcc_unreachable (); + } + return r; +} + +/* Attribute handling. */ + +/* Return nonzero if the function is an interrupt function. */ + +int +xstormy16_interrupt_function_p (void) +{ + tree attributes; + + /* The dwarf2 mechanism asks for INCOMING_FRAME_SP_OFFSET before + any functions are declared, which is demonstrably wrong, but + it is worked around here. FIXME. */ + if (!cfun) + return 0; + + attributes = TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)); + return lookup_attribute ("interrupt", attributes) != NULL_TREE; +} + +#undef TARGET_ATTRIBUTE_TABLE +#define TARGET_ATTRIBUTE_TABLE xstormy16_attribute_table + +static tree xstormy16_handle_interrupt_attribute + (tree *, tree, tree, int, bool *); +static tree xstormy16_handle_below100_attribute + (tree *, tree, tree, int, bool *); + +static const struct attribute_spec xstormy16_attribute_table[] = +{ + /* name, min_len, max_len, decl_req, type_req, fn_type_req, handler, + affects_type_identity. */ + { "interrupt", 0, 0, false, true, true, + xstormy16_handle_interrupt_attribute , false }, + { "BELOW100", 0, 0, false, false, false, + xstormy16_handle_below100_attribute, false }, + { "below100", 0, 0, false, false, false, + xstormy16_handle_below100_attribute, false }, + { NULL, 0, 0, false, false, false, NULL, false } +}; + +/* Handle an "interrupt" attribute; + arguments as in struct attribute_spec.handler. */ + +static tree +xstormy16_handle_interrupt_attribute (tree *node, tree name, + tree args ATTRIBUTE_UNUSED, + int flags ATTRIBUTE_UNUSED, + bool *no_add_attrs) +{ + if (TREE_CODE (*node) != FUNCTION_TYPE) + { + warning (OPT_Wattributes, "%qE attribute only applies to functions", + name); + *no_add_attrs = true; + } + + return NULL_TREE; +} + +/* Handle an "below" attribute; + arguments as in struct attribute_spec.handler. */ + +static tree +xstormy16_handle_below100_attribute (tree *node, + tree name ATTRIBUTE_UNUSED, + tree args ATTRIBUTE_UNUSED, + int flags ATTRIBUTE_UNUSED, + bool *no_add_attrs) +{ + if (TREE_CODE (*node) != VAR_DECL + && TREE_CODE (*node) != POINTER_TYPE + && TREE_CODE (*node) != TYPE_DECL) + { + warning (OPT_Wattributes, + "%<__BELOW100__%> attribute only applies to variables"); + *no_add_attrs = true; + } + else if (args == NULL_TREE && TREE_CODE (*node) == VAR_DECL) + { + if (! (TREE_PUBLIC (*node) || TREE_STATIC (*node))) + { + warning (OPT_Wattributes, "__BELOW100__ attribute not allowed " + "with auto storage class"); + *no_add_attrs = true; + } + } + + return NULL_TREE; +} + +#undef TARGET_INIT_BUILTINS +#define TARGET_INIT_BUILTINS xstormy16_init_builtins +#undef TARGET_EXPAND_BUILTIN +#define TARGET_EXPAND_BUILTIN xstormy16_expand_builtin + +static struct +{ + const char * name; + int md_code; + const char * arg_ops; /* 0..9, t for temp register, r for return value. */ + const char * arg_types; /* s=short,l=long, upper case for unsigned. */ +} + s16builtins[] = +{ + { "__sdivlh", CODE_FOR_sdivlh, "rt01", "sls" }, + { "__smodlh", CODE_FOR_sdivlh, "tr01", "sls" }, + { "__udivlh", CODE_FOR_udivlh, "rt01", "SLS" }, + { "__umodlh", CODE_FOR_udivlh, "tr01", "SLS" }, + { NULL, 0, NULL, NULL } +}; + +static void +xstormy16_init_builtins (void) +{ + tree args[2], ret_type, arg = NULL_TREE, ftype; + int i, a, n_args; + + ret_type = void_type_node; + + for (i = 0; s16builtins[i].name; i++) + { + n_args = strlen (s16builtins[i].arg_types) - 1; + + gcc_assert (n_args <= (int) ARRAY_SIZE (args)); + + for (a = n_args - 1; a >= 0; a--) + args[a] = NULL_TREE; + + for (a = n_args; a >= 0; a--) + { + switch (s16builtins[i].arg_types[a]) + { + case 's': arg = short_integer_type_node; break; + case 'S': arg = short_unsigned_type_node; break; + case 'l': arg = long_integer_type_node; break; + case 'L': arg = long_unsigned_type_node; break; + default: gcc_unreachable (); + } + if (a == 0) + ret_type = arg; + else + args[a-1] = arg; + } + ftype = build_function_type_list (ret_type, args[0], args[1], NULL_TREE); + add_builtin_function (s16builtins[i].name, ftype, + i, BUILT_IN_MD, NULL, NULL_TREE); + } +} + +static rtx +xstormy16_expand_builtin (tree exp, rtx target, + rtx subtarget ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED, + int ignore ATTRIBUTE_UNUSED) +{ + rtx op[10], args[10], pat, copyto[10], retval = 0; + tree fndecl, argtree; + int i, a, o, code; + + fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); + argtree = TREE_OPERAND (exp, 1); + i = DECL_FUNCTION_CODE (fndecl); + code = s16builtins[i].md_code; + + for (a = 0; a < 10 && argtree; a++) + { + args[a] = expand_normal (TREE_VALUE (argtree)); + argtree = TREE_CHAIN (argtree); + } + + for (o = 0; s16builtins[i].arg_ops[o]; o++) + { + char ao = s16builtins[i].arg_ops[o]; + char c = insn_data[code].operand[o].constraint[0]; + enum machine_mode omode; + + copyto[o] = 0; + + omode = (enum machine_mode) insn_data[code].operand[o].mode; + if (ao == 'r') + op[o] = target ? target : gen_reg_rtx (omode); + else if (ao == 't') + op[o] = gen_reg_rtx (omode); + else + op[o] = args[(int) hex_value (ao)]; + + if (! (*insn_data[code].operand[o].predicate) (op[o], GET_MODE (op[o]))) + { + if (c == '+' || c == '=') + { + copyto[o] = op[o]; + op[o] = gen_reg_rtx (omode); + } + else + op[o] = copy_to_mode_reg (omode, op[o]); + } + + if (ao == 'r') + retval = op[o]; + } + + pat = GEN_FCN (code) (op[0], op[1], op[2], op[3], op[4], + op[5], op[6], op[7], op[8], op[9]); + emit_insn (pat); + + for (o = 0; s16builtins[i].arg_ops[o]; o++) + if (copyto[o]) + { + emit_move_insn (copyto[o], op[o]); + if (op[o] == retval) + retval = copyto[o]; + } + + return retval; +} + +/* Look for combinations of insns that can be converted to BN or BP + opcodes. This is, unfortunately, too complex to do with MD + patterns. */ + +static void +combine_bnp (rtx insn) +{ + int insn_code, regno, need_extend; + unsigned int mask; + rtx cond, reg, and_insn, load, qireg, mem; + enum machine_mode load_mode = QImode; + enum machine_mode and_mode = QImode; + rtx shift = NULL_RTX; + + insn_code = recog_memoized (insn); + if (insn_code != CODE_FOR_cbranchhi + && insn_code != CODE_FOR_cbranchhi_neg) + return; + + cond = XVECEXP (PATTERN (insn), 0, 0); /* set */ + cond = XEXP (cond, 1); /* if */ + cond = XEXP (cond, 0); /* cond */ + switch (GET_CODE (cond)) + { + case NE: + case EQ: + need_extend = 0; + break; + case LT: + case GE: + need_extend = 1; + break; + default: + return; + } + + reg = XEXP (cond, 0); + if (! REG_P (reg)) + return; + regno = REGNO (reg); + if (XEXP (cond, 1) != const0_rtx) + return; + if (! find_regno_note (insn, REG_DEAD, regno)) + return; + qireg = gen_rtx_REG (QImode, regno); + + if (need_extend) + { + /* LT and GE conditionals should have a sign extend before + them. */ + for (and_insn = prev_real_insn (insn); + and_insn != NULL_RTX; + and_insn = prev_real_insn (and_insn)) + { + int and_code = recog_memoized (and_insn); + + if (and_code == CODE_FOR_extendqihi2 + && rtx_equal_p (SET_DEST (PATTERN (and_insn)), reg) + && rtx_equal_p (XEXP (SET_SRC (PATTERN (and_insn)), 0), qireg)) + break; + + if (and_code == CODE_FOR_movhi_internal + && rtx_equal_p (SET_DEST (PATTERN (and_insn)), reg)) + { + /* This is for testing bit 15. */ + and_insn = insn; + break; + } + + if (reg_mentioned_p (reg, and_insn)) + return; + + if (! NOTE_P (and_insn) && ! NONJUMP_INSN_P (and_insn)) + return; + } + } + else + { + /* EQ and NE conditionals have an AND before them. */ + for (and_insn = prev_real_insn (insn); + and_insn != NULL_RTX; + and_insn = prev_real_insn (and_insn)) + { + if (recog_memoized (and_insn) == CODE_FOR_andhi3 + && rtx_equal_p (SET_DEST (PATTERN (and_insn)), reg) + && rtx_equal_p (XEXP (SET_SRC (PATTERN (and_insn)), 0), reg)) + break; + + if (reg_mentioned_p (reg, and_insn)) + return; + + if (! NOTE_P (and_insn) && ! NONJUMP_INSN_P (and_insn)) + return; + } + + if (and_insn) + { + /* Some mis-optimizations by GCC can generate a RIGHT-SHIFT + followed by an AND like this: + + (parallel [(set (reg:HI r7) (lshiftrt:HI (reg:HI r7) (const_int 3))) + (clobber (reg:BI carry))] + + (set (reg:HI r7) (and:HI (reg:HI r7) (const_int 1))) + + Attempt to detect this here. */ + for (shift = prev_real_insn (and_insn); shift; + shift = prev_real_insn (shift)) + { + if (recog_memoized (shift) == CODE_FOR_lshrhi3 + && rtx_equal_p (SET_DEST (XVECEXP (PATTERN (shift), 0, 0)), reg) + && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (shift), 0, 0)), 0), reg)) + break; + + if (reg_mentioned_p (reg, shift) + || (! NOTE_P (shift) && ! NONJUMP_INSN_P (shift))) + { + shift = NULL_RTX; + break; + } + } + } + } + + if (and_insn == NULL_RTX) + return; + + for (load = shift ? prev_real_insn (shift) : prev_real_insn (and_insn); + load; + load = prev_real_insn (load)) + { + int load_code = recog_memoized (load); + + if (load_code == CODE_FOR_movhi_internal + && rtx_equal_p (SET_DEST (PATTERN (load)), reg) + && xstormy16_below100_operand (SET_SRC (PATTERN (load)), HImode) + && ! MEM_VOLATILE_P (SET_SRC (PATTERN (load)))) + { + load_mode = HImode; + break; + } + + if (load_code == CODE_FOR_movqi_internal + && rtx_equal_p (SET_DEST (PATTERN (load)), qireg) + && xstormy16_below100_operand (SET_SRC (PATTERN (load)), QImode)) + { + load_mode = QImode; + break; + } + + if (load_code == CODE_FOR_zero_extendqihi2 + && rtx_equal_p (SET_DEST (PATTERN (load)), reg) + && xstormy16_below100_operand (XEXP (SET_SRC (PATTERN (load)), 0), QImode)) + { + load_mode = QImode; + and_mode = HImode; + break; + } + + if (reg_mentioned_p (reg, load)) + return; + + if (! NOTE_P (load) && ! NONJUMP_INSN_P (load)) + return; + } + if (!load) + return; + + mem = SET_SRC (PATTERN (load)); + + if (need_extend) + { + mask = (load_mode == HImode) ? 0x8000 : 0x80; + + /* If the mem includes a zero-extend operation and we are + going to generate a sign-extend operation then move the + mem inside the zero-extend. */ + if (GET_CODE (mem) == ZERO_EXTEND) + mem = XEXP (mem, 0); + } + else + { + if (!xstormy16_onebit_set_operand (XEXP (SET_SRC (PATTERN (and_insn)), 1), + load_mode)) + return; + + mask = (int) INTVAL (XEXP (SET_SRC (PATTERN (and_insn)), 1)); + + if (shift) + mask <<= INTVAL (XEXP (SET_SRC (XVECEXP (PATTERN (shift), 0, 0)), 1)); + } + + if (load_mode == HImode) + { + rtx addr = XEXP (mem, 0); + + if (! (mask & 0xff)) + { + addr = plus_constant (Pmode, addr, 1); + mask >>= 8; + } + mem = gen_rtx_MEM (QImode, addr); + } + + if (need_extend) + XEXP (cond, 0) = gen_rtx_SIGN_EXTEND (HImode, mem); + else + XEXP (cond, 0) = gen_rtx_AND (and_mode, mem, GEN_INT (mask)); + + INSN_CODE (insn) = -1; + delete_insn (load); + + if (and_insn != insn) + delete_insn (and_insn); + + if (shift != NULL_RTX) + delete_insn (shift); +} + +static void +xstormy16_reorg (void) +{ + rtx insn; + + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + { + if (! JUMP_P (insn)) + continue; + combine_bnp (insn); + } +} + +/* Worker function for TARGET_RETURN_IN_MEMORY. */ + +static bool +xstormy16_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) +{ + const HOST_WIDE_INT size = int_size_in_bytes (type); + return (size == -1 || size > UNITS_PER_WORD * NUM_ARGUMENT_REGISTERS); +} + +#undef TARGET_ASM_ALIGNED_HI_OP +#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" +#undef TARGET_ASM_ALIGNED_SI_OP +#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" +#undef TARGET_ENCODE_SECTION_INFO +#define TARGET_ENCODE_SECTION_INFO xstormy16_encode_section_info + +/* Select_section doesn't handle .bss_below100. */ +#undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS +#define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS false + +#undef TARGET_ASM_OUTPUT_MI_THUNK +#define TARGET_ASM_OUTPUT_MI_THUNK xstormy16_asm_output_mi_thunk +#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK +#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall + +#undef TARGET_PRINT_OPERAND +#define TARGET_PRINT_OPERAND xstormy16_print_operand +#undef TARGET_PRINT_OPERAND_ADDRESS +#define TARGET_PRINT_OPERAND_ADDRESS xstormy16_print_operand_address + +#undef TARGET_MEMORY_MOVE_COST +#define TARGET_MEMORY_MOVE_COST xstormy16_memory_move_cost +#undef TARGET_RTX_COSTS +#define TARGET_RTX_COSTS xstormy16_rtx_costs +#undef TARGET_ADDRESS_COST +#define TARGET_ADDRESS_COST xstormy16_address_cost + +#undef TARGET_BUILD_BUILTIN_VA_LIST +#define TARGET_BUILD_BUILTIN_VA_LIST xstormy16_build_builtin_va_list +#undef TARGET_EXPAND_BUILTIN_VA_START +#define TARGET_EXPAND_BUILTIN_VA_START xstormy16_expand_builtin_va_start +#undef TARGET_GIMPLIFY_VA_ARG_EXPR +#define TARGET_GIMPLIFY_VA_ARG_EXPR xstormy16_gimplify_va_arg_expr + +#undef TARGET_PROMOTE_FUNCTION_MODE +#define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote +#undef TARGET_PROMOTE_PROTOTYPES +#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true + +#undef TARGET_FUNCTION_ARG +#define TARGET_FUNCTION_ARG xstormy16_function_arg +#undef TARGET_FUNCTION_ARG_ADVANCE +#define TARGET_FUNCTION_ARG_ADVANCE xstormy16_function_arg_advance + +#undef TARGET_RETURN_IN_MEMORY +#define TARGET_RETURN_IN_MEMORY xstormy16_return_in_memory +#undef TARGET_FUNCTION_VALUE +#define TARGET_FUNCTION_VALUE xstormy16_function_value +#undef TARGET_LIBCALL_VALUE +#define TARGET_LIBCALL_VALUE xstormy16_libcall_value +#undef TARGET_FUNCTION_VALUE_REGNO_P +#define TARGET_FUNCTION_VALUE_REGNO_P xstormy16_function_value_regno_p + +#undef TARGET_MACHINE_DEPENDENT_REORG +#define TARGET_MACHINE_DEPENDENT_REORG xstormy16_reorg + +#undef TARGET_PREFERRED_RELOAD_CLASS +#define TARGET_PREFERRED_RELOAD_CLASS xstormy16_preferred_reload_class +#undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS +#define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xstormy16_preferred_reload_class + +#undef TARGET_LEGITIMATE_ADDRESS_P +#define TARGET_LEGITIMATE_ADDRESS_P xstormy16_legitimate_address_p +#undef TARGET_MODE_DEPENDENT_ADDRESS_P +#define TARGET_MODE_DEPENDENT_ADDRESS_P xstormy16_mode_dependent_address_p + +#undef TARGET_CAN_ELIMINATE +#define TARGET_CAN_ELIMINATE xstormy16_can_eliminate + +#undef TARGET_TRAMPOLINE_INIT +#define TARGET_TRAMPOLINE_INIT xstormy16_trampoline_init + +struct gcc_target targetm = TARGET_INITIALIZER; + +#include "gt-stormy16.h" diff --git a/gcc-4.9/gcc/config/stormy16/stormy16.h b/gcc-4.9/gcc/config/stormy16/stormy16.h new file mode 100644 index 000000000..5bcc5d7e6 --- /dev/null +++ b/gcc-4.9/gcc/config/stormy16/stormy16.h @@ -0,0 +1,504 @@ +/* Xstormy16 cpu description. + Copyright (C) 1997-2014 Free Software Foundation, Inc. + Contributed by Red Hat, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + <http://www.gnu.org/licenses/>. */ + + +/* Driver configuration. */ + +#undef ASM_SPEC +#define ASM_SPEC "" + +#undef LINK_SPEC +#define LINK_SPEC "%{h*} %{v:-V} \ + %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}" + +/* For xstormy16: + - If -msim is specified, everything is built and linked as for the sim. + - If -T is specified, that linker script is used, and it should provide + appropriate libraries. + - If neither is specified, everything is built as for the sim, but no + I/O support is assumed. */ +#undef LIB_SPEC +#define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:%{!T*:-lnosys}} -)" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "crt0.o%s crti.o%s crtbegin.o%s" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtend.o%s crtn.o%s" + + +/* Run-time target specifications. */ + +#define TARGET_CPU_CPP_BUILTINS() \ + do \ + { \ + builtin_define_std ("xstormy16"); \ + builtin_assert ("machine=xstormy16"); \ + builtin_assert ("cpu=xstormy16"); \ + } \ + while (0) + +/* Storage Layout. */ + +#define BITS_BIG_ENDIAN 1 + +#define BYTES_BIG_ENDIAN 0 + +#define WORDS_BIG_ENDIAN 0 + +#define UNITS_PER_WORD 2 + +#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ + do \ + { \ + if (GET_MODE_CLASS (MODE) == MODE_INT \ + && GET_MODE_SIZE (MODE) < 2) \ + (MODE) = HImode; \ + } \ + while (0) + +#define PARM_BOUNDARY 16 + +#define STACK_BOUNDARY 16 + +#define FUNCTION_BOUNDARY 16 + +#define BIGGEST_ALIGNMENT 16 + +#define DATA_ALIGNMENT(TYPE, ALIGN) \ + (TREE_CODE (TYPE) == ARRAY_TYPE \ + && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ + && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) + +#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ + (TREE_CODE (EXP) == STRING_CST \ + && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) + +#define STRICT_ALIGNMENT 1 + +#define PCC_BITFIELD_TYPE_MATTERS 1 + +/* Layout of Source Language Data Types. */ + +#define INT_TYPE_SIZE 16 + +#define SHORT_TYPE_SIZE 16 + +#define LONG_TYPE_SIZE 32 + +#define LONG_LONG_TYPE_SIZE 64 + +#define FLOAT_TYPE_SIZE 32 + +#define DOUBLE_TYPE_SIZE 64 + +#define LONG_DOUBLE_TYPE_SIZE 64 + +#define DEFAULT_SIGNED_CHAR 0 + +#define SIZE_TYPE "unsigned int" + +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "long int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 32 + + +/* Register Basics. */ + +#define FIRST_PSEUDO_REGISTER 19 + +#define FIXED_REGISTERS \ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 } + +#define CALL_USED_REGISTERS \ + { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1 } + + +/* Order of allocation of registers. */ + +#define REG_ALLOC_ORDER { 7, 6, 5, 4, 3, 2, 1, 0, 9, 8, 10, 11, 12, 13, 14, 15, 16 } + + +/* How Values Fit in Registers. */ + +#define HARD_REGNO_NREGS(REGNO, MODE) \ + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + +#define HARD_REGNO_MODE_OK(REGNO, MODE) ((REGNO) != 16 || (MODE) == BImode) + +/* A C expression that is nonzero if it is desirable to choose register + allocation so as to avoid move instructions between a value of mode MODE1 + and a value of mode MODE2. + + If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are + ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be + zero. */ +#define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) != BImode && (MODE2) != BImode) + + +/* Register Classes. */ + +enum reg_class +{ + NO_REGS, + R0_REGS, + R1_REGS, + TWO_REGS, + R2_REGS, + EIGHT_REGS, + R8_REGS, + ICALL_REGS, + GENERAL_REGS, + ALL_REGS, + LIM_REG_CLASSES +}; + +#define N_REG_CLASSES ((int) LIM_REG_CLASSES) + +#define REG_CLASS_NAMES \ +{ \ + "NO_REGS", \ + "R0_REGS", \ + "R1_REGS", \ + "TWO_REGS", \ + "R2_REGS", \ + "EIGHT_REGS", \ + "R8_REGS", \ + "ICALL_REGS", \ + "GENERAL_REGS", \ + "ALL_REGS" \ +} + +#define REG_CLASS_CONTENTS \ +{ \ + { 0x00000 }, \ + { 0x00001 }, \ + { 0x00002 }, \ + { 0x00003 }, \ + { 0x00004 }, \ + { 0x000FF }, \ + { 0x00100 }, \ + { 0x00300 }, \ + { 0x6FFFF }, \ + { (1 << FIRST_PSEUDO_REGISTER) - 1 } \ +} + +#define REGNO_REG_CLASS(REGNO) \ + ( (REGNO) == 0 ? R0_REGS \ + : (REGNO) == 1 ? R1_REGS \ + : (REGNO) == 2 ? R2_REGS \ + : (REGNO) < 8 ? EIGHT_REGS \ + : (REGNO) == 8 ? R8_REGS \ + : (REGNO) <= 18 ? GENERAL_REGS \ + : ALL_REGS) + +#define BASE_REG_CLASS GENERAL_REGS + +#define INDEX_REG_CLASS GENERAL_REGS + +#define REGNO_OK_FOR_BASE_P(NUM) 1 + +#define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM) + +/* This chip has the interesting property that only the first eight + registers can be moved to/from memory. */ +#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ + xstormy16_secondary_reload_class (CLASS, MODE, X) + + +/* Basic Stack Layout. */ + +/* We want to use post-increment instructions to push things on the stack, + because we don't have any pre-increment ones. */ +#define STACK_PUSH_CODE POST_INC + +#define FRAME_GROWS_DOWNWARD 0 + +#define ARGS_GROW_DOWNWARD 1 + +#define STARTING_FRAME_OFFSET 0 + +#define FIRST_PARM_OFFSET(FUNDECL) 0 + +#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \ + ((COUNT) == 0 \ + ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ + : NULL_RTX) + +#define INCOMING_RETURN_ADDR_RTX \ + gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-4))) + +#define INCOMING_FRAME_SP_OFFSET (xstormy16_interrupt_function_p () ? -6 : -4) + + +/* Register That Address the Stack Frame. */ + +#define STATIC_CHAIN_REGNUM 1 +#define HARD_FRAME_POINTER_REGNUM 13 +#define STACK_POINTER_REGNUM 15 +#define CARRY_REGNUM 16 +#define FRAME_POINTER_REGNUM 17 +#define ARG_POINTER_REGNUM 18 + + +/* Eliminating the Frame Pointer and the Arg Pointer. */ + +#define ELIMINABLE_REGS \ +{ \ + {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ + {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ +} + +#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ + (OFFSET) = xstormy16_initial_elimination_offset (FROM, TO) + + +/* Passing Function Arguments on the Stack. */ + +#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) + + +/* Function Arguments in Registers. */ + +#define NUM_ARGUMENT_REGISTERS 6 +#define FIRST_ARGUMENT_REGISTER 2 + +#define XSTORMY16_WORD_SIZE(TYPE, MODE) \ + ((((TYPE) ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ + + 1) \ + / 2) + +/* For this platform, the value of CUMULATIVE_ARGS is the number of words + of arguments that have been passed in registers so far. */ +#define CUMULATIVE_ARGS int + +#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ + (CUM) = 0 + +#define FUNCTION_ARG_REGNO_P(REGNO) \ + ((REGNO) >= FIRST_ARGUMENT_REGISTER \ + && (REGNO) < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS) + + +/* How Scalar Function Values are Returned. */ + +/* The number of the hard register that is used to return a scalar value from a + function call. */ +#define RETURN_VALUE_REGNUM FIRST_ARGUMENT_REGISTER + + +/* Function Entry and Exit. */ + +#define EPILOGUE_USES(REGNO) \ + xstormy16_epilogue_uses (REGNO) + + +/* Generating Code for Profiling. */ + +/* This declaration must be present, but it can be an abort if profiling is + not implemented. */ + +#define FUNCTION_PROFILER(FILE, LABELNO) xstormy16_function_profiler () + + +/* Trampolines for Nested Functions. */ + +#define TRAMPOLINE_SIZE 8 +#define TRAMPOLINE_ALIGNMENT 16 + + +/* Addressing Modes. */ + +#define HAVE_POST_INCREMENT 1 + +#define HAVE_PRE_DECREMENT 1 + +#define MAX_REGS_PER_ADDRESS 1 + + +/* Describing Relative Costs of Operations. */ + +#define BRANCH_COST(speed_p, predictable_p) 5 + +#define SLOW_BYTE_ACCESS 0 + +#define NO_FUNCTION_CSE + + +/* Dividing the output into sections. */ + +#define TEXT_SECTION_ASM_OP ".text" + +#define DATA_SECTION_ASM_OP ".data" + +#define BSS_SECTION_ASM_OP "\t.section\t.bss" + +/* Define the pseudo-ops used to switch to the .ctors and .dtors sections. + There are no shared libraries on this target so these sections need + not be writable. + + Defined in elfos.h. */ + +#undef CTORS_SECTION_ASM_OP +#undef DTORS_SECTION_ASM_OP +#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\"" +#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\"" + +#define TARGET_ASM_INIT_SECTIONS xstormy16_asm_init_sections + +#define JUMP_TABLES_IN_TEXT_SECTION 1 + +/* The Overall Framework of an Assembler File. */ + +#define ASM_COMMENT_START ";" + +#define ASM_APP_ON "#APP\n" + +#define ASM_APP_OFF "#NO_APP\n" + +/* Output of Data. */ + +#define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '|') + +#define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ + xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1) +#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ + xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0) + + +/* Output and Generation of Labels. */ +#define SYMBOL_FLAG_XSTORMY16_BELOW100 (SYMBOL_FLAG_MACH_DEP << 0) + +#define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL) \ + do \ + { \ + const char *rn = XSTR (SYMBOL, 0); \ + \ + if (SYMBOL_REF_FUNCTION_P (SYMBOL)) \ + ASM_OUTPUT_LABEL_REF ((STREAM), rn); \ + else \ + assemble_name (STREAM, rn); \ + } \ + while (0) + +#define ASM_OUTPUT_LABEL_REF(STREAM, NAME) \ + do \ + { \ + fputs ("@fptr(", STREAM); \ + assemble_name (STREAM, NAME); \ + fputc (')', STREAM); \ + } \ + while (0) + +/* Globalizing directive for a label. */ +#define GLOBAL_ASM_OP "\t.globl " + + +/* Output of Assembler Instructions. */ + +#define REGISTER_NAMES \ +{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \ + "r11", "r12", "r13", "psw", "sp", "carry", "fp", "ap" } + +#define ADDITIONAL_REGISTER_NAMES \ + { { "r14", 14 }, \ + { "r15", 15 } } + +#define REGISTER_PREFIX "" +#define LOCAL_LABEL_PREFIX "." +#define USER_LABEL_PREFIX "" +#define IMMEDIATE_PREFIX "#" + +#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ + fprintf (STREAM, "\tpush %d\n", REGNO) + +#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ + fprintf (STREAM, "\tpop %d\n", REGNO) + + +/* Output of dispatch tables. */ + +/* This port does not use the ASM_OUTPUT_ADDR_VEC_ELT macro, because + this could cause label alignment to appear between the 'br' and the table, + which would be bad. Instead, it controls the output of the table + itself. */ +#define ASM_OUTPUT_ADDR_VEC(LABEL, BODY) \ + xstormy16_output_addr_vec (file, LABEL, BODY) + +/* Alignment for ADDR_VECs is the same as for code. */ +#define ADDR_VEC_ALIGN(ADDR_VEC) 1 + + +/* Assembler Commands for Exception Regions. */ + +#define DWARF2_UNWIND_INFO 0 +#define DWARF_CIE_DATA_ALIGNMENT 1 + +/* Assembler Commands for Alignment. */ + +#define ASM_OUTPUT_ALIGN(STREAM, POWER) \ + fprintf ((STREAM), "\t.p2align %d\n", (POWER)) + + +/* Macros Affecting all Debug Formats. */ + +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG + + +/* Macros for SDB and Dwarf Output. */ + +/* Define this macro if addresses in Dwarf 2 debugging info should not + be the same size as pointers on the target architecture. The + macro's value should be the size, in bytes, to use for addresses in + the debugging info. + + Some architectures use word addresses to refer to code locations, + but Dwarf 2 info always uses byte addresses. On such machines, + Dwarf 2 addresses need to be larger than the architecture's + pointers. */ +#define DWARF2_ADDR_SIZE 4 + + +/* Miscellaneous Parameters. */ + +#define CASE_VECTOR_MODE SImode + +#define WORD_REGISTER_OPERATIONS + +#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND + +#define MOVE_MAX 2 + +#define SHIFT_COUNT_TRUNCATED 1 + +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 + +#define Pmode HImode + +#define FUNCTION_MODE HImode + +#define NO_IMPLICIT_EXTERN_C diff --git a/gcc-4.9/gcc/config/stormy16/stormy16.md b/gcc-4.9/gcc/config/stormy16/stormy16.md new file mode 100644 index 000000000..c19321365 --- /dev/null +++ b/gcc-4.9/gcc/config/stormy16/stormy16.md @@ -0,0 +1,1250 @@ +;; XSTORMY16 Machine description template +;; Copyright (C) 1997-2014 Free Software Foundation, Inc. +;; Contributed by Red Hat, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. + +;; Constraints +;; a $0 +;; b $1 +;; c $2 +;; d $8 +;; e $0..$7 +;; t $0..$1 +;; z $8..$9 +;; I 0..3 +;; J 2**N mask +;; K 2**N antimask +;; L 0..255 +;; M -255..0 +;; N -3..0 +;; O 1..4 +;; P -4..-1 +;; Q post-inc mem (push) +;; R pre-dec mem (pop) +;; S immediate mem +;; T Rx +;; U -inf..1 or 16..inf +;; Z 0 + +(define_constants + [ + (CARRY_REG 16) + ] +) + +;; :::::::::::::::::::: +;; :: +;; :: Attributes +;; :: +;; :::::::::::::::::::: + +; Categorize branches for the conditional in the length attribute. +(define_attr "branch_class" "notdirectbranch,br12,bcc12,bcc8p2,bcc8p4" + (const_string "notdirectbranch")) + +; The length of an instruction, used for branch shortening. +(define_attr "length" "" + (cond + [(eq_attr "branch_class" "br12") + (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -2046)) + (lt (minus (match_dup 0) (pc)) (const_int 2048))) + (const_int 2) + (const_int 4)) + (eq_attr "branch_class" "bcc12") + (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -2044)) + (lt (minus (match_dup 0) (pc)) (const_int 2048))) + (const_int 4) + (const_int 8)) + (eq_attr "branch_class" "bcc8p2") + (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -124)) + (lt (minus (match_dup 0) (pc)) (const_int 128))) + (const_int 4) + (const_int 8)) + (eq_attr "branch_class" "bcc8p4") + (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -122)) + (lt (minus (match_dup 0) (pc)) (const_int 128))) + (const_int 6) + (const_int 10))] + (const_int 2))) + +; The operand which determines the setting of Rpsw. +; The numbers indicate the operand number, +; 'clobber' indicates it is changed in some unspecified way +; 'nop' means it is not changed. +(define_attr "psw_operand" "clobber,nop,0,1,2,3,4" (const_string "0")) + +(define_asm_attributes [(set_attr "length" "4") + (set_attr "psw_operand" "clobber")]) + +(include "predicates.md") +(include "constraints.md") + +;; :::::::::::::::::::: +;; :: +;; :: Moves +;; :: +;; :::::::::::::::::::: +;; push/pop qi and hi are here as separate insns rather than part of +;; the movqi/hi patterns because we need to ensure that reload isn't +;; passed anything it can't cope with. Without these patterns, we +;; might end up with + +;; (set (mem (post_inc (sp))) mem (post_inc (reg))) + +;; If, in this example, reg needs reloading, reload will read reg from +;; the stack , adjust sp, and store reg back at what is now the wrong +;; offset. By using separate patterns for push and pop we ensure that +;; insns like this one are never generated. + +(define_insn "pushqi1" + [(set (mem:QI (post_inc:HI (reg:HI 15))) + (match_operand:QI 0 "register_operand" "r"))] + "" + "push %0" + [(set_attr "psw_operand" "nop") + (set_attr "length" "2")]) + +(define_insn "popqi1" + [(set (match_operand:QI 0 "register_operand" "=r") + (mem:QI (pre_dec:HI (reg:HI 15))))] + "" + "pop %0" + [(set_attr "psw_operand" "nop") + (set_attr "length" "2")]) + +(define_expand "movqi" + [(set (match_operand:QI 0 "nonimmediate_nonstack_operand" "") + (match_operand:QI 1 "general_operand" ""))] + "" + { xstormy16_expand_move (QImode, operands[0], operands[1]); + DONE; + }) + +(define_insn "movqi_internal" + [(set (match_operand:QI 0 "nonimmediate_nonstack_operand" "=r,m,e,e,T,r,S,W,e") + (match_operand:QI 1 "general_operand" "r,e,m,i,i,i,i,ie,W"))] + "" + "@ + mov %0,%1 + mov.b %0,%1 + mov.b %0,%1 + mov %0,%1 + mov Rx,%1 + mov %0,%1 + mov.b %0,%1 + mov.b %0,%1 + mov.b %0,%1" + [(set_attr_alternative "length" + [(const_int 2) + (if_then_else (match_operand:QI 0 "short_memory_operand" "") + (const_int 2) + (const_int 4)) + (if_then_else (match_operand:QI 1 "short_memory_operand" "") + (const_int 2) + (const_int 4)) + (const_int 2) + (const_int 2) + (const_int 4) + (const_int 4) + (const_int 2) + (const_int 2)]) + (set_attr "psw_operand" "0,0,0,0,nop,0,nop,0,0")]) + +(define_insn "pushhi1" + [(set (mem:HI (post_inc:HI (reg:HI 15))) + (match_operand:HI 0 "register_operand" "r"))] + "" + "push %0" + [(set_attr "psw_operand" "nop") + (set_attr "length" "2")]) + +(define_insn "pophi1" + [(set (match_operand:HI 0 "register_operand" "=r") + (mem:HI (pre_dec:HI (reg:HI 15))))] + "" + "pop %0" + [(set_attr "psw_operand" "nop") + (set_attr "length" "2")]) + +(define_expand "movhi" + [(set (match_operand:HI 0 "nonimmediate_nonstack_operand" "") + (match_operand:HI 1 "xs_hi_general_operand" ""))] + "" + { xstormy16_expand_move (HImode, operands[0], operands[1]); + DONE; + }) + +(define_insn "movhi_internal" + [(set (match_operand:HI 0 "nonimmediate_nonstack_operand" "=r,m,e,e,T,r,S,W,e") + (match_operand:HI 1 "xs_hi_general_operand" "r,e,m,L,L,i,i,ie,W"))] + "" + "@ + mov %0,%1 + mov.w %0,%1 + mov.w %0,%1 + mov.w %0,%1 + mov.w Rx,%1 + mov.w %0,%1 + mov.w %0,%1 + mov.w %0,%1 + mov.w %0,%1" + [(set_attr_alternative "length" + [(const_int 2) + (if_then_else (match_operand:QI 0 "short_memory_operand" "") + (const_int 2) + (const_int 4)) + (if_then_else (match_operand:QI 1 "short_memory_operand" "") + (const_int 2) + (const_int 4)) + (const_int 2) + (const_int 2) + (const_int 4) + (const_int 4) + (const_int 4) + (const_int 4)]) + (set_attr "psw_operand" "0,0,0,0,nop,0,nop,0,0")]) + +(define_expand "movsi" + [(set (match_operand:SI 0 "nonimmediate_operand" "") + (match_operand:SI 1 "general_operand" ""))] + "" + { xstormy16_expand_move (SImode, operands[0], operands[1]); + DONE; + }) + +(define_insn_and_split "*movsi_internal" + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,Q,r,m,e,&e,e,r,S") + (match_operand:SI 1 "general_operand" "r,r,R,e,o, V,L,i,i"))] + "" + "#" + "reload_completed" + [(pc)] + { xstormy16_split_move (SImode, operands[0], operands[1]); + DONE; + } + [(set_attr_alternative "length" + [(const_int 4) + (const_int 4) + (const_int 4) + (if_then_else (match_operand:QI 0 "short_memory_operand" "") + (const_int 6) + (const_int 8)) + (if_then_else (match_operand:QI 1 "short_memory_operand" "") + (const_int 6) + (const_int 8)) + (if_then_else (match_operand:QI 1 "short_memory_operand" "") + (const_int 6) + (const_int 8)) + (const_int 4) + (const_int 8) + (const_int 8)])]) + +;; :::::::::::::::::::: +;; :: +;; :: Conversions +;; :: +;; :::::::::::::::::::: + +(define_insn "extendqihi2" + [(set (match_operand:HI 0 "register_operand" "=r") + (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))] + "" + "cbw %0") + +(define_insn "zero_extendqihi2" + [(set (match_operand:HI 0 "register_operand" "=e,r") + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,0")))] + "" + "@ + mov.b %0, %1 + shl %0,#8\n\tshr %0,#8" + [(set_attr "psw_operand" "nop,0") + (set_attr_alternative "length" + [(const_int 4) + (const_int 8)])]) + +;; :::::::::::::::::::: +;; :: +;; :: Bit field extraction +;; :: +;; :::::::::::::::::::: + +;; Extract an unsigned bit field +;(define_insn "extzv" +; [(set (match_operand:SI 0 "register_operand" "=r") +; (zero_extract:SI (match_operand:SI 1 "register_operand" "r") +; (match_operand:SI 2 "const_int_operand" "n") +; (match_operand:SI 3 "const_int_operand" "n")))] +; "" +; "extzv %0,%1,%2,%3" +; [(set_attr "length" "4")]) + +;; Insert a bit field +;(define_insn "insv" +; [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") +; (match_operand:SI 1 "const_int_operand" "n") +; (match_operand:SI 2 "const_int_operand" "n")) +; (match_operand:SI 3 "nonmemory_operand" "ri"))] +; "" +; "insv %0,%1,%2,%3" +; [(set_attr "length" "4")]) + + +;; :::::::::::::::::::: +;; :: +;; :: 16-bit Integer arithmetic +;; :: +;; :::::::::::::::::::: + +;; Addition +; Note - the early clobber modifier is no longer needed on operand 3 +; and in fact can cause some reload spill failures if it is present. +; Note that the 'Z' constraint matches "add $reg,0", which reload +; will occasionally emit. We avoid the "add $reg,imm" match because +; it clobbers the carry. +(define_insn "addhi3" + [(set (match_operand:HI 0 "register_operand" "=r,r,r,T,T,r,r,r") + (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,0,0") + (match_operand:HI 2 "xs_hi_nonmemory_operand" "O,P,Z,L,M,Ir,N,i"))) + (clobber (reg:BI CARRY_REG))] + "" + "@ + inc %0,%o2 + dec %0,%O2 + ; + add Rx,%2 + sub Rx,#%n2 + add %0,%2 + sub %0,#%n2 + add %0,%2" + [(set_attr "length" "2,2,0,2,2,2,2,4")]) + +(define_insn "addchi4" + [(set (match_operand:HI 0 "register_operand" "=T,r,r") + (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0") + (match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i"))) + (set (reg:BI CARRY_REG) + (truncate:BI (lshiftrt:SI (plus:SI (zero_extend:SI (match_dup 1)) + (zero_extend:SI (match_dup 2))) + (const_int 16))))] + "" + "@ + add Rx,%2 + add %0,%2 + add %0,%2" + [(set_attr "length" "2,2,4")]) + +(define_insn "addchi5" + [(set (match_operand:HI 0 "register_operand" "=T,r,r") + (plus:HI (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0") + (zero_extend:HI (reg:BI CARRY_REG))) + (match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i"))) + (set (reg:BI CARRY_REG) + (truncate:BI (lshiftrt:SI (plus:SI (plus:SI + (zero_extend:SI (match_dup 1)) + (zero_extend:SI (reg:BI CARRY_REG))) + (zero_extend:SI (match_dup 2))) + (const_int 16))))] + "" + "@ + adc Rx,%2 + adc %0,%2 + adc %0,%2" + [(set_attr "length" "2,2,4")]) + +;; Subtraction +; Operand 3 is marked earlyclobber because that helps reload +; to generate better code---this pattern will never need the +; carry register as an input, and some output reloads or input +; reloads might need to use it. In fact, without the '&' reload +; will fail in some cases. +(define_insn "subhi3" + [(set (match_operand:HI 0 "register_operand" "=r,r,T,T,r,r,r") + (minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0,0,0,0") + (match_operand:HI 2 "xs_hi_nonmemory_operand" "O,P,L,M,rI,M,i"))) + (clobber (reg:BI CARRY_REG))] + "" + "@ + dec %0,%o2 + inc %0,%O2 + sub Rx,%2 + add Rx,#%n2 + sub %0,%2 + add %0,#%n2 + sub %0,%2" + [(set_attr "length" "2,2,2,2,2,2,4")]) + +(define_insn "subchi4" + [(set (match_operand:HI 0 "register_operand" "=T,r,r") + (minus:HI (match_operand:HI 1 "register_operand" "0,0,0") + (match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i"))) + (set (reg:BI CARRY_REG) + (truncate:BI (lshiftrt:SI (minus:SI (zero_extend:SI (match_dup 1)) + (zero_extend:SI (match_dup 2))) + (const_int 16))))] + "" + "@ + sub Rx,%2 + sub %0,%2 + sub %0,%2" + [(set_attr "length" "2,2,4")]) + +(define_insn "subchi5" + [(set (match_operand:HI 0 "register_operand" "=T,r,r") + (minus:HI (minus:HI (match_operand:HI 1 "register_operand" "0,0,0") + (zero_extend:HI (reg:BI CARRY_REG))) + (match_operand:HI 2 "xs_hi_nonmemory_operand" "L,Ir,i"))) + (set (reg:BI CARRY_REG) + (truncate:BI (lshiftrt:SI (minus:SI (minus:SI + (zero_extend:SI (match_dup 1)) + (zero_extend:SI (reg:BI CARRY_REG))) + (zero_extend:SI (match_dup 2))) + (const_int 16))))] + "" + "@ + sbc Rx,%2 + sbc %0,%2 + sbc %0,%2" + [(set_attr "length" "2,2,4")]) + +; Basic multiplication +(define_insn "mulhi3" + [(set (match_operand:HI 0 "register_operand" "=a") + (mult:HI (match_operand:HI 1 "register_operand" "%a") + (match_operand:HI 2 "register_operand" "c"))) + (clobber (match_scratch:HI 3 "=b")) + ] + "" + "mul" + [(set_attr "psw_operand" "nop")]) + +;; Unsigned multiplication producing 64-bit results from 32-bit inputs +; The constraint on operand 0 is 't' because it is actually two regs +; long, and both regs must match the constraint. +(define_insn "umulhisi3" + [(set (match_operand:SI 0 "register_operand" "=t") + (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%a")) + (zero_extend:SI (match_operand:HI 2 "register_operand" "c")))) + ] + "" + "mul" + [(set_attr "psw_operand" "nop")]) + +;; Unsigned division giving both quotient and remainder +(define_insn "udivmodhi4" + [(set (match_operand:HI 0 "register_operand" "=a") + (udiv:HI (match_operand:HI 1 "register_operand" "a") + (match_operand:HI 2 "register_operand" "c"))) + (set (match_operand:HI 3 "register_operand" "=b") + (umod:HI (match_dup 1) + (match_dup 2)))] + "" + "div" + [(set_attr "psw_operand" "nop")]) + +;; Signed division giving both quotient and remainder +(define_insn "divmodhi4" + [(set (match_operand:HI 0 "register_operand" "=a") + (div:HI (match_operand:HI 1 "register_operand" "a") + (match_operand:HI 2 "register_operand" "c"))) + (set (match_operand:HI 3 "register_operand" "=b") + (mod:HI (match_dup 1) + (match_dup 2)))] + "" + "sdiv" + [(set_attr "psw_operand" "nop")]) + +;; Signed 32/16 division +(define_insn "sdivlh" + [(set (match_operand:HI 0 "register_operand" "=a") + (div:HI (match_operand:SI 2 "register_operand" "t") + (match_operand:HI 3 "register_operand" "c"))) + (set (match_operand:HI 1 "register_operand" "=b") + (mod:HI (match_dup 2) + (match_dup 3)))] + "" + "sdivlh" + [(set_attr "psw_operand" "nop")]) + +;; Unsigned 32/16 division +(define_insn "udivlh" + [(set (match_operand:HI 0 "register_operand" "=a") + (udiv:HI (match_operand:SI 2 "register_operand" "t") + (match_operand:HI 3 "register_operand" "c"))) + (set (match_operand:HI 1 "register_operand" "=b") + (umod:HI (match_dup 2) + (match_dup 3)))] + "" + "divlh" + [(set_attr "psw_operand" "nop")]) + +;; Negation + +(define_expand "neghi2" + [(set (match_operand:HI 0 "register_operand" "") + (not:HI (match_operand:HI 1 "register_operand" ""))) + (parallel [(set (match_dup 0) (plus:HI (match_dup 0) (const_int 1))) + (clobber (reg:BI CARRY_REG))])] + "" + "") + +;; :::::::::::::::::::: +;; :: +;; :: 16-bit Integer Shifts and Rotates +;; :: +;; :::::::::::::::::::: + +;; Arithmetic Shift Left +(define_insn "ashlhi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (ashift:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "nonmemory_operand" "ri"))) + (clobber (reg:BI CARRY_REG))] + "" + "shl %0,%2") + +;; Arithmetic Shift Right +(define_insn "ashrhi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "nonmemory_operand" "ri"))) + (clobber (reg:BI CARRY_REG))] + "" + "asr %0,%2") + +;; Logical Shift Right +(define_insn "lshrhi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "nonmemory_operand" "ri"))) + (clobber (reg:BI CARRY_REG))] + "" + "shr %0,%2") + +;; :::::::::::::::::::: +;; :: +;; :: 16-Bit Integer Logical operations +;; :: +;; :::::::::::::::::::: + +;; Logical AND, 16-bit integers +(define_insn "andhi3" + [(set (match_operand:HI 0 "xstormy16_splittable_below100_or_register" "=T,r,r,r,W") + (and:HI (match_operand:HI 1 "xstormy16_below100_or_register" "%0,0,0,0,0") + (match_operand:HI 2 "nonmemory_operand" "L,r,K,i,K")))] + "" + "@ + and Rx,%2 + and %0,%2 + clr1 %0,%B2 + and %0,%2 + #" + [(set_attr "length" "2,2,2,4,2")]) + +(define_split + [(set (match_operand:HI 0 "xstormy16_below100_operand" "") + (and:HI (match_operand:HI 1 "xstormy16_below100_operand" "") + (match_operand:HI 2 "xstormy16_onebit_clr_operand" "")))] + "" + [(set (match_dup 3) + (and:QI (match_dup 4) + (match_dup 5)))] + { int s = ((INTVAL (operands[2]) & 0xff) == 0xff) ? 1 : 0; + operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, s); + operands[4] = simplify_gen_subreg (QImode, operands[1], HImode, s); + operands[5] = simplify_gen_subreg (QImode, operands[2], HImode, s); + operands[5] = GEN_INT (INTVAL (operands[5]) | ~ (HOST_WIDE_INT) 0xff); + }) + +;; Inclusive OR, 16-bit integers +(define_insn "iorhi3" + [(set (match_operand:HI 0 "xstormy16_splittable_below100_or_register" "=T,r,r,r,W") + (ior:HI (match_operand:HI 1 "xstormy16_below100_or_register" "%0,0,0,0,0") + (match_operand:HI 2 "nonmemory_operand" "L,r,J,i,J")))] + "" + "@ + or Rx,%2 + or %0,%2 + set1 %0,%B2 + or %0,%2 + #" + [(set_attr "length" "2,2,2,4,2")]) + +(define_split + [(set (match_operand:HI 0 "xstormy16_below100_operand" "") + (ior:HI (match_operand:HI 1 "xstormy16_below100_operand" "") + (match_operand:HI 2 "xstormy16_onebit_set_operand" "")))] + "" + [(set (match_dup 3) + (ior:QI (match_dup 4) + (match_dup 5)))] + { int s = ((INTVAL (operands[2]) & 0xff) == 0x00) ? 1 : 0; + operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, s); + operands[4] = simplify_gen_subreg (QImode, operands[1], HImode, s); + operands[5] = simplify_gen_subreg (QImode, operands[2], HImode, s); + operands[5] = GEN_INT (INTVAL (operands[5]) & 0xff); + }) + +;; Exclusive OR, 16-bit integers +(define_insn "xorhi3" + [(set (match_operand:HI 0 "register_operand" "=T,r,r") + (xor:HI (match_operand:HI 1 "register_operand" "%0,0,0") + (match_operand:HI 2 "nonmemory_operand" "L,r,i")))] + "" + "@ + xor Rx,%2 + xor %0,%2 + xor %0,%2" + [(set_attr "length" "2,2,4")]) + +;; One's complement, 16-bit integers +(define_insn "one_cmplhi2" + [(set (match_operand:HI 0 "register_operand" "=r") + (not:HI (match_operand:HI 1 "register_operand" "0")))] + "" + "not %0") + +;; :::::::::::::::::::: +;; :: +;; :: 32-bit Integer arithmetic +;; :: +;; :::::::::::::::::::: + +;; Addition +(define_insn_and_split "addsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (match_operand:SI 1 "register_operand" "%0") + (match_operand:SI 2 "nonmemory_operand" "ri"))) + (clobber (reg:BI CARRY_REG))] + "" + "#" + "reload_completed" + [(pc)] + { xstormy16_expand_arith (SImode, PLUS, operands[0], operands[1], + operands[2]); + DONE; + } + [(set_attr "length" "4")]) + +;; Subtraction +(define_insn_and_split "subsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "nonmemory_operand" "ri"))) + (clobber (reg:BI CARRY_REG))] + "" + "#" + "reload_completed" + [(pc)] + { xstormy16_expand_arith (SImode, MINUS, operands[0], operands[1], + operands[2]); + DONE; + } + [(set_attr "length" "4")]) + +(define_expand "negsi2" + [(parallel [(set (match_operand:SI 0 "register_operand" "") + (neg:SI (match_operand:SI 1 "register_operand" ""))) + (clobber (reg:BI CARRY_REG))])] + "" + { operands[2] = gen_reg_rtx (HImode); }) + +(define_insn_and_split "*negsi2_internal" + [(set (match_operand:SI 0 "register_operand" "=&r") + (neg:SI (match_operand:SI 1 "register_operand" "r"))) + (clobber (reg:BI CARRY_REG))] + "" + "#" + "reload_completed" + [(pc)] + { xstormy16_expand_arith (SImode, NEG, operands[0], operands[0], + operands[1]); + DONE; + }) + +;; :::::::::::::::::::: +;; :: +;; :: 32-bit Integer Shifts and Rotates +;; :: +;; :::::::::::::::::::: + +;; Arithmetic Shift Left +(define_expand "ashlsi3" + [(parallel [(set (match_operand:SI 0 "register_operand" "") + (ashift:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (clobber (reg:BI CARRY_REG)) + (clobber (match_dup 3))])] + "" + { if (! const_int_operand (operands[2], SImode)) + FAIL; + operands[3] = gen_reg_rtx (HImode); + }) + +;; Arithmetic Shift Right +(define_expand "ashrsi3" + [(parallel [(set (match_operand:SI 0 "register_operand" "") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (clobber (reg:BI CARRY_REG)) + (clobber (match_dup 3))])] + "" + { if (! const_int_operand (operands[2], SImode)) + FAIL; + operands[3] = gen_reg_rtx (HImode); + }) + +;; Logical Shift Right +(define_expand "lshrsi3" + [(parallel [(set (match_operand:SI 0 "register_operand" "") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (clobber (reg:BI CARRY_REG)) + (clobber (match_dup 3))])] + "" + { if (! const_int_operand (operands[2], SImode)) + FAIL; + operands[3] = gen_reg_rtx (HImode); + }) + +(define_insn "*shiftsi" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (match_operator:SI 4 "shift_operator" + [(match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "const_int_operand" "U,n")])) + (clobber (reg:BI CARRY_REG)) + (clobber (match_operand:HI 3 "" "=X,r"))] + "" + "* return xstormy16_output_shift (SImode, GET_CODE (operands[4]), + operands[0], operands[2], operands[3]);" + [(set_attr "length" "6,10") + (set_attr "psw_operand" "clobber,clobber")]) + + +;; :::::::::::::::::::: +;; :: +;; :: Branches +;; :: +;; :::::::::::::::::::: + +(define_expand "cbranchhi4" + [(set (pc) + (if_then_else (match_operator 0 "comparison_operator" + [(match_operand:HI 1 "register_operand" "") + (match_operand:HI 2 "nonmemory_operand" "")]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (reg:BI CARRY_REG))] + "" + { + xstormy16_emit_cbranch (GET_CODE (operands[0]), operands[1], operands[2], + operands[3]); + DONE; +}) + +(define_insn "cbranchhi" + [(set (pc) + (if_then_else (match_operator:HI 1 "comparison_operator" + [(match_operand:HI 2 "nonmemory_operand" + "r,e,L") + (match_operand:HI 3 "nonmemory_operand" + "r,L,e")]) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:BI CARRY_REG))] + "" + "* +{ + return xstormy16_output_cbranch_hi (operands[1], \"%l0\", 0, insn); +}" + [(set_attr "branch_class" "bcc12") + (set_attr "psw_operand" "0,0,1")]) + +(define_insn "cbranchhi_neg" + [(set (pc) + (if_then_else (match_operator:HI 1 "comparison_operator" + [(match_operand:HI 2 "nonmemory_operand" + "r,e,L") + (match_operand:HI 3 "nonmemory_operand" + "r,L,e")]) + (pc) + (label_ref (match_operand 0 "" "")))) + (clobber (reg:BI CARRY_REG))] + "" + "* +{ + return xstormy16_output_cbranch_hi (operands[1], \"%l0\", 1, insn); +}" + [(set_attr "branch_class" "bcc12") + (set_attr "psw_operand" "0,0,1")]) + +(define_insn "*eqbranchsi" + [(set (pc) + (if_then_else (match_operator:SI 1 "equality_operator" + [(match_operand:SI 2 "register_operand" + "r") + (const_int 0)]) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (match_operand:SI 3 "register_operand" "=2"))] + "" + "* +{ + return xstormy16_output_cbranch_si (operands[1], \"%l0\", 0, insn); +}" + [(set_attr "branch_class" "bcc8p2") + (set_attr "psw_operand" "clobber")]) + +(define_insn "*ineqbranch_1" + [(set (pc) + (if_then_else (match_operator:HI 4 "xstormy16_ineqsi_operator" + [(minus:HI (match_operand:HI 1 "register_operand" "T,r,r") + (zero_extend:HI (reg:BI CARRY_REG))) + (match_operand:HI 3 "nonmemory_operand" "L,r,i")]) + (label_ref (match_operand 0 "" "")) + (pc))) + (set (match_operand:HI 2 "register_operand" "=1,1,1") + (minus:HI (minus:HI (match_dup 1) (zero_extend:HI (reg:BI CARRY_REG))) + (match_dup 3))) + (clobber (reg:BI CARRY_REG))] + "" + "* +{ + return xstormy16_output_cbranch_si (operands[4], \"%l0\", 0, insn); +}" + [(set_attr "branch_class" "bcc8p2,bcc8p2,bcc8p4") + (set_attr "psw_operand" "2,2,2")]) + +;; :::::::::::::::::::: +;; :: +;; :: Call and branch instructions +;; :: +;; :::::::::::::::::::: + +;; Subroutine call instruction returning no value. Operand 0 is the function +;; to call; operand 1 is the number of bytes of arguments pushed (in mode +;; `SImode', except it is normally a `const_int'); operand 2 is the number of +;; registers used as operands. + +;; On most machines, operand 2 is not actually stored into the RTL pattern. It +;; is supplied for the sake of some RISC machines which need to put this +;; information into the assembler code; they can put it in the RTL instead of +;; operand 1. + +(define_expand "call" + [(call (match_operand:HI 0 "memory_operand" "m") + (match_operand 1 "" "")) + (use (match_operand 2 "immediate_operand" ""))] + "" + "xstormy16_expand_call (NULL_RTX, operands[0], operands[1]); DONE;") + +;; Subroutine call instruction returning a value. Operand 0 is the hard +;; register in which the value is returned. There are three more operands, the +;; same as the three operands of the `call' instruction (but with numbers +;; increased by one). + +;; Subroutines that return `BLKmode' objects use the `call' insn. + +(define_expand "call_value" + [(set (match_operand 0 "register_operand" "=r") + (call (match_operand:HI 1 "memory_operand" "m") + (match_operand:SI 2 "" ""))) + (use (match_operand 3 "immediate_operand" ""))] + "" + "xstormy16_expand_call (operands[0], operands[1], operands[2]); DONE;") + +(define_insn "*call_internal" + [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "i,r")) + (match_operand 1 "" "")) + (use (match_operand:HI 2 "nonmemory_operand" "X,z"))] + "" + "@ + callf %C0 + call %2,%0" + [(set_attr "length" "4,2") + (set_attr "psw_operand" "clobber")]) + +(define_insn "*call_value_internal" + [(set (match_operand 3 "register_operand" "=r,r") + (call (mem:HI (match_operand:HI 0 "nonmemory_operand" "i,r")) + (match_operand 1 "" ""))) + (use (match_operand:HI 2 "nonmemory_operand" "X,z"))] + "" + "@ + callf %C0 + call %2,%0" + [(set_attr "length" "4,2") + (set_attr "psw_operand" "clobber")]) + +;; Subroutine return +(define_expand "return" + [(return)] + "direct_return()" + "") + +(define_insn "return_internal" + [(return)] + "" + "ret" + [(set_attr "psw_operand" "nop")]) + +(define_insn "return_internal_interrupt" + [(return) + (unspec_volatile [(const_int 0)] 1)] + "" + "iret" + [(set_attr "psw_operand" "clobber")]) + +;; Normal unconditional jump +(define_insn "jump" + [(set (pc) (label_ref (match_operand 0 "" "")))] + "" + "* +{ + return xstormy16_output_cbranch_hi (NULL_RTX, \"%l0\", 0, insn); +}" + [(set_attr "branch_class" "br12") + (set_attr "psw_operand" "nop")]) + +;; Indirect jump through a register +(define_expand "indirect_jump" + [(set (match_dup 1) (const_int 0)) + (parallel [(set (pc) (match_operand:HI 0 "register_operand" "")) + (use (match_dup 1))])] + "" + "operands[1] = gen_reg_rtx (HImode);") + +(define_insn "" + [(set (pc) (match_operand:HI 0 "register_operand" "r")) + (use (match_operand:HI 1 "register_operand" "z"))] + "" + "jmp %1,%0" + [(set_attr "length" "4") + (set_attr "psw_operand" "nop")]) + +;; Table-based switch statements. +(define_expand "casesi" + [(use (match_operand:SI 0 "register_operand" "")) + (use (match_operand:SI 1 "immediate_operand" "")) + (use (match_operand:SI 2 "immediate_operand" "")) + (use (label_ref (match_operand 3 "" ""))) + (use (label_ref (match_operand 4 "" "")))] + "" + " +{ + xstormy16_expand_casesi (operands[0], operands[1], operands[2], + operands[3], operands[4]); + DONE; +}") + +(define_insn "tablejump_pcrel" + [(set (pc) (mem:HI (plus:HI (pc) + (match_operand:HI 0 "register_operand" "r")))) + (use (label_ref:SI (match_operand 1 "" "")))] + "" + "br %0" + [(set_attr "psw_operand" "nop")]) + +;; :::::::::::::::::::: +;; :: +;; :: Prologue and Epilogue instructions +;; :: +;; :::::::::::::::::::: + +;; Called after register allocation to add any instructions needed for +;; the prologue. Using a prologue insn is favored compared to putting +;; all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro, +;; since it allows the scheduler to intermix instructions with the +;; saves of the caller saved registers. In some cases, it might be +;; necessary to emit a barrier instruction as the last insn to prevent +;; such scheduling. +(define_expand "prologue" + [(const_int 1)] + "" + { + xstormy16_expand_prologue (); + DONE; + }) + +;; Called after register allocation to add any instructions needed for +;; the epilogue. Using an epilogue insn is favored compared to putting +;; all of the instructions in the TARGET_ASM_FUNCTION_EPILOGUE macro, +;; since it allows the scheduler to intermix instructions with the +;; restores of the caller saved registers. In some cases, it might be +;; necessary to emit a barrier instruction as the first insn to +;; prevent such scheduling. +(define_expand "epilogue" + [(const_int 2)] + "" + { + xstormy16_expand_epilogue (); + DONE; + }) + +;; :::::::::::::::::::: +;; :: +;; :: Miscellaneous instructions +;; :: +;; :::::::::::::::::::: + +;; No operation, needed in case the user uses -g but not -O. +(define_insn "nop" + [(const_int 0)] + "" + "nop" + [(set_attr "psw_operand" "nop")]) + +;; Pseudo instruction that prevents the scheduler from moving code above this +;; point. +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "" + [(set_attr "length" "0") + (set_attr "psw_operand" "nop")]) + +;;--------------------------------------------------------------------------- + +(define_expand "iorqi3" + [(match_operand:QI 0 "xstormy16_below100_or_register" "") + (match_operand:QI 1 "xstormy16_below100_or_register" "") + (match_operand:QI 2 "nonmemory_operand" "")] + "" + { + xstormy16_expand_iorqi3 (operands); + DONE; + }) + +(define_insn "iorqi3_internal" + [(set (match_operand:QI 0 "xstormy16_below100_or_register" "=Wr") + (ior:QI (match_operand:QI 1 "xstormy16_below100_or_register" "0") + (match_operand:QI 2 "xstormy16_onebit_set_operand" "i")))] + "" + "set1 %0,%B2" + [(set_attr "length" "2") + (set_attr "psw_operand" "0")]) + +(define_peephole2 + [(set (match_operand:QI 0 "register_operand" "") + (match_operand:QI 1 "xstormy16_below100_operand" "")) + (set (match_operand:HI 2 "register_operand" "") + (ior:HI (match_operand:HI 3 "register_operand" "") + (match_operand:QI 4 "xstormy16_onebit_set_operand" ""))) + (set (match_operand:QI 5 "xstormy16_below100_operand" "") + (match_operand:QI 6 "register_operand" "")) + ] + "REGNO (operands[0]) == REGNO (operands[2]) + && REGNO (operands[0]) == REGNO (operands[3]) + && REGNO (operands[0]) == REGNO (operands[6]) + && rtx_equal_p (operands[1], operands[5])" + [(set (match_dup 1) + (ior:QI (match_dup 1) + (match_dup 4))) + ] + "") + + +(define_expand "andqi3" + [(match_operand:QI 0 "xstormy16_below100_or_register" "") + (match_operand:QI 1 "xstormy16_below100_or_register" "") + (match_operand:QI 2 "nonmemory_operand" "")] + "" + { + xstormy16_expand_andqi3 (operands); + DONE; + }) + +(define_insn "andqi3_internal" + [(set (match_operand:QI 0 "xstormy16_below100_or_register" "=Wr") + (and:QI (match_operand:QI 1 "xstormy16_below100_or_register" "0") + (match_operand:QI 2 "xstormy16_onebit_clr_operand" "i")))] + "" + "clr1 %0,%B2" + [(set_attr "length" "2") + (set_attr "psw_operand" "0")]) + +(define_peephole2 + [(set (match_operand:HI 0 "register_operand" "") + (and:HI (match_operand:HI 1 "register_operand" "") + (match_operand 2 "immediate_operand" ""))) + (set (match_operand:HI 3 "register_operand" "") + (zero_extend:HI (match_operand:QI 4 "register_operand" ""))); + ] + "REGNO (operands[0]) == REGNO (operands[1]) + && REGNO (operands[0]) == REGNO (operands[3]) + && REGNO (operands[0]) == REGNO (operands[4])" + [(set (match_dup 0) + (and:HI (match_dup 1) + (match_dup 5))) + ] + "operands[5] = GEN_INT (INTVAL (operands[2]) & 0xff);") + +(define_peephole2 + [(set (match_operand:QI 0 "register_operand" "") + (match_operand:QI 1 "xstormy16_below100_operand" "")) + (set (match_operand:HI 2 "register_operand" "") + (and:HI (match_operand:HI 3 "register_operand" "") + (match_operand:QI 4 "xstormy16_onebit_clr_operand" ""))) + (set (match_operand:QI 5 "xstormy16_below100_operand" "") + (match_operand:QI 6 "register_operand" "")) + ] + "REGNO (operands[0]) == REGNO (operands[2]) + && REGNO (operands[0]) == REGNO (operands[3]) + && REGNO (operands[0]) == REGNO (operands[6]) + && rtx_equal_p (operands[1], operands[5])" + [(set (match_dup 1) + (and:QI (match_dup 1) + (match_dup 4))) + ] + "") + +;; GCC uses different techniques to optimize MSB and LSB accesses, so +;; we have to code those separately. + +(define_insn "*bclrx" + [(set (pc) + (if_then_else (eq:HI (and:QI (match_operand:QI 1 "xstormy16_below100_operand" "W") + (match_operand:HI 2 "immediate_operand" "i")) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:BI CARRY_REG))] + "" + "bn %1,%B2,%l0" + [(set_attr "length" "4") + (set_attr "psw_operand" "nop")]) + +(define_insn "*bclrx2" + [(set (pc) + (if_then_else (zero_extract:HI + (xor:HI (subreg:HI + (match_operand:QI 1 "xstormy16_below100_operand" "W") 0) + (match_operand:HI 2 "xstormy16_onebit_set_operand" "J")) + (const_int 1) + (match_operand:HI 3 "immediate_operand" "i")) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:BI CARRY_REG))] + "" + "bn %1,%B2,%l0" + [(set_attr "length" "4") + (set_attr "psw_operand" "nop")]) + +(define_insn "*bclrx3" + [(set (pc) + (if_then_else (eq:HI (and:HI (zero_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W")) + (match_operand:HI 2 "immediate_operand" "i")) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:BI CARRY_REG))] + "" + "bn %1,%B2,%l0" + [(set_attr "length" "4") + (set_attr "psw_operand" "nop")]) + +(define_insn "*bclr7" + [(set (pc) + (if_then_else (xor:HI (lshiftrt:HI (subreg:HI + (match_operand:QI 1 "xstormy16_below100_operand" "W") 0) + (const_int 7)) + (const_int 1)) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:BI CARRY_REG))] + "" + "bn %1,#7,%l0" + [(set_attr "length" "4") + (set_attr "psw_operand" "nop")]) + +(define_insn "*bclr15" + [(set (pc) + (if_then_else (ge:HI (sign_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W")) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:BI CARRY_REG))] + "" + "bn %1,#7,%l0" + [(set_attr "length" "4") + (set_attr "psw_operand" "nop")]) + +(define_insn "*bsetx" + [(set (pc) + (if_then_else (ne:HI (and:QI (match_operand:QI 1 "xstormy16_below100_operand" "W") + (match_operand:HI 2 "immediate_operand" "i")) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:BI CARRY_REG))] + "" + "bp %1,%B2,%l0" + [(set_attr "length" "4") + (set_attr "psw_operand" "nop")]) + +(define_insn "*bsetx2" + [(set (pc) + (if_then_else (zero_extract:HI (match_operand:QI 1 "xstormy16_below100_operand" "W") + (const_int 1) + (match_operand:HI 2 "immediate_operand" "i")) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:BI CARRY_REG))] + "" + "bp %1,%b2,%l0" + [(set_attr "length" "4") + (set_attr "psw_operand" "nop")]) + +(define_insn "*bsetx3" + [(set (pc) + (if_then_else (ne:HI (and:HI (zero_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W")) + (match_operand:HI 2 "immediate_operand" "i")) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:BI CARRY_REG))] + "" + "bp %1,%B2,%l0" + [(set_attr "length" "4") + (set_attr "psw_operand" "nop")]) + +(define_insn "*bset7" + [(set (pc) + (if_then_else (lshiftrt:HI (subreg:HI (match_operand:QI 1 "xstormy16_below100_operand" "W") 0) + (const_int 7)) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:BI CARRY_REG))] + "" + "bp %1,#7,%l0" + [(set_attr "length" "4") + (set_attr "psw_operand" "nop")]) + +(define_insn "*bset15" + [(set (pc) + (if_then_else (lt:HI (sign_extend:HI (match_operand:QI 1 "xstormy16_below100_operand" "W")) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (reg:BI CARRY_REG))] + "" + "bp %1,#7,%l0" + [(set_attr "length" "4") + (set_attr "psw_operand" "nop")]) diff --git a/gcc-4.9/gcc/config/stormy16/stormy16.opt b/gcc-4.9/gcc/config/stormy16/stormy16.opt new file mode 100644 index 000000000..01efdca60 --- /dev/null +++ b/gcc-4.9/gcc/config/stormy16/stormy16.opt @@ -0,0 +1,24 @@ +; Options for the XSTORMY16 port of the compiler. + +; Copyright (C) 2005-2014 Free Software Foundation, Inc. +; +; This file is part of GCC. +; +; GCC is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License as published by the Free +; Software Foundation; either version 3, or (at your option) any later +; version. +; +; GCC is distributed in the hope that it will be useful, but WITHOUT ANY +; WARRANTY; without even the implied warranty of MERCHANTABILITY or +; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +; for more details. +; +; You should have received a copy of the GNU General Public License +; along with GCC; see the file COPYING3. If not see +; <http://www.gnu.org/licenses/>. + +; Not used by the compiler +msim +Target RejectNegative +Provide libraries for the simulator |