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| author | Rong Xu <xur@google.com> | 2014-09-05 20:22:13 -0700 |
|---|---|---|
| committer | Rong Xu <xur@google.com> | 2014-09-05 20:22:13 -0700 |
| commit | 142855c94b3bc9e140a1b55c1a424259285d751c (patch) | |
| tree | 8b4f309643aab7f51e85b9cc66b05f209426c5d3 /gcc-4.9/gcc/testsuite | |
| parent | 4254ad78d813b8c4cfc6c07218aee6b1be554f23 (diff) | |
| download | toolchain_gcc-142855c94b3bc9e140a1b55c1a424259285d751c.tar.gz toolchain_gcc-142855c94b3bc9e140a1b55c1a424259285d751c.tar.bz2 toolchain_gcc-142855c94b3bc9e140a1b55c1a424259285d751c.zip | |
[gcc-4.9] Backport fix for PR62040 and PR62262
Backport two patches from upstream gcc 4.9 branch that fix PR62040 and PR62262
Change-Id: If4f557a650e00261b9bc83e008eb63b13ca798cb
Diffstat (limited to 'gcc-4.9/gcc/testsuite')
| -rw-r--r-- | gcc-4.9/gcc/testsuite/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c | 21 | ||||
| -rw-r--r-- | gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c | 20 |
3 files changed, 51 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/testsuite/ChangeLog b/gcc-4.9/gcc/testsuite/ChangeLog index 4a7de28b3..51626c35e 100644 --- a/gcc-4.9/gcc/testsuite/ChangeLog +++ b/gcc-4.9/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2014-09-04 Guozhi Wei <carrot@google.com> + + PR target/62040 + * gcc.target/aarch64/pr62040.c: New test. + +2014-08-27 Guozhi Wei <carrot@google.com> + + PR target/62262 + * gcc.target/aarch64/pr62262.c: New test. + 2014-08-26 Dominik Vogt <vogt@linux.vnet.ibm.com> * gfortran.dg/bessel_7.f90: Bump allowed precision to avoid diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c new file mode 100644 index 000000000..cfb4979f8 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-g -Os" } */ + +#include "arm_neon.h" + +extern void bar (int32x4_t); + +void +foo () +{ + int32x4x4_t rows; + uint64x2x2_t row01; + + row01.val[0] = vreinterpretq_u64_s32 (rows.val[0]); + row01.val[1] = vreinterpretq_u64_s32 (rows.val[1]); + uint64x1_t row3l = vget_low_u64 (row01.val[0]); + row01.val[0] = vcombine_u64 (vget_low_u64 (row01.val[1]), row3l); + int32x4_t xxx = vreinterpretq_s32_u64 (row01.val[0]); + int32x4_t out = vtrn1q_s32 (xxx, xxx); + bar (out); +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c new file mode 100644 index 000000000..5bf90bf7f --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fprofile-use" } */ + +static inline int CLZ(int mask) { + return mask ? __builtin_clz(mask) : 32; +} + +int foo(int value) +{ + if (value == 0) + return 0; + + int bias = CLZ(value); + value >>= bias; + int zeros = CLZ(value << 1); + value <<= zeros; + + int packed = (unsigned)(value << 9) >> 9; + return packed; +} |