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authorBen Cheng <bccheng@google.com>2014-04-22 20:33:12 (GMT)
committerBen Cheng <bccheng@google.com>2014-04-22 20:33:12 (GMT)
commite3cc64dec20832769406aa38cde83c7dd4194bf4 (patch)
treeef8e39be37cfe0cb69d850043b7924389ff17164 /gcc-4.9/gcc/testsuite/gcc.target
parentf33c7b3122b1d7950efa88067c9a156229ba647b (diff)
downloadtoolchain_gcc-e3cc64dec20832769406aa38cde83c7dd4194bf4.zip
toolchain_gcc-e3cc64dec20832769406aa38cde83c7dd4194bf4.tar.gz
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[4.9] GCC 4.9.0 official release refresh
Change-Id: Ic99a7da8b44b789a48aeec93b33e93944d6e6767
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.target')
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60034.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60580_1.c45
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60675.C277
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60697.c638
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/test_fp_attribute_1.c26
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/test_fp_attribute_2.c26
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/pr60650-2.c37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/pr60650.c41
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/pr60657.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/pr60663.c11
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/avr/dev-specific-rmw.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/387-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/387-4.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff32x4-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff64x2-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi32x4-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi64x2-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-1.c32
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-2.c32
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-builtin.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-3.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-9.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/isa-1.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_1.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_4.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_5.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_6.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_1.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_4.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_5.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_6.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-1.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-1.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-1.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr27971.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr30970.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-4a.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr60693.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr60700.c59
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-1.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-5.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c22
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c27
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60676.c128
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-2.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/s390/20140327-1.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c54
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c12
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/s390/s390.exp10
88 files changed, 1635 insertions, 77 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60034.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60034.c
new file mode 100644
index 0000000..ab7e7f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60034.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-std=gnu99 -O" } */
+
+static unsigned long global_max_fast;
+
+void __libc_mallopt (int param_number, int value)
+{
+ __asm__ __volatile__ ("# %[_SDT_A21]" :: [_SDT_A21] "nor" ((global_max_fast)));
+ global_max_fast = 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60580_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60580_1.c
new file mode 100644
index 0000000..1adf508
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60580_1.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -fomit-frame-pointer -fno-inline --save-temps" } */
+
+void
+func_leaf (void)
+{
+ int a = 0;
+}
+
+void
+func_no_leaf (void)
+{
+ int a = 0;
+ func_leaf ();
+}
+
+void
+func1 (void)
+{
+ int a = 0;
+ func_no_leaf ();
+}
+
+/*
+ * This function calls XXX(), which modifies SP. This is incompatible to
+ * -fomit-frame-pointer generated code as SP is used to access the frame.
+ */
+__attribute__ ((optimize("no-omit-frame-pointer")))
+void
+func2 (void)
+{
+ int a = 0;
+ func_no_leaf ();
+}
+
+void
+func3 (void)
+{
+ int a = 0;
+ func_no_leaf ();
+}
+
+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60675.C b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60675.C
new file mode 100644
index 0000000..aa88cdb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60675.C
@@ -0,0 +1,277 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c++11 -w -O2 -fPIC" } */
+namespace CLHEP {
+ static const double meter = 1000.*10;
+ static const double meter2 = meter*meter;
+ static const double megaelectronvolt = 1. ;
+ static const double gigaelectronvolt = 1.e+3;
+ static const double GeV = gigaelectronvolt;
+ static const double megavolt = megaelectronvolt;
+ static const double volt = 1.e-6*megavolt;
+ static const double tesla = volt*1.e+9/meter2;
+ }
+ using CLHEP::GeV;
+ using CLHEP::tesla;
+ namespace std {
+ typedef long int ptrdiff_t;
+ }
+ extern "C" {
+ extern double cos (double __x) throw ();
+ extern double sin (double __x) throw ();
+ extern double sqrt (double __x) throw ();
+ }
+ namespace std __attribute__ ((__visibility__ ("default"))) {
+ using ::cos;
+ using ::sin;
+ using ::sqrt;
+ template<class _CharT> struct char_traits;
+ template<typename _CharT, typename _Traits = char_traits<_CharT> > struct basic_ostream;
+ typedef basic_ostream<char> ostream;
+ template<typename _Iterator> struct iterator_traits { };
+ template<typename _Tp> struct iterator_traits<_Tp*> {
+ typedef ptrdiff_t difference_type;
+ typedef _Tp& reference;
+ };
+ }
+ namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) {
+ using std::iterator_traits;
+ template<typename _Iterator, typename _Container> struct __normal_iterator {
+ _Iterator _M_current;
+ typedef iterator_traits<_Iterator> __traits_type;
+ typedef typename __traits_type::difference_type difference_type;
+ typedef typename __traits_type::reference reference;
+ explicit __normal_iterator(const _Iterator& __i) : _M_current(__i) { }
+ reference operator*() const {
+ return *_M_current;
+ }
+ __normal_iterator operator+(difference_type __n) const {
+ return __normal_iterator(_M_current + __n);
+ }
+ };
+ template<typename _Tp> struct new_allocator {
+ };
+ }
+ namespace std __attribute__ ((__visibility__ ("default"))) {
+ template<typename _Tp> struct allocator: public __gnu_cxx::new_allocator<_Tp> {
+ };
+ struct ios_base { };
+ template<typename _CharT, typename _Traits> struct basic_ios : public ios_base { };
+ template<typename _CharT, typename _Traits> struct basic_ostream : virtual public basic_ios<_CharT, _Traits> {
+ typedef basic_ostream<_CharT, _Traits> __ostream_type;
+ __ostream_type& operator<<(__ostream_type& (*__pf)(__ostream_type&)) { }
+ __ostream_type& operator<<(const void* __p) {
+ return _M_insert(__p);
+ }
+ template<typename _ValueT> __ostream_type& _M_insert(_ValueT __v);
+ };
+ template<typename _CharT, typename _Traits> inline basic_ostream<_CharT, _Traits>& endl(basic_ostream<_CharT, _Traits>& __os) {
+ }
+ }
+ typedef double G4double;
+ typedef int G4int;
+ extern __thread std::ostream *G4cout_p;
+ struct G4Field;
+ struct G4FieldManager {
+ inline G4Field* GetDetectorField() ;
+ };
+ namespace CLHEP {
+ struct Hep3Vector {
+ Hep3Vector(double x, double y, double z);
+ inline ~Hep3Vector();
+ inline double x() const;
+ inline double y() const;
+ inline double z() const;
+ inline double mag() const;
+ inline Hep3Vector cross(const Hep3Vector &) const;
+ double dx;
+ double dy;
+ double dz;
+ };
+ Hep3Vector operator / (const Hep3Vector &, double a);
+ inline double Hep3Vector::x() const {
+ return dx;
+ }
+ inline double Hep3Vector::y() const {
+ return dy;
+ }
+ inline double Hep3Vector::z() const {
+ return dz;
+ }
+ inline Hep3Vector operator + (const Hep3Vector & a, const Hep3Vector & b) { }
+ inline Hep3Vector operator * (const Hep3Vector & p, double a) { }
+ inline double operator * (const Hep3Vector & a, const Hep3Vector & b) { }
+ inline Hep3Vector::Hep3Vector(double x1, double y1, double z1) : dx(x1), dy(y1), dz(z1) {
+ }
+ inline Hep3Vector::~Hep3Vector() { }
+ inline Hep3Vector Hep3Vector::cross(const Hep3Vector & p) const {
+ return Hep3Vector(dy*p.dz-p.dy*dz, dz*p.dx-p.dz*dx, dx*p.dy-p.dx*dy);
+ }
+ }
+ typedef CLHEP::Hep3Vector G4ThreeVector;
+ namespace std __attribute__ ((__visibility__ ("default"))) {
+ template<typename _Tp, typename _Alloc = std::allocator<_Tp> > struct vector
+ {
+ typedef _Tp *pointer;
+ typedef __gnu_cxx::__normal_iterator<pointer, vector> iterator;
+ iterator begin() { }
+ };
+ }
+ struct G4TransportationManager {
+ static G4TransportationManager* GetTransportationManager();
+ inline G4FieldManager* GetFieldManager() const;
+ };
+ struct G4ErrorMatrix {
+ G4ErrorMatrix(G4int p, G4int q, G4int i);
+ virtual ~G4ErrorMatrix();
+ struct G4ErrorMatrix_row {
+ inline G4ErrorMatrix_row(G4ErrorMatrix&,G4int);
+ G4double & operator[](G4int);
+ G4ErrorMatrix& _a;
+ G4int _r;
+ };
+ inline G4ErrorMatrix_row operator[] (G4int);
+ std::vector<G4double > m;
+ G4int nrow, ncol;
+ };
+ inline G4ErrorMatrix::G4ErrorMatrix_row G4ErrorMatrix::operator[] (G4int r) {
+ G4ErrorMatrix_row b(*this,r);
+ return b;
+ }
+ inline G4double &G4ErrorMatrix::G4ErrorMatrix_row::operator[](G4int c) {
+ return *(_a.m.begin()+_r*_a.ncol+c);
+ }
+ inline G4ErrorMatrix:: G4ErrorMatrix_row::G4ErrorMatrix_row(G4ErrorMatrix&a, G4int r) : _a(a) {
+ _r = r;
+ };
+ struct G4DynamicParticle {
+ G4double GetCharge() const;
+ };
+ struct G4Step;
+ struct G4Track {
+ const G4DynamicParticle* GetDynamicParticle() const;
+ const G4ThreeVector& GetPosition() const;
+ G4ThreeVector GetMomentum() const;
+ const G4Step* GetStep() const;
+ };
+ struct G4StepPoint {
+ const G4ThreeVector& GetPosition() const;
+ G4ThreeVector GetMomentum() const;
+ };
+ struct G4Step {
+ G4StepPoint* GetPreStepPoint() const;
+ G4double GetStepLength() const;
+ };
+ namespace HepGeom {
+ template<class T> struct BasicVector3D {
+ T v_[3];
+ BasicVector3D(T x1, T y1, T z1) { }
+ operator T * () {
+ return v_;
+ }
+ T x() const {
+ return v_[0];
+ }
+ T y() const {
+ return v_[1];
+ }
+ T z() const {
+ return v_[2];
+ }
+ T perp2() const { }
+ T perp() const {
+ return std::sqrt(perp2());
+ }
+ T mag2() const { }
+ T mag() const {
+ return std::sqrt(mag2());
+ }
+ T theta() const { }
+ };
+ inline BasicVector3D<double> operator-(const BasicVector3D<double> & a,const BasicVector3D<double> & b) { }
+ inline BasicVector3D<double> operator*(const BasicVector3D<double> & v, double a) { }
+ template<class T> struct Point3D : public BasicVector3D<T> {
+ explicit Point3D(const double * a) : BasicVector3D<double>(a[0],a[1],a[2]) { }
+ Point3D(const CLHEP::Hep3Vector & v) : BasicVector3D<double>(v.dx,v.dy,v.dz) { }
+ };
+ }
+ typedef HepGeom::Point3D<G4double> G4Point3D;
+ namespace HepGeom {
+ template<class T> struct Vector3D : public BasicVector3D<T> {
+ Vector3D(const BasicVector3D<double> & v) : BasicVector3D<double>(v) { }
+ Vector3D(const CLHEP::Hep3Vector & v) : BasicVector3D<double>(v.dx,v.dy,v.dz) { }
+ operator CLHEP::Hep3Vector () const { }
+ };
+ }
+ typedef HepGeom::Vector3D<G4double> G4Vector3D;
+ struct G4ErrorFreeTrajState
+{
+ virtual G4int PropagateError( const G4Track* aTrack );
+ G4int PropagateErrorMSC( const G4Track* aTrack );
+ };
+ G4int G4ErrorFreeTrajState::PropagateError( const G4Track* aTrack ) {
+ G4double stepLengthCm = aTrack->GetStep()->GetStepLength()/10.;
+ G4Point3D vposPost = aTrack->GetPosition()/10.;
+ G4Vector3D vpPost = aTrack->GetMomentum()/GeV;
+ G4Point3D vposPre = aTrack->GetStep()->GetPreStepPoint()->GetPosition()/10.;
+ G4Vector3D vpPre = aTrack->GetStep()->GetPreStepPoint()->GetMomentum()/GeV;
+ G4double pPre = vpPre.mag();
+ G4double pPost = vpPost.mag();
+ G4double pInvPre = 1./pPre;
+ G4double pInvPost = 1./pPost;
+ G4double deltaPInv = pInvPost - pInvPre;
+ G4Vector3D vpPreNorm = vpPre * pInvPre;
+ G4Vector3D vpPostNorm = vpPost * pInvPost;
+ (*G4cout_p) << "G4EP: vpPreNorm " << vpPreNorm << " vpPostNorm " << vpPostNorm << std::endl;
+ G4double sinpPre = std::sin( vpPreNorm.theta() );
+ G4double sinpPostInv = 1./std::sin( vpPreNorm.theta() );
+ G4ErrorMatrix transf(5, 5, 0 );
+ G4double charge = aTrack->GetDynamicParticle()->GetCharge();
+ G4double h1[3], h2[3];
+ G4Field* field
+= G4TransportationManager::GetTransportationManager()->GetFieldManager()->GetDetectorField()
+;
+ if( charge != 0. && field )
+ {
+ G4ThreeVector HPre = G4ThreeVector( h1[0], h1[1], h1[2] ) / tesla *10.;
+ G4ThreeVector HPost= G4ThreeVector( h2[0], h2[1], h2[2] ) / tesla *10.;
+ {
+ G4double pInvAver = 1./(pInvPre + pInvPost );
+ G4double CFACT8 = 2.997925E-4;
+ G4ThreeVector vHAverNorm( (HPre*pInvPre + HPost*pInvPost ) * pInvAver * charge * CFACT8 );
+ G4double HAver = vHAverNorm.mag();
+ G4double pAver = (pPre+pPost)*0.5;
+ G4double QAver = -HAver/pAver;
+ G4double thetaAver = QAver * stepLengthCm;
+ G4double sinThetaAver = std::sin(thetaAver);
+ G4double cosThetaAver = std::cos(thetaAver);
+ G4double gamma = vHAverNorm * vpPostNorm;
+ G4ThreeVector AN2 = vHAverNorm.cross( vpPostNorm );
+ G4double AU = 1./vpPreNorm.perp();
+ G4ThreeVector vUPre( -AU*vpPreNorm.y(), AU*vpPreNorm.x(), 0. );
+ G4ThreeVector vVPre( -vpPreNorm.z()*vUPre.y(), vpPreNorm.z()*vUPre.x(), vpPreNorm.x()*vUPre.y() - vpPreNorm.y()*vUPre.x() );
+ AU = 1./vpPostNorm.perp();
+ G4ThreeVector vUPost( -AU*vpPostNorm.y(), AU*vpPostNorm.x(), 0. );
+ G4ThreeVector vVPost( -vpPostNorm.z()*vUPost.y(), vpPostNorm.z()*vUPost.x(), vpPostNorm.x()*vUPost.y() - vpPostNorm.y()*vUPost.x() );
+ G4Point3D deltaPos( vposPre - vposPost );
+ G4double QP = QAver * pAver;
+ G4double ANV = -( vHAverNorm.x()*vUPost.x() + vHAverNorm.y()*vUPost.y() );
+ G4double ANU = ( vHAverNorm.x()*vVPost.x() + vHAverNorm.y()*vVPost.y() + vHAverNorm.z()*vVPost.z() );
+ G4double OMcosThetaAver = 1. - cosThetaAver;
+ G4double TMSINT = thetaAver - sinThetaAver;
+ G4ThreeVector vHUPre( -vHAverNorm.z() * vUPre.y(), vHAverNorm.z() * vUPre.x(), vHAverNorm.x() * vUPre.y() - vHAverNorm.y() * vUPre.x() );
+ G4ThreeVector vHVPre( vHAverNorm.y() * vVPre.z() - vHAverNorm.z() * vVPre.y(), vHAverNorm.z() * vVPre.x() - vHAverNorm.x() * vVPre.z(), vHAverNorm.x() * vVPre.y() - vHAverNorm.y() * vVPre.x() );
+ transf[0][1] = -deltaPInv/thetaAver* ( TMSINT*gamma*(vHAverNorm.x()*vVPre.x()+vHAverNorm.y()*vVPre.y()+vHAverNorm.z()*vVPre.z()) + sinThetaAver*(vVPre.x()*vpPostNorm.x()+vVPre.y()*vpPostNorm.y()+vVPre.z()*vpPostNorm.z()) + OMcosThetaAver*(vHVPre.x()*vpPostNorm.x()+vHVPre.y()*vpPostNorm.y()+vHVPre.z()*vpPostNorm.z()) );
+ transf[0][2] = -sinpPre*deltaPInv/thetaAver* ( TMSINT*gamma*(vHAverNorm.x()*vUPre.x()+vHAverNorm.y()*vUPre.y() ) + sinThetaAver*(vUPre.x()*vpPostNorm.x()+vUPre.y()*vpPostNorm.y() ) + OMcosThetaAver*(vHUPre.x()*vpPostNorm.x()+vHUPre.y()*vpPostNorm.y()+vHUPre.z()*vpPostNorm.z()) );
+ transf[0][3] = -deltaPInv/stepLengthCm*(vUPre.x()*vpPostNorm.x()+vUPre.y()*vpPostNorm.y() );
+ transf[1][1] = cosThetaAver*(vVPre.x()*vVPost.x()+vVPre.y()*vVPost.y()+vVPre.z()*vVPost.z()) + sinThetaAver*(vHVPre.x()*vVPost.x()+vHVPre.y()*vVPost.y()+vHVPre.z()*vVPost.z()) + OMcosThetaAver*(vHAverNorm.x()*vVPre.x()+vHAverNorm.y()*vVPre.y()+vHAverNorm.z()*vVPre.z())* (vHAverNorm.x()*vVPost.x()+vHAverNorm.y()*vVPost.y()+vHAverNorm.z()*vVPost.z()) + ANV*( -sinThetaAver*(vVPre.x()*vpPostNorm.x()+vVPre.y()*vpPostNorm.y()+vVPre.z()*vpPostNorm.z()) + OMcosThetaAver*(vVPre.x()*AN2.x()+vVPre.y()*AN2.y()+vVPre.z()*AN2.z()) - TMSINT*gamma*(vHAverNorm.x()*vVPre.x()+vHAverNorm.y()*vVPre.y()+vHAverNorm.z()*vVPre.z()) );
+ transf[1][2] = cosThetaAver*(vUPre.x()*vVPost.x()+vUPre.y()*vVPost.y() ) + sinThetaAver*(vHUPre.x()*vVPost.x()+vHUPre.y()*vVPost.y()+vHUPre.z()*vVPost.z()) + OMcosThetaAver*(vHAverNorm.x()*vUPre.x()+vHAverNorm.y()*vUPre.y() )* (vHAverNorm.x()*vVPost.x()+vHAverNorm.y()*vVPost.y()+vHAverNorm.z()*vVPost.z()) + ANV*( -sinThetaAver*(vUPre.x()*vpPostNorm.x()+vUPre.y()*vpPostNorm.y() ) + OMcosThetaAver*(vUPre.x()*AN2.x()+vUPre.y()*AN2.y() ) - TMSINT*gamma*(vHAverNorm.x()*vUPre.x()+vHAverNorm.y()*vUPre.y() ) );
+ transf[2][0] = -QP*ANU*(vpPostNorm.x()*deltaPos.x()+vpPostNorm.y()*deltaPos.y()+vpPostNorm.z()*deltaPos.z())*sinpPostInv *(1.+deltaPInv*pAver);
+ transf[2][3] = -QAver*ANU*(vUPre.x()*vpPostNorm.x()+vUPre.y()*vpPostNorm.y() )*sinpPostInv;
+ transf[3][4] = (vVPre.x()*vUPost.x()+vVPre.y()*vUPost.y() );
+ transf[4][0] = pAver*(vVPost.x()*deltaPos.x()+vVPost.y()*deltaPos.y()+vVPost.z()*deltaPos.z()) *(1.+deltaPInv*pAver);
+ transf[4][1] = ( sinThetaAver*(vVPre.x()*vVPost.x()+vVPre.y()*vVPost.y()+vVPre.z()*vVPost.z()) + OMcosThetaAver*(vHVPre.x()*vVPost.x()+vHVPre.y()*vVPost.y()+vHVPre.z()*vVPost.z()) + TMSINT*(vHAverNorm.x()*vVPost.x()+vHAverNorm.y()*vVPost.y()+vHAverNorm.z()*vVPost.z())* (vHAverNorm.x()*vVPre.x()+vHAverNorm.y()*vVPre.y()+vHAverNorm.z()*vVPre.z()) )/QAver;
+ transf[4][2] = ( sinThetaAver*(vUPre.x()*vVPost.x()+vUPre.y()*vVPost.y() ) + OMcosThetaAver*(vHUPre.x()*vVPost.x()+vHUPre.y()*vVPost.y()+vHUPre.z()*vVPost.z()) + TMSINT*(vHAverNorm.x()*vVPost.x()+vHAverNorm.y()*vVPost.y()+vHAverNorm.z()*vVPost.z())* (vHAverNorm.x()*vUPre.x()+vHAverNorm.y()*vUPre.y() ) )*sinpPre/QAver;
+ }
+ }
+ PropagateErrorMSC( aTrack );
+ }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60697.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60697.c
new file mode 100644
index 0000000..57ccecb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr60697.c
@@ -0,0 +1,638 @@
+/* { dg-do compile } */
+/* { dg-options "-w -O3 -mcpu=cortex-a53" } */
+typedef struct __sFILE __FILE;
+typedef __FILE FILE;
+typedef int atom_id;
+typedef float real;
+typedef real rvec[3];
+typedef real matrix[3][3];
+enum {
+ ebCGS,ebMOLS,ebSBLOCKS,ebNR
+};
+enum {
+ efepNO, efepYES, efepNR
+};
+enum {
+ esolNO, esolMNO, esolWATER, esolWATERWATER, esolNR
+};
+typedef struct {
+ int nr;
+ atom_id *index;
+ atom_id *a;
+} t_block;
+enum {
+ F_LJ,
+ F_LJLR,
+ F_SR,
+ F_LR,
+ F_DVDL,
+};
+typedef struct {
+ t_block excl;
+} t_atoms;
+typedef struct {
+ t_atoms atoms;
+ t_block blocks[ebNR];
+} t_topology;
+typedef struct {
+} t_nsborder;
+extern FILE *debug;
+typedef struct {
+} t_nrnb;
+typedef struct {
+ int nri,maxnri;
+ int nrj,maxnrj;
+ int maxlen;
+ int solvent;
+ int *gid;
+ int *jindex;
+ atom_id *jjnr;
+ int *nsatoms;
+} t_nblist;
+typedef struct {
+ int nrx,nry,nrz;
+} t_grid;
+typedef struct {
+} t_commrec;
+enum { eNL_VDWQQ, eNL_VDW, eNL_QQ,
+ eNL_VDWQQ_FREE, eNL_VDW_FREE, eNL_QQ_FREE,
+ eNL_VDWQQ_SOLMNO, eNL_VDW_SOLMNO, eNL_QQ_SOLMNO,
+ eNL_VDWQQ_WATER, eNL_QQ_WATER,
+ eNL_VDWQQ_WATERWATER, eNL_QQ_WATERWATER,
+ eNL_NR };
+typedef struct {
+ real rlist,rlistlong;
+ real rcoulomb_switch,rcoulomb;
+ real rvdw_switch,rvdw;
+ int efep;
+ int cg0,hcg;
+ int *solvent_type;
+ int *mno_index;
+ rvec *cg_cm;
+ t_nblist nlist_sr[eNL_NR];
+ t_nblist nlist_lr[eNL_NR];
+ int bTwinRange;
+ rvec *f_twin;
+ int *eg_excl;
+} t_forcerec;
+typedef struct {
+ real *chargeA,*chargeB,*chargeT;
+ int *bPerturbed;
+ int *typeA,*typeB;
+ unsigned short *cTC,*cENER,*cACC,*cFREEZE,*cXTC,*cVCM;
+} t_mdatoms;
+enum { egCOUL, egLJ, egBHAM, egLR, egLJLR, egCOUL14, egLJ14, egNR };
+typedef struct {
+ real *ee[egNR];
+} t_grp_ener;
+typedef struct {
+ t_grp_ener estat;
+} t_groups;
+typedef unsigned long t_excl;
+static void reset_nblist(t_nblist *nl)
+{
+ nl->nri = 0;
+ nl->nrj = 0;
+ nl->maxlen = 0;
+ if (nl->maxnri > 0) {
+ nl->gid[0] = -1;
+ if (nl->maxnrj > 1) {
+ nl->jindex[0] = 0;
+ nl->jindex[1] = 0;
+ }
+ }
+}
+static void reset_neighbor_list(t_forcerec *fr,int bLR,int eNL)
+{
+ reset_nblist(&(fr->nlist_lr[eNL]));
+}
+static void close_i_nblist(t_nblist *nlist)
+{
+ int nri = nlist->nri;
+ int len;
+ nlist->jindex[nri+1] = nlist->nrj;
+ len=nlist->nrj - nlist->jindex[nri];
+ if (nlist->solvent==esolMNO)
+ len *= nlist->nsatoms[3*nri];
+ if(len > nlist->maxlen)
+ nlist->maxlen = len;
+}
+static void close_nblist(t_nblist *nlist)
+{
+ if (nlist->maxnri > 0) {
+ int nri = nlist->nri;
+ if ((nlist->jindex[nri+1] > nlist->jindex[nri]) &&
+ (nlist->gid[nri] != -1)) {
+ nlist->nri++;
+ nlist->jindex[nri+2] = nlist->nrj;
+ }
+ }
+}
+static void close_neighbor_list(t_forcerec *fr,int bLR,int eNL)
+{
+ close_nblist(&(fr->nlist_lr[eNL]));
+}
+static void add_j_to_nblist(t_nblist *nlist,atom_id j_atom)
+{
+ int nrj=nlist->nrj;
+ nlist->jjnr[nrj] = j_atom;
+ nlist->nrj ++;
+}
+static void put_in_list(int bHaveLJ[],
+ int ngid,t_mdatoms *md,
+ int icg,int jgid,int nj,atom_id jjcg[],
+ atom_id index[],
+ t_excl bExcl[],int shift,
+ t_forcerec *fr,int bLR,
+ int bVDWOnly,int bCoulOnly)
+{
+ t_nblist *vdwc,*vdw,*coul;
+ t_nblist *vdwc_ww=((void *)0),*coul_ww=((void *)0);
+ t_nblist *vdwc_free=((void *)0),*vdw_free=((void *)0),*coul_free=((void *)0);
+ int i,j,jcg,igid,gid,ind_ij;
+ atom_id jj,jj0,jj1,i_atom;
+ int i0,nicg,len;
+ int *type,*typeB;
+ unsigned short *cENER;
+ real *charge,*chargeB;
+ real qi,qiB,qq,rlj;
+ int bWater,bMNO,bFree,bFreeJ,bNotEx,*bPert;
+ charge = md->chargeA;
+ chargeB = md->chargeB;
+ type = md->typeA;
+ typeB = md->typeB;
+ cENER = md->cENER;
+ bPert = md->bPerturbed;
+ i0 = index[icg];
+ nicg = index[icg+1]-i0;
+ bMNO = (fr->solvent_type[icg] == esolMNO);
+ if (bLR) {
+ if (bWater) {
+ vdw = &fr->nlist_lr[eNL_VDW];
+ coul = &fr->nlist_lr[eNL_QQ_WATER];
+ vdwc_ww = &fr->nlist_lr[eNL_VDWQQ_WATERWATER];
+ } else if(bMNO) {
+ vdwc = &fr->nlist_lr[eNL_VDWQQ_SOLMNO];
+ }
+ if (fr->efep != efepNO) {
+ vdw_free = &fr->nlist_lr[eNL_VDW_FREE];
+ coul_free = &fr->nlist_lr[eNL_QQ_FREE];
+ }
+ }
+ else {
+ if (bWater) {
+ } else if(bMNO) {
+ vdwc = &fr->nlist_sr[eNL_VDWQQ_SOLMNO];
+ }
+ if (fr->efep != efepNO) {
+ vdwc_free = &fr->nlist_sr[eNL_VDWQQ_FREE];
+ }
+ }
+ if (fr->efep==efepNO) {
+ if (bWater) {
+ igid = cENER[i_atom];
+ gid = ((igid < jgid) ? (igid*ngid+jgid) : (jgid*ngid+igid));
+ if (!bCoulOnly && !bVDWOnly) {
+ new_i_nblist(vdwc,bLR ? F_LJLR : F_LJ,i_atom,shift,gid,((void *)0));
+ new_i_nblist(vdwc_ww,bLR ? F_LJLR : F_LJ,i_atom,shift,gid,((void *)0));
+ }
+ if (!bCoulOnly)
+ new_i_nblist(vdw,bLR ? F_LJLR : F_LJ,i_atom,shift,gid,((void *)0));
+ if (!bVDWOnly) {
+ new_i_nblist(coul,bLR ? F_LR : F_SR,i_atom,shift,gid,((void *)0));
+ new_i_nblist(coul_ww,bLR ? F_LR : F_SR,i_atom,shift,gid,((void *)0));
+ }
+ for(j=0; (j<nj); j++) {
+ jcg=jjcg[j];
+ if (jcg==icg)
+ jj0 = index[jcg];
+ if (bWater && (fr->solvent_type[jcg] == esolWATER)) {
+ if (bVDWOnly)
+ add_j_to_nblist(vdw,jj0);
+ else {
+ add_j_to_nblist(coul_ww,jj0);
+ add_j_to_nblist(vdwc_ww,jj0);
+ }
+ } else {
+ jj1 = index[jcg+1];
+ if (bCoulOnly) {
+ for(jj=jj0; (jj<jj1); jj++) {
+ if (fabs(charge[jj]) > 1.2e-38)
+ add_j_to_nblist(coul,jj);
+ }
+ } else if (bVDWOnly) {
+ for(jj=jj0; (jj<jj1); jj++)
+ if (bHaveLJ[type[jj]])
+ add_j_to_nblist(vdw,jj);
+ } else {
+ for(jj=jj0; (jj<jj1); jj++) {
+ if (bHaveLJ[type[jj]]) {
+ if (fabs(charge[jj]) > 1.2e-38)
+ add_j_to_nblist(vdwc,jj);
+ add_j_to_nblist(vdw,jj);
+ } else if (fabs(charge[jj]) > 1.2e-38)
+ add_j_to_nblist(coul,jj);
+ }
+ }
+ }
+ }
+ close_i_nblist(vdw);
+ close_i_nblist(coul);
+ close_i_nblist(vdwc);
+ close_i_nblist(coul_ww);
+ close_i_nblist(vdwc_ww);
+ } else if (bMNO) {
+ igid = cENER[i_atom];
+ gid = ((igid < jgid) ? (igid*ngid+jgid) : (jgid*ngid+igid));
+ if (!bCoulOnly && !bVDWOnly)
+ new_i_nblist(vdwc,bLR ? F_LJLR : F_LJ,i_atom,shift,gid,
+ &(fr->mno_index[icg*3]));
+ if (!bCoulOnly)
+ new_i_nblist(vdw,bLR ? F_LR : F_SR,i_atom,shift,gid,
+ &(fr->mno_index[icg*3]));
+ if (!bVDWOnly)
+ new_i_nblist(coul,bLR ? F_LR : F_SR,i_atom,shift,gid,
+ &(fr->mno_index[icg*3]));
+ for(j=0; (j<nj); j++) {
+ jcg=jjcg[j];
+ if (jcg == icg)
+ jj0 = index[jcg];
+ jj1=index[jcg+1];
+ for(jj=jj0; (jj<jj1); jj++) {
+ if (bCoulOnly) {
+ if (fabs(charge[jj]) > 1.2e-38)
+ add_j_to_nblist(coul,jj);
+ } else if (bVDWOnly) {
+ if (bHaveLJ[type[jj]])
+ add_j_to_nblist(vdw,jj);
+ } else {
+ if (bHaveLJ[type[jj]]) {
+ if (fabs(charge[jj]) > 1.2e-38)
+ add_j_to_nblist(vdwc,jj);
+ add_j_to_nblist(vdw,jj);
+ } else if (fabs(charge[jj]) > 1.2e-38)
+ add_j_to_nblist(coul,jj);
+ }
+ }
+ close_i_nblist(vdw);
+ close_i_nblist(coul);
+ close_i_nblist(vdwc);
+ }
+ } else {
+ for(i=0; i<nicg; i++) {
+ igid = cENER[i_atom];
+ gid = ((igid < jgid) ? (igid*ngid+jgid) : (jgid*ngid+igid));
+ qi = charge[i_atom];
+ if (!bCoulOnly && !bVDWOnly)
+ new_i_nblist(vdwc,bLR ? F_LJLR : F_LJ,i_atom,shift,gid,((void *)0));
+ if (!bCoulOnly)
+ new_i_nblist(vdw,bLR ? F_LR : F_SR,i_atom,shift,gid,((void *)0));
+ if (!bVDWOnly)
+ new_i_nblist(coul,bLR ? F_LR : F_SR,i_atom,shift,gid,((void *)0));
+ if (!(bVDWOnly || fabs(qi)<1.2e-38) || !(bCoulOnly || !bHaveLJ[type[i_atom]])) {
+ for(j=0; (j<nj); j++) {
+ jcg=jjcg[j];
+ if (jcg == icg)
+ jj0 = i0 + i + 1;
+ else
+ jj0 = index[jcg];
+ jj1=index[jcg+1];
+ for(jj=jj0; jj<jj1; jj++) {
+ bNotEx = !((int) ((bExcl)[((atom_id) (jj))] & (1<<((atom_id) (i)))));
+ if (bNotEx) {
+ if (bCoulOnly) {
+ if (fabs(charge[jj]) > 1.2e-38)
+ add_j_to_nblist(coul,jj);
+ } else if (bVDWOnly) {
+ if (bHaveLJ[type[jj]])
+ add_j_to_nblist(vdw,jj);
+ } else {
+ if (bHaveLJ[type[jj]]) {
+ if (fabs(qi) > 1.2e-38 && (fabs(charge[jj]) > 1.2e-38))
+ add_j_to_nblist(vdwc,jj);
+ add_j_to_nblist(vdw,jj);
+ } else if (fabs(qi) > 1.2e-38 && (fabs(charge[jj]) > 1.2e-38))
+ add_j_to_nblist(coul,jj);
+ }
+ }
+ }
+ }
+ }
+ close_i_nblist(vdw);
+ close_i_nblist(coul);
+ close_i_nblist(vdwc);
+ }
+ }
+ } else {
+ for(i=0; i<nicg; i++) {
+ igid = cENER[i_atom];
+ gid = ((igid < jgid) ? (igid*ngid+jgid) : (jgid*ngid+igid));
+ qi = charge[i_atom];
+ qiB = chargeB[i_atom];
+ if (!bCoulOnly && !bVDWOnly)
+ new_i_nblist(vdwc,bLR ? F_LJLR : F_LJ,i_atom,shift,gid,
+ bMNO ? &(fr->mno_index[icg*3]) : ((void *)0));
+ if (!bCoulOnly)
+ new_i_nblist(vdw,bLR ? F_LR : F_SR,i_atom,shift,gid,
+ bMNO ? &(fr->mno_index[icg*3]) : ((void *)0));
+ new_i_nblist(coul,bLR ? F_LR : F_SR,i_atom,shift,gid,
+ bMNO ? &(fr->mno_index[icg*3]) : ((void *)0));
+ new_i_nblist(vdw_free,F_DVDL,i_atom,shift,gid,((void *)0));
+ new_i_nblist(coul_free,F_DVDL,i_atom,shift,gid,((void *)0));
+ new_i_nblist(vdwc_free,F_DVDL,i_atom,shift,gid,((void *)0));
+ if (!(bVDWOnly || (fabs(qi)<1.2e-38 && fabs(qiB)<1.2e-38)) ||
+ !(bCoulOnly || (!bHaveLJ[type[i_atom]] && !bHaveLJ[typeB[i_atom]]))) {
+ for(j=0; (j<nj); j++) {
+ jcg=jjcg[j];
+ if (jcg == icg)
+ jj0 = i0 + i + 1;
+ else
+ jj0 = index[jcg];
+ jj1=index[jcg+1];
+ bFree = bPert[i_atom];
+ for(jj=jj0; (jj<jj1); jj++) {
+ bFreeJ = bFree || bPert[jj];
+ if ((!bWater && !bMNO) || i==0 || bFreeJ) {
+ bNotEx = !((int) ((bExcl)[((atom_id) (jj))] & (1<<((atom_id) (i)))));
+ if (bNotEx) {
+ if (bFreeJ) {
+ if (bCoulOnly)
+ add_j_to_nblist(coul_free,jj);
+ else if (bVDWOnly)
+ add_j_to_nblist(vdw_free,jj);
+ add_j_to_nblist(vdwc_free,jj);
+ } else if (bCoulOnly) {
+ add_j_to_nblist(coul,jj);
+ } else if (bVDWOnly) {
+ if (bHaveLJ[type[jj]])
+ add_j_to_nblist(vdw,jj);
+ } else {
+ if (bHaveLJ[type[jj]]) {
+ if (fabs(qi) > 1.2e-38 && (fabs(charge[jj]) > 1.2e-38))
+ add_j_to_nblist(vdwc,jj);
+ add_j_to_nblist(vdw,jj);
+ } else if (fabs(qi) > 1.2e-38 && (fabs(charge[jj]) > 1.2e-38))
+ add_j_to_nblist(coul,jj);
+ }
+ }
+ }
+ }
+ }
+ }
+ close_i_nblist(vdw);
+ close_i_nblist(coul);
+ close_i_nblist(vdwc);
+ if (bWater && (i==0)) {
+ close_i_nblist(coul_ww);
+ close_i_nblist(vdwc_ww);
+ }
+ close_i_nblist(vdw_free);
+ close_i_nblist(coul_free);
+ close_i_nblist(vdwc_free);
+ }
+ }
+}
+static void setexcl(atom_id start,atom_id end,t_block *excl,int b,
+ t_excl bexcl[])
+{
+ atom_id i,k;
+ if (b) {
+ for(i=start; i<end; i++) {
+ for(k=excl->index[i]; k<excl->index[i+1]; k++) {
+ (bexcl)[((atom_id) (excl->a[k]))] |= (1<<((atom_id) (i-start)));
+ }
+ }
+ }
+}
+int calc_naaj(int icg,int cgtot)
+{
+ int naaj;
+ if ((cgtot % 2) == 1) {
+ naaj = 1+(cgtot/2);
+ }
+ else if ((cgtot % 4) == 0) {
+ if (icg < cgtot/2) {
+ if ((icg % 2) == 0)
+ naaj=1+(cgtot/2);
+ }
+ else {
+ if ((icg % 2) == 1)
+ naaj=1+(cgtot/2);
+ }
+ }
+ else {
+ if ((icg % 2) == 0)
+ naaj=1+(cgtot/2);
+ else
+ naaj=cgtot/2;
+ }
+ return naaj;
+}
+static void get_dx(int Nx,real gridx,real grid_x,real rc2,real x,
+ int *dx0,int *dx1,real *dcx2)
+{
+ real dcx,tmp;
+ int xgi,xgi0,xgi1,i;
+ xgi = (int)(Nx+x*grid_x)-Nx;
+ if (xgi < 0) {
+ *dx0 = 0;
+ *dx1 = -1;
+ } else if (xgi >= Nx) {
+ *dx0 = Nx;
+ *dx1 = Nx-1;
+ } else {
+ dcx2[xgi] = 0;
+ *dx0 = xgi;
+ xgi0 = xgi-1;
+ *dx1 = xgi;
+ xgi1 = xgi+1;
+ }
+ for(i=xgi0; i>=0; i--) {
+ dcx = (i+1)*gridx-x;
+ tmp = dcx*dcx;
+ if (tmp >= rc2)
+ *dx0 = i;
+ dcx2[i] = tmp;
+ }
+ for(i=xgi1; i<Nx; i++) {
+ dcx = i*gridx-x;
+ tmp = dcx*dcx;
+ if (tmp >= rc2)
+ *dx1 = i;
+ dcx2[i] = tmp;
+ }
+}
+static void do_longrange(FILE *log,t_commrec *cr,t_topology *top,t_forcerec *fr,
+ int ngid,t_mdatoms *md,int icg,
+ int jgid,int nlr,
+ atom_id lr[],t_excl bexcl[],int shift,
+ rvec x[],rvec box_size,t_nrnb *nrnb,
+ real lambda,real *dvdlambda,
+ t_groups *grps,int bVDWOnly,int bCoulOnly,
+ int bDoForces,int bHaveLJ[])
+{
+ int i;
+ for(i=0; (i<eNL_NR); i++) {
+ if ((fr->nlist_lr[i].nri > fr->nlist_lr[i].maxnri-32) || bDoForces) {
+ close_neighbor_list(fr,1,i);
+ do_fnbf(log,cr,fr,x,fr->f_twin,md,
+ grps->estat.ee[egLJLR],grps->estat.ee[egLR],box_size,
+ nrnb,lambda,dvdlambda,1,i);
+ reset_neighbor_list(fr,1,i);
+ }
+ }
+ if (!bDoForces) {
+ put_in_list(bHaveLJ,ngid,md,icg,jgid,nlr,lr,top->blocks[ebCGS].index,
+ bexcl,shift,fr,
+ 1,bVDWOnly,bCoulOnly);
+ }
+}
+static int ns5_core(FILE *log,t_commrec *cr,t_forcerec *fr,int cg_index[],
+ matrix box,rvec box_size,int ngid,
+ t_topology *top,t_groups *grps,
+ t_grid *grid,rvec x[],t_excl bexcl[],int *bExcludeAlleg,
+ t_nrnb *nrnb,t_mdatoms *md,
+ real lambda,real *dvdlambda,
+ int bHaveLJ[])
+{
+ static atom_id **nl_lr_ljc,**nl_lr_one,**nl_sr=((void *)0);
+ static int *nlr_ljc,*nlr_one,*nsr;
+ static real *dcx2=((void *)0),*dcy2=((void *)0),*dcz2=((void *)0);
+ t_block *cgs=&(top->blocks[ebCGS]);
+ unsigned short *gid=md->cENER;
+ int tx,ty,tz,dx,dy,dz,cj;
+ int dx0,dx1,dy0,dy1,dz0,dz1;
+ int Nx,Ny,Nz,shift=-1,j,nrj,nns,nn=-1;
+ real gridx,gridy,gridz,grid_x,grid_y,grid_z;
+ int icg=-1,iicg,cgsnr,i0,nri,naaj,min_icg,icg_naaj,jjcg,cgj0,jgid;
+ int bVDWOnly,bCoulOnly;
+ rvec xi,*cgcm;
+ real r2,rs2,rvdw2,rcoul2,rm2,rl2,XI,YI,ZI,dcx,dcy,dcz,tmp1,tmp2;
+ int *i_eg_excl;
+ int use_twinrange,use_two_cutoffs;
+ cgsnr = cgs->nr;
+ rs2 = ((fr->rlist)*(fr->rlist));
+ if (fr->bTwinRange) {
+ rvdw2 = ((fr->rvdw)*(fr->rvdw));
+ rcoul2 = ((fr->rcoulomb)*(fr->rcoulomb));
+ } else {
+ }
+ rm2 = (((rvdw2) < (rcoul2)) ? (rvdw2) : (rcoul2) );
+ rl2 = (((rvdw2) > (rcoul2)) ? (rvdw2) : (rcoul2) );
+ use_twinrange = (rs2 < rm2);
+ use_two_cutoffs = (rm2 < rl2);
+ bVDWOnly = (rvdw2 > rcoul2);
+ bCoulOnly = !bVDWOnly;
+ if (nl_sr == ((void *)0)) {
+ (nl_sr)=save_calloc("nl_sr","ns.c",1341, (ngid),sizeof(*(nl_sr)));
+ (nsr)=save_calloc("nsr","ns.c",1343, (ngid),sizeof(*(nsr)));
+ (nlr_ljc)=save_calloc("nlr_ljc","ns.c",1344, (ngid),sizeof(*(nlr_ljc)));
+ (nlr_one)=save_calloc("nlr_one","ns.c",1345, (ngid),sizeof(*(nlr_one)));
+ if (use_twinrange)
+ (nl_lr_ljc)=save_calloc("nl_lr_ljc","ns.c",1349, (ngid),sizeof(*(nl_lr_ljc)));
+ if (use_two_cutoffs)
+ (nl_lr_one)=save_calloc("nl_lr_one","ns.c",1353, (ngid),sizeof(*(nl_lr_one)));
+ for(j=0; (j<ngid); j++) {
+ (nl_sr[j])=save_calloc("nl_sr[j]","ns.c",1356, (1024),sizeof(*(nl_sr[j])));
+ if (use_twinrange)
+ (nl_lr_ljc[j])=save_calloc("nl_lr_ljc[j]","ns.c",1358, (1024),sizeof(*(nl_lr_ljc[j])));
+ if (use_two_cutoffs)
+ (nl_lr_one[j])=save_calloc("nl_lr_one[j]","ns.c",1360, (1024),sizeof(*(nl_lr_one[j])));
+ }
+ if (debug)
+ fprintf(debug,"ns5_core: rs2 = %g, rvdw2 = %g, rcoul2 = %g (nm^2)\n",
+ rs2,rvdw2,rcoul2);
+ }
+ cgcm = fr->cg_cm;
+ Nx = grid->nrx;
+ Ny = grid->nry;
+ if (dcx2 == ((void *)0)) {
+ (dcx2)=save_calloc("dcx2","ns.c",1379, (Nx*2),sizeof(*(dcx2)));
+ (dcy2)=save_calloc("dcy2","ns.c",1380, (Ny*2),sizeof(*(dcy2)));
+ (dcz2)=save_calloc("dcz2","ns.c",1381, (Nz*2),sizeof(*(dcz2)));
+ }
+ gridx = box[0][0]/grid->nrx;
+ gridy = box[1][1]/grid->nry;
+ gridz = box[2][2]/grid->nrz;
+ grid_x = 1/gridx;
+ grid_y = 1/gridy;
+ grid_z = 1/gridz;
+ for(iicg=fr->cg0; (iicg < fr->hcg); iicg++) {
+ icg = cg_index[iicg];
+ if (icg != iicg)
+ fatal_error(0,"icg = %d, iicg = %d, file %s, line %d",icg,iicg,"ns.c",
+ 1408);
+ if(bExcludeAlleg[icg])
+ i_eg_excl = fr->eg_excl + ngid*gid[cgs->index[icg]];
+ setexcl(cgs->index[icg],cgs->index[icg+1],&top->atoms.excl,1,bexcl);
+ naaj = calc_naaj(icg,cgsnr);
+ icg_naaj = icg+naaj;
+ for (tz=-1; tz<=1; tz++) {
+ ZI = cgcm[icg][2]+tz*box[2][2];
+ get_dx(Nz,gridz,grid_z,rcoul2,ZI,&dz0,&dz1,dcz2);
+ if (dz0 > dz1)
+ for (ty=-1; ty<=1; ty++) {
+ YI = cgcm[icg][1]+ty*box[1][1]+tz*box[2][1];
+ get_dx(Ny,gridy,grid_y,rcoul2,YI,&dy0,&dy1,dcy2);
+ for (tx=-1; tx<=1; tx++) {
+ get_dx(Nx,gridx,grid_x,rcoul2,XI,&dx0,&dx1,dcx2);
+ shift=((2*1 +1)*((2*1 +1)*((tz)+1)+(ty)+1)+(tx)+1);
+ for (dx=dx0; (dx<=dx1); dx++) {
+ for (dy=dy0; (dy<=dy1); dy++) {
+ for (dz=dz0; (dz<=dz1); dz++) {
+ if (tmp2 > dcz2[dz]) {
+ for (j=0; (j<nrj); j++) {
+ if (((jjcg >= icg) && (jjcg < icg_naaj)) ||
+ ((jjcg < min_icg))) {
+ if (r2 < rl2) {
+ if (!i_eg_excl[jgid]) {
+ if (r2 < rs2) {
+ if (nsr[jgid] >= 1024) {
+ put_in_list(bHaveLJ,ngid,md,icg,jgid,
+ nsr[jgid],nl_sr[jgid],
+ cgs->index, bexcl,
+ shift,fr,0,0,0);
+ }
+ } else if (r2 < rm2) {
+ } else if (use_two_cutoffs) {
+ if (nlr_one[jgid] >= 1024) {
+ do_longrange(log,cr,top,fr,ngid,md,icg,jgid,
+ nlr_one[jgid],
+ nl_lr_one[jgid],bexcl,shift,x,
+ box_size,nrnb,
+ lambda,dvdlambda,grps,
+ bVDWOnly,bCoulOnly,0,
+ bHaveLJ);
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+}
+int search_neighbours(FILE *log,t_forcerec *fr,
+ rvec x[],matrix box,
+ t_topology *top,t_groups *grps,
+ t_commrec *cr,t_nsborder *nsb,
+ t_nrnb *nrnb,t_mdatoms *md,
+ real lambda,real *dvdlambda)
+{
+ static t_grid *grid=((void *)0);
+ static t_excl *bexcl;
+ static int *bHaveLJ;
+ static int *cg_index=((void *)0),*slab_index=((void *)0);
+ static int *bExcludeAlleg;
+ rvec box_size;
+ int i,j,m,ngid;
+ int nsearch;
+ nsearch = ns5_core(log,cr,fr,cg_index,box,box_size,ngid,top,grps,
+ grid,x,bexcl,bExcludeAlleg,nrnb,md,lambda,dvdlambda,bHaveLJ);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test_fp_attribute_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test_fp_attribute_1.c
new file mode 100644
index 0000000..7538250
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test_fp_attribute_1.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -fno-omit-frame-pointer -fno-inline --save-temps" } */
+
+void
+leaf (void)
+{
+ int a = 0;
+}
+
+__attribute__ ((optimize("omit-frame-pointer")))
+void
+non_leaf_1 (void)
+{
+ leaf ();
+}
+
+__attribute__ ((optimize("omit-frame-pointer")))
+void
+non_leaf_2 (void)
+{
+ leaf ();
+}
+
+/* { dg-final { scan-assembler-times "str\tx30, \\\[sp\\\]" 2 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test_fp_attribute_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test_fp_attribute_2.c
new file mode 100644
index 0000000..675091f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test_fp_attribute_2.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -fomit-frame-pointer -fno-inline --save-temps" } */
+
+void
+leaf (void)
+{
+ int a = 0;
+}
+
+__attribute__ ((optimize("no-omit-frame-pointer")))
+void
+non_leaf_1 (void)
+{
+ leaf ();
+}
+
+__attribute__ ((optimize("no-omit-frame-pointer")))
+void
+non_leaf_2 (void)
+{
+ leaf ();
+}
+
+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60650-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60650-2.c
new file mode 100644
index 0000000..1946760
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60650-2.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -march=armv7-a" } */
+
+int a, h, j;
+long long d, e, i;
+int f;
+fn1 (void *p1, int p2)
+{
+ switch (p2)
+ case 8:
+{
+ register b = *(long long *) p1, c asm ("r2");
+ asm ("%0": "=r" (a), "=r" (c):"r" (b), "r" (0));
+ *(long long *) p1 = c;
+ }
+}
+
+fn2 ()
+{
+ int k;
+ k = f;
+ while (1)
+ {
+ fn1 (&i, sizeof i);
+ e = d + k;
+ switch (d)
+ case 0:
+ (
+ {
+ register l asm ("r4");
+ register m asm ("r0");
+ asm (" .err .endif\n\t": "=r" (h), "=r" (j):"r" (m),
+ "r"
+ (l));;
+ });
+ }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60650.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60650.c
new file mode 100644
index 0000000..17a5ed4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60650.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } {"-mfloat-abi=softfp" } } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -mabi=apcs-gnu -mfloat-abi=softfp" } */
+
+
+struct super_block
+{
+ int s_blocksize_bits;
+};
+struct btrfs_fs_info
+{
+ struct super_block *sb;
+};
+struct btrfs_root
+{
+ struct btrfs_fs_info *fs_info;
+} *b;
+
+
+int a, c, d;
+long long e;
+
+truncate_one_csum (struct btrfs_root *p1, long long p2, long long p3)
+{
+ int f, g, i = p1->fs_info->sb->s_blocksize_bits;
+ g = a;
+ long long h = p2 + p3;
+ f = foo1 (b, 0, c, 0);
+ e = f / g;
+ e <<= p1->fs_info->sb->s_blocksize_bits;
+ if (d < p2)
+ {
+ int j = e - h >> i;
+ foo2 (p1, 0, j);
+ }
+ else
+ {
+ asm ("1\t.long ");
+ __builtin_unreachable ();
+ }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60657.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60657.c
new file mode 100644
index 0000000..66355c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60657.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv7-a" } */
+
+
+void foo (void);
+
+void
+bar (int x, int y)
+{
+ y = 9999;
+ if (x & (1 << y))
+ foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60663.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60663.c
new file mode 100644
index 0000000..b79b830
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60663.c
@@ -0,0 +1,11 @@
+/* PR rtl-optimization/60663 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv7-a" } */
+
+int
+foo (void)
+{
+ unsigned i, j;
+ asm ("%0 %1" : "=r" (i), "=r" (j));
+ return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/dev-specific-rmw.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/dev-specific-rmw.c
new file mode 100644
index 0000000..0a8393e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/dev-specific-rmw.c
@@ -0,0 +1,13 @@
+/* Verify that rmw instructions supported */
+/* { dg-do assemble } */
+
+int main()
+{
+ #ifdef __AVR_ISA_RMW__
+ __asm("xch Z, r12");
+ __asm("las Z, r12");
+ __asm("lac Z, r12");
+ __asm("lat Z, r12");
+ #endif
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-3.c
index 1b8dc8b..0c51a21 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-3.c
@@ -1,6 +1,6 @@
/* Verify that 387 mathematical constants are recognized. */
/* { dg-do compile } */
-/* { dg-options "-O2 -mfpmath=387 -mfancy-math-387" } */
+/* { dg-options "-O2 -mfpmath=387 -mfancy-math-387 -mtune=generic" } */
/* { dg-final { scan-assembler "fldpi" } } */
/* { dg-require-effective-target large_long_double } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-4.c
index 27c48ed..10fe931 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-4.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mfancy-math-387" } */
+/* { dg-options "-O2 -mfancy-math-387 -mtune=generic" } */
/* { dg-final { scan-assembler "fldpi" } } */
/* { dg-require-effective-target large_long_double } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c
index 238f020..ee1f313 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c
index c57ef8f..5c3f22f 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c
index 801bd39..41a07d2 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c
index facee9f..7e7e018 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c
index 67ca4a7..8c08bf5 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c
index b2d539b..8e33a98 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c
index 46d173f..4d61d7a 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c
index 97affb4..a788681 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c
index e711256..70bd5cd 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c
index 97affb4..a788681 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c
index 67f3afc..691e02f 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c
index 843128b..45527f5 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c
index f8f399f..ae7966f 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c
index 0a23a28..d96fee1 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c
index 1cb90b5..404c2ee 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
index 1fe52bb..0c476cd 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load -mno-prefer-avx128" } */
#define N 1024
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
index 933f265..30b42aa 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load -mno-prefer-avx128" } */
void
avx_test (char **cp, char **ep)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
index 1d35ef5..dcd630d 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -dp -mavx -mno-avx256-split-unaligned-load -mno-avx256-split-unaligned-store -fno-common" } */
+/* { dg-options "-O3 -dp -mavx -mno-avx256-split-unaligned-load -mno-avx256-split-unaligned-store -mno-prefer-avx128 -fno-common" } */
#define N 1024
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
index 77eaa42..5e8c30d 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store -fno-common" } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store -mno-prefer-avx128 -fno-common" } */
#define N 1024
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
index 48e2efa..eeabfe9 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store" } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store -mno-prefer-avx128" } */
#define N 1024
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c
index 8568245..68ff923 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -dp -mavx -mno-avx256-split-unaligned-load -mno-avx256-split-unaligned-store -fno-common" } */
+/* { dg-options "-O3 -dp -mavx -mno-avx256-split-unaligned-load -mno-avx256-split-unaligned-store -mno-prefer-avx128 -fno-common" } */
#define N 1024
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff32x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff32x4-2.c
index 271c862..35eabc2 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff32x4-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff32x4-2.c
@@ -43,7 +43,7 @@ TEST (void)
for (i = 0; i < SIZE; i++)
{
s1.a[i] = 1.2 / (i + 0.378);
- s1.a[i] = 91.02 / (i + 4.3578);
+ s2.a[i] = 91.02 / (i + 4.3578);
u1.a[i] = DEFAULT_VALUE;
u2.a[i] = DEFAULT_VALUE;
u3.a[i] = DEFAULT_VALUE;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff64x2-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff64x2-2.c
index 4842942..9fee420 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff64x2-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff64x2-2.c
@@ -43,7 +43,7 @@ TEST (void)
for (i = 0; i < SIZE; i++)
{
s1.a[i] = 1.2 / (i + 0.378);
- s1.a[i] = 91.02 / (i + 4.3578);
+ s2.a[i] = 91.02 / (i + 4.3578);
u1.a[i] = DEFAULT_VALUE;
u2.a[i] = DEFAULT_VALUE;
u3.a[i] = DEFAULT_VALUE;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi32x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi32x4-2.c
index 105c715..9b1603c 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi32x4-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi32x4-2.c
@@ -43,7 +43,7 @@ TEST (void)
for (i = 0; i < SIZE; i++)
{
s1.a[i] = 1.2 / (i + 0.378);
- s1.a[i] = 91.02 / (i + 4.3578);
+ s2.a[i] = 91.02 / (i + 4.3578);
u1.a[i] = DEFAULT_VALUE;
u2.a[i] = DEFAULT_VALUE;
u3.a[i] = DEFAULT_VALUE;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi64x2-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi64x2-2.c
index d79d8f6..85a5918 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi64x2-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi64x2-2.c
@@ -43,7 +43,7 @@ TEST (void)
for (i = 0; i < SIZE; i++)
{
s1.a[i] = 1.2 / (i + 0.378);
- s1.a[i] = 91.02 / (i + 4.3578);
+ s2.a[i] = 91.02 / (i + 4.3578);
u1.a[i] = DEFAULT_VALUE;
u2.a[i] = DEFAULT_VALUE;
u3.a[i] = DEFAULT_VALUE;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-1.c
index a05cb27..c66a9d8 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-1.c
@@ -2,10 +2,10 @@
/* { dg-options "-O2 -mbmi " } */
/* { dg-final { scan-assembler "andn\[^\\n]*eax" } } */
/* { dg-final { scan-assembler-times "bextr\[ \\t]+\[^\\n]*eax" 2 } } */
-/* { dg-final { scan-assembler "blsi\[^\\n]*eax" } } */
-/* { dg-final { scan-assembler "blsmsk\[^\\n]*eax" } } */
-/* { dg-final { scan-assembler "blsr\[^\\n]*eax" } } */
-/* { dg-final { scan-assembler "tzcntl\[^\\n]*eax" } } */
+/* { dg-final { scan-assembler-times "blsi\[^\\n]*eax" 2 } } */
+/* { dg-final { scan-assembler-times "blsmsk\[^\\n]*eax" 2 } } */
+/* { dg-final { scan-assembler-times "blsr\[^\\n]*eax" 2 } } */
+/* { dg-final { scan-assembler-times "tzcntl\[^\\n]*eax" 2 } } */
#include <x86intrin.h>
@@ -36,19 +36,43 @@ func_blsi32 (unsigned int X)
}
unsigned int
+func_blsi32_2 (unsigned int X)
+{
+ return _blsi_u32(X);
+}
+
+unsigned int
func_blsmsk32 (unsigned int X)
{
return __blsmsk_u32(X);
}
unsigned int
+func_blsmsk32_2 (unsigned int X)
+{
+ return _blsmsk_u32(X);
+}
+
+unsigned int
func_blsr32 (unsigned int X)
{
return __blsr_u32(X);
}
unsigned int
+func_blsr32_2 (unsigned int X)
+{
+ return _blsr_u32(X);
+}
+
+unsigned int
func_tzcnt32 (unsigned int X)
{
return __tzcnt_u32(X);
}
+
+unsigned int
+func_tzcnt32_2 (unsigned int X)
+{
+ return _tzcnt_u32(X);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-2.c
index 68d06a2..6eea66a 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-2.c
@@ -2,10 +2,10 @@
/* { dg-options "-O2 -mbmi " } */
/* { dg-final { scan-assembler "andn\[^\\n]*rax" } } */
/* { dg-final { scan-assembler-times "bextr\[ \\t]+\[^\\n]*rax" 2 } } */
-/* { dg-final { scan-assembler "blsi\[^\\n]*rax" } } */
-/* { dg-final { scan-assembler "blsmsk\[^\\n]*rax" } } */
-/* { dg-final { scan-assembler "blsr\[^\\n]*rax" } } */
-/* { dg-final { scan-assembler "tzcntq\[^\\n]*rax" } } */
+/* { dg-final { scan-assembler-times "blsi\[^\\n]*rax" 2 } } */
+/* { dg-final { scan-assembler-times "blsmsk\[^\\n]*rax" 2 } } */
+/* { dg-final { scan-assembler-times "blsr\[^\\n]*rax" 2 } } */
+/* { dg-final { scan-assembler-times "tzcntq\[^\\n]*rax" 2 } } */
#include <x86intrin.h>
@@ -36,19 +36,43 @@ func_blsi64 (unsigned long long X)
}
unsigned long long
+func_blsi64_2 (unsigned long long X)
+{
+ return _blsi_u64 (X);
+}
+
+unsigned long long
func_blsmsk64 (unsigned long long X)
{
return __blsmsk_u64 (X);
}
unsigned long long
+func_blsmsk64_2 (unsigned long long X)
+{
+ return _blsmsk_u64 (X);
+}
+
+unsigned long long
func_blsr64 (unsigned long long X)
{
return __blsr_u64 (X);
}
unsigned long long
+func_blsr64_2 (unsigned long long X)
+{
+ return _blsr_u64 (X);
+}
+
+unsigned long long
func_tzcnt64 (unsigned long long X)
{
return __tzcnt_u64 (X);
}
+
+unsigned long long
+func_tzcnt64_2 (unsigned long long X)
+{
+ return _tzcnt_u64 (X);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-builtin.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-builtin.c
index 7135cc9..3e59a71 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-builtin.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-builtin.c
@@ -2,7 +2,7 @@
and add instructions FMA4 systems. */
/* { dg-do compile { target { ! { ia32 } } } } */
-/* { dg-options "-O2 -mfma4" } */
+/* { dg-options "-O2 -mfma4 -mno-fma" } */
#ifndef __FP_FAST_FMAF
# error "__FP_FAST_FMAF should be defined"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma-2.c
index c15be1e..ae6ca8d 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma-2.c
@@ -3,7 +3,7 @@
vfnmsubss on FMA4 systems. */
/* { dg-do compile { target { ! { ia32 } } } } */
-/* { dg-options "-O2 -funsafe-math-optimizations -mfma4" } */
+/* { dg-options "-O2 -funsafe-math-optimizations -mfma4 -mno-fma" } */
extern void exit (int);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma.c
index 63b35dc..1b8fb84 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma.c
@@ -3,7 +3,7 @@
vfnmsubss on FMA4 systems. */
/* { dg-do compile { target { ! { ia32 } } } } */
-/* { dg-options "-O2 -mfma4" } */
+/* { dg-options "-O2 -mfma4 -mno-fma" } */
extern void exit (int);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector-2.c
index d8b0d08..b518aa8 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { ! { ia32 } } } } */
-/* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic" } */
+/* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic -mno-fma" } */
float r[256], s[256];
float x[256];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector.c
index db5ffdd..cd55063 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector.c
@@ -2,7 +2,7 @@
instructions vector into vfmaddps on FMA4 systems. */
/* { dg-do compile { target { ! { ia32 } } } } */
-/* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic" } */
+/* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic -mno-fma" } */
extern void exit (int);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-2.c
index 88c14b2..e535586 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-2.c
@@ -1,5 +1,6 @@
/* Test whether using target specific options, we can generate FMA4 code. */
/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=k8" } } */
/* { dg-options "-O2 -march=k8" } */
extern void exit (int);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-3.c
index f3f4db7..bac7986 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-3.c
@@ -2,6 +2,7 @@
setting the architecture. */
/* { dg-do compile } */
/* { dg-require-effective-target lp64 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=k8" } } */
/* { dg-options "-O2 -march=k8 -mno-sse3" } */
extern void exit (int);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-9.c
index 78714e1..14b7abd 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-9.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-9.c
@@ -1,5 +1,6 @@
/* Test whether using target specific options, we can generate FMA4 code. */
/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=k8" } } */
/* { dg-options "-O2 -march=k8 -mfpmath=sse -msse2" } */
extern void exit (int);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-1.c
index d98c14f..3a4406f 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-1.c
@@ -1,4 +1,5 @@
/* { dg-do run } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=x86-64" } } */
/* { dg-options "-march=x86-64 -msse4" } */
extern void abort (void);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_1.c
index 1d99b4c..94e512b 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic -mno-fma4" } */
/* Test that the compiler properly optimizes floating point multiply
and add instructions into FMA3 instructions. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_2.c
index e101100..ffceab4 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic -mno-fma4" } */
/* Test that the compiler properly optimizes floating point multiply
and add instructions into FMA3 instructions. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_3.c
index f099e25..cdb4d33 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic -mno-fma4" } */
/* Test that the compiler properly optimizes floating point multiply
and add instructions into FMA3 instructions. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_4.c
index 969f31c..dda487e 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_4.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic -mno-fma4" } */
/* Test that the compiler properly optimizes floating point multiply
and add instructions into FMA3 instructions. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_5.c
index 85ccdd0..98909ae 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_5.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic -mno-fma4" } */
/* Test that the compiler properly optimizes floating point multiply
and add instructions into FMA3 instructions. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_6.c
index 019ed9a..538065a 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_6.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic -mno-fma4" } */
/* Test that the compiler properly optimizes floating point multiply
and add instructions into FMA3 instructions. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_1.c
index d1913d7..ff10981 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic -mno-fma4" } */
/* Test that the compiler properly optimizes floating point multiply
and add instructions into FMA3 instructions. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_2.c
index 5e01425..38c6b52 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic -mno-fma4" } */
/* Test that the compiler properly optimizes floating point multiply
and add instructions into FMA3 instructions. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_3.c
index 7b9e3f5..177ba35 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic -mno-fma4" } */
/* Test that the compiler properly optimizes floating point multiply
and add instructions into FMA3 instructions. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_4.c
index cc675c1..8ee68d1 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_4.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic -mno-fma4" } */
/* Test that the compiler properly optimizes floating point multiply
and add instructions into FMA3 instructions. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_5.c
index ac0b361..23288d0 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_5.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic -mno-fma4" } */
/* Test that the compiler properly optimizes floating point multiply
and add instructions into FMA3 instructions. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_6.c
index c84ac11..07a5fba 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_6.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic -mno-fma4" } */
/* Test that the compiler properly optimizes floating point multiply
and add instructions into FMA3 instructions. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-1.c
index a2b66d9..3117771 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-1.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
/* { dg-options "-O2 -march=atom -mmemcpy-strategy=vector_loop:-1:align" } */
/* { dg-final { scan-assembler-times "movdqa" 8 { target { ! { ia32 } } } } } */
/* { dg-final { scan-assembler-times "movdqa" 4 { target { ia32 } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-2.c
index c2f49f0..303edca 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-2.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
/* { dg-options "-O2 -march=atom -mmemcpy-strategy=vector_loop:3000:align,libcall:-1:align" } */
/* { dg-final { scan-assembler-times "movdqa" 8 { target { ! { ia32 } } } } } */
/* { dg-final { scan-assembler-times "movdqa" 4 { target { ia32 } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-1.c
index c61c067..1ea682a 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-1.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */
/* { dg-final { scan-assembler-times "movdqa" 8 { target { ! { ia32 } } } } } */
/* { dg-final { scan-assembler-times "movdqa" 4 { target { ia32 } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-2.c
index 8a646d5..3befef9 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-2.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */
/* { dg-final { scan-assembler-times "movdqa" 4} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-1.c
index ad0d130..f7e4516 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-1.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */
/* { dg-final { scan-assembler-times "movdqa" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-2.c
index f2ceb44..92e6100 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-2.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */
/* { dg-final { scan-assembler-times "movdqa" 4} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27971.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27971.c
index 27888de..149bf2b 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27971.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27971.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -mno-tbm" } */
unsigned array[4];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30970.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30970.c
index 96d64e5..b1fc2d3 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30970.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30970.c
@@ -1,5 +1,5 @@
/* { dg-do compile }
-/* { dg-options "-msse2 -O2 -ftree-vectorize" } */
+/* { dg-options "-msse2 -O2 -ftree-vectorize -mtune=generic" } */
#define N 256
int b[N];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-4a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-4a.c
index bea6c1f..19e872a 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-4a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-4a.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */
+/* { dg-options "-O1 -msse4.2 -ftree-vectorize -mno-avx" } */
#include "pr42542-4.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390.c
index 7dc925a..749c61a 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-std=c99 -O3" } */
+/* { dg-options "-std=c99 -O3 -mno-fma -mno-fma4" } */
extern double fma (double, double, double);
void fun() __attribute__((target("fma")));
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60693.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60693.c
new file mode 100644
index 0000000..e6033a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60693.c
@@ -0,0 +1,13 @@
+/* PR target/60693 */
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+
+void bar (char *);
+
+void
+foo (void)
+{
+ char buf[4096];
+ __builtin_memcpy (buf, (void *) 0x8000, 4096);
+ bar (buf);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60700.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60700.c
new file mode 100644
index 0000000..5428f36
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60700.c
@@ -0,0 +1,59 @@
+/* PR rtl-optimization/60700 */
+/* { dg-do run { target ia32 } } */
+/* { dg-options "-O3 -march=i686" } */
+
+int
+__attribute__((noinline))
+foo (void)
+{
+ return 0;
+}
+
+void *g = (void *)1;
+
+struct st {
+ char data[36]; /* must be greater than 32. */
+};
+
+int
+__attribute__((noinline))
+repro(struct st **out)
+{
+ int status = 0;
+
+ *out = 0;
+
+ status = foo();
+ if (status != 0) {
+ return status;
+ }
+
+ if (0 == g) {
+ status = 999;
+ return status;
+ }
+
+ *out = (struct st *)__builtin_malloc(sizeof(struct st));
+ if (0 == *out) {
+ status = 42;
+ return status;
+ }
+
+ __builtin_memset(*out, 0, sizeof(struct st));
+
+ return status;
+}
+
+int
+main ()
+{
+ struct st *p;
+ int ret = repro (&p);
+ unsigned int i;
+
+ for (i = 0; i < sizeof (p->data)/sizeof (p->data[0]); i++)
+ if (p->data[i] != 0)
+ __builtin_abort ();
+
+ return ret;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c
index a2313a4..6a50573 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c
@@ -1,4 +1,5 @@
/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=core2" } } */
/* { dg-options "-O2 -msse4 -march=core2 -dp" } */
#include <emmintrin.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-1.c
index ef89059..a825229 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-1.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* This test checks for absolute memory operands. */
/* { dg-require-effective-target nonpic } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=k8" } } */
/* { dg-options "-O2 -msse2 -march=k8" } */
/* { dg-final { scan-assembler "andpd\[^\\n\]*magic" } } */
/* { dg-final { scan-assembler "andnpd\[^\\n\]*magic" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-2.c
index b68a639..37953ca 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-2.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=k8" } } */
/* { dg-options "-O2 -msse2 -march=k8" } */
/* { dg-final { scan-assembler "andpd" } } */
/* { dg-final { scan-assembler "andnpd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-5.c
index 75133e9..4e22e59 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-5.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-5.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* This test checks for absolute memory operands. */
/* { dg-require-effective-target nonpic } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=k8" } } */
/* { dg-options "-O2 -msse2 -march=k8" } */
/* { dg-final { scan-assembler "pand\[^\\n\]*magic" } } */
/* { dg-final { scan-assembler "pandn\[^\\n\]*magic" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c
new file mode 100644
index 0000000..8a5cbfa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2" } */
+/* { dg-final { scan-assembler-times "lq" 1 } } */
+/* { dg-final { scan-assembler-times "stq" 1 } } */
+/* { dg-final { scan-assembler-not "bl __atomic" } } */
+/* { dg-final { scan-assembler-not "lqarx" } } */
+/* { dg-final { scan-assembler-not "stqcx" } } */
+
+__int128
+atomic_load_128_relaxed (__int128 *ptr)
+{
+ return __atomic_load_n (ptr, __ATOMIC_RELAXED);
+}
+
+void
+atomic_store_128_relaxed (__int128 *ptr, __int128 val)
+{
+ __atomic_store_n (ptr, val, __ATOMIC_RELAXED);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c
new file mode 100644
index 0000000..d166498
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O3 -mcpu=power8" } */
+/* { dg-final { scan-assembler "vbpermq" } } */
+/* { dg-final { scan-assembler "mfvsrd" } } */
+/* { dg-final { scan-assembler-not "stfd" } } */
+/* { dg-final { scan-assembler-not "stxvd2x" } } */
+
+#include <altivec.h>
+
+#if __LITTLE_ENDIAN__
+#define OFFSET 1
+#else
+#define OFFSET 0
+#endif
+
+long foos (vector signed char a, vector signed char b)
+{
+ return vec_extract (vec_vbpermq (a, b), OFFSET);
+}
+
+long foou (vector unsigned char a, vector unsigned char b)
+{
+ return vec_extract (vec_vbpermq (a, b), OFFSET);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60676.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60676.c
new file mode 100644
index 0000000..86fd8c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60676.c
@@ -0,0 +1,128 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xxsldwi" } } */
+/* { dg-final { scan-assembler "xxpermdi" } } */
+
+#include <altivec.h>
+
+vector double
+v2df_shift (vector double a, vector double b)
+{
+ return vec_xxsldwi (a, b, 1);
+}
+
+vector float
+v4sf_shift (vector float a, vector float b)
+{
+ return vec_xxsldwi (a, b, 1);
+}
+
+vector long long
+v2di_shift (vector long long a, vector long long b)
+{
+ return vec_xxsldwi (a, b, 1);
+}
+
+vector unsigned long long
+v2diu_shift (vector unsigned long long a, vector unsigned long long b)
+{
+ return vec_xxsldwi (a, b, 1);
+}
+
+vector int
+v4si_shift (vector int a, vector int b)
+{
+ return vec_xxsldwi (a, b, 1);
+}
+
+vector unsigned int
+v4siu_shift (vector unsigned int a, vector unsigned int b)
+{
+ return vec_xxsldwi (a, b, 1);
+}
+
+vector short
+v8hi_shift (vector short a, vector short b)
+{
+ return vec_xxsldwi (a, b, 1);
+}
+
+vector unsigned short
+v8hiu_shift (vector unsigned short a, vector unsigned short b)
+{
+ return vec_xxsldwi (a, b, 1);
+}
+
+vector signed char
+v16qi_shift (vector signed char a, vector signed char b)
+{
+ return vec_xxsldwi (a, b, 1);
+}
+
+vector unsigned char
+v16qiu_shift (vector unsigned char a, vector unsigned char b)
+{
+ return vec_xxsldwi (a, b, 1);
+}
+
+vector double
+v2df_permute (vector double a, vector double b)
+{
+ return vec_xxpermdi (a, b, 1);
+}
+
+vector float
+v4sf_permute (vector float a, vector float b)
+{
+ return vec_xxpermdi (a, b, 1);
+}
+
+vector long long
+v2di_permute (vector long long a, vector long long b)
+{
+ return vec_xxpermdi (a, b, 1);
+}
+
+vector unsigned long long
+v2diu_permute (vector unsigned long long a, vector unsigned long long b)
+{
+ return vec_xxpermdi (a, b, 1);
+}
+
+vector int
+v4si_permute (vector int a, vector int b)
+{
+ return vec_xxpermdi (a, b, 1);
+}
+
+vector unsigned int
+v4siu_permute (vector unsigned int a, vector unsigned int b)
+{
+ return vec_xxpermdi (a, b, 1);
+}
+
+vector short
+v8hi_permute (vector short a, vector short b)
+{
+ return vec_xxpermdi (a, b, 1);
+}
+
+vector unsigned short
+v8hiu_permute (vector unsigned short a, vector unsigned short b)
+{
+ return vec_xxpermdi (a, b, 1);
+}
+
+vector signed char
+v16qi_permute (vector signed char a, vector signed char b)
+{
+ return vec_xxpermdi (a, b, 1);
+}
+
+vector unsigned char
+v16qiu_permute (vector unsigned char a, vector unsigned char b)
+{
+ return vec_xxpermdi (a, b, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c
new file mode 100644
index 0000000..e1f0ca8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7" } */
+/* { dg-final { scan-assembler "lfd" } } */
+/* { dg-final { scan-assembler-not "lxvd2x" } } */
+
+#include <altivec.h>
+
+#if __LITTLE_ENDIAN__
+#define OFFSET 1
+#else
+#define OFFSET 0
+#endif
+
+double get_value (vector double *p) { return vec_extract (*p, OFFSET); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-2.c
new file mode 100644
index 0000000..be29af8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xxlor" } } */
+/* { dg-final { scan-assembler-not "lfd" } } */
+/* { dg-final { scan-assembler-not "lxvd2x" } } */
+
+#include <altivec.h>
+
+#if __LITTLE_ENDIAN__
+#define OFFSET 1
+#else
+#define OFFSET 0
+#endif
+
+double get_value (vector double v) { return vec_extract (v, OFFSET); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c
new file mode 100644
index 0000000..ea42126
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O3 -mcpu=power8" } */
+/* { dg-final { scan-assembler "mfvsrd" } } */
+/* { dg-final { scan-assembler-not "stfd" } } */
+/* { dg-final { scan-assembler-not "stxvd2x" } } */
+
+#include <altivec.h>
+
+#if __LITTLE_ENDIAN__
+#define OFFSET 1
+#else
+#define OFFSET 0
+#endif
+
+long get_value (vector long v) { return vec_extract (v, OFFSET); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/20140327-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/20140327-1.c
new file mode 100644
index 0000000..f71c38f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/20140327-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -m31 -mzarch" } */
+
+void
+foo ()
+{
+ asm ("" ::: "%f4");
+}
+
+/* { dg-final { scan-assembler "ld" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c
index c1b98e2..982a748 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c
@@ -27,8 +27,8 @@ foo (struct __htm_tdb* tdb, int reg, int *mem, uint64_t *mem64)
cc = __builtin_tbegin ((void *)0x12345678);
cc = __builtin_tbegin (tdb);
cc = __builtin_tbegin (&global_tdb);
- cc = __builtin_tbegin ((void *)(long long)(reg + 0x12345678));
- cc = __builtin_tbegin ((void *)(long long)(reg));
+ cc = __builtin_tbegin ((void *)(long)(reg + 0x12345678));
+ cc = __builtin_tbegin ((void *)(long)(reg));
__builtin_tbegin_nofloat ((void *)0);
__builtin_tbegin_nofloat ((void *)-99999);
@@ -36,8 +36,8 @@ foo (struct __htm_tdb* tdb, int reg, int *mem, uint64_t *mem64)
cc = __builtin_tbegin_nofloat ((void *)0x12345678);
cc = __builtin_tbegin_nofloat (tdb);
cc = __builtin_tbegin_nofloat (&global_tdb);
- cc = __builtin_tbegin_nofloat ((void *)(long long)(reg + 0x12345678));
- cc = __builtin_tbegin_nofloat ((void *)(long long)(reg));
+ cc = __builtin_tbegin_nofloat ((void *)(long)(reg + 0x12345678));
+ cc = __builtin_tbegin_nofloat ((void *)(long)(reg));
__builtin_tbegin_retry ((void *)0, 0);
cc = __builtin_tbegin_retry ((void *)0, 1);
@@ -50,9 +50,9 @@ foo (struct __htm_tdb* tdb, int reg, int *mem, uint64_t *mem64)
cc = __builtin_tbegin_retry (&global_tdb, 42);
cc = __builtin_tbegin_retry ((void *)0x12345678, global);
cc = __builtin_tbegin_retry (
- (void *)(long long) (reg + 0x12345678), global + 1);
+ (void *)(long) (reg + 0x12345678), global + 1);
cc = __builtin_tbegin_retry (
- (void *)(long long)(reg), global - 1);
+ (void *)(long)(reg), global - 1);
__builtin_tbegin_retry_nofloat ((void *)0, 0);
cc = __builtin_tbegin_retry_nofloat ((void *)0, 1);
@@ -65,9 +65,9 @@ foo (struct __htm_tdb* tdb, int reg, int *mem, uint64_t *mem64)
cc = __builtin_tbegin_retry_nofloat (&global_tdb, 42);
cc = __builtin_tbegin_retry_nofloat ((void *)0x12345678, global);
cc = __builtin_tbegin_retry_nofloat (
- (void *)(long long) (reg + 0x12345678), global + 1);
+ (void *)(long) (reg + 0x12345678), global + 1);
cc = __builtin_tbegin_retry_nofloat (
- (void *)(long long)(reg), global - 1);
+ (void *)(long)(reg), global - 1);
__builtin_tbeginc ();
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c
index df7e2ba..6022efb 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c
@@ -1,12 +1,50 @@
-/* { dg-do compile } */
-/* { dg-options "-O3 -march=zEC12 -mzarch" } */
+/* { dg-do run } */
+/* { dg-require-effective-target htm } */
+/* { dg-options "-O3 -march=zEC12 -mzarch --save-temps" } */
-int
-foo ()
+/* __builtin_tbegin has to emit clobbers for all FPRs since the tbegin
+ instruction does not automatically preserves them. If the
+ transaction body is fully contained in a function the backend tries
+ after reload to get rid of the FPR save/restore operations
+ triggered by the clobbers. This testcase failed since the backend
+ was able to get rid of all FPR saves/restores and since these were
+ the only stack operations also of the entire stack space. So even
+ the save/restore of the stack pointer was omitted in the end.
+ However, since the frame layout has been fixed before, the prologue
+ still generated the stack pointer decrement making foo return with
+ a modified stack pointer. */
+
+void abort(void);
+
+void __attribute__((noinline))
+foo (int a)
+{
+ if (__builtin_tbegin (0) == 0)
+ __builtin_tend ();
+}
+
+#ifdef __s390x__
+#define GET_STACK_POINTER(SP) \
+ asm volatile ("stg %%r15, %0" : "=QRST" (SP));
+#else
+#define GET_STACK_POINTER(SP) \
+ asm volatile ("st %%r15, %0" : "=QR" (SP));
+#endif
+
+int main(void)
{
- __builtin_tbegin_nofloat (0);
- __builtin_tbegin_retry_nofloat (0, 42);
+ unsigned long new_sp, old_sp;
+
+ GET_STACK_POINTER (old_sp);
+ foo(42);
+ GET_STACK_POINTER (new_sp);
+
+ if (old_sp != new_sp)
+ abort ();
+
+ return 0;
}
+
/* Make sure no FPR saves/restores are emitted. */
-/* { dg-final { scan-assembler-not "std" } } */
-/* { dg-final { scan-assembler-not "ld" } } */
+/* { dg-final { scan-assembler-not "\tstd\t" } } */
+/* { dg-final { scan-assembler-not "\tld\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c
new file mode 100644
index 0000000..df7e2ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
+
+int
+foo ()
+{
+ __builtin_tbegin_nofloat (0);
+ __builtin_tbegin_retry_nofloat (0, 42);
+}
+/* Make sure no FPR saves/restores are emitted. */
+/* { dg-final { scan-assembler-not "std" } } */
+/* { dg-final { scan-assembler-not "ld" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/s390.exp b/gcc-4.9/gcc/testsuite/gcc.target/s390/s390.exp
index 1b6d94a..f2ba929 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/s390/s390.exp
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/s390.exp
@@ -24,17 +24,17 @@ if ![istarget s390*-*-*] then {
# Load support procs.
load_lib gcc-dg.exp
-# Return 1 if htm (etnd - extract nesting depth) instructions can be
-# compiled.
+# Return 1 if htm (etnd - extract nesting depth) instructions are
+# understood by the assembler and can be executed.
proc check_effective_target_htm { } {
if { ![check_runtime s390_check_htm [subst {
int main (void)
{
- unsigned int nd = 77;
- asm (".insn rre,0xb2ec0000,%0,0" : "=d" (nd));
+ unsigned int nd;
+ asm ("etnd %0" : "=d" (nd));
return nd;
}
- }]] } { return 0 } else { return 1 }
+ }] "-march=zEC12 -mzarch" ] } { return 0 } else { return 1 }
}
# If a testcase doesn't have special options, use these.