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| author | Steve Ellcey <Steve.Ellcey@imgtec.com> | 2015-03-19 15:09:08 -0700 |
|---|---|---|
| committer | Steve Ellcey <Steve.Ellcey@imgtec.com> | 2015-03-19 15:09:08 -0700 |
| commit | 9f57376006c7afb1561fe3e7a8d8be64f3196acd (patch) | |
| tree | 67be4e16ff59195e9a80737ebf6b262e2ab92911 /gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c | |
| parent | 3951a3654b8197466bee3e6732b3bc94e4018f68 (diff) | |
| download | toolchain_gcc-9f57376006c7afb1561fe3e7a8d8be64f3196acd.tar.gz toolchain_gcc-9f57376006c7afb1561fe3e7a8d8be64f3196acd.tar.bz2 toolchain_gcc-9f57376006c7afb1561fe3e7a8d8be64f3196acd.zip | |
Update MSA Support in MIPS GCC.
Change-Id: Id87035be4552719dc05096bb98b49d4bed91a07a
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c')
| -rw-r--r-- | gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c index 0cdb1b7f2..8354bf7c4 100644 --- a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c @@ -6,7 +6,7 @@ foo (int *r4) { int r5 = r4[0]; int r6 = r4[1]; - r4[2] = r5 * r5; + r4[2] = (r5 << 1) + r6; { register int r5asm asm ("$5") = r5; register int r6asm asm ("$6") = r6; |