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authorBen Cheng <bccheng@google.com>2014-03-25 22:37:19 -0700
committerBen Cheng <bccheng@google.com>2014-03-25 22:37:19 -0700
commit1bc5aee63eb72b341f506ad058502cd0361f0d10 (patch)
treec607e8252f3405424ff15bc2d00aa38dadbb2518 /gcc-4.9/gcc/testsuite/gcc.dg/pr27861-1.c
parent283a0bf58fcf333c58a2a92c3ebbc41fb9eb1fdb (diff)
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Initial checkin of GCC 4.9.0 from trunk (r208799).
Change-Id: I48a3c08bb98542aa215912a75f03c0890e497dba
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.dg/pr27861-1.c')
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/pr27861-1.c67
1 files changed, 67 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/pr27861-1.c b/gcc-4.9/gcc/testsuite/gcc.dg/pr27861-1.c
new file mode 100644
index 000000000..cf269dc0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/pr27861-1.c
@@ -0,0 +1,67 @@
+/* PR target/27861 */
+/* The following code used to cause an ICE during RTL expansion, as
+ expand shift was stripping the SUBREG of a rotate shift count, and
+ later producing a VAR_DECL tree whose DECL_RTL's mode didn't match
+ the VAR_DECL's type's mode. */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef struct sim_state *SIM_DESC;
+typedef enum
+{
+ SIM_OPEN_STANDALONE, SIM_OPEN_DEBUG
+}
+SIM_RC;
+typedef unsigned int unsigned32 __attribute__ ((__mode__ (__SI__)));
+typedef unsigned int unsigned64 __attribute__ ((__mode__ (__DI__)));
+typedef unsigned32 unsigned_address;
+typedef unsigned_address address_word;
+static __inline__ unsigned64
+ __attribute__ ((__unused__)) ROTR64 (unsigned64 val, int shift)
+{
+ unsigned64 result;
+ result = (((val) >> (shift)) | ((val) << ((64) - (shift))));
+ return result;
+}
+typedef struct _sim_cpu sim_cpu;
+enum
+{
+ TRACE_MEMORY_IDX, TRACE_MODEL_IDX, TRACE_ALU_IDX, TRACE_CORE_IDX,
+};
+typedef struct _trace_data
+{
+ char trace_flags[32];
+}
+TRACE_DATA;
+typedef enum
+{
+ nr_watchpoint_types,
+}
+watchpoint_type;
+typedef struct _sim_watchpoints
+{
+ TRACE_DATA trace_data;
+}
+sim_cpu_base;
+struct _sim_cpu
+{
+ sim_cpu_base base;
+};
+struct sim_state
+{
+ sim_cpu cpu[1];
+};
+typedef address_word instruction_address;
+do_dror (SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned64 x,
+ unsigned64 y)
+{
+ unsigned64 result;
+ result = ROTR64 (x, y);
+ {
+ if ((((-1) & (1 << (TRACE_ALU_IDX))) != 0
+ && (((&(((&(sd)->cpu[0])))->base.trace_data))->
+ trace_flags)[TRACE_ALU_IDX] != 0))
+ trace_result_word1 (sd, ((&(sd)->cpu[0])), TRACE_ALU_IDX, (result));
+ }
+}
+