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| author | Steve Ellcey <Steve.Ellcey@imgtec.com> | 2015-03-19 15:09:08 -0700 |
|---|---|---|
| committer | Steve Ellcey <Steve.Ellcey@imgtec.com> | 2015-03-19 15:09:08 -0700 |
| commit | 9f57376006c7afb1561fe3e7a8d8be64f3196acd (patch) | |
| tree | 67be4e16ff59195e9a80737ebf6b262e2ab92911 /gcc-4.9/gcc/target.def | |
| parent | 3951a3654b8197466bee3e6732b3bc94e4018f68 (diff) | |
| download | toolchain_gcc-9f57376006c7afb1561fe3e7a8d8be64f3196acd.tar.gz toolchain_gcc-9f57376006c7afb1561fe3e7a8d8be64f3196acd.tar.bz2 toolchain_gcc-9f57376006c7afb1561fe3e7a8d8be64f3196acd.zip | |
Update MSA Support in MIPS GCC.
Change-Id: Id87035be4552719dc05096bb98b49d4bed91a07a
Diffstat (limited to 'gcc-4.9/gcc/target.def')
| -rw-r--r-- | gcc-4.9/gcc/target.def | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/target.def b/gcc-4.9/gcc/target.def index a67ffa8b5..7bbc91d96 100644 --- a/gcc-4.9/gcc/target.def +++ b/gcc-4.9/gcc/target.def @@ -3218,6 +3218,17 @@ If not defined, the default is to return @code{NULL_RTX}.", rtx, (rtx reg), hook_rtx_rtx_null) +/* Given a register return the mode of the corresponding DWARF frame + register. */ +DEFHOOK +(dwarf_frame_reg_mode, + "Given a register, this hook should return the mode which the\n\ +corresponding Dwarf frame register should have. This is normally\n\ +used to return a smaller mode than the raw mode to prevent call\n\ +clobbered parts of a register altering the frame register size", + enum machine_mode, (int regno), + default_dwarf_frame_reg_mode) + /* If expand_builtin_init_dwarf_reg_sizes needs to fill in table entries not corresponding directly to registers below FIRST_PSEUDO_REGISTER, this hook should generate the necessary |