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| author | Dan Albert <danalbert@google.com> | 2016-01-14 16:43:34 -0800 |
|---|---|---|
| committer | Dan Albert <danalbert@google.com> | 2016-01-22 14:51:24 -0800 |
| commit | 3186be22b6598fbd467b126347d1c7f48ccb7f71 (patch) | |
| tree | 2b176d3ce027fa5340160978effeb88ec9054aaa /gcc-4.8.1/gcc/testsuite/gcc.target/i386 | |
| parent | a45222a0e5951558bd896b0513bf638eb376e086 (diff) | |
| download | toolchain_gcc-3186be22b6598fbd467b126347d1c7f48ccb7f71.tar.gz toolchain_gcc-3186be22b6598fbd467b126347d1c7f48ccb7f71.tar.bz2 toolchain_gcc-3186be22b6598fbd467b126347d1c7f48ccb7f71.zip | |
Check in a pristine copy of GCC 4.8.1.
The copy of GCC that we use for Android is still not working for
mingw. Rather than finding all the differences that have crept into
our GCC, just check in a copy from
ftp://ftp.gnu.org/gnu/gcc/gcc-4.9.3/gcc-4.8.1.tar.bz2.
GCC 4.8.1 was chosen because it is what we have been using for mingw
thus far, and the emulator doesn't yet work when upgrading to 4.9.
Bug: http://b/26523949
Change-Id: Iedc0f05243d4332cc27ccd46b8a4b203c88dcaa3
Diffstat (limited to 'gcc-4.8.1/gcc/testsuite/gcc.target/i386')
2509 files changed, 81788 insertions, 0 deletions
diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000609-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000609-1.c new file mode 100644 index 000000000..a083a5d53 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000609-1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O1 -ffast-math -march=i686" } */ + + +/* Sanity check for fp_jcc_* with TARGET_CMOVE. */ + +extern void abort (void); + +static int test(double a) +{ + if (a) + return 0; +} + +static double zero = 0.0; + +int main () +{ + test (zero); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000614-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000614-1.c new file mode 100644 index 000000000..5e86f02e4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000614-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +void bar(char *p) +{ +} + +static inline void foo (unsigned long base, unsigned char val) +{ + val ^= (1<<2); + bar (val & (1<<5) ? "1" : "2"); + bar (val & (1<<4) ? "1" : "2"); + bar (val & (1<<3) ? "1" : "2"); + bar (val & (1<<2) ? "1" : "2"); + bar (val & (1<<1) ? "1" : "2"); + bar (val & (1<<0) ? "1" : "2"); + asm volatile ("": :"a" (val), "d" (base)); +} + +int main (void) +{ + foo (23, 1); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000614-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000614-2.c new file mode 100644 index 000000000..5b0490707 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000614-2.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +extern void abort (void); +extern void exit (int); + +char buf[8]; + +void bar(char *p) +{ +} + +int main() +{ + union { + unsigned int val; + unsigned char p[4]; + } serial; + + int i; + serial.val = 0; + bar(buf); + for(i = 0; i < 8; i += 4) + { + serial.p [0] += buf [i + 0]; + serial.p [1] += buf [i + 1]; + serial.p [2] += buf [i + 2]; + serial.p [3] += buf [i + 3]; + } + if (serial.val) + abort(); + exit(0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000720-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000720-1.c new file mode 100644 index 000000000..84e136c52 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000720-1.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-mpreferred-stack-boundary=2 -march=i586 -O2 -fomit-frame-pointer" } */ + +extern void *foo(void *a, const void *b, unsigned c); + +extern inline void * +bar(void *a, const void *b, unsigned c) +{ + int d0, d1, d2; + __asm__ __volatile__( + "" : + "=&c" (d0), "=&D" (d1), "=&S" (d2) : + "0" (c/4), "q" (c), "1" (a), "2" (b) : + "memory"); + return a; +} + +typedef struct { + unsigned char a; + unsigned b : 2; + unsigned c : 4; + unsigned d : 2; +} *baz; + +static int +dead(unsigned short *v, char *w, unsigned char *x, int y, int z) +{ + int i = 0; + unsigned short j = *v; + + while (y > 0) { + ((baz)x)->a = j; + ((baz)x)->b = 0; + ((baz)x)->c = 0; + ((baz)x)->d = 0; + __builtin_constant_p(i) ? foo(x, w, i) : bar(x, w, i); + } + return z - y; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000724-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000724-1.c new file mode 100644 index 000000000..cbcd4f1f1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000724-1.c @@ -0,0 +1,72 @@ +/* { dg-do run { target *-*-linux* } } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -fomit-frame-pointer" } */ + +extern void abort (void); +extern void exit (int); + +struct s { + struct { int a; } a; + int b; + struct { struct { int a; } a; struct t { struct t *a, *b; } b; } c; +}; + +int bar(int (*fn)(void *), void *arg, unsigned long flags) +{ + return 0; +} + +int baz(void *x) +{ + return 0; +} + +void do_check (struct s *) asm ("do_check") __attribute__((regparm(1))); + +void __attribute__((regparm(1))) do_check(struct s *x) +{ + if (x->a.a || x->b || x->c.a.a) + abort(); + if (x->c.b.a != &x->c.b || x->c.b.b != &x->c.b) + abort(); +} + +#define NT "\n\t" + +asm ("\n" +"___checkme:" +NT "pushl %eax; pushl %ebx; pushl %ecx; pushl %edx; pushl %esi; pushl %edi" + +NT "pushl $0; pushl $0; pushl $0; pushl $0; pushl $0" +NT "pushl $0; pushl $0; pushl $0; pushl $0; pushl $0" + +NT "movl %ecx, %eax" +NT "call do_check" + +NT "popl %eax; popl %eax; popl %eax; popl %eax; popl %eax" +NT "popl %eax; popl %eax; popl %eax; popl %eax; popl %eax" + +NT "popl %edi; popl %esi; popl %edx; popl %ecx; popl %ebx; popl %eax" +NT "ret" +); + +extern inline void do_asm(struct s * x) +{ + asm volatile("call ___checkme" : : "c" (x) : "memory"); +} + +int foo(void) +{ + struct s x = { { 0 }, 0, { { 0 }, { &x.c.b, &x.c.b } } }; + bar(baz, &x, 1); + do_asm(&x); + bar(baz, &x, 1); + do_asm(&x); + return 0; +} + +int main() +{ + foo(); + exit(0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000807-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000807-1.c new file mode 100644 index 000000000..efdf97b14 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000807-1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-Os -fpic" } */ + +#include <string.h> + +typedef struct +{ + char *a; + char *b; +} *foo; + +void +bar (foo x) +{ + char *c = x->b; + char *d = (void *)0; + unsigned int e = 0, f = 0, g; + while (*c != ':') + if (*c == '%') + { + ++c; + switch (*c++) + { + case 'N': + g = strlen (x->a); + if (e + g >= f) { + char *h = d; + f += 256 + g; + d = (char *) __builtin_alloca (f); + memcpy (d, h, e); + }; + memcpy (&d[e], x->a, g); + e += g; + break; + } + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000904-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000904-1.c new file mode 100644 index 000000000..0fbce57e1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20000904-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O0 -fpic" } */ + +static struct { + unsigned short a, b, c, d; +} x[10]; + +int foo(int i) +{ + return ((*((char *)&x[i] + i)) | (*((char *)&x[i] + i))); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20001127-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20001127-1.c new file mode 100644 index 000000000..b62c6f979 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20001127-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern inline float bar (float x) +{ + register long double value; + asm volatile ("frndint" : "=t" (value) : "0" (x)); + return value; +} + +float a; + +float foo (float b) +{ + return a + bar (b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20010520-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20010520-1.c new file mode 100644 index 000000000..ab4ed16ce --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20010520-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-w" } */ + +void f () +{ + int i __asm__ ("%eax"); + __asm__ volatile ("" : "=a" (i)); +} + + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20011009-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20011009-1.c new file mode 100644 index 000000000..e79a475a1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20011009-1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +extern void abort (void); +extern void exit (int); + +#ifdef __sun__ +#define COMMENT "/" +#else +#define COMMENT "#" +#endif + +int main () +{ + int x; + + asm ("movl $26, %0 " COMMENT " 26 |-> reg \n\t" + "movl $28, %0" : "=r" (x)); + if (x != 28) + abort (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20011029-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20011029-2.c new file mode 100644 index 000000000..c1068de6e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20011029-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int foo (int s) +{ + for (;;) + { + int a[32]; + int y, z; + __asm__ __volatile__ ("" : "=c" (y), "=D" (z) + : "a" (0), "0" (32), "1" (a) : "memory"); + if (({ register char r; + __asm__ __volatile__ ("" : "=q" (r) + : "r" (s % 32), "m" (a[s / 32]) + : "cc"); r; })) + continue; + else if (({ register char r; + __asm__ __volatile__ ("" : "=q" (r) + : "r" (0), "m" (a[0]) + : "cc"); r; })) + continue; + } + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20011107-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20011107-1.c new file mode 100644 index 000000000..c1cfe88a4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20011107-1.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -mtune=k6" } */ + +void +foo (unsigned char *x, const unsigned char *y) +{ + int a = 6; + unsigned char *b; + for (;;) + { + unsigned char *c = x; + + while (1) + { + if (c + 2 < y) + c += 3; + else + break; + } + b = x + a; + if (*c == 4 || *c == 5) + { + unsigned char d = c[2]; + + if (b[3] == 7 || b[3] == 8) + { + int e = b[3] == 8; + if (d < b[4] * 8 && b[5 + d / 8] & (1 << (d % 8))) + e = !e; + if (!e) + x[-3] = 26; + } + } + else if (*c == 7 && b[3] == 8) + { + int f; + for (f = 0; f < (int) c[1]; f++) + if (!(c[2 + f] == 0)) + break; + if (f == c[1]) + x[-3] = 26; + } + x -= 2; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20011119-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20011119-1.c new file mode 100644 index 000000000..9e85f6f5a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20011119-1.c @@ -0,0 +1,82 @@ +/* Test for reload failing to eliminate from argp to sp. */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target nonpic } */ +/* { dg-options "-O2 -fomit-frame-pointer" } */ + +static int ustrsize (const char *s); +static int (*ucwidth) (int c); +static int (*ugetxc) (const char **s); +static int (*usetc) (char *s, int c); + +char *ustrzcat(char *dest, int size, const char *src) +{ + int pos = ustrsize(dest); + int c; + + size -= pos + ucwidth(0); + + while ((c = ugetxc(&src)) != 0) { + size -= ucwidth(c); + if (size < 0) + break; + + pos += usetc(dest+pos, c); + } + + usetc(dest+pos, 0); + + return dest; +} + +static int __attribute__((noinline)) +ustrsize (const char *s) +{ + return 0; +} + +static int +ucwidth_ (int c) +{ + return 1; +} + +static int +ugetxc_ (const char **s) +{ + return '\0'; +} + +static int +usetc_ (char *s, int c) +{ + return 1; +} + +int +main() +{ + ucwidth = ucwidth_; + ugetxc = ugetxc_; + usetc = usetc_; + + /* ??? It is impossible to explicitly modify the hard frame pointer. + This will run afoul of code in flow.c that declines to mark regs + in eliminate_regs in regs_ever_used. Apparently, we have to wait + for reload to decide that it won't need a frame pointer before a + variable can be allocated to %ebp. + + So save, restore, and clobber %ebp by hand. */ + + asm ("pushl %%ebp\n\t" + "movl $-1, %%ebp\n\t" + "pushl $0\n\t" + "pushl $0\n\t" + "pushl $0\n\t" + "call %P0\n\t" + "addl $12, %%esp\n\t" + "popl %%ebp" + : : "i"(ustrzcat) : "memory" ); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020201-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020201-3.c new file mode 100644 index 000000000..9d7265457 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020201-3.c @@ -0,0 +1,16 @@ +/* This testcase ICEd because a SFmode variable was given a MMX register + for which there is no movsf exists. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=i686 -mmmx -fno-strict-aliasing" } */ + +struct A { unsigned int a, b; }; + +void foo (struct A *x, int y, int z) +{ + const float d = 1.0; + float e = (float) y + z; + + x->a = *(unsigned int *) &d; + x->b = *(unsigned int *) &e; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020218-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020218-1.c new file mode 100644 index 000000000..4d3d256af --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020218-1.c @@ -0,0 +1,35 @@ +/* Verify that X86-64 only SSE registers aren't restored on IA-32. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-final { scan-assembler-not "xmm8" } } */ + +extern void abort (void); +extern void exit (int); + +void *bar (void *p, void *q) +{ + if (p != (void *) 26 || q != (void *) 35) + abort (); + return (void *) 76; +} + +void *foo (void **args) +{ + void *argcookie = &args[1]; + + __builtin_return (__builtin_apply (args[0], &argcookie, + 2 * sizeof (void *))); +} + +int main (void) +{ + void *args[3]; + + args[0] = (void *) bar; + args[1] = (void *) 26; + args[2] = (void *) 35; + if (foo (args) != (void *) 76) + abort (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020224-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020224-1.c new file mode 100644 index 000000000..2905719fa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020224-1.c @@ -0,0 +1,41 @@ +/* PR target/5755 + This testcase failed because the caller of a function returning struct + expected the callee to pop up the hidden return structure pointer, + while callee was actually not poping it up (as the hidden argument + was passed in register). */ +/* { dg-do run } */ +/* { dg-options "-O2 -fomit-frame-pointer" } */ + +extern void abort (void); +extern void exit (int); + +typedef struct { + int a1, a2; +} A; + +A a; + +A __attribute__ ((regparm (2))) +foo (int x) +{ + return a; +} + +int __attribute__ ((regparm (2))) +bar (int x) +{ + int r = foo(0).a2; + return r; +} + +int +main () +{ + int f; + a.a1 = 530; + a.a2 = 980; + f = bar (0); + if (f != 980) + abort (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020426-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020426-1.c new file mode 100644 index 000000000..57690f1d3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020426-1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-msoft-float -mfp-ret-in-387" } */ + +void f() { + __builtin_apply(0, 0, 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020523.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020523.c new file mode 100644 index 000000000..0684d5feb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020523.c @@ -0,0 +1,41 @@ +/* PR target/6753 + This testcase was miscompiled because sse_mov?fcc_const0* + patterns were missing earlyclobber. */ + +/* { dg-do run } */ +/* { dg-options "-O2 -msse -mfpmath=sse -ffast-math" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +float one = 1.f; + +void bar (float f) +{ + if (__builtin_memcmp (&one, &f, sizeof (float))) + abort (); +} + +float foo (void) +{ + return 1.f; +} + +typedef struct +{ + float t; +} T; + +static void +sse_test (void) +{ + int i; + T x[1]; + + for (i = 0; i < 1; i++) + { + x[i].t = foo (); + x[i].t = 0.f > x[i].t ? 0.f : x[i].t; + bar (x[i].t); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020531-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020531-1.c new file mode 100644 index 000000000..cd7cac347 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020531-1.c @@ -0,0 +1,21 @@ +/* PR optimization/6842 + This testcase caused ICE when trying to optimize V8QI subreg of VOIDmode + CONST_DOUBLE. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mmmx" } */ + +typedef char __v8qi __attribute__ ((vector_size (8))); +extern void abort (void); +extern void exit (int); + +void foo (void) +{ + unsigned long long a = 0x0102030405060708LL; + unsigned long long b = 0x1020304050607080LL; + unsigned long long c; + + c = (unsigned long long) __builtin_ia32_paddusb ((__v8qi) a, (__v8qi) b); + __builtin_ia32_emms (); + if (c != 0x1122334455667788LL) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020616-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020616-1.c new file mode 100644 index 000000000..5641826b4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020616-1.c @@ -0,0 +1,35 @@ +/* PR opt/6722 */ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#if !__PIC__ +register int k asm("%ebx"); +#elif __amd64 +register int k asm("%r12"); +#else +register int k asm("%esi"); +#endif + +void __attribute__((noinline)) +foo() +{ + k = 1; +} + +void test() +{ + int i; + for (i = 0; i < 10; i += k) + { + k = 0; + foo(); + } +} + +int main() +{ + int old = k; + test(); + k = old; + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020729-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020729-1.c new file mode 100644 index 000000000..7e1abafd2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20020729-1.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=k6" } */ + +static inline void * +baz (void *s, unsigned long c, unsigned int count) +{ + int d0, d1; + __asm__ __volatile__ ("" + : "=&c" (d0), "=&D" (d1) + :"a" (c), "q" (count), "0" (count / 4), "1" ((long) s) + :"memory"); + return s; +} + +struct A +{ + unsigned long *a; +}; + +inline static void * +bar (struct A *x, int y) +{ + char *ptr; + + ptr = (void *) x->a[y >> 12]; + ptr += y % (1UL << 12); + return (void *) ptr; +} + +int +foo (struct A *x, unsigned int *y, int z, int u) +{ + int a, b, c, d, e; + + z += *y; + c = z + u; + a = (z >> 12) + 1; + do + { + b = (a << 12); + d = b - z; + e = c - z; + if (e < d) + d = e; + baz (bar (x, z), 0, d); + z = b; + a++; + } + while (z < c); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20030217-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20030217-1.c new file mode 100644 index 000000000..d2b24802b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20030217-1.c @@ -0,0 +1,19 @@ +/* Test whether denormal floating point constants in hexadecimal notation + are parsed correctly. */ +/* { dg-do run } */ +/* { dg-options "-std=c99" } */ +/* { dg-require-effective-target large_long_double } */ + +long double d = 0x0.0000003ffffffff00000p-16357L; +long double e = 0x0.0000003ffffffff00000p-16356L; + +extern void abort (void); +extern void exit (int); + +int +main (void) +{ + if (d != e / 2.0) + abort (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20030217-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20030217-2.c new file mode 100644 index 000000000..d0606a242 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20030217-2.c @@ -0,0 +1,23 @@ +/* Test whether denormal floating point constants in hexadecimal notation + are parsed correctly. */ +/* { dg-do run } */ +/* { dg-options "-std=c99" } */ + +long double d; +long double e; + +long double f = 2.2250738585072014E-308L; + +extern void abort (void); +extern void exit (int); + +int +main (void) +{ + d = 0x0.0000003ffffffff00000p-1048L; + e = 0x0.0000003ffffffff00000p-1047L; + if (d != e / 2.0) + abort (); + + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20030926-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20030926-1.c new file mode 100644 index 000000000..ebde34085 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20030926-1.c @@ -0,0 +1,18 @@ +/* PR optimization/11741 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -minline-all-stringops" } */ +/* { dg-options "-O2 -minline-all-stringops -march=pentium4" { target ia32 } } */ + +extern void *memcpy (void *, const void *, __SIZE_TYPE__); +extern __SIZE_TYPE__ strlen (const char *); + +void +foo (char *p) +{ + for (;;) + { + memcpy (p, p + 1, strlen (p)); + p++; + } +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20040112-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20040112-1.c new file mode 100644 index 000000000..168fd2f0b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20040112-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "testb" } } */ +ftn (char *sp) +{ + char status; + + while (1) + { + *sp = 0xE8; + status = *(volatile char *) sp; + if (status & 0x80) + break; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20050113-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20050113-1.c new file mode 100644 index 000000000..44deb30cb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20050113-1.c @@ -0,0 +1,6 @@ +/* PR middle-end/19164 */ +/* { dg-do compile } */ +/* { dg-options "-mmmx" } */ + +typedef short int V __attribute__ ((vector_size (8))); +static V v = (V) 0x00FF00FF00FF00FFLL; diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060125-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060125-1.c new file mode 100644 index 000000000..ed9dcce84 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060125-1.c @@ -0,0 +1,30 @@ +/* PR rtl-optimization/25703 */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -mtune=i486" } */ + +extern void abort (void); + +struct a +{ + int a; + char b,c,d,e; +}; + +__attribute__ ((noinline)) +__attribute__ ((regparm(1))) t(struct a a) +{ + if (a.a!=1 || a.b!=1 || a.c!=1) + abort(); +} + +int main() +{ + struct a a; + a.c=1; + a.a=1; + a.b=1; + t(a); + return 0; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060125-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060125-2.c new file mode 100644 index 000000000..1747a634d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060125-2.c @@ -0,0 +1,30 @@ +/* PR rtl-optimization/25703 */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -mtune=pentiumpro" } */ + +extern void abort (void); + +struct a +{ + int a; + char b,c,d,e; +}; + +__attribute__ ((noinline)) +__attribute__ ((regparm(1))) t(struct a a) +{ + if (a.a!=1 || a.b!=1 || a.c!=1) + abort(); +} + +int main() +{ + struct a a; + a.c=1; + a.a=1; + a.b=1; + t(a); + return 0; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060218-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060218-1.c new file mode 100644 index 000000000..b94cbd8c9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060218-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ + +void +foo (void) +{ + register int cc __asm ("cc"); /* { dg-error "invalid register name" } */ + __asm ("" : : "r" (cc) : "cc"); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060512-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060512-1.c new file mode 100644 index 000000000..374d18aea --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060512-1.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-std=gnu99 -msse2 -mpreferred-stack-boundary=4" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <emmintrin.h> + +__m128i __attribute__ ((__noinline__)) +vector_using_function () +{ + volatile __m128i vx; /* We want to force a vector-aligned store into the stack. */ + vx = _mm_xor_si128 (vx, vx); + return vx; +} +int __attribute__ ((__noinline__, __force_align_arg_pointer__)) +self_aligning_function (int x, int y) +{ + __m128i ignored = vector_using_function (); + return (x + y); +} +int g_1 = 20; +int g_2 = 22; + +static void +sse2_test (void) +{ + int result; + asm ("pushl %esi"); /* Disalign runtime stack. */ + result = self_aligning_function (g_1, g_2); + if (result != 42) + abort (); + asm ("popl %esi"); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060512-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060512-2.c new file mode 100644 index 000000000..d3a779cb4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060512-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-std=gnu99 -mpreferred-stack-boundary=4" } */ +int +outer_function (int x, int y) +{ + int __attribute__ ((__noinline__, __force_align_arg_pointer__)) + nested_function (int x, int y) + { + return (x + y); + } + return (3 + nested_function (x, y)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060512-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060512-3.c new file mode 100644 index 000000000..3370b9ec2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060512-3.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-std=gnu99 -msse2 -mstackrealign -mpreferred-stack-boundary=4" } */ + +#include "sse2-check.h" + +#include <emmintrin.h> + +__m128i __attribute__ ((__noinline__)) +vector_using_function () +{ + volatile __m128i vx; /* We want to force a vector-aligned store into the stack. */ + vx = _mm_xor_si128 (vx, vx); + return vx; +} +int __attribute__ ((__noinline__)) +self_aligning_function (int x, int y) +{ + __m128i ignored = vector_using_function (); + return (x + y); +} +int g_1 = 20; +int g_2 = 22; + +static void +sse2_test (void) +{ + int result; + asm ("pushl %esi"); /* Disalign runtime stack. */ + result = self_aligning_function (g_1, g_2); + if (result != 42) + abort (); + asm ("popl %esi"); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060512-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060512-4.c new file mode 100644 index 000000000..bf7693799 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060512-4.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-mstackrealign -mpreferred-stack-boundary=4" } */ +int +outer_function (int x, int y) +{ + int __attribute__ ((__noinline__)) + nested_function (int x, int y) + { + return (x + y); + } + return (3 + nested_function (x, y)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060821-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060821-1.c new file mode 100644 index 000000000..29a9afe87 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20060821-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse3" } */ +/* { dg-final { scan-assembler-not "%mm" } } */ +/* PR 28825 */ +#include <pmmintrin.h> +__m128 ggg(float* m) +{ + return (__m128) {m[0], m[5], m[10], m[10]}; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20080723-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20080723-1.c new file mode 100644 index 000000000..a2ed5bf86 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/20080723-1.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +extern void abort (void); +extern void exit (int); + +static inline __attribute__((always_inline)) +void +prefetch (void *x) +{ + asm volatile("prefetcht0 %0" : : "m" (*(unsigned long *)x)); +} + +struct hlist_head +{ + struct hlist_node *first; +}; + +struct hlist_node +{ + struct hlist_node *next; + unsigned long i_ino; +}; + +struct hlist_node * find_inode_fast(struct hlist_head *head, unsigned long ino) +{ + struct hlist_node *node; + + for (node = head->first; + node && (prefetch (node->next), 1); + node = node->next) + { + if (node->i_ino == ino) + break; + } + return node ? node : 0; +} + +struct hlist_node g2; +struct hlist_node g1 = { &g2 }; +struct hlist_head h = { &g1 }; + +int +main() +{ + if (find_inode_fast (&h, 1) != 0) + abort (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-1.c new file mode 100644 index 000000000..c4ea1e7d4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-1.c @@ -0,0 +1,22 @@ +/* Verify that -mno-fancy-math-387 works. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */ +/* { dg-options "-O -ffast-math -mfpmath=387 -mno-fancy-math-387 -march=i386" } */ +/* { dg-final { scan-assembler "call\t(.*)sin" } } */ +/* { dg-final { scan-assembler "call\t(.*)cos" } } */ +/* { dg-final { scan-assembler "call\t(.*)sqrt" } } */ +/* { dg-final { scan-assembler "call\t(.*)atan2" } } */ +/* { dg-final { scan-assembler "call\t(.*)log" } } */ +/* { dg-final { scan-assembler "call\t(.*)exp" } } */ +/* { dg-final { scan-assembler "call\t(.*)tan" } } */ +/* { dg-final { scan-assembler "call\t(.*)fmod" } } */ + +double f1(double x) { return __builtin_sin(x); } +double f2(double x) { return __builtin_cos(x); } +double f3(double x) { return __builtin_sqrt(x); } +double f4(double x, double y) { return __builtin_atan2(x,y); } +double f5(double x) { return __builtin_log(x); } +double f6(double x) { return __builtin_exp(x); } +double f7(double x) { return __builtin_tan(x); } +double f8(double x, double y) { return __builtin_fmod(x,y); } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-10.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-10.c new file mode 100644 index 000000000..0ff1b2a7c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-10.c @@ -0,0 +1,20 @@ +/* PR tree-optimization/24964 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mfpmath=387 -mfancy-math-387" } */ + +double fabs(double x); + +double test1(double x) +{ + double t = fabs(x); + return t*t; +} + +double test2(double x) +{ + double t = -x; + return t*t; +} + +/* { dg-final { scan-assembler-not "fchs" } } */ +/* { dg-final { scan-assembler-not "fabs" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-11.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-11.c new file mode 100644 index 000000000..869f6061c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-11.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mfpmath=387 -mfancy-math-387" } */ + +double foo(double x, double y) +{ + double t = -x * y; + return -t; +} + +/* { dg-final { scan-assembler-not "fchs" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-12.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-12.c new file mode 100644 index 000000000..62c1d483c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-12.c @@ -0,0 +1,16 @@ +/* PR target/26915 */ +/* { dg-do compile } */ +/* { dg-options "-O -mfpmath=387 -mfancy-math-387" } */ + +double testm0(void) +{ + return -0.0; +} + +double testm1(void) +{ + return -1.0; +} + +/* { dg-final { scan-assembler "fldz" } } */ +/* { dg-final { scan-assembler "fld1" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-2.c new file mode 100644 index 000000000..8d5dba1f9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-2.c @@ -0,0 +1,22 @@ +/* Verify that -march overrides -mno-fancy-math-387. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i686" } } */ +/* { dg-options "-O -ffast-math -mfpmath=387 -march=i686 -mno-fancy-math-387" } */ +/* { dg-final { scan-assembler "fsin" } } */ +/* { dg-final { scan-assembler "fcos" } } */ +/* { dg-final { scan-assembler "fsqrt" } } */ +/* { dg-final { scan-assembler "fpatan" } } */ +/* { dg-final { scan-assembler "fyl2x" } } */ +/* { dg-final { scan-assembler "f2xm1" } } */ +/* { dg-final { scan-assembler "fptan" } } */ +/* { dg-final { scan-assembler "fprem" } } */ + +double f1(double x) { return __builtin_sin(x); } +double f2(double x) { return __builtin_cos(x); } +double f3(double x) { return __builtin_sqrt(x); } +double f4(double x, double y) { return __builtin_atan2(x,y); } +double f5(double x) { return __builtin_log(x); } +double f6(double x) { return __builtin_exp(x); } +double f7(double x) { return __builtin_tan(x); } +double f8(double x, double y) { return __builtin_fmod(x,y); } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-3.c new file mode 100644 index 000000000..1b8dc8bab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-3.c @@ -0,0 +1,11 @@ +/* Verify that 387 mathematical constants are recognized. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mfpmath=387 -mfancy-math-387" } */ +/* { dg-final { scan-assembler "fldpi" } } */ +/* { dg-require-effective-target large_long_double } */ + +long double add_pi(long double x) +{ + return x + 3.1415926535897932385128089594061862044L; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-4.c new file mode 100644 index 000000000..27c48ed20 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-4.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mfancy-math-387" } */ +/* { dg-final { scan-assembler "fldpi" } } */ +/* { dg-require-effective-target large_long_double } */ + +long double atanl (long double); + +long double pi() +{ + return 4.0 * atanl (1.0); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-5.c new file mode 100644 index 000000000..a39f77a58 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-5.c @@ -0,0 +1,12 @@ +/* Verify that -mno-fancy-math-387 works. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */ +/* { dg-options "-O -ffast-math -mfpmath=387 -mno-fancy-math-387 -march=i386" } */ +/* { dg-final { scan-assembler "call\t(.*)atan" } } */ +/* { dg-final { scan-assembler "call\t(.*)log1p" } } */ +/* { dg-final { scan-assembler "call\t(.*)drem" } } */ + +double f1(double x) { return __builtin_atan(x); } +double f2(double x) { return __builtin_log1p(x); } +double f3(double x, double y) { return __builtin_drem(x,y); } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-6.c new file mode 100644 index 000000000..f9506ba79 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-6.c @@ -0,0 +1,12 @@ +/* Verify that -march overrides -mno-fancy-math-387. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i686" } } */ +/* { dg-options "-O -ffast-math -mfpmath=387 -march=i686 -mno-fancy-math-387" } */ +/* { dg-final { scan-assembler "fpatan" } } */ +/* { dg-final { scan-assembler "fyl2xp1" } } */ +/* { dg-final { scan-assembler "fprem1" } } */ + +double f1(double x) { return __builtin_atan(x); } +double f2(double x) { return __builtin_log1p(x); } +double f3(double x, double y) { return __builtin_drem(x,y); } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-7.c new file mode 100644 index 000000000..e01ed2e05 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-7.c @@ -0,0 +1,13 @@ +/* Verify that 387 fsincos instruction is generated. */ +/* { dg-do compile } */ +/* { dg-options "-O -ffast-math -mfpmath=387 -mfancy-math-387" } */ +/* { dg-final { scan-assembler "fsincos" } } */ + +extern double sin (double); +extern double cos (double); + +double f1(double x) +{ + return sin(x) + cos (x); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-8.c new file mode 100644 index 000000000..2dbcd740f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-8.c @@ -0,0 +1,15 @@ +/* Verify that 387 fptan instruction is generated. Also check that + inherent load of 1.0 is used in further calculations. */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -mfpmath=387 -mfancy-math-387" } */ +/* { dg-final { scan-assembler "fptan" } } */ +/* { dg-final { scan-assembler-not "fld1" } } */ + +extern double tan (double); + +double f1(double x) +{ + return 1.0 / tan(x); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-9.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-9.c new file mode 100644 index 000000000..2667aa468 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/387-9.c @@ -0,0 +1,35 @@ +/* Verify that 387 fsincos instruction is generated. */ +/* { dg-do compile } */ +/* { dg-options "-O -funsafe-math-optimizations -mfpmath=387 -mfancy-math-387" } */ + +extern double sin (double); +extern double cos (double); +extern void sincos (double, double *, double *); + +double f1(double x) +{ + double s, c; + sincos (x, &s, &c); + return s + c; +} + +double f2(double x) +{ + double s, c, tmp; + sincos (x, &s, &tmp); + c = cos (x); + return s + c; +} + +double f3(double x) +{ + double s, c, tmp; + sincos (x, &tmp, &c); + s = sin (x); + return s + c; +} + +/* { dg-final { scan-assembler "fsincos" } } */ +/* { dg-final { scan-assembler-not "fsin " } } */ +/* { dg-final { scan-assembler-not "fcos" } } */ +/* { dg-final { scan-assembler-not "call" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/3dnow-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/3dnow-1.c new file mode 100644 index 000000000..953dc2aef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/3dnow-1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target 3dnow } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -m3dnow" } */ + +/* Test that the intrinsics compile with optimization. All of them are + defined as inline functions in mmintrin.h that reference the proper + builtin functions. Defining away "extern" and "__inline" results in + all of them being compiled as proper functions. */ + +#define extern +#define __inline + +#include <mm3dnow.h> diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/3dnow-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/3dnow-2.c new file mode 100644 index 000000000..84b854087 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/3dnow-2.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target 3dnow } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -m3dnow" } */ + +/* Test that the intrinsics compile without optimization. All of them are + defined as inline functions in mmintrin.h that reference the proper + builtin functions. Defining away "extern" and "__inline" results in + all of them being compiled as proper functions. */ + +#define extern +#define __inline + +#include <mm3dnow.h> diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/3dnowA-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/3dnowA-1.c new file mode 100644 index 000000000..e502dc98f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/3dnowA-1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target 3dnow } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow" } */ + +/* Test that the intrinsics compile with optimization. All of them are + defined as inline functions in mmintrin.h that reference the proper + builtin functions. Defining away "extern" and "__inline" results in + all of them being compiled as proper functions. */ + +#define extern +#define __inline + +#include <mm3dnow.h> diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/3dnowA-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/3dnowA-2.c new file mode 100644 index 000000000..8475094ab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/3dnowA-2.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target 3dnow } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow" } */ + +/* Test that the intrinsics compile without optimization. All of them are + defined as inline functions in mmintrin.h that reference the proper + builtin functions. Defining away "extern" and "__inline" results in + all of them being compiled as proper functions. */ + +#define extern +#define __inline + +#include <mm3dnow.h> diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/47698.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/47698.c new file mode 100644 index 000000000..2c751093a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/47698.c @@ -0,0 +1,10 @@ +/* { dg-options "-Os" } */ +/* { dg-final { scan-assembler-not "cmov" } } */ + +extern volatile unsigned long mmio; +unsigned long foo(int cond) +{ + if (cond) + return mmio; + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980211-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980211-1.c new file mode 100644 index 000000000..ad6312b37 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980211-1.c @@ -0,0 +1,29 @@ +/* Test long double on x86 and x86-64. */ + +/* { dg-do run } */ +/* { dg-options -O2 } */ + +extern void abort (void); + +__inline int +__signbitl0 (long double __x) +{ + union { long double __l; int __i[3]; } __u = { __l: __x }; + + return (__u.__i[2] & 0x8000) != 0; +} + +void +foo (long double x, long double y) +{ + long double z = x / y; + if (__signbitl0 (x) && __signbitl0 (z)) + abort (); +} + +int main() +{ + if (sizeof (long double) > sizeof (double)) + foo (-0.0, -1.0); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980226-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980226-1.c new file mode 100644 index 000000000..d5587c71b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980226-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options -O2 } */ + +extern int printf (const char *, ...); +extern double bar (double); + +int +baz (double d) +{ + double e = bar (d); + asm volatile ("" : : : "st"); + return printf ("%lg\n", e); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980312-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980312-1.c new file mode 100644 index 000000000..3a125f259 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980312-1.c @@ -0,0 +1,25 @@ +/* { dg-do link } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=pentiumpro" } */ + +extern __inline double +__expm1 (double __x) +{ + double __temp; + __temp = 1.0; + return __temp; +} +extern __inline double +__sgn1 (double __x) +{ + return __x >= 0.0 ? 1.0 : -1.0; +} +double +tanh (double __x) +{ + return __expm1 (__x) * __sgn1 (-__x); +} +main () +{ + return tanh (3.45) != 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980313-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980313-1.c new file mode 100644 index 000000000..8698aa61c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980313-1.c @@ -0,0 +1,26 @@ +/* { dg-do link } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=pentiumpro" } */ + +extern __inline double +__expm1 (double __x) +{ + double __temp; + __temp -= 1.0; + return __temp; +} +extern __inline double +__sgn1 (double __x) +{ + return __x >= 0.0 ? 1.0 : -1.0; +} +double +tanh (double __x) +{ + register double __exm1 = __expm1 (__x); + return __exm1 / (__exm1 + 2.0) * __sgn1 (-__x); +} +main () +{ + return tanh (3.45) != 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980414-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980414-1.c new file mode 100644 index 000000000..6a2130a59 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980414-1.c @@ -0,0 +1,78 @@ +/* Test double on x86. */ + +/* { dg-do run } */ +/* { dg-options -O2 } */ + +extern void abort (void); + +static __inline double +mypow (double __x, double __y) +{ + register double __value, __exponent; + long __p = (long) __y; + if (__y == (double) __p) + { + double __r = 1.0; + if (__p == 0) + return 1.0; + if (__p < 0) + { + __p = -__p; + __x = 1.0 / __x; + } + while (1) + { + if (__p & 1) + __r *= __x; + __p >>= 1; + if (__p == 0) + return __r; + __x *= __x; + } + } + __asm __volatile__ + ("fmul %%st(1),%%st\n\t" /* y * log2(x) */ + "fst %%st(1)\n\t" + "frndint\n\t" /* int(y * log2(x)) */ + "fxch %%st(1)\n\t" + "fsub %%st(1),%%st\n\t" /* fract(y * log2(x)) */ + "f2xm1\n\t" /* 2^(fract(y * log2(x))) - 1 */ + : "=t" (__value), "=u" (__exponent) : "0" (__x), "1" (__y)); + __value += 1.0; + __asm __volatile__ + ("fscale" + : "=t" (__value) : "0" (__value), "u" (__exponent)); + return __value; +} + +const double E1 = 2.71828182845904523536028747135; + +double fact (double x) +{ + double corr; + corr = 1.0; + return corr * mypow(x/E1, x); +} + +int main () +{ + double y, z; + + y = fact (46.2); + z = mypow (46.2/E1, 46.2); + +#if 0 + printf ("%26.19e, %26.19e\n", y, z); +#endif + + if (y > z) + y -= z; + else + y = z - y; + + y /= z; + if (y > 0.1) + abort (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980520-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980520-1.c new file mode 100644 index 000000000..f4393307c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980520-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options -O2 } */ + +int bug(void) +{ + unsigned long a, b; + + __asm__("" + : "=d" (a) + : + : "memory"); + __asm__ __volatile__("" + : + : "g" (b) + : "memory"); + return a; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980709-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980709-1.c new file mode 100644 index 000000000..595b7cbaa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/980709-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options -O2 } */ + +extern __inline__ int test_and_set_bit(int nr, volatile void * addr) +{ + int oldbit; + __asm__ __volatile__( "" + "btsl %2,%1\n\tsbbl %0,%0" + :"=r" (oldbit),"=m" (addr) + :"ir" (nr)); + return oldbit; +} +struct buffer_head { + unsigned long b_state; +}; +extern void lock_buffer(struct buffer_head * bh) +{ + while (test_and_set_bit(2 , &bh->b_state)) + __wait_on_buffer(bh); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990117-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990117-1.c new file mode 100644 index 000000000..a89dad119 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990117-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=pentiumpro" } */ + +extern __inline double +fabs (double __x) +{ + register double __value; + __asm __volatile__ + ("fabs" + : "=t" (__value) : "0" (__x)); + return __value; +} +int +foo () +{ + int i, j, k; + double x = 0, y = ((i == j) ? 1 : 0); + for (i = 0; i < 10; i++) + ; + fabs (x - y); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990130-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990130-1.c new file mode 100644 index 000000000..b2754fb08 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990130-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options -O0 } */ + +typedef int SItype __attribute__ ((mode (SI))); +typedef int DItype __attribute__ ((mode (DI))); +typedef unsigned int USItype __attribute__ ((mode (SI))); + struct DIstruct {SItype low, high;}; +typedef union +{ + struct DIstruct s; + DItype ll; +} DIunion; +DItype +__muldi3 (DItype u, DItype v) +{ + DIunion w; + DIunion uu, vv; + uu.ll = u, + vv.ll = v; + w.ll = ({DIunion __w; __asm__ ("mull %3" : "=a" ((USItype) ( __w.s.low )), "=d" ((USItype) ( __w.s.high )) : "%0" ((USItype) ( uu.s.low )), "rm" ((USItype) ( vv.s.low ))) ; __w.ll; }) ; + w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high + + (USItype) uu.s.high * (USItype) vv.s.low); + return w.ll; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990213-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990213-2.c new file mode 100644 index 000000000..21392bfca --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990213-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-fPIC" } */ + +struct normal_encoding {}; +struct unknown_encoding {}; +static const struct normal_encoding latin1_encoding = {}; + +struct encoding* +XmlInitUnknownEncoding(void *mem) +{ + int i; + struct unknown_encoding *e = mem; + for (i = 0; i < sizeof(struct normal_encoding); i++) + ((char *)mem)[i] = ((char *)&latin1_encoding)[i]; + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990214-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990214-1.c new file mode 100644 index 000000000..3c203e9f7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990214-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-fPIC" } */ + +typedef int int64_t __attribute__ ((__mode__ ( __DI__ ))) ; +unsigned * +bar (int64_t which) +{ + switch (which & 15 ) { + case 0 : + break; + case 1 : + case 5 : + case 2 : ; + } + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990424-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990424-1.c new file mode 100644 index 000000000..dd2913992 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990424-1.c @@ -0,0 +1,30 @@ +/* Test that stack alignment is preserved with pending_stack_adjust + with stdcall functions. */ + +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options -mpreferred-stack-boundary=4 } */ + +void __attribute__((stdcall)) foo(int a, int b, int c); + +extern void abort (void); +extern void exit (int); + +int +main () +{ + foo(1, 2, 3); + foo(1, 2, 3); + exit (0); +} + +void __attribute__((stdcall)) +foo(int a, int b, int c) +{ + static int last_align = -1; + int dummy, align = (int)&dummy & 15; + if (last_align < 0) + last_align = align; + else if (align != last_align) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990524-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990524-1.c new file mode 100644 index 000000000..295ffacc9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/990524-1.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=pentiumpro" } */ + +typedef struct t_anim_info { + char *new_filename; + long first_frame_nr; +} t_anim_info; +static int +p_frames_to_multilayer(t_anim_info *ainfo_ptr, + long range_from, long range_to) +{ + long l_cur_frame_nr; + long l_step, l_begin, l_end; + int l_tmp_image_id; + int l_new_image_id; + if(range_from > range_to) + { + l_step = -1; + if(range_to < ainfo_ptr->first_frame_nr) + { l_begin = ainfo_ptr->first_frame_nr; + } + } + else + { + l_step = 1; + } + l_cur_frame_nr = l_begin; + while(1) + { + if(ainfo_ptr->new_filename == ((void *)0) ) + if(l_tmp_image_id < 0) + gimp_image_delete(l_tmp_image_id); + if(l_cur_frame_nr == l_end) + break; + l_cur_frame_nr += l_step; + } + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/991129-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/991129-1.c new file mode 100644 index 000000000..038979a77 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/991129-1.c @@ -0,0 +1,16 @@ +/* Test against a problem in push_reload. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2" } */ + +unsigned long foo (unsigned long long x, unsigned long y) +{ + unsigned long a; + + x += y; + + asm ("" : "=a" (a) : "A" (x), "rm" (y)); + + return a; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/991209-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/991209-1.c new file mode 100644 index 000000000..15a46cfc4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/991209-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-ansi -pedantic" } */ + +int foo () +{ + return 1; +} + +register char *stack_ptr __asm ("%esp"); /* { dg-warning "file-scope declaration of 'stack_ptr' specifies 'register'" } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/991214-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/991214-1.c new file mode 100644 index 000000000..74b603da7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/991214-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2" } */ + +/* Test against a problem with the combiner substituting explicit hard reg + references when it shouldn't. */ +void foo (int, int) __attribute__ ((regparm (3))); +void __attribute__((regparm(3))) foo (int x, int y) +{ + __asm__ __volatile__("" : : "d" (x), "r" (y)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/991230-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/991230-1.c new file mode 100644 index 000000000..2c9f011ce --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/991230-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O -ffast-math -mtune=i486" } */ + +/* Test that floating point greater-than tests are compiled correctly with + -ffast-math. */ + +extern void abort (void); + +static int gt (double a, double b) +{ + if (a > b) + return 4; + return 0; +} + +static double zero = 0.0; + +int main () +{ + if (gt (zero, zero)) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/abi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/abi-1.c new file mode 100644 index 000000000..62b80ef40 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/abi-1.c @@ -0,0 +1,8 @@ +/* Make certain that we pass V2DF in the correct register for SSE1. */ +/* { dg-do compile } */ +/* { dg-options "-O1 -msse -mno-sse2" } */ + +typedef double v2df __attribute__((vector_size (16))); +v2df foo (void) { return (v2df){ 1.0, 2.0 }; } + +/* { dg-final { scan-assembler-times "xmm0" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/abi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/abi-2.c new file mode 100644 index 000000000..39eafc250 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/abi-2.c @@ -0,0 +1,9 @@ +/* Make certain that we pass __m256i in the correct register for AVX. */ +/* { dg-do compile } */ +/* { dg-options "-O1 -mavx" } */ +/* { dg-options "-mabi=sysv -O1 -mavx" { target x86_64-*-mingw* } } */ + +typedef long long __m256i __attribute__ ((__vector_size__ (32))); +__m256i foo (void) { return (__m256i){ 1, 2, 3, 4 }; } + +/* { dg-final { scan-assembler-times "ymm0" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/addr-sel-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/addr-sel-1.c new file mode 100644 index 000000000..27623ffd9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/addr-sel-1.c @@ -0,0 +1,17 @@ +/* PR rtl-optimization/28940 */ +/* Origin: Lev Makhlis <lmakhlis@bmc.com> */ + +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target nonpic } */ +/* { dg-options "-O2 -mtune=i686" } */ + +char a[10], b[10]; + +int f(int i) +{ + return a[i+1] + b[i+1]; +} + +/* { dg-final { scan-assembler "a\\+1" } } */ +/* { dg-final { scan-assembler "b\\+1" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c new file mode 100644 index 000000000..daf5779b1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-madx -O2" } */ +/* { dg-final { scan-assembler "adcx" } } */ + +#include <x86intrin.h> + +volatile unsigned char c; +volatile unsigned int x, y; +unsigned int *sum; + +void extern +adx_test (void) +{ + c = _addcarryx_u32 (c, x, y, sum); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c new file mode 100644 index 000000000..d38d7ee78 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-options "-madx -O2" } */ +/* { dg-require-effective-target adx } */ + +#include <x86intrin.h> +#include "adx-check.h" + +static void +adx_test (void) +{ + volatile unsigned char c; + unsigned int x; + volatile unsigned int y, sum_ref; + + c = 0; + x = y = 0xFFFFFFFF; + sum_ref = 0xFFFFFFFE; + + /* X = 0xFFFFFFFF, Y = 0xFFFFFFFF, C = 0. */ + c = _addcarryx_u32 (c, x, y, &x); + /* X = 0xFFFFFFFE, Y = 0xFFFFFFFF, C = 1. */ + c = _addcarryx_u32 (c, x, y, &x); + /* X = 0xFFFFFFFE, Y = 0xFFFFFFFF, C = 1. */ + + if (x != sum_ref) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx32-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx32-3.c new file mode 100644 index 000000000..0ed33a950 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx32-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-adx -O2" } */ +/* { dg-final { scan-assembler "adcl" } } */ + +#include <x86intrin.h> + +volatile unsigned char c; +volatile unsigned int x, y; +unsigned int *sum; + +void extern +adx_test (void) +{ + c = _addcarryx_u32 (c, x, y, sum); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c new file mode 100644 index 000000000..45beca851 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-madx -O2" } */ +/* { dg-final { scan-assembler "adcx" } } */ + +#include <x86intrin.h> + +volatile unsigned char c; +volatile unsigned long long x, y; +unsigned long long *sum; + +void extern +adx_test (void) +{ + c = _addcarryx_u64 (c, x, y, sum); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c new file mode 100644 index 000000000..6aa2539c0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c @@ -0,0 +1,27 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-options "-madx -O2" } */ +/* { dg-require-effective-target adx } */ + +#include <x86intrin.h> +#include "adx-check.h" + +static void +adx_test (void) +{ + volatile unsigned char c; + unsigned long long x; + volatile unsigned long long y, sum_ref; + + c = 0; + x = y = 0xFFFFFFFFFFFFFFFFLL; + sum_ref = 0xFFFFFFFFFFFFFFFELL; + + /* X = 0xFFFFFFFFFFFFFFFF, Y = 0xFFFFFFFFFFFFFFFF, C = 0. */ + c = _addcarryx_u64 (c, x, y, &x); + /* X = 0xFFFFFFFFFFFFFFFE, Y = 0xFFFFFFFFFFFFFFFF, C = 1. */ + c = _addcarryx_u64 (c, x, y, &x); + /* X = 0xFFFFFFFFFFFFFFFE, Y = 0xFFFFFFFFFFFFFFFF, C = 1. */ + + if (x != sum_ref) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx64-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx64-3.c new file mode 100644 index 000000000..4bbf74bfc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-addcarryx64-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mno-adx -O2" } */ +/* { dg-final { scan-assembler "adcq" } } */ + +#include <x86intrin.h> + +volatile unsigned char c; +volatile unsigned long long x, y; +unsigned long long *sum; + +void extern +adx_test (void) +{ + c = _addcarryx_u64 (c, x, y, sum); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-check.h new file mode 100644 index 000000000..580cb49ed --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/adx-check.h @@ -0,0 +1,40 @@ +#include <stdlib.h> +#include "cpuid.h" + +static void adx_test (void); + +static void __attribute__ ((noinline)) do_test (void) +{ + adx_test (); +} + + int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run ADX test only if host has ADX support. */ + + if (__get_cpuid_max (0, NULL) < 7) + return 0; + + __cpuid_count (7, 0, eax, ebx, ecx, edx); + + if ((ebx & bit_ADX) == bit_ADX) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + return 0; + } +#ifdef DEBUG + printf ("SKIPPED\n"); +#endif + + return 0; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aes-avx-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aes-avx-check.h new file mode 100644 index 000000000..f2a4ead40 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aes-avx-check.h @@ -0,0 +1,41 @@ +#ifdef DEBUG +#include <stdio.h> +#endif +#include <stdlib.h> +#include "cpuid.h" +#include "avx-os-support.h" + +static void aes_avx_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + aes_avx_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run AES + AVX test only if host has AES + AVX support. */ + if (((ecx & (bit_AVX | bit_OSXSAVE | bit_AES)) + == (bit_AVX | bit_OSXSAVE | bit_AES)) + && avx_os_support ()) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aes-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aes-check.h new file mode 100644 index 000000000..7e794423e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aes-check.h @@ -0,0 +1,37 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void aes_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + aes_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run AES test only if host has AES support. */ + if (ecx & bit_AES) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesdec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesdec.c new file mode 100644 index 000000000..affe3d19c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesdec.c @@ -0,0 +1,75 @@ +/* { dg-do run } */ +/* { dg-require-effective-target aes } */ +/* { dg-options "-O2 -maes" } */ + +#ifndef CHECK_H +#define CHECK_H "aes-check.h" +#endif + +#ifndef TEST +#define TEST aes_test +#endif + +#include CHECK_H + +#include <wmmintrin.h> +#include <string.h> + +extern void abort (void); + +#define NUM 1024 + +static __m128i src1[NUM]; +static __m128i src2[NUM]; +static __m128i edst[NUM]; + +static __m128i resdst[NUM]; + +/* Initialize input/output vectors. (Currently, there is only one set + of input/output vectors). */ +static void +init_data (__m128i *s1, __m128i *s2, __m128i *d) +{ + int i; + for (i = 0; i < NUM; i++) + { + s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72, + 0x73745665, 0x7b5b5465); + s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565, + 0x68617929, 0x48692853); + d[i] = _mm_setr_epi32 (0xb730392a, 0xb58eb95e, + 0xfaea2787, 0x138ac342); + } +} + +static void +TEST (void) +{ + int i; + + init_data (src1, src2, edst); + + for (i = 0; i < NUM; i += 16) + { + resdst[i] = _mm_aesdec_si128 (src1[i], src2[i]); + resdst[i + 1] = _mm_aesdec_si128 (src1[i + 1], src2[i + 1]); + resdst[i + 2] = _mm_aesdec_si128 (src1[i + 2], src2[i + 2]); + resdst[i + 3] = _mm_aesdec_si128 (src1[i + 3], src2[i + 3]); + resdst[i + 4] = _mm_aesdec_si128 (src1[i + 4], src2[i + 4]); + resdst[i + 5] = _mm_aesdec_si128 (src1[i + 5], src2[i + 5]); + resdst[i + 6] = _mm_aesdec_si128 (src1[i + 6], src2[i + 6]); + resdst[i + 7] = _mm_aesdec_si128 (src1[i + 7], src2[i + 7]); + resdst[i + 8] = _mm_aesdec_si128 (src1[i + 8], src2[i + 8]); + resdst[i + 9] = _mm_aesdec_si128 (src1[i + 9], src2[i + 9]); + resdst[i + 10] = _mm_aesdec_si128 (src1[i + 10], src2[i + 10]); + resdst[i + 11] = _mm_aesdec_si128 (src1[i + 11], src2[i + 11]); + resdst[i + 12] = _mm_aesdec_si128 (src1[i + 12], src2[i + 12]); + resdst[i + 13] = _mm_aesdec_si128 (src1[i + 13], src2[i + 13]); + resdst[i + 14] = _mm_aesdec_si128 (src1[i + 14], src2[i + 14]); + resdst[i + 15] = _mm_aesdec_si128 (src1[i + 15], src2[i + 15]); + } + + for (i = 0; i < NUM; i++) + if (memcmp (edst + i, resdst + i, sizeof (__m128i))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesdeclast.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesdeclast.c new file mode 100644 index 000000000..417264a13 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesdeclast.c @@ -0,0 +1,77 @@ +/* { dg-do run } */ +/* { dg-require-effective-target aes } */ +/* { dg-options "-O2 -maes" } */ + +#ifndef CHECK_H +#define CHECK_H "aes-check.h" +#endif + +#ifndef TEST +#define TEST aes_test +#endif + +#include CHECK_H + +#include <wmmintrin.h> +#include <string.h> + +extern void abort (void); + +#define NUM 1024 + +static __m128i src1[NUM]; +static __m128i src2[NUM]; +static __m128i edst[NUM]; + +static __m128i resdst[NUM]; + +/* Initialize input/output vectors. (Currently, there is only one set of + input/output vectors). */ + +static void +init_data (__m128i *s1, __m128i *s2, __m128i *d) +{ + int i; + + for (i = 0; i < NUM; i++) + { + s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72, + 0x73745665, 0x7b5b5465); + s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565, + 0x68617929, 0x48692853); + d[i] = _mm_setr_epi32 (0x72a593d0, 0xd410637b, + 0x6b317f95, 0xc5a391ef); + } +} + +static void +TEST (void) +{ + int i; + + init_data (src1, src2, edst); + + for (i = 0; i < NUM; i += 16) + { + resdst[i] = _mm_aesdeclast_si128 (src1[i], src2[i]); + resdst[i + 1] = _mm_aesdeclast_si128 (src1[i + 1], src2[i + 1]); + resdst[i + 2] = _mm_aesdeclast_si128 (src1[i + 2], src2[i + 2]); + resdst[i + 3] = _mm_aesdeclast_si128 (src1[i + 3], src2[i + 3]); + resdst[i + 4] = _mm_aesdeclast_si128 (src1[i + 4], src2[i + 4]); + resdst[i + 5] = _mm_aesdeclast_si128 (src1[i + 5], src2[i + 5]); + resdst[i + 6] = _mm_aesdeclast_si128 (src1[i + 6], src2[i + 6]); + resdst[i + 7] = _mm_aesdeclast_si128 (src1[i + 7], src2[i + 7]); + resdst[i + 8] = _mm_aesdeclast_si128 (src1[i + 8], src2[i + 8]); + resdst[i + 9] = _mm_aesdeclast_si128 (src1[i + 9], src2[i + 9]); + resdst[i + 10] = _mm_aesdeclast_si128 (src1[i + 10], src2[i + 10]); + resdst[i + 11] = _mm_aesdeclast_si128 (src1[i + 11], src2[i + 11]); + resdst[i + 12] = _mm_aesdeclast_si128 (src1[i + 12], src2[i + 12]); + resdst[i + 13] = _mm_aesdeclast_si128 (src1[i + 13], src2[i + 13]); + resdst[i + 14] = _mm_aesdeclast_si128 (src1[i + 14], src2[i + 14]); + resdst[i + 15] = _mm_aesdeclast_si128 (src1[i + 15], src2[i + 15]); + } + + for (i = 0; i < NUM; i++) + if (memcmp (edst + i, resdst + i, sizeof (__m128i))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesenc.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesenc.c new file mode 100644 index 000000000..d2a8b6031 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesenc.c @@ -0,0 +1,76 @@ +/* { dg-do run } */ +/* { dg-require-effective-target aes } */ +/* { dg-options "-O2 -maes" } */ + +#ifndef CHECK_H +#define CHECK_H "aes-check.h" +#endif + +#ifndef TEST +#define TEST aes_test +#endif + +#include CHECK_H + +#include <wmmintrin.h> +#include <string.h> + +extern void abort (void); + +#define NUM 1024 + +static __m128i src1[NUM]; +static __m128i src2[NUM]; +static __m128i edst[NUM]; + +static __m128i resdst[NUM]; + +/* Initialize input/output vectors. (Currently, there is only one set + of input/output vectors). */ + +static void +init_data (__m128i *s1, __m128i *s2, __m128i *d) +{ + int i; + for (i = 0; i < NUM; i++) + { + s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72, + 0x73745665, 0x7b5b5465); + s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565, + 0x68617929, 0x48692853); + d[i] = _mm_setr_epi32 (0xded7e595, 0x8b104b58, + 0x9fdba3c5, 0xa8311c2f); + } +} + +static void +TEST (void) +{ + int i; + + init_data (src1, src2, edst); + + for (i = 0; i < NUM; i += 16) + { + resdst[i] = _mm_aesenc_si128 (src1[i], src2[i]); + resdst[i + 1] = _mm_aesenc_si128 (src1[i + 1], src2[i + 1]); + resdst[i + 2] = _mm_aesenc_si128 (src1[i + 2], src2[i + 2]); + resdst[i + 3] = _mm_aesenc_si128 (src1[i + 3], src2[i + 3]); + resdst[i + 4] = _mm_aesenc_si128 (src1[i + 4], src2[i + 4]); + resdst[i + 5] = _mm_aesenc_si128 (src1[i + 5], src2[i + 5]); + resdst[i + 6] = _mm_aesenc_si128 (src1[i + 6], src2[i + 6]); + resdst[i + 7] = _mm_aesenc_si128 (src1[i + 7], src2[i + 7]); + resdst[i + 8] = _mm_aesenc_si128 (src1[i + 8], src2[i + 8]); + resdst[i + 9] = _mm_aesenc_si128 (src1[i + 9], src2[i + 9]); + resdst[i + 10] = _mm_aesenc_si128 (src1[i + 10], src2[i + 10]); + resdst[i + 11] = _mm_aesenc_si128 (src1[i + 11], src2[i + 11]); + resdst[i + 12] = _mm_aesenc_si128 (src1[i + 12], src2[i + 12]); + resdst[i + 13] = _mm_aesenc_si128 (src1[i + 13], src2[i + 13]); + resdst[i + 14] = _mm_aesenc_si128 (src1[i + 14], src2[i + 14]); + resdst[i + 15] = _mm_aesenc_si128 (src1[i + 15], src2[i + 15]); + } + + for (i = 0; i < NUM; i++) + if (memcmp (edst + i, resdst + i, sizeof (__m128i))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesenclast.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesenclast.c new file mode 100644 index 000000000..fd72597e9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesenclast.c @@ -0,0 +1,76 @@ +/* { dg-do run } */ +/* { dg-require-effective-target aes } */ +/* { dg-options "-O2 -maes" } */ + +#ifndef CHECK_H +#define CHECK_H "aes-check.h" +#endif + +#ifndef TEST +#define TEST aes_test +#endif + +#include CHECK_H + +#include <wmmintrin.h> +#include <string.h> + +extern void abort (void); + +#define NUM 1024 + +static __m128i src1[NUM]; +static __m128i src2[NUM]; +static __m128i edst[NUM]; + +static __m128i resdst[NUM]; + +/* Initialize input/output vectors. (Currently, there is only one + set of input/output vectors). */ + +static void +init_data (__m128i *s1, __m128i *s2, __m128i *d) +{ + int i; + for (i = 0; i < NUM; i++) + { + s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72, + 0x73745665, 0x7b5b5465); + s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565, + 0x68617929, 0x48692853); + d[i] = _mm_setr_epi32 (0x53fdc611, 0x177ec425, + 0x938c5964, 0xc7fb881e); + } +} + +static void +TEST (void) +{ + int i; + + init_data (src1, src2, edst); + + for (i = 0; i < NUM; i += 16) + { + resdst[i] = _mm_aesenclast_si128 (src1[i], src2[i]); + resdst[i + 1] = _mm_aesenclast_si128 (src1[i + 1], src2[i + 1]); + resdst[i + 2] = _mm_aesenclast_si128 (src1[i + 2], src2[i + 2]); + resdst[i + 3] = _mm_aesenclast_si128 (src1[i + 3], src2[i + 3]); + resdst[i + 4] = _mm_aesenclast_si128 (src1[i + 4], src2[i + 4]); + resdst[i + 5] = _mm_aesenclast_si128 (src1[i + 5], src2[i + 5]); + resdst[i + 6] = _mm_aesenclast_si128 (src1[i + 6], src2[i + 6]); + resdst[i + 7] = _mm_aesenclast_si128 (src1[i + 7], src2[i + 7]); + resdst[i + 8] = _mm_aesenclast_si128 (src1[i + 8], src2[i + 8]); + resdst[i + 9] = _mm_aesenclast_si128 (src1[i + 9], src2[i + 9]); + resdst[i + 10] = _mm_aesenclast_si128 (src1[i + 10], src2[i + 10]); + resdst[i + 11] = _mm_aesenclast_si128 (src1[i + 11], src2[i + 11]); + resdst[i + 12] = _mm_aesenclast_si128 (src1[i + 12], src2[i + 12]); + resdst[i + 13] = _mm_aesenclast_si128 (src1[i + 13], src2[i + 13]); + resdst[i + 14] = _mm_aesenclast_si128 (src1[i + 14], src2[i + 14]); + resdst[i + 15] = _mm_aesenclast_si128 (src1[i + 15], src2[i + 15]); + } + + for (i = 0; i < NUM; i++) + if (memcmp(edst + i, resdst + i, sizeof (__m128i))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesimc.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesimc.c new file mode 100644 index 000000000..676f919f5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aesimc.c @@ -0,0 +1,74 @@ +/* { dg-do run } */ +/* { dg-require-effective-target aes } */ +/* { dg-options "-O2 -maes" } */ + +#ifndef CHECK_H +#define CHECK_H "aes-check.h" +#endif + +#ifndef TEST +#define TEST aes_test +#endif + +#include CHECK_H + +#include <wmmintrin.h> +#include <string.h> + +extern void abort (void); + +#define NUM 1024 + +static __m128i src1[NUM]; +static __m128i edst[NUM]; + +static __m128i resdst[NUM]; + +/* Initialize input/output vectors. (Currently, there is only one set + of input/output vectors). */ + +static void +init_data (__m128i *s1, __m128i *d) +{ + int i; + + for (i = 0; i < NUM; i++) + { + s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72, + 0x73745665, 0x7b5b5465); + d[i] = _mm_setr_epi32 (0x81c3b3e5, 0x2b18330a, + 0x44b109c8, 0x627a6f66); + } +} + +static void +TEST (void) +{ + int i; + + init_data (src1, edst); + + for (i = 0; i < NUM; i += 16) + { + resdst[i] = _mm_aesimc_si128 (src1[i]); + resdst[i + 1] = _mm_aesimc_si128 (src1[i + 1]); + resdst[i + 2] = _mm_aesimc_si128 (src1[i + 2]); + resdst[i + 3] = _mm_aesimc_si128 (src1[i + 3]); + resdst[i + 4] = _mm_aesimc_si128 (src1[i + 4]); + resdst[i + 5] = _mm_aesimc_si128 (src1[i + 5]); + resdst[i + 6] = _mm_aesimc_si128 (src1[i + 6]); + resdst[i + 7] = _mm_aesimc_si128 (src1[i + 7]); + resdst[i + 8] = _mm_aesimc_si128 (src1[i + 8]); + resdst[i + 9] = _mm_aesimc_si128 (src1[i + 9]); + resdst[i + 10] = _mm_aesimc_si128 (src1[i + 10]); + resdst[i + 11] = _mm_aesimc_si128 (src1[i + 11]); + resdst[i + 12] = _mm_aesimc_si128 (src1[i + 12]); + resdst[i + 13] = _mm_aesimc_si128 (src1[i + 13]); + resdst[i + 14] = _mm_aesimc_si128 (src1[i + 14]); + resdst[i + 15] = _mm_aesimc_si128 (src1[i + 15]); + } + + for (i = 0; i < NUM; i++) + if (memcmp(edst + i, resdst + i, sizeof (__m128i))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aeskeygenassist.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aeskeygenassist.c new file mode 100644 index 000000000..f033bd6a0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aeskeygenassist.c @@ -0,0 +1,74 @@ +/* { dg-do run } */ +/* { dg-require-effective-target aes } */ +/* { dg-options "-O2 -maes" } */ + +#ifndef CHECK_H +#define CHECK_H "aes-check.h" +#endif + +#ifndef TEST +#define TEST aes_test +#endif + +#include CHECK_H + +#include <wmmintrin.h> +#include <string.h> + +extern void abort (void); + +#define NUM 1024 +#define IMM8 1 + +static __m128i src1[NUM]; +static __m128i edst[NUM]; + +static __m128i resdst[NUM]; + +/* Initialize input/output vectors. (Currently, there is only one set + of input/output vectors). */ + +static void +init_data (__m128i *s1, __m128i *d) +{ + int i; + for (i = 0; i < NUM; i++) + { + s1[i] = _mm_setr_epi32 (0x16157e2b, 0xa6d2ae28, + 0x8815f7ab, 0x3c4fcf09); + d[i] = _mm_setr_epi32 (0x24b5e434, 0x3424b5e5, + 0xeb848a01, 0x01eb848b); + } +} + +static void +TEST (void) +{ + int i; + + init_data (src1, edst); + + for (i = 0; i < NUM; i += 16) + { + resdst[i] = _mm_aeskeygenassist_si128 (src1[i], IMM8); + resdst[i + 1] = _mm_aeskeygenassist_si128 (src1[i + 1], IMM8); + resdst[i + 2] = _mm_aeskeygenassist_si128 (src1[i + 2], IMM8); + resdst[i + 3] = _mm_aeskeygenassist_si128 (src1[i + 3], IMM8); + resdst[i + 4] = _mm_aeskeygenassist_si128 (src1[i + 4], IMM8); + resdst[i + 5] = _mm_aeskeygenassist_si128 (src1[i + 5], IMM8); + resdst[i + 6] = _mm_aeskeygenassist_si128 (src1[i + 6], IMM8); + resdst[i + 7] = _mm_aeskeygenassist_si128 (src1[i + 7], IMM8); + resdst[i + 8] = _mm_aeskeygenassist_si128 (src1[i + 8], IMM8); + resdst[i + 9] = _mm_aeskeygenassist_si128 (src1[i + 9], IMM8); + resdst[i + 10] = _mm_aeskeygenassist_si128 (src1[i + 10], IMM8); + resdst[i + 11] = _mm_aeskeygenassist_si128 (src1[i + 11], IMM8); + resdst[i + 12] = _mm_aeskeygenassist_si128 (src1[i + 12], IMM8); + resdst[i + 13] = _mm_aeskeygenassist_si128 (src1[i + 13], IMM8); + resdst[i + 14] = _mm_aeskeygenassist_si128 (src1[i + 14], IMM8); + resdst[i + 15] = _mm_aeskeygenassist_si128 (src1[i + 15], IMM8); + } + + for (i = 0; i < NUM; i++) + if (memcmp(edst + i, resdst + i, sizeof (__m128i))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aggregate-ret1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aggregate-ret1.c new file mode 100644 index 000000000..6d46dc5ef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aggregate-ret1.c @@ -0,0 +1,29 @@ +/* target/36834 */ +/* Check that, with keep_aggregate_return_pointer attribute, callee does + not pop the stack for the implicit pointer arg when returning a large + structure in memory. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ + +struct foo { + int a; + int b; + int c; + int d; +}; + +__attribute__ ((callee_pop_aggregate_return(0))) +struct foo +bar (void) +{ + struct foo retval; + retval.a = 1; + retval.b = 2; + retval.c = 3; + retval.d = 4; + return retval; +} + +/* { dg-final { scan-assembler-not "ret\[ \t\]\\\$4" } } */ + + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aggregate-ret2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aggregate-ret2.c new file mode 100644 index 000000000..16e0109ef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aggregate-ret2.c @@ -0,0 +1,29 @@ +/* target/36834 */ +/* Check that, with dont_keep_aggregate_return_pointer attribute, callee + pops the stack for the implicit pointer arg when returning a large + structure in memory. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ + +struct foo { + int a; + int b; + int c; + int d; +}; + +__attribute__ ((callee_pop_aggregate_return(1))) +struct foo +bar (void) +{ + struct foo retval; + retval.a = 1; + retval.b = 2; + retval.c = 3; + retval.d = 4; + return retval; +} + +/* { dg-final { scan-assembler "ret\[ \t\]\\\$4" } } */ + + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aggregate-ret3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aggregate-ret3.c new file mode 100644 index 000000000..e3c5b0943 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aggregate-ret3.c @@ -0,0 +1,28 @@ +/* Check that, with keep_aggregate_return_pointer attribute, callee does + not pop the stack for the implicit pointer arg when returning a large + structure in memory. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ + +struct foo { + int a; + int b; + int c; + int d; +}; + +__attribute__ ((ms_abi)) +struct foo +bar (void) +{ + struct foo retval; + retval.a = 1; + retval.b = 2; + retval.c = 3; + retval.d = 4; + return retval; +} + +/* { dg-final { scan-assembler-not "ret\[ \t\]\\\$4" } } */ + + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aggregate-ret4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aggregate-ret4.c new file mode 100644 index 000000000..6e70f49f7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/aggregate-ret4.c @@ -0,0 +1,28 @@ +/* Check that, with dont_keep_aggregate_return_pointer attribute, callee + pops the stack for the implicit pointer arg when returning a large + structure in memory. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ + +struct foo { + int a; + int b; + int c; + int d; +}; + +__attribute__ ((sysv_abi)) +struct foo +bar (void) +{ + struct foo retval; + retval.a = 1; + retval.b = 2; + retval.c = 3; + retval.d = 4; + return retval; +} + +/* { dg-final { scan-assembler "ret\[ \t\]\\\$4" } } */ + + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/alias-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/alias-1.c new file mode 100644 index 000000000..a556259a1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/alias-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-alias "" } */ + +int yum; +void dessert (void) { ++yum; } +extern void jelly (void) __attribute__ ((alias ("dessert"), weak)); +extern void wobbly (void) __attribute__ ((alias ("jelly"), weak)); + +/* { dg-final { scan-assembler "wobbly" } } */ +/* { dg-final { scan-assembler "jelly" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/align-main-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/align-main-1.c new file mode 100644 index 000000000..f62284f43 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/align-main-1.c @@ -0,0 +1,28 @@ +/* Test for stack alignment when PREFERRED_STACK_BOUNDARY < alignment + of local variable. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */ +/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" } } */ +/* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */ +/* { dg-skip-if "Options about stack-boundary aren't support" { x86_64-*-mingw* } { "*" } { "" } } */ + +#include <stddef.h> + +#define ALIGNMENT 128 + +typedef int aligned __attribute__((aligned(ALIGNMENT))); +extern void abort(void); + +__attribute__ ((noinline)) +void check(void * a) +{ + if (((ptrdiff_t)a & (ALIGNMENT-1)) != 0) + abort(); +} + +int main() +{ + aligned a = 1; + check(&a); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/align-main-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/align-main-2.c new file mode 100644 index 000000000..b81758918 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/align-main-2.c @@ -0,0 +1,26 @@ +/* Test for stack alignment when PREFERRED_STACK_BOUNDARY > alignment + of local variable. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */ +/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */ +/* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" } } */ +/* { dg-skip-if "Options about stack-boundary aren't support" { x86_64-*-mingw* } { "*" } { "" } } */ +#include <stddef.h> + +#define ALIGNMENT 32 +typedef int aligned __attribute__((aligned(ALIGNMENT))); +extern void abort(void); + +__attribute__ ((noinline)) +void check(void * a) +{ + if (((ptrdiff_t)a & (ALIGNMENT-1)) != 0) + abort(); +} + +int main() +{ + aligned a = 1; + check(&a); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/align-main-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/align-main-3.c new file mode 100644 index 000000000..6f8c75803 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/align-main-3.c @@ -0,0 +1,14 @@ +/* Test for stack alignment with sibcall optimization. */ +/* { dg-do compile { target { *-*-linux* && ia32 } } } */ +/* { dg-options "-O2 -mpreferred-stack-boundary=4 -mincoming-stack-boundary=2" } */ +/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%\[re\]?sp" } } */ +/* { dg-final { scan-assembler "call\[\\t \]*foo" } } */ +/* { dg-final { scan-assembler-not "jmp\[\\t \]*foo" } } */ + +extern int foo (void); + +int +main () +{ + return foo (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/all_one_m128i.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/all_one_m128i.c new file mode 100644 index 000000000..fa973e420 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/all_one_m128i.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef long long __m128i __attribute__ ((__vector_size__ (16))); +typedef int __v4si __attribute__ ((__vector_size__ (16))); + +__m128i foo () +{ + __m128i minus_1 = (__m128i) (__v4si) { -1, -1, -1, -1 }; + + return minus_1; +} + +/* { dg-final { scan-assembler "pcmpeqd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/all_one_m256i.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/all_one_m256i.c new file mode 100644 index 000000000..1c3ca08b1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/all_one_m256i.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx2" } */ + +typedef long long __m256i __attribute__ ((__vector_size__ (32))); +typedef int __v8si __attribute__ ((__vector_size__ (32))); + +__m256i foo () +{ + __m256i minus_1 = (__m256i) (__v8si) { -1, -1, -1, -1, -1, -1, -1, -1 }; + + return minus_1; +} + +/* { dg-final { scan-assembler "vpcmpeqd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-1.c new file mode 100644 index 000000000..8988f79c7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-mno-sse" } */ +/* { dg-additional-options "-mabi=sysv" { target *-*-mingw* } } */ + +double foo(void) { return 0; } /* { dg-error "SSE disabled" } */ +void bar(double x) { } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-2.c new file mode 100644 index 000000000..6146e8efa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-2.c @@ -0,0 +1,8 @@ +/* PR target/26223 */ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-mno-80387" } */ +/* { dg-additional-options "-mabi=sysv" { target *-*-mingw* } } */ + +long double foo(long double x) { return x; } /* { dg-error "x87 disabled" } */ +long double bar(long double x) { return x; } + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-3.c new file mode 100644 index 000000000..6b7bf6a6e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -fomit-frame-pointer -mno-sse -mtune=k8" } */ +/* { dg-final { scan-assembler "subq\[\\t \]*\\\$88,\[\\t \]*%rsp" } } */ +/* { dg-final { scan-assembler-not "subq\[\\t \]*\\\$216,\[\\t \]*%rsp" } } */ + +#include <stdarg.h> + +void foo (va_list va_arglist); + +void +test (int a1, ...) +{ + va_list va_arglist; + va_start (va_arglist, a1); + foo (va_arglist); + va_end (va_arglist); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-4.c new file mode 100644 index 000000000..e88fde6af --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-4.c @@ -0,0 +1,46 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mno-sse" } */ + +#include <stdarg.h> +#include <assert.h> + +int n1 = 30; +int n2 = 324; +void *n3 = (void *) &n2; +int n4 = 407; + +int e1; +int e2; +void *e3; +int e4; + +static void +__attribute__((noinline)) +foo (va_list va_arglist) +{ + e2 = va_arg (va_arglist, int); + e3 = va_arg (va_arglist, void *); + e4 = va_arg (va_arglist, int); +} + +static void +__attribute__((noinline)) +test (int a1, ...) +{ + e1 = a1; + va_list va_arglist; + va_start (va_arglist, a1); + foo (va_arglist); + va_end (va_arglist); +} + +int +main () +{ + test (n1, n2, n3, n4); + assert (n1 == e1); + assert (n2 == e2); + assert (n3 == e3); + assert (n4 == e4); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-5.c new file mode 100644 index 000000000..da2a14ee4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-5.c @@ -0,0 +1,63 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-options "-O2" } */ + +#include <stdarg.h> +#include <assert.h> + +int n1 = 30; +double n2 = 324; +double n3 = 39494.94; +double n4 = 407; +double n5 = 32.304; +double n6 = 394.14; +double n7 = 4.07; +double n8 = 32.4; +double n9 = 314.194; +double n10 = 0.1407; + +int e1; +double e2; +double e3; +double e4; +double e5; +double e6; +double e7; +double e8; +double e9; +double e10; + +static void +__attribute__((noinline)) +test (int a1, ...) +{ + e1 = a1; + va_list va_arglist; + va_start (va_arglist, a1); + e2 = va_arg (va_arglist, double); + e3 = va_arg (va_arglist, double); + e4 = va_arg (va_arglist, double); + e5 = va_arg (va_arglist, double); + e6 = va_arg (va_arglist, double); + e7 = va_arg (va_arglist, double); + e8 = va_arg (va_arglist, double); + e9 = va_arg (va_arglist, double); + e10 = va_arg (va_arglist, double); + va_end (va_arglist); +} + +int +main () +{ + test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10); + assert (n1 == e1); + assert (n2 == e2); + assert (n3 == e3); + assert (n4 == e4); + assert (n5 == e5); + assert (n6 == e6); + assert (n7 == e7); + assert (n8 == e8); + assert (n9 == e9); + assert (n10 == e10); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-6.c new file mode 100644 index 000000000..6d076ad38 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/amd64-abi-6.c @@ -0,0 +1,70 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-options "-O2" } */ + +#include <stdarg.h> +#include <assert.h> + +int n1 = 30; +double n2 = 324; +double n3 = 39494.94; +double n4 = 407; +double n5 = 32.304; +double n6 = 394.14; +double n7 = 4.07; +double n8 = 32.4; +double n9 = 314.194; +double n10 = 0.1407; + +int e1; +double e2; +double e3; +double e4; +double e5; +double e6; +double e7; +double e8; +double e9; +double e10; + +static void +__attribute__((noinline)) +foo (va_list va_arglist) +{ + e2 = va_arg (va_arglist, double); + e3 = va_arg (va_arglist, double); + e4 = va_arg (va_arglist, double); + e5 = va_arg (va_arglist, double); + e6 = va_arg (va_arglist, double); + e7 = va_arg (va_arglist, double); + e8 = va_arg (va_arglist, double); + e9 = va_arg (va_arglist, double); + e10 = va_arg (va_arglist, double); +} + +static void +__attribute__((noinline)) +test (int a1, ...) +{ + va_list va_arglist; + e1 = a1; + va_start (va_arglist, a1); + foo (va_arglist); + va_end (va_arglist); +} + +int +main () +{ + test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10); + assert (n1 == e1); + assert (n2 == e2); + assert (n3 == e3); + assert (n4 == e4); + assert (n5 == e5); + assert (n6 == e6); + assert (n7 == e7); + assert (n8 == e8); + assert (n9 == e9); + assert (n10 == e10); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/andor-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/andor-1.c new file mode 100644 index 000000000..6cc12b348 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/andor-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "andl" } } */ + +unsigned int foo(unsigned int x) +{ + unsigned int t = x & ~1; + return t | 1; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/andor-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/andor-2.c new file mode 100644 index 000000000..88118aab5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/andor-2.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=i686" } */ + +int h(int x, int y) +{ + if ((x >= 0 && x <= 1) && (y >= 0 && y <= 1)) + return x && y; + else + return -1; +} + +int g(int x, int y) +{ + if ((x >= 0 && x <= 1) && (y >= 0 && y <= 1)) + return x || y; + else + return -1; +} + +int f(int x, int y) +{ + if (x != 0 && x != 1) + return -2; + + else + return !x; +} + +/* { dg-final { scan-assembler-not "setne" } } */ +/* { dg-final { scan-assembler-not "sete" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-1.c new file mode 100644 index 000000000..999c57679 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-m32" } */ + +register unsigned int EAX asm ("r14"); /* { dg-error "register name" } */ + +void foo () +{ + EAX = 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-2.c new file mode 100644 index 000000000..09a545517 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-2.c @@ -0,0 +1,62 @@ +/* PR opt/13862 */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O" } */ + +typedef struct _fame_syntax_t_ { +} fame_syntax_t; + +typedef struct _fame_bitbuffer_t_ +{ + unsigned char * base; + unsigned char * data; + unsigned long shift; +} fame_bitbuffer_t; + +#define fast_bitbuffer_write(data, shift, c, l) \ +{ \ + int d; \ + \ + asm("add %1, %%ecx\n" /* ecx = shift + length */ \ + "shrd %%cl, %2, %3\n" /* adjust code to fit in */ \ + "shr %%cl, %2\n" /* adjust code to fit in */ \ + "mov %%ecx, %1\n" /* shift += length */ \ + "bswap %2\n" /* reverse byte order of code */ \ + "shr $5, %%ecx\n" /* get dword increment */ \ + "or %2, (%0)\n" /* put first 32 bits */ \ + "bswap %3\n" /* reverse byte order of code */ \ + "lea (%0, %%ecx, 4), %0\n" /* data += (ecx>32) */ \ + "andl $31, %1\n" /* mask shift */ \ + "orl %3, (%0)\n" /* put last 32 bits */ \ + : "=r"(data), "=r"(shift), "=a"(d), "=d"(d), "=c"(d) \ + : "0"(data), "1"(shift), "2"((unsigned long) c), "3"(0), \ + "c"((unsigned long) l) \ + : "memory"); \ +} + +#define bitbuffer_write(bb, c, l) \ + fast_bitbuffer_write((bb)->data, (bb)->shift, c, l) + +typedef enum { frame_type_I, frame_type_P } frame_type_t; + +typedef struct _fame_syntax_mpeg1_t_ { + fame_bitbuffer_t buffer; + frame_type_t frame_type; +} fame_syntax_mpeg1_t; + +#define FAME_SYNTAX_MPEG1(x) ((fame_syntax_mpeg1_t *) x) + +void mpeg1_start_picture(fame_syntax_t *syntax) +{ + fame_syntax_mpeg1_t *syntax_mpeg1 = FAME_SYNTAX_MPEG1(syntax); + bitbuffer_write(&syntax_mpeg1->buffer, 0xFFFF, 16); + + switch(syntax_mpeg1->frame_type) { + case frame_type_I: + bitbuffer_write(&syntax_mpeg1->buffer, 0, 1); + break; + case frame_type_P: + bitbuffer_write(&syntax_mpeg1->buffer, 0, 1); + break; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-3.c new file mode 100644 index 000000000..ec37898ab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-3.c @@ -0,0 +1,35 @@ +/* PR inline-asm/6806 */ +/* { dg-do run } */ +/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */ +/* { dg-options "-O2" } */ + +extern void abort (void); + +volatile int out = 1; +volatile int a = 2; +volatile int b = 4; +volatile int c = 8; +volatile int d = 16; +volatile int e = 32; +volatile int f = 64; + +int +main () +{ + asm volatile ("xorl %%eax, %%eax \n\t" + "xorl %%esi, %%esi \n\t" + "addl %1, %0 \n\t" + "addl %2, %0 \n\t" + "addl %3, %0 \n\t" + "addl %4, %0 \n\t" + "addl %5, %0 \n\t" + "addl %6, %0" + : "+r" (out) + : "r" (a), "r" (b), "r" (c), "g" (d), "g" (e), "g" (f) + : "%eax", "%esi"); + + if (out != 127) + abort (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-4.c new file mode 100644 index 000000000..b86801032 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-4.c @@ -0,0 +1,47 @@ +/* Test if functions marked __attribute__((used)), but with address never + taken in C code, don't use alternate calling convention for local + functions on IA-32. */ +/* { dg-do run } */ +/* The asm in this test uses an absolute address. */ +/* { dg-require-effective-target nonpic } */ +/* { dg-options "-O2" } */ + +extern void abort (void); + +static int foo (int, int, int, int) __asm ("foo"); +static __attribute__((noinline, used)) int +foo (int i, int j, int k, int l) +{ + return i + j + k + l; +} + +void +bar (void) +{ + if (foo (1, 2, 3, 4) != 10) + abort (); +} + +int (*fn) (int, int, int, int); + +void +baz (void) +{ + /* Darwin loads 64-bit regions above the 4GB boundary so + we need to use this instead. */ +#if defined (__LP64__) && defined (__MACH__) + __asm ("leaq foo(%%rip), %0" : "=r" (fn)); +#else + __asm ("movl $foo, %k0" : "=r" (fn)); +#endif + if (fn (2, 3, 4, 5) != 14) + abort (); +} + +int +main (void) +{ + bar (); + baz (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-5.c new file mode 100644 index 000000000..d41298023 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-5.c @@ -0,0 +1,26 @@ +/* PR inline-asm/11676 */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2" } */ + +extern void abort (void); +static int bar(int x) __asm__("bar") __attribute__((regparm(1))); +static int __attribute__((regparm(1), noinline, used)) +bar(int x) +{ + if (x != 0) + abort (); +} + +static int __attribute__((regparm(1), noinline)) +foo(int x) +{ + x = 0; + __asm__ __volatile__("call bar" : "=a"(x) : "a"(x)); +} + +int main() +{ + foo(1); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-6.c new file mode 100644 index 000000000..6aa37ef42 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-6.c @@ -0,0 +1,16 @@ +/* PR rtl-optimization/44174 */ +/* Testcase by Jakub Jelinek <jakub@gcc.gnu.org> */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -fpic" { target fpic } } */ + +int f0 (int, int, int, int, int); +int f1 (void); + +void +f2 (void) +{ + unsigned v1, v2, v3, v4; + __asm__ ("" : "=a" (v1), "=d" (v2), "=c" (v3), "=r" (v4)); + f0 (f1 (), f1 (), f1 (), f1 (), (v4 >> 8) & 0xff); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-dialect-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-dialect-1.c new file mode 100644 index 000000000..b29017eeb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/asm-dialect-1.c @@ -0,0 +1,16 @@ +/* { dg-options "-masm=intel" } */ +/* { dg-require-effective-target masm_intel } */ + +extern void abort (void); + +int +main (void) +{ + int f = 0; + asm ("{movl $42, %%eax | mov eax, 42}" : :); + asm ("{movl $41, %0||mov %0, 43}" : "=r"(f)); + if (f != 42) + abort (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/attr-returns_twice-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/attr-returns_twice-1.c new file mode 100644 index 000000000..cd820d276 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/attr-returns_twice-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-Wclobbered" } */ + +int newsetjmp(void) __attribute__((returns_twice)); +void g(int); + +int +main (void) +{ + register int reg asm ("esi") = 1; /* { dg-warning "might be clobbered" "" } */ + + if (!newsetjmp ()) + { + reg = 2; + g (reg); + } + else + { + g (reg); + } + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/attributes-error.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/attributes-error.c new file mode 100644 index 000000000..405eda501 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/attributes-error.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ + +void foo1(int i, int j) __attribute__((fastcall, cdecl)); /* { dg-error "not compatible" } */ +void foo2(int i, int j) __attribute__((fastcall, stdcall)); /* { dg-error "not compatible" } */ +void foo3(int i, int j) __attribute__((fastcall, regparm(2))); /* { dg-error "not compatible" } */ +void foo4(int i, int j) __attribute__((stdcall, cdecl)); /* { dg-error "not compatible" } */ +void foo5(int i, int j) __attribute__((stdcall, fastcall)); /* { dg-error "not compatible" } */ +void foo6(int i, int j) __attribute__((cdecl, fastcall)); /* { dg-error "not compatible" } */ +void foo7(int i, int j) __attribute__((cdecl, stdcall)); /* { dg-error "not compatible" } */ +void foo8(int i, int j) __attribute__((regparm(2), fastcall)); /* { dg-error "not compatible" } */ + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-1.c new file mode 100644 index 000000000..4f40abb26 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-1.c @@ -0,0 +1,164 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mavx2 -maes -mpclmul" } */ + +#include <mm_malloc.h> + +/* Test that the intrinsics compile with optimization. All of them are + defined as inline functions in {,x,e,p,t,s,w,g,a,b}mmintrin.h and + mm3dnow.h that reference the proper builtin functions. Defining away + "extern" and "__inline" results in all of them being compiled as proper + functions. */ + +#define extern +#define __inline + +/* Following intrinsics require immediate arguments. */ + +/* ammintrin.h */ +#define __builtin_ia32_extrqi(X, I, L) __builtin_ia32_extrqi(X, 1, 1) +#define __builtin_ia32_insertqi(X, Y, I, L) __builtin_ia32_insertqi(X, Y, 1, 1) + +/* immintrin.h */ +#define __builtin_ia32_blendpd256(X, Y, M) __builtin_ia32_blendpd256(X, Y, 1) +#define __builtin_ia32_blendps256(X, Y, M) __builtin_ia32_blendps256(X, Y, 1) +#define __builtin_ia32_dpps256(X, Y, M) __builtin_ia32_dpps256(X, Y, 1) +#define __builtin_ia32_shufpd256(X, Y, M) __builtin_ia32_shufpd256(X, Y, 1) +#define __builtin_ia32_shufps256(X, Y, M) __builtin_ia32_shufps256(X, Y, 1) +#define __builtin_ia32_cmpsd(X, Y, O) __builtin_ia32_cmpsd(X, Y, 1) +#define __builtin_ia32_cmpss(X, Y, O) __builtin_ia32_cmpss(X, Y, 1) +#define __builtin_ia32_cmppd(X, Y, O) __builtin_ia32_cmppd(X, Y, 1) +#define __builtin_ia32_cmpps(X, Y, O) __builtin_ia32_cmpps(X, Y, 1) +#define __builtin_ia32_cmppd256(X, Y, O) __builtin_ia32_cmppd256(X, Y, 1) +#define __builtin_ia32_cmpps256(X, Y, O) __builtin_ia32_cmpps256(X, Y, 1) +#define __builtin_ia32_vextractf128_pd256(X, N) __builtin_ia32_vextractf128_pd256(X, 1) +#define __builtin_ia32_vextractf128_ps256(X, N) __builtin_ia32_vextractf128_ps256(X, 1) +#define __builtin_ia32_vextractf128_si256(X, N) __builtin_ia32_vextractf128_si256(X, 1) +#define __builtin_ia32_vpermilpd(X, N) __builtin_ia32_vpermilpd(X, 1) +#define __builtin_ia32_vpermilpd256(X, N) __builtin_ia32_vpermilpd256(X, 1) +#define __builtin_ia32_vpermilps(X, N) __builtin_ia32_vpermilps(X, 1) +#define __builtin_ia32_vpermilps256(X, N) __builtin_ia32_vpermilps256(X, 1) +#define __builtin_ia32_vpermil2pd(X, Y, C, I) __builtin_ia32_vpermil2pd(X, Y, C, 1) +#define __builtin_ia32_vpermil2pd256(X, Y, C, I) __builtin_ia32_vpermil2pd256(X, Y, C, 1) +#define __builtin_ia32_vpermil2ps(X, Y, C, I) __builtin_ia32_vpermil2ps(X, Y, C, 1) +#define __builtin_ia32_vpermil2ps256(X, Y, C, I) __builtin_ia32_vpermil2ps256(X, Y, C, 1) +#define __builtin_ia32_vperm2f128_pd256(X, Y, C) __builtin_ia32_vperm2f128_pd256(X, Y, 1) +#define __builtin_ia32_vperm2f128_ps256(X, Y, C) __builtin_ia32_vperm2f128_ps256(X, Y, 1) +#define __builtin_ia32_vperm2f128_si256(X, Y, C) __builtin_ia32_vperm2f128_si256(X, Y, 1) +#define __builtin_ia32_vinsertf128_pd256(X, Y, C) __builtin_ia32_vinsertf128_pd256(X, Y, 1) +#define __builtin_ia32_vinsertf128_ps256(X, Y, C) __builtin_ia32_vinsertf128_ps256(X, Y, 1) +#define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1) +#define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1) +#define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1) +#define __builtin_ia32_mpsadbw256(X, Y, M) __builtin_ia32_mpsadbw256(X, Y, 1) +#define __builtin_ia32_palignr256(X, Y, M) __builtin_ia32_palignr256(X, Y, 8) +#define __builtin_ia32_pblendw256(X, Y, M) __builtin_ia32_pblendw256(X, Y, 8) +#define __builtin_ia32_pshufd256(X, M) __builtin_ia32_pshufd256(X, 8) +#define __builtin_ia32_pshufhw256(X, M) __builtin_ia32_pshufhw256(X, 8) +#define __builtin_ia32_pshuflw256(X, M) __builtin_ia32_pshuflw256(X, 8) +#define __builtin_ia32_pslldqi256(X, M) __builtin_ia32_pslldqi256(X, 8) +#define __builtin_ia32_psrldqi256(X, M) __builtin_ia32_psrldqi256(X, 8) +#define __builtin_ia32_pblendd128(X, Y, M) __builtin_ia32_pblendd128(X, Y, 1) +#define __builtin_ia32_pblendd256(X, Y, M) __builtin_ia32_pblendd256(X, Y, 1) +#define __builtin_ia32_permdf256(X, M) __builtin_ia32_permdf256(X, 1) +#define __builtin_ia32_permdi256(X, M) __builtin_ia32_permdi256(X, 1) +#define __builtin_ia32_permti256(X, Y, M) __builtin_ia32_permti256(X, Y, 1) +#define __builtin_ia32_extract128i256(X, M) __builtin_ia32_extract128i256(X, 1) +#define __builtin_ia32_insert128i256(X, Y, M) __builtin_ia32_insert128i256(X, Y, 1) +#define __builtin_ia32_gathersiv2df(A, B, C, D, M) __builtin_ia32_gathersiv2df(A, B, C, D, 1) +#define __builtin_ia32_gathersiv4df(A, B, C, D, M) __builtin_ia32_gathersiv4df(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv2df(A, B, C, D, M) __builtin_ia32_gatherdiv2df(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv4df(A, B, C, D, M) __builtin_ia32_gatherdiv4df(A, B, C, D, 1) +#define __builtin_ia32_gathersiv4sf(A, B, C, D, M) __builtin_ia32_gathersiv4sf(A, B, C, D, 1) +#define __builtin_ia32_gathersiv8sf(A, B, C, D, M) __builtin_ia32_gathersiv8sf(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv4sf(A, B, C, D, M) __builtin_ia32_gatherdiv4sf(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv4sf256(A, B, C, D, M) \ + __builtin_ia32_gatherdiv4sf256(A, B, C, D, 1) +#define __builtin_ia32_gathersiv2di(A, B, C, D, M) __builtin_ia32_gathersiv2di(A, B, C, D, 1) +#define __builtin_ia32_gathersiv4di(A, B, C, D, M) __builtin_ia32_gathersiv4di(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv2di(A, B, C, D, M) __builtin_ia32_gatherdiv2di(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv4di(A, B, C, D, M) __builtin_ia32_gatherdiv4di(A, B, C, D, 1) +#define __builtin_ia32_gathersiv4si(A, B, C, D, M) __builtin_ia32_gathersiv4si(A, B, C, D, 1) +#define __builtin_ia32_gathersiv8si(A, B, C, D, M) __builtin_ia32_gathersiv8si(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv4si(A, B, C, D, M) __builtin_ia32_gatherdiv4si(A, B, C, D, 1) +#define __builtin_ia32_gatherdiv4si256(A, B, C, D, M) \ + __builtin_ia32_gatherdiv4si256(A, B, C, D, 1) + +/* wmmintrin.h */ +#define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1) +#define __builtin_ia32_pclmulqdq128(X, Y, I) __builtin_ia32_pclmulqdq128(X, Y, 1) + +/* smmintrin.h */ +#define __builtin_ia32_roundpd(V, M) __builtin_ia32_roundpd(V, 1) +#define __builtin_ia32_roundsd(D, V, M) __builtin_ia32_roundsd(D, V, 1) +#define __builtin_ia32_roundps(V, M) __builtin_ia32_roundps(V, 1) +#define __builtin_ia32_roundss(D, V, M) __builtin_ia32_roundss(D, V, 1) + +#define __builtin_ia32_pblendw128(X, Y, M) __builtin_ia32_pblendw128 (X, Y, 1) +#define __builtin_ia32_blendps(X, Y, M) __builtin_ia32_blendps(X, Y, 1) +#define __builtin_ia32_blendpd(X, Y, M) __builtin_ia32_blendpd(X, Y, 1) +#define __builtin_ia32_dpps(X, Y, M) __builtin_ia32_dpps(X, Y, 1) +#define __builtin_ia32_dppd(X, Y, M) __builtin_ia32_dppd(X, Y, 1) +#define __builtin_ia32_insertps128(D, S, N) __builtin_ia32_insertps128(D, S, 1) +#define __builtin_ia32_vec_ext_v4sf(X, N) __builtin_ia32_vec_ext_v4sf(X, 1) +#define __builtin_ia32_vec_set_v16qi(D, S, N) __builtin_ia32_vec_set_v16qi(D, S, 1) +#define __builtin_ia32_vec_set_v4si(D, S, N) __builtin_ia32_vec_set_v4si(D, S, 1) +#define __builtin_ia32_vec_set_v2di(D, S, N) __builtin_ia32_vec_set_v2di(D, S, 1) +#define __builtin_ia32_vec_ext_v16qi(X, N) __builtin_ia32_vec_ext_v16qi(X, 1) +#define __builtin_ia32_vec_ext_v4si(X, N) __builtin_ia32_vec_ext_v4si(X, 1) +#define __builtin_ia32_vec_ext_v2di(X, N) __builtin_ia32_vec_ext_v2di(X, 1) +#define __builtin_ia32_mpsadbw128(X, Y, M) __builtin_ia32_mpsadbw128(X, Y, 1) +#define __builtin_ia32_pcmpistrm128(X, Y, M) \ + __builtin_ia32_pcmpistrm128(X, Y, 1) +#define __builtin_ia32_pcmpistri128(X, Y, M) \ + __builtin_ia32_pcmpistri128(X, Y, 1) +#define __builtin_ia32_pcmpestrm128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestrm128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestri128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestri128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpistria128(X, Y, M) \ + __builtin_ia32_pcmpistria128(X, Y, 1) +#define __builtin_ia32_pcmpistric128(X, Y, M) \ + __builtin_ia32_pcmpistric128(X, Y, 1) +#define __builtin_ia32_pcmpistrio128(X, Y, M) \ + __builtin_ia32_pcmpistrio128(X, Y, 1) +#define __builtin_ia32_pcmpistris128(X, Y, M) \ + __builtin_ia32_pcmpistris128(X, Y, 1) +#define __builtin_ia32_pcmpistriz128(X, Y, M) \ + __builtin_ia32_pcmpistriz128(X, Y, 1) +#define __builtin_ia32_pcmpestria128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestria128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestric128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestric128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestrio128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestrio128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestris128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestris128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestriz128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestriz128(X, LX, Y, LY, 1) + +/* tmmintrin.h */ +#define __builtin_ia32_palignr128(X, Y, N) __builtin_ia32_palignr128(X, Y, 8) +#define __builtin_ia32_palignr(X, Y, N) __builtin_ia32_palignr(X, Y, 8) + +/* emmintrin.h */ +#define __builtin_ia32_psrldqi128(A, B) __builtin_ia32_psrldqi128(A, 8) +#define __builtin_ia32_pslldqi128(A, B) __builtin_ia32_pslldqi128(A, 8) +#define __builtin_ia32_pshufhw(A, N) __builtin_ia32_pshufhw(A, 0) +#define __builtin_ia32_pshuflw(A, N) __builtin_ia32_pshuflw(A, 0) +#define __builtin_ia32_pshufd(A, N) __builtin_ia32_pshufd(A, 0) +#define __builtin_ia32_vec_set_v8hi(A, D, N) \ + __builtin_ia32_vec_set_v8hi(A, D, 0) +#define __builtin_ia32_vec_ext_v8hi(A, N) __builtin_ia32_vec_ext_v8hi(A, 0) +#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0) + +/* xmmintrin.h */ +#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, A, _MM_HINT_NTA) +#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0) +#define __builtin_ia32_vec_set_v4hi(A, D, N) \ + __builtin_ia32_vec_set_v4hi(A, D, 0) +#define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0) +#define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0) + +#include <wmmintrin.h> +#include <immintrin.h> +#include <mm3dnow.h> diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-2.c new file mode 100644 index 000000000..17bc64e4d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-2.c @@ -0,0 +1,162 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mavx2 -msse4a -maes -mpclmul" } */ + +#include <mm_malloc.h> + +/* Test that the intrinsics compile without optimization. All of them are + defined as inline functions in {,x,e,p,t,s,w,g,a,b}mmintrin.h and + mm3dnow.h that reference the proper builtin functions. Defining away + "extern" and "__inline" results in all of them being compiled as proper + functions. */ + +#define extern +#define __inline + +#include <wmmintrin.h> +#include <immintrin.h> +#include <ammintrin.h> +#include <mm3dnow.h> + +#define _CONCAT(x,y) x ## y + +#define test_1(func, type, op1_type, imm) \ + type _CONCAT(_,func) (op1_type A, int const I) \ + { return func (A, imm); } + +#define test_1x(func, type, op1_type, imm1, imm2) \ + type _CONCAT(_,func) (op1_type A, int const I, int const L) \ + { return func (A, imm1, imm2); } + +#define test_2(func, type, op1_type, op2_type, imm) \ + type _CONCAT(_,func) (op1_type A, op2_type B, int const I) \ + { return func (A, B, imm); } + +#define test_2x(func, type, op1_type, op2_type, imm1, imm2) \ + type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \ + { return func (A, B, imm1, imm2); } + +#define test_3(func, type, op1_type, op2_type, op3_type, imm) \ + type _CONCAT(_,func) (op1_type A, op2_type B, \ + op3_type C, int const I) \ + { return func (A, B, C, imm); } + +#define test_4(func, type, op1_type, op2_type, op3_type, op4_type, imm) \ + type _CONCAT(_,func) (op1_type A, op2_type B, \ + op3_type C, op4_type D, int const I) \ + { return func (A, B, C, D, imm); } + + +/* Following intrinsics require immediate arguments. They + are defined as macros for non-optimized compilations. */ + +/* ammintrin.h */ +test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1) +test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1) + +/* immintrin.h */ +test_2 (_mm256_blend_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_blend_ps, __m256, __m256, __m256, 1) +test_2 (_mm256_dp_ps, __m256, __m256, __m256, 1) +test_2 (_mm256_shuffle_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_shuffle_ps, __m256, __m256, __m256, 1) +test_2 (_mm_cmp_sd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_cmp_ss, __m128, __m128, __m128, 1) +test_2 (_mm_cmp_pd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_cmp_ps, __m128, __m128, __m128, 1) +test_2 (_mm256_cmp_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_cmp_ps, __m256, __m256, __m256, 1) +test_1 (_mm256_extractf128_pd, __m128d, __m256d, 1) +test_1 (_mm256_extractf128_ps, __m128, __m256, 1) +test_1 (_mm256_extractf128_si256, __m128i, __m256i, 1) +test_1 (_mm256_extract_epi8, int, __m256i, 20) +test_1 (_mm256_extract_epi16, int, __m256i, 13) +test_1 (_mm256_extract_epi32, int, __m256i, 6) +#ifdef __x86_64__ +test_1 (_mm256_extract_epi64, long long, __m256i, 2) +#endif +test_1 (_mm_permute_pd, __m128d, __m128d, 1) +test_1 (_mm256_permute_pd, __m256d, __m256d, 1) +test_1 (_mm_permute_ps, __m128, __m128, 1) +test_1 (_mm256_permute_ps, __m256, __m256, 1) +test_2 (_mm256_permute2f128_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_permute2f128_ps, __m256, __m256, __m256, 1) +test_2 (_mm256_permute2f128_si256, __m256i, __m256i, __m256i, 1) +test_2 (_mm256_insertf128_pd, __m256d, __m256d, __m128d, 1) +test_2 (_mm256_insertf128_ps, __m256, __m256, __m128, 1) +test_2 (_mm256_insertf128_si256, __m256i, __m256i, __m128i, 1) +test_2 (_mm256_insert_epi8, __m256i, __m256i, int, 30) +test_2 (_mm256_insert_epi16, __m256i, __m256i, int, 7) +test_2 (_mm256_insert_epi32, __m256i, __m256i, int, 3) +#ifdef __x86_64__ +test_2 (_mm256_insert_epi64, __m256i, __m256i, long long, 1) +#endif +test_1 (_mm256_round_pd, __m256d, __m256d, 1) +test_1 (_mm256_round_ps, __m256, __m256, 1) + +/* wmmintrin.h */ +test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1) +test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1) + +/* smmintrin.h */ +test_1 (_mm_round_pd, __m128d, __m128d, 1) +test_1 (_mm_round_ps, __m128, __m128, 1) +test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_round_ss, __m128, __m128, __m128, 1) + +test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1) +test_2 (_mm_blend_ps, __m128, __m128, __m128, 1) +test_2 (_mm_blend_pd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_dp_ps, __m128, __m128, __m128, 1) +test_2 (_mm_dp_pd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_insert_ps, __m128, __m128, __m128, 1) +test_1 (_mm_extract_ps, int, __m128, 1) +test_2 (_mm_insert_epi8, __m128i, __m128i, int, 1) +test_2 (_mm_insert_epi32, __m128i, __m128i, int, 1) +#ifdef __x86_64__ +test_2 (_mm_insert_epi64, __m128i, __m128i, long long, 1) +#endif +test_1 (_mm_extract_epi8, int, __m128i, 1) +test_1 (_mm_extract_epi32, int, __m128i, 1) +#ifdef __x86_64__ +test_1 (_mm_extract_epi64, long long, __m128i, 1) +#endif +test_2 (_mm_mpsadbw_epu8, __m128i, __m128i, __m128i, 1) +test_2 (_mm_cmpistrm, __m128i, __m128i, __m128i, 1) +test_2 (_mm_cmpistri, int, __m128i, __m128i, 1) +test_4 (_mm_cmpestrm, __m128i, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestri, int, __m128i, int, __m128i, int, 1) +test_2 (_mm_cmpistra, int, __m128i, __m128i, 1) +test_2 (_mm_cmpistrc, int, __m128i, __m128i, 1) +test_2 (_mm_cmpistro, int, __m128i, __m128i, 1) +test_2 (_mm_cmpistrs, int, __m128i, __m128i, 1) +test_2 (_mm_cmpistrz, int, __m128i, __m128i, 1) +test_4 (_mm_cmpestra, int, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestrc, int, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) + +/* tmmintrin.h */ +test_2 (_mm_alignr_epi8, __m128i, __m128i, __m128i, 1) +test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1) + +/* emmintrin.h */ +test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1) +test_1 (_mm_srli_si128, __m128i, __m128i, 1) +test_1 (_mm_slli_si128, __m128i, __m128i, 1) +test_1 (_mm_extract_epi16, int, __m128i, 1) +test_2 (_mm_insert_epi16, __m128i, __m128i, int, 1) +test_1 (_mm_shufflehi_epi16, __m128i, __m128i, 1) +test_1 (_mm_shufflelo_epi16, __m128i, __m128i, 1) +test_1 (_mm_shuffle_epi32, __m128i, __m128i, 1) + +/* xmmintrin.h */ +test_2 (_mm_shuffle_ps, __m128, __m128, __m128, 1) +test_1 (_mm_extract_pi16, int, __m64, 1) +test_1 (_m_pextrw, int, __m64, 1) +test_2 (_mm_insert_pi16, __m64, __m64, int, 1) +test_2 (_m_pinsrw, __m64, __m64, int, 1) +test_1 (_mm_shuffle_pi16, __m64, __m64, 1) +test_1 (_m_pshufw, __m64, __m64, 1) +test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA) + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-3.c new file mode 100644 index 000000000..6a180fa88 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target dfp } */ +/* { dg-options "-O2 -mavx -std=gnu99" } */ + +_Decimal128 +foo128 (_Decimal128 z) +{ + return z + 1.0dl; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-2-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-2-vec.c new file mode 100644 index 000000000..bf48b8071 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-2-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double ceil (double); + +#define NUM 4 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) ceil (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) ceil (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-vec.c new file mode 100644 index 000000000..ac0911fe8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-ceil-sfix-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceil-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceil-vec.c new file mode 100644 index 000000000..0e76ab802 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceil-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-ceil-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceilf-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceilf-sfix-vec.c new file mode 100644 index 000000000..789b78e76 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceilf-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-ceilf-sfix-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceilf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceilf-vec.c new file mode 100644 index 000000000..c324a9b4f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-ceilf-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-ceilf-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-check.h new file mode 100644 index 000000000..7ddca9d7b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-check.h @@ -0,0 +1,38 @@ +#include <stdlib.h> +#include "cpuid.h" +#include "m256-check.h" +#include "avx-os-support.h" + +static void avx_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + avx_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run AVX test only if host has AVX support. */ + if (((ecx & (bit_AVX | bit_OSXSAVE)) == (bit_AVX | bit_OSXSAVE)) + && avx_os_support ()) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cmpsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cmpsd-1.c new file mode 100644 index 000000000..7898606b0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cmpsd-1.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ +/* { dg-options "-O2 -mavx -std=c99" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cmpsd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cmpsd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cmpsd-2.c new file mode 100644 index 000000000..3162912b8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cmpsd-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx" } */ + +#include <emmintrin.h> + +__m128d +foo (__m128d x, __m128d y) +{ + return _mm_cmpeq_sd (x, y); +} + + +/* { dg-final { scan-assembler "vcmpeqsd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cmpss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cmpss-1.c new file mode 100644 index 000000000..e0ee934da --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cmpss-1.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ +/* { dg-options "-O2 -mavx -std=c99" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-cmpss-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cmpss-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cmpss-2.c new file mode 100644 index 000000000..0fcc620c4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cmpss-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx" } */ + +#include <xmmintrin.h> + +__m128 +foo (__m128 x, __m128 y) +{ + return _mm_cmpeq_ss (x, y); +} + + +/* { dg-final { scan-assembler "vcmpeqss" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cond-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cond-1.c new file mode 100644 index 000000000..e233ec962 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cond-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mavx" } */ +/* { dg-require-effective-target avx_runtime } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include "sse4_1-cond-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-copysign-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-copysign-vec.c new file mode 100644 index 000000000..9b45a093a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-copysign-vec.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-copysign-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-copysignf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-copysignf-vec.c new file mode 100644 index 000000000..00aa6f57f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-copysignf-vec.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-copysignf-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-1.c new file mode 100644 index 000000000..ce651649d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mavx -mno-avx2" } */ +/* { dg-require-effective-target avx_runtime } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include "sse2-cvt-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-2-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-2-vec.c new file mode 100644 index 000000000..0081dcf38 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-2-vec.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK_H + +#include <math.h> + +#define NUM 4 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=sse"))) +TEST (void) +{ + double a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (float) a[i]; + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (float) a[i]) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-2.c new file mode 100644 index 000000000..de1afecca --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mno-avx2 -mtune=generic -fdump-tree-vect-details" } */ + +#include "avx-cvt-1.c" + +/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 6 "vect" } } */ +/* { dg-final { scan-assembler "vcvttpd2dq(y\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*YMMWORD PTR)" } } */ +/* { dg-final { scan-assembler "vcvtdq2ps\[^\n\r\]*ymm" } } */ +/* { dg-final { scan-assembler "vcvtps2pd\[^\n\r\]*(%xmm\[^\n\r\]*%ymm|ymm\[^\n\r\]*xmm)" } } */ +/* { dg-final { scan-assembler "vcvttps2dq\[^\n\r\]*ymm" } } */ +/* { dg-final { scan-assembler "vcvtdq2pd\[^\n\r\]*(%xmm\[^\n\r\]*%ymm|ymm\[^\n\r\]*xmm)" } } */ +/* { dg-final { scan-assembler "vcvtpd2ps(y\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*YMMWORD PTR)" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-3.c new file mode 100644 index 000000000..a9b898a95 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mno-avx2 -mtune=generic -mprefer-avx128 -fdump-tree-vect-details" } */ + +#include "avx-cvt-1.c" + +/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 6 "vect" } } */ +/* { dg-final { scan-assembler "vcvttpd2dq(x\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*XMMWORD PTR)" } } */ +/* { dg-final { scan-assembler "vcvtdq2ps\[^\n\r\]*xmm" } } */ +/* { dg-final { scan-assembler "vcvtps2pd\[^\n\r\]*(%xmm\[^\n\r\]*%xmm|xmm\[^\n\r\]*xmm)" } } */ +/* { dg-final { scan-assembler "vcvttps2dq\[^\n\r\]*xmm" } } */ +/* { dg-final { scan-assembler "vcvtdq2pd\[^\n\r\]*xmm\[^\n\r\]*xmm" } } */ +/* { dg-final { scan-assembler "vcvtpd2ps(x\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*XMMWORD PTR)" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-vec.c new file mode 100644 index 000000000..4dcfa3989 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-cvt-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvt-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-extract-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-extract-1.c new file mode 100644 index 000000000..2684125f5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-extract-1.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx" } */ +/* { dg-require-effective-target avx_runtime } */ + +#include "sse2-extract-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floor-sfix-2-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floor-sfix-2-vec.c new file mode 100644 index 000000000..275199cf8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floor-sfix-2-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double floor (double); + +#define NUM 4 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) floor (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) floor (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floor-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floor-sfix-vec.c new file mode 100644 index 000000000..efa557cf7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floor-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-floor-sfix-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floor-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floor-vec.c new file mode 100644 index 000000000..1d7fe5043 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floor-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-floor-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floorf-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floorf-sfix-vec.c new file mode 100644 index 000000000..0c1587a12 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floorf-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-floorf-sfix-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floorf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floorf-vec.c new file mode 100644 index 000000000..73da85be9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-floorf-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-floorf-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-lrint-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-lrint-vec.c new file mode 100644 index 000000000..2df65d203 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-lrint-vec.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-lrint-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-lrintf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-lrintf-vec.c new file mode 100644 index 000000000..e08b2f565 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-lrintf-vec.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-lrintf-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-mul-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-mul-1.c new file mode 100644 index 000000000..0d511c95c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-mul-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O3 -mavx" } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include "sse2-mul-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-os-support.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-os-support.h new file mode 100644 index 000000000..fb1ce7562 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-os-support.h @@ -0,0 +1,18 @@ +/* Check if the OS supports executing AVX instructions. */ + +#define XCR_XFEATURE_ENABLED_MASK 0x0 + +#define XSTATE_FP 0x1 +#define XSTATE_SSE 0x2 +#define XSTATE_YMM 0x4 + +static int +avx_os_support (void) +{ + unsigned int eax, edx; + unsigned int ecx = XCR_XFEATURE_ENABLED_MASK; + + __asm__ ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (ecx)); + + return (eax & (XSTATE_SSE | XSTATE_YMM)) == (XSTATE_SSE | XSTATE_YMM); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-pr51581-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-pr51581-1.c new file mode 100644 index 000000000..a1d84bf68 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-pr51581-1.c @@ -0,0 +1,23 @@ +/* PR tree-optimization/51581 */ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -mavx -fno-vect-cost-model" } */ +/* { dg-require-effective-target avx } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif +#ifndef TEST +#define TEST avx_test +#endif + +#define main main1 +#include "../../gcc.c-torture/execute/pr51581-1.c" +#undef main + +#include CHECK_H + +static void +TEST (void) +{ + main1 (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-pr51581-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-pr51581-2.c new file mode 100644 index 000000000..6ff54d997 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-pr51581-2.c @@ -0,0 +1,23 @@ +/* PR tree-optimization/51581 */ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -mavx -fno-vect-cost-model" } */ +/* { dg-require-effective-target avx } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif +#ifndef TEST +#define TEST avx_test +#endif + +#define main main1 +#include "../../gcc.c-torture/execute/pr51581-2.c" +#undef main + +#include CHECK_H + +static void +TEST (void) +{ + main1 (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-recip-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-recip-vec.c new file mode 100644 index 000000000..efeff7ece --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-recip-vec.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx -mfpmath=sse -mrecip" } */ +/* { dg-require-effective-target avx } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-recip-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-reduc-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-reduc-1.c new file mode 100644 index 000000000..1df1ee032 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-reduc-1.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mavx" } */ +/* { dg-require-effective-target avx_runtime } */ + +extern void abort (void); +double ad[1024]; +float af[1024]; +short as[1024]; +int ai[1024]; +long long all[1024]; +unsigned short aus[1024]; +unsigned int au[1024]; +unsigned long long aull[1024]; + +#define F(var) \ +__attribute__((noinline, noclone)) __typeof (var[0]) \ +f##var (void) \ +{ \ + int i; \ + __typeof (var[0]) r = 0; \ + for (i = 0; i < 1024; i++) \ + r = r > var[i] ? r : var[i]; \ + return r; \ +} + +#define TESTS \ +F (ad) F (af) F (as) F (ai) F (all) F (aus) F (au) F (aull) + +TESTS + +int +main () +{ + int i; + for (i = 0; i < 1024; i++) + { +#undef F +#define F(var) var[i] = i; + TESTS + } + for (i = 1023; i < 32 * 1024; i += 1024 + 271) + { +#undef F +#define F(var) var[i & 1023] = i; if (f##var () != i) abort (); + TESTS + } + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rint-sfix-2-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rint-sfix-2-vec.c new file mode 100644 index 000000000..9f273af5c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rint-sfix-2-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double rint (double); + +#define NUM 4 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) rint (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) rint (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rint-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rint-sfix-vec.c new file mode 100644 index 000000000..824f2eb7d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rint-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-rint-sfix-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rint-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rint-vec.c new file mode 100644 index 000000000..c1d420c6c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rint-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-rint-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rintf-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rintf-sfix-vec.c new file mode 100644 index 000000000..e5ddf790d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rintf-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-rintf-sfix-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rintf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rintf-vec.c new file mode 100644 index 000000000..caf365da6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-rintf-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-rintf-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-round-sfix-2-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-round-sfix-2-vec.c new file mode 100644 index 000000000..ddb46d925 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-round-sfix-2-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double round (double); + +#define NUM 4 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) round (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) round (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-round-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-round-sfix-vec.c new file mode 100644 index 000000000..5adfffa5f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-round-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-round-sfix-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-round-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-round-vec.c new file mode 100644 index 000000000..c43c05704 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-round-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-round-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-roundf-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-roundf-sfix-vec.c new file mode 100644 index 000000000..1fd459123 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-roundf-sfix-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-roundf-sfix-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-roundf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-roundf-vec.c new file mode 100644 index 000000000..978013eb1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-roundf-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-roundf-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-1.c new file mode 100644 index 000000000..e85784890 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-1.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (short *v) +{ + return _mm256_set_epi16 (v[15], v[14], v[13], v[12], + v[11], v[10], v[9], v[8], + v[7], v[6], v[5], v[4], + v[3], v[2], v[1], v[0]); +} + +static void +avx_test (void) +{ + short v[16] = + { + -3, 60, 48, 104, -90, 37, -48, 78, + 4, 33, 81, 4, -89, 17, 8, 68 + }; + union256i_w u; + + u.x = foo (v); + if (check_union256i_w (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-2.c new file mode 100644 index 000000000..ac1fc458b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-2.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (short x1, short x2, short x3, short x4, + short x5, short x6, short x7, short x8, + short x9, short x10, short x11, short x12, + short x13, short x14, short x15, short x16) +{ + return _mm256_set_epi16 (x1, x2, x3, x4, x5, x6, x7, x8, + x9, x10, x11, x12, x13, x14, x15, x16); +} + +static void +avx_test (void) +{ + short v[16] = + { + -3, 60, 48, 104, -90, 37, -48, 78, + 4, 33, 81, 4, -89, 17, 8, 68 + }; + union256i_w u; + + u.x = foo (v[15], v[14], v[13], v[12], + v[11], v[10], v[9], v[8], + v[7], v[6], v[5], v[4], + v[3], v[2], v[1], v[0]); + if (check_union256i_w (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-3.c new file mode 100644 index 000000000..c215d5675 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-3.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (short x) +{ + return _mm256_set_epi16 (x, x, x, x, x, x, x, x, + x, x, x, x, x, x, x, x); +} + +static void +avx_test (void) +{ + short e = 345; + short v[16]; + union256i_w u; + int i; + + for (i = 0; i < ARRAY_SIZE (v); i++) + v[i] = e; + u.x = foo (e); + if (check_union256i_w (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-4.c new file mode 100644 index 000000000..a707fc8dc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-4.c @@ -0,0 +1,83 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (short x, int i) +{ + switch (i) + { + case 15: + return _mm256_set_epi16 (x, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0); + case 14: + return _mm256_set_epi16 (0, x, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0); + case 13: + return _mm256_set_epi16 (0, 0, x, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0); + case 12: + return _mm256_set_epi16 (0, 0, 0, x, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0); + case 11: + return _mm256_set_epi16 (0, 0, 0, 0, x, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0); + case 10: + return _mm256_set_epi16 (0, 0, 0, 0, 0, x, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0); + case 9: + return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, x, 0, + 0, 0, 0, 0, 0, 0, 0, 0); + case 8: + return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, x, + 0, 0, 0, 0, 0, 0, 0, 0); + case 7: + return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0, + x, 0, 0, 0, 0, 0, 0, 0); + case 6: + return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0, + 0, x, 0, 0, 0, 0, 0, 0); + case 5: + return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, x, 0, 0, 0, 0, 0); + case 4: + return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, x, 0, 0, 0, 0); + case 3: + return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, x, 0, 0, 0); + case 2: + return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, x, 0, 0); + case 1: + return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, x, 0); + case 0: + return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, x); + default: + abort (); + } +} + +static void +avx_test (void) +{ + short e = 0xbeef; + short v[16]; + union256i_w u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 0; + v[i] = e; + u.x = foo (e, i); + if (check_union256i_w (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-5.c new file mode 100644 index 000000000..ad77eda29 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v16hi-5.c @@ -0,0 +1,83 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (short x, int i) +{ + switch (i) + { + case 15: + return _mm256_set_epi16 (x, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1); + case 14: + return _mm256_set_epi16 (1, x, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1); + case 13: + return _mm256_set_epi16 (1, 1, x, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1); + case 12: + return _mm256_set_epi16 (1, 1, 1, x, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1); + case 11: + return _mm256_set_epi16 (1, 1, 1, 1, x, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1); + case 10: + return _mm256_set_epi16 (1, 1, 1, 1, 1, x, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1); + case 9: + return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, x, 1, + 1, 1, 1, 1, 1, 1, 1, 1); + case 8: + return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, x, + 1, 1, 1, 1, 1, 1, 1, 1); + case 7: + return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1, + x, 1, 1, 1, 1, 1, 1, 1); + case 6: + return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1, + 1, x, 1, 1, 1, 1, 1, 1); + case 5: + return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, x, 1, 1, 1, 1, 1); + case 4: + return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, x, 1, 1, 1, 1); + case 3: + return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, x, 1, 1, 1); + case 2: + return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, x, 1, 1); + case 1: + return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, x, 1); + case 0: + return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, x); + default: + abort (); + } +} + +static void +avx_test (void) +{ + short e = 0xbeef; + short v[16]; + union256i_w u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 1; + v[i] = e; + u.x = foo (e, i); + if (check_union256i_w (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-1.c new file mode 100644 index 000000000..9d9381578 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-1.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (char *v) +{ + return _mm256_set_epi8 (v[31], v[30], v[29], v[28], + v[27], v[26], v[25], v[24], + v[23], v[22], v[21], v[20], + v[19], v[18], v[17], v[16], + v[15], v[14], v[13], v[12], + v[11], v[10], v[9], v[8], + v[7], v[6], v[5], v[4], + v[3], v[2], v[1], v[0]); +} + +static void +avx_test (void) +{ + char v[32] = + { + -3, 60, 48, 104, -90, 37, -48, 78, + 4, 33, 81, 4, -89, 17, 8, 68, + -13, 30, 78, 149, -70, -37, 98, 38, + 41, 73, 89, 14, 80, 117, 108, 8 + }; + union256i_b u; + + u.x = foo (v); + if (check_union256i_b (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-2.c new file mode 100644 index 000000000..508ed51a8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (char x1, char x2, char x3, char x4, + char x5, char x6, char x7, char x8, + char x9, char x10, char x11, char x12, + char x13, char x14, char x15, char x16, + char x17, char x18, char x19, char x20, + char x21, char x22, char x23, char x24, + char x25, char x26, char x27, char x28, + char x29, char x30, char x31, char x32) +{ + return _mm256_set_epi8 (x1, x2, x3, x4, x5, x6, x7, x8, + x9, x10, x11, x12, x13, x14, x15, x16, + x17, x18, x19, x20, x21, x22, x23, x24, + x25, x26, x27, x28, x29, x30, x31, x32); +} + +static void +avx_test (void) +{ + char v[32] = + { + -3, 60, 48, 104, -90, 37, -48, 78, + 4, 33, 81, 4, -89, 17, 8, 68, + -13, 30, 78, 149, -70, -37, 98, 38, + 41, 73, 89, 14, 80, 117, 108, 8 + }; + union256i_b u; + + u.x = foo (v[31], v[30], v[29], v[28], + v[27], v[26], v[25], v[24], + v[23], v[22], v[21], v[20], + v[19], v[18], v[17], v[16], + v[15], v[14], v[13], v[12], + v[11], v[10], v[9], v[8], + v[7], v[6], v[5], v[4], + v[3], v[2], v[1], v[0]); + if (check_union256i_b (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-3.c new file mode 100644 index 000000000..da92c8e2c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-3.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (char x) +{ + return _mm256_set_epi8 (x, x, x, x, x, x, x, x, + x, x, x, x, x, x, x, x, + x, x, x, x, x, x, x, x, + x, x, x, x, x, x, x, x); +} + +static void +avx_test (void) +{ + char e = -45; + char v[32]; + union256i_b u; + int i; + + for (i = 0; i < ARRAY_SIZE (v); i++) + v[i] = e; + u.x = foo (e); + if (check_union256i_b (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-4.c new file mode 100644 index 000000000..7220695ba --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-4.c @@ -0,0 +1,131 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (char x, int i) +{ + switch (i) + { + case 31: + return _mm256_set_epi8 (x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 30: + return _mm256_set_epi8 (0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 29: + return _mm256_set_epi8 (0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 28: + return _mm256_set_epi8 (0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 27: + return _mm256_set_epi8 (0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 26: + return _mm256_set_epi8 (0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 25: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 24: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 23: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 22: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 21: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 20: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 19: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 18: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 17: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 16: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 15: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 14: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 13: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 12: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 11: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 10: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 9: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0); + case 8: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0); + case 7: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0); + case 6: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0); + case 5: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0); + case 4: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0); + case 3: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0); + case 2: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0); + case 1: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0); + case 0: + return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x); + default: + abort (); + } +} + +static void +avx_test (void) +{ + char e = 0xa1; + char v[32]; + union256i_b u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 0; + v[i] = e; + u.x = foo (e, i); + if (check_union256i_b (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-5.c new file mode 100644 index 000000000..0fcadda91 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v32qi-5.c @@ -0,0 +1,131 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (char x, int i) +{ + switch (i) + { + case 31: + return _mm256_set_epi8 (x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 30: + return _mm256_set_epi8 (1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 29: + return _mm256_set_epi8 (1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 28: + return _mm256_set_epi8 (1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 27: + return _mm256_set_epi8 (1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 26: + return _mm256_set_epi8 (1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 25: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 24: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 23: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 22: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 21: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 20: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 19: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 18: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 17: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 16: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 15: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 14: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 13: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 12: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 11: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 10: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 9: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 8: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1); + case 7: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1); + case 6: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1); + case 5: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1); + case 4: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1); + case 3: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1); + case 2: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1); + case 1: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1); + case 0: + return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x); + default: + abort (); + } +} + +static void +avx_test (void) +{ + char e = 0xa1; + char v[32]; + union256i_b u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 1; + v[i] = e; + u.x = foo (e, i); + if (check_union256i_b (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-1.c new file mode 100644 index 000000000..89e6ec2f3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256d +__attribute__((noinline)) +foo (double *v) +{ + return _mm256_set_pd (v[3], v[2], v[1], v[0]); +} + +static void +avx_test (void) +{ + double v[4] = { -3, 2, 1, 9 }; + union256d u; + + u.x = foo (v); + if (check_union256d (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-2.c new file mode 100644 index 000000000..51df025ed --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-2.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256d +__attribute__((noinline)) +foo (double x1, double x2, double x3, double x4) +{ + return _mm256_set_pd (x1, x2, x3, x4); +} + +static void +avx_test (void) +{ + double v[4] = { -3, 2, 1, 9 }; + union256d u; + + u.x = foo (v[3], v[2], v[1], v[0]); + if (check_union256d (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-3.c new file mode 100644 index 000000000..01b2ff51d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-3.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256d +__attribute__((noinline)) +foo (double x) +{ + return _mm256_set_pd (x, x, x, x); +} + +static void +avx_test (void) +{ + double e = 34.5; + double v[4]; + union256d u; + int i; + + for (i = 0; i < ARRAY_SIZE (v); i++) + v[i] = e; + u.x = foo (e); + if (check_union256d (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-4.c new file mode 100644 index 000000000..e2f6300a3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-4.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256d +__attribute__((noinline)) +foo (double x, int i) +{ + switch (i) + { + case 3: + return _mm256_set_pd (x, 0, 0, 0); + case 2: + return _mm256_set_pd (0, x, 0, 0); + case 1: + return _mm256_set_pd (0, 0, x, 0); + case 0: + return _mm256_set_pd (0, 0, 0, x); + default: + abort (); + } +} + +static void +avx_test (void) +{ + double e = -3.234; + double v[4]; + union256d u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 0; + v[i] = e; + u.x = foo (e, i); + if (check_union256d (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-5.c new file mode 100644 index 000000000..6f418a668 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4df-5.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256d +__attribute__((noinline)) +foo (double x, int i) +{ + switch (i) + { + case 3: + return _mm256_set_pd (x, 1, 1, 1); + case 2: + return _mm256_set_pd (1, x, 1, 1); + case 1: + return _mm256_set_pd (1, 1, x, 1); + case 0: + return _mm256_set_pd (1, 1, 1, x); + default: + abort (); + } +} + +static void +avx_test (void) +{ + double e = -3.234; + double v[4]; + union256d u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 1; + v[i] = e; + u.x = foo (e, i); + if (check_union256d (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-1.c new file mode 100644 index 000000000..84b6278a3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (long long *v) +{ + return _mm256_set_epi64x (v[3], v[2], v[1], v[0]); +} + +static void +avx_test (void) +{ + long long v[4] + = { 0x12e9e94645ad8LL, 0x851c0b39446LL, + 0x786784645245LL, 0x9487731234LL }; + union256i_q u; + + u.x = foo (v); + if (check_union256i_q (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-2.c new file mode 100644 index 000000000..f3dc138a8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-2.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (long long x1, long long x2, long long x3, long long x4) +{ + return _mm256_set_epi64x (x1, x2, x3, x4); +} + +static void +avx_test (void) +{ + long long v[4] + = { 0x12e9e94645ad8LL, 0x851c0b39446LL, + 0x786784645245LL, 0x9487731234LL }; + union256i_q u; + + u.x = foo (v[3], v[2], v[1], v[0]); + if (check_union256i_q (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-3.c new file mode 100644 index 000000000..95710d822 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-3.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (long long x) +{ + return _mm256_set_epi64x (x, x, x, x); +} + +static void +avx_test (void) +{ + long long e = 0xfed178ab134badf1LL; + long long v[4]; + union256i_q u; + int i; + + for (i = 0; i < ARRAY_SIZE (v); i++) + v[i] = e; + u.x = foo (e); + if (check_union256i_q (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-4.c new file mode 100644 index 000000000..83f8c15fa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-4.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (long long x, int i) +{ + switch (i) + { + case 3: + return _mm256_set_epi64x (x, 0, 0, 0); + case 2: + return _mm256_set_epi64x (0, x, 0, 0); + case 1: + return _mm256_set_epi64x (0, 0, x, 0); + case 0: + return _mm256_set_epi64x (0, 0, 0, x); + default: + abort (); + } +} + +static void +avx_test (void) +{ + long long e = 0xabadbeef01234567LL; + long long v[4]; + union256i_q u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 0; + v[i] = e; + u.x = foo (e, i); + if (check_union256i_q (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-5.c new file mode 100644 index 000000000..7bc260c7b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v4di-5.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (long long x, int i) +{ + switch (i) + { + case 3: + return _mm256_set_epi64x (x, 1, 1, 1); + case 2: + return _mm256_set_epi64x (1, x, 1, 1); + case 1: + return _mm256_set_epi64x (1, 1, x, 1); + case 0: + return _mm256_set_epi64x (1, 1, 1, x); + default: + abort (); + } +} + +static void +avx_test (void) +{ + long long e = 0xabadbeef01234567LL; + long long v[4]; + union256i_q u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 1; + v[i] = e; + u.x = foo (e, i); + if (check_union256i_q (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-1.c new file mode 100644 index 000000000..6f1ba7101 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256 +__attribute__((noinline)) +foo (float *v) +{ + return _mm256_set_ps (v[7], v[6], v[5], v[4], + v[3], v[2], v[1], v[0]); +} + +static void +avx_test (void) +{ + float v[8] = { -3, 2, 1, 9, 23, -173, -13, 69 }; + union256 u; + + u.x = foo (v); + if (check_union256 (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-2.c new file mode 100644 index 000000000..4d809d7ca --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-2.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +__m256 +__attribute__((noinline)) +foo (float x1, float x2, float x3, float x4, + float x5, float x6, float x7, float x8) +{ + return _mm256_set_ps (x1, x2, x3, x4, x5, x6, x7, x8); +} + +void +avx_test (void) +{ + float v[8] = { -3, 2, 1, 9, 23, -173, -13, 69 }; + union256 u; + + u.x = foo (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]); + + if (check_union256 (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-3.c new file mode 100644 index 000000000..96f5e3318 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-3.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256 +__attribute__((noinline)) +foo (float x) +{ + return _mm256_set_ps (x, x, x, x, x, x, x, x); +} + +static void +avx_test (void) +{ + float e = 34.5; + float v[8]; + union256 u; + int i; + + for (i = 0; i < ARRAY_SIZE (v); i++) + v[i] = e; + u.x = foo (e); + if (check_union256 (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-4.c new file mode 100644 index 000000000..73be30369 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256 +__attribute__((noinline)) +foo (float x, int i) +{ + switch (i) + { + case 7: + return _mm256_set_ps (x, 0, 0, 0, 0, 0, 0, 0); + case 6: + return _mm256_set_ps (0, x, 0, 0, 0, 0, 0, 0); + case 5: + return _mm256_set_ps (0, 0, x, 0, 0, 0, 0, 0); + case 4: + return _mm256_set_ps (0, 0, 0, x, 0, 0, 0, 0); + case 3: + return _mm256_set_ps (0, 0, 0, 0, x, 0, 0, 0); + case 2: + return _mm256_set_ps (0, 0, 0, 0, 0, x, 0, 0); + case 1: + return _mm256_set_ps (0, 0, 0, 0, 0, 0, x, 0); + case 0: + return _mm256_set_ps (0, 0, 0, 0, 0, 0, 0, x); + default: + abort (); + } +} + +static void +avx_test (void) +{ + float e = -3.234; + float v[8]; + union256 u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 0; + v[i] = e; + u.x = foo (e, i); + if (check_union256 (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-5.c new file mode 100644 index 000000000..80dc156d5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8sf-5.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256 +__attribute__((noinline)) +foo (float x, int i) +{ + switch (i) + { + case 7: + return _mm256_set_ps (x, 1, 1, 1, 1, 1, 1, 1); + case 6: + return _mm256_set_ps (1, x, 1, 1, 1, 1, 1, 1); + case 5: + return _mm256_set_ps (1, 1, x, 1, 1, 1, 1, 1); + case 4: + return _mm256_set_ps (1, 1, 1, x, 1, 1, 1, 1); + case 3: + return _mm256_set_ps (1, 1, 1, 1, x, 1, 1, 1); + case 2: + return _mm256_set_ps (1, 1, 1, 1, 1, x, 1, 1); + case 1: + return _mm256_set_ps (1, 1, 1, 1, 1, 1, x, 1); + case 0: + return _mm256_set_ps (1, 1, 1, 1, 1, 1, 1, x); + default: + abort (); + } +} + +static void +avx_test (void) +{ + float e = -3.234; + float v[8]; + union256 u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 1; + v[i] = e; + u.x = foo (e, i); + if (check_union256 (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-1.c new file mode 100644 index 000000000..7aa029ea5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-1.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (int *v) +{ + return _mm256_set_epi32 (v[7], v[6], v[5], v[4], + v[3], v[2], v[1], v[0]); +} + +static void +avx_test (void) +{ + int v[8] + = { 19832468, 6576856, 8723467, 234566, + 786784, 645245, 948773, 1234 }; + union256i_d u; + + u.x = foo (v); + if (check_union256i_d (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-2.c new file mode 100644 index 000000000..e822c785b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-2.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +__m256i +__attribute__((noinline)) +foo (int x1, int x2, int x3, int x4, + int x5, int x6, int x7, int x8) +{ + return _mm256_set_epi32 (x1, x2, x3, x4, x5, x6, x7, x8); +} + +static void +avx_test (void) +{ + int v[8] = { -3, 2, 1, 9, 23, -173, -13, 69 }; + union256i_d u; + + u.x = foo (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]); + + if (check_union256i_d (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-3.c new file mode 100644 index 000000000..594436b37 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-3.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (int x) +{ + return _mm256_set_epi32 (x, x, x, x, x, x, x, x); +} + +static void +avx_test (void) +{ + int e = 0xabadbeef; + int v[8]; + union256i_d u; + int i; + + for (i = 0; i < ARRAY_SIZE (v); i++) + v[i] = e; + u.x = foo (e); + if (check_union256i_d (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-4.c new file mode 100644 index 000000000..2cad62769 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (int x, int i) +{ + switch (i) + { + case 7: + return _mm256_set_epi32 (x, 0, 0, 0, 0, 0, 0, 0); + case 6: + return _mm256_set_epi32 (0, x, 0, 0, 0, 0, 0, 0); + case 5: + return _mm256_set_epi32 (0, 0, x, 0, 0, 0, 0, 0); + case 4: + return _mm256_set_epi32 (0, 0, 0, x, 0, 0, 0, 0); + case 3: + return _mm256_set_epi32 (0, 0, 0, 0, x, 0, 0, 0); + case 2: + return _mm256_set_epi32 (0, 0, 0, 0, 0, x, 0, 0); + case 1: + return _mm256_set_epi32 (0, 0, 0, 0, 0, 0, x, 0); + case 0: + return _mm256_set_epi32 (0, 0, 0, 0, 0, 0, 0, x); + default: + abort (); + } +} + +static void +avx_test (void) +{ + int e = 0xabadbeef; + int v[8]; + union256i_d u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 0; + v[i] = e; + u.x = foo (e, i); + if (check_union256i_d (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-5.c new file mode 100644 index 000000000..456e87772 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set-v8si-5.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__((noinline)) +foo (int x, int i) +{ + switch (i) + { + case 7: + return _mm256_set_epi32 (x, 1, 1, 1, 1, 1, 1, 1); + case 6: + return _mm256_set_epi32 (1, x, 1, 1, 1, 1, 1, 1); + case 5: + return _mm256_set_epi32 (1, 1, x, 1, 1, 1, 1, 1); + case 4: + return _mm256_set_epi32 (1, 1, 1, x, 1, 1, 1, 1); + case 3: + return _mm256_set_epi32 (1, 1, 1, 1, x, 1, 1, 1); + case 2: + return _mm256_set_epi32 (1, 1, 1, 1, 1, x, 1, 1); + case 1: + return _mm256_set_epi32 (1, 1, 1, 1, 1, 1, x, 1); + case 0: + return _mm256_set_epi32 (1, 1, 1, 1, 1, 1, 1, x); + default: + abort (); + } +} + +static void +avx_test (void) +{ + int e = 0xabadbeef; + int v[8]; + union256i_d u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 1; + v[i] = e; + u.x = foo (e, i); + if (check_union256i_d (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set1-epi32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set1-epi32-1.c new file mode 100644 index 000000000..2d774aef3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set1-epi32-1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256i_d u; + int e [8]; + int source[1] = {1234}; + + u.x = _mm256_set1_epi32 (source[0]); + + for (i = 0; i < 8; i++) + e[i] = source[0]; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set1-pd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set1-pd-256-1.c new file mode 100644 index 000000000..21aea2940 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set1-pd-256-1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u; + double e [4]; + double source[1] = {26156.643}; + + u.x = _mm256_set1_pd (source[0]); + + for (i = 0; i < 4; i++) + e[i] = source[0]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set1-ps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set1-ps-256-1.c new file mode 100644 index 000000000..c5f2d1023 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-set1-ps-256-1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u; + float e [8]; + float source[1] = {1234.234f}; + + u.x = _mm256_set1_ps (source[0]); + + for (i = 0; i < 8; i++) + e[i] = source[0]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-setzero-pd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-setzero-pd-256-1.c new file mode 100644 index 000000000..43656cf81 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-setzero-pd-256-1.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u; + double e [4]; + + u.x = _mm256_setzero_pd (); + + for (i = 0; i < 4; i++) + e[i] = 0.0; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-setzero-ps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-setzero-ps-256-1.c new file mode 100644 index 000000000..ffbf431fc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-setzero-ps-256-1.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u; + float e [8]; + + u.x = _mm256_setzero_ps (); + + for (i = 0; i < 8; i++) + e[i] = 0.0; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-setzero-si256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-setzero-si256-1.c new file mode 100644 index 000000000..01eef2a4e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-setzero-si256-1.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256i_q u; + long long e [4]; + + u.x = _mm256_setzero_si256 (); + + for (i = 0; i < 4; i++) + e[i] = 0; + + if (check_union256i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-trunc-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-trunc-vec.c new file mode 100644 index 000000000..a1ee6d461 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-trunc-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-truncf-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-truncf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-truncf-vec.c new file mode 100644 index 000000000..a1ee6d461 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-truncf-vec.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */ +/* { dg-require-effective-target avx } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-truncf-vec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddpd-1.c new file mode 100644 index 000000000..afed3d035 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-addpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddpd-256-1.c new file mode 100644 index 000000000..2d0394354 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddpd-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576); + u.x = _mm256_add_pd (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddps-1.c new file mode 100644 index 000000000..ba905097f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-addps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddps-256-1.c new file mode 100644 index 000000000..363a4dedb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddps-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4); + s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9); + u.x = _mm256_add_ps (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsd-1.c new file mode 100644 index 000000000..5c562a01d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-addsd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddss-1.c new file mode 100644 index 000000000..093f61b63 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddss-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-addss-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-1.c new file mode 100644 index 000000000..7c0fc2fdf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -mfpmath=sse" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse3-addsubpd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-256-1.c new file mode 100644 index 000000000..7f431ec36 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-256-1.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576); + u.x = _mm256_addsub_pd (s1.x, s2.x); + + for (i = 0; i < 4; i++) + if (i % 2) + e[i] = s1.a[i] + s2.a[i]; + else + e[i] = s1.a[i] - s2.a[i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsubps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsubps-1.c new file mode 100644 index 000000000..1dbe3f353 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsubps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -mfpmath=sse" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse3-addsubps.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsubps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsubps-256-1.c new file mode 100644 index 000000000..e6977f9b9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaddsubps-256-1.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4); + s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9); + u.x = _mm256_addsub_ps (s1.x, s2.x); + + for (i = 0; i < 8; i++) + if (i % 2) + e[i] = s1.a[i] + s2.a[i]; + else + e[i] = s1.a[i] - s2.a[i]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesdec-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesdec-1.c new file mode 100644 index 000000000..c926dd197 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesdec-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target vaes } */ +/* { dg-options "-O2 -maes -mavx" } */ + +#define CHECK_H "aes-avx-check.h" +#define TEST aes_avx_test + +#include "aesdec.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesdeclast-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesdeclast-1.c new file mode 100644 index 000000000..467462606 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesdeclast-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target vaes } */ +/* { dg-options "-O2 -maes -mavx" } */ + +#define CHECK_H "aes-avx-check.h" +#define TEST aes_avx_test + +#include "aesdeclast.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesenc-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesenc-1.c new file mode 100644 index 000000000..313f10105 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesenc-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target vaes } */ +/* { dg-options "-O2 -maes -mavx" } */ + +#define CHECK_H "aes-avx-check.h" +#define TEST aes_avx_test + +#include "aesenc.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesenclast-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesenclast-1.c new file mode 100644 index 000000000..0df9130ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesenclast-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target vaes } */ +/* { dg-options "-O2 -maes -mavx" } */ + +#define CHECK_H "aes-avx-check.h" +#define TEST aes_avx_test + +#include "aesenclast.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesimc-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesimc-1.c new file mode 100644 index 000000000..29f910a47 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaesimc-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target vaes } */ +/* { dg-options "-O2 -maes -mavx" } */ + +#define CHECK_H "aes-avx-check.h" +#define TEST aes_avx_test + +#include "aesimc.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaeskeygenassist-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaeskeygenassist-1.c new file mode 100644 index 000000000..7c0d564a3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vaeskeygenassist-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target vaes } */ +/* { dg-options "-O2 -maes -mavx" } */ + +#define CHECK_H "aes-avx-check.h" +#define TEST aes_avx_test + +#include "aeskeygenassist.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandnpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandnpd-1.c new file mode 100644 index 000000000..c5f3c1d38 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandnpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-andnpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandnpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandnpd-256-1.c new file mode 100644 index 000000000..27e4ccdd1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandnpd-256-1.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u, s1, s2; + long long source1[4]={34545, 95567, 23443, 5675}; + long long source2[4]={674, 57897, 93459, 45624}; + long long d[4]; + long long e[4]; + + s1.x = _mm256_loadu_pd ((double *)source1); + s2.x = _mm256_loadu_pd ((double *)source2); + u.x = _mm256_andnot_pd (s1.x, s2.x); + + _mm256_storeu_pd ((double *)d, u.x); + + for (i = 0; i < 4; i++) + e[i] = (~source1[i]) & source2[i]; + + if (checkVl (d, e, 4)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandnps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandnps-1.c new file mode 100644 index 000000000..357db7e8d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandnps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-andnps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandnps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandnps-256-1.c new file mode 100644 index 000000000..7b5a3dbe8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandnps-256-1.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u, s1, s2; + int source1[8]={34545, 95567, 23443, 5675, 2323, 67, 2345, 45667}; + int source2[8]={674, 57897, 93459, 45624, 54674, 1237, 67436, 79608}; + int d[8]; + int e[8]; + + s1.x = _mm256_loadu_ps ((float *)source1); + s2.x = _mm256_loadu_ps ((float *)source2); + u.x = _mm256_andnot_ps (s1.x, s2.x); + + _mm256_storeu_ps ((float *)d, u.x); + + for (i = 0; i < 8; i++) + e[i] = (~source1[i]) & source2[i]; + + if (checkVi (d, e, 8)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandpd-1.c new file mode 100644 index 000000000..0a9532d5d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-andpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandpd-256-1.c new file mode 100644 index 000000000..b0675ec65 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandpd-256-1.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u, s1, s2; + + union + { + double d[4]; + long long ll[4]; + }source1, source2, e; + + s1.x = _mm256_set_pd (345.45, 95567, 2344.3, 567.5); + s2.x = _mm256_set_pd (674, 57.897, 934.59, 4562.4); + + _mm256_storeu_pd (source1.d, s1.x); + _mm256_storeu_pd (source2.d, s2.x); + + u.x = _mm256_and_pd (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e.ll[i] = source1.ll[i] & source2.ll[i]; + + if (check_union256d (u, e.d)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandps-1.c new file mode 100644 index 000000000..54bba79ab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-andps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandps-256-1.c new file mode 100644 index 000000000..4dc123bf3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vandps-256-1.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u, s1, s2; + + union + { + float f[8]; + int i[8]; + }source1, source2, e; + + s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667); + s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608); + + _mm256_storeu_ps (source1.f, s1.x); + _mm256_storeu_ps (source2.f, s2.x); + + u.x = _mm256_and_ps (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e.i[i] = source1.i[i] & source2.i[i]; + + if (check_union256 (u, e.f)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendpd-1.c new file mode 100644 index 000000000..0a9031f44 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-blendpd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendpd-256-1.c new file mode 100644 index 000000000..39e7c1bd5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendpd-256-1.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 12 +#endif + +void static +avx_test (void) +{ + int i; + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (34545, 95567, 23443, 5675); + s2.x = _mm256_set_pd (674, 57897, 93459, 45624); + u.x = _mm256_blend_pd (s1.x, s2.x, MASK); + + for (i = 0; i < 4; i++) + e[i] = (MASK & (0x01 << i)) ? s2.a[i] : s1.a[i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendps-256-1.c new file mode 100644 index 000000000..9f5dde29f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendps-256-1.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 114 +#endif + +void static +avx_test (void) +{ + int i; + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667); + s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608); + u.x = _mm256_blend_ps (s1.x, s2.x, MASK); + + for (i = 0; i < 8; i++) + e[i] = (MASK & (0x01 << i)) ? s2.a[i] : s1.a[i]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendvpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendvpd-256-1.c new file mode 100644 index 000000000..2f668c22e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendvpd-256-1.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 6 +#endif + +#define mask_v(pos) (((MASK >> (pos)) & 1ULL) << 63) + +void static +avx_test (void) +{ + int i; + union256d u, mask, s1, s2; + long long m[4]={mask_v(0), mask_v(1), mask_v(2), mask_v(3)}; + double e [4]; + + s1.x = _mm256_set_pd (34545, 95567, 23443, 5675); + s2.x = _mm256_set_pd (674, 57897, 93459, 45624); + mask.x = _mm256_set_pd (m[0], m[1], m[2], m[3]); + + u.x = _mm256_blendv_pd (s1.x, s2.x, mask.x); + + for (i = 0; i < 4; i++) + e[i] = (m[i] & (1ULL << 63)) ? s2.a[i] : s1.a[i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendvps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendvps-256-1.c new file mode 100644 index 000000000..0e48d690e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vblendvps-256-1.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 214 +#endif + +#define mask_v(pos) (((MASK >> (pos)) & 1U) << 31) + +void static +avx_test (void) +{ + int i; + union256 u, mask, s1, s2; + int m[8]={mask_v(0), mask_v(1), mask_v(2), mask_v(3), + mask_v(4), mask_v(5), mask_v(6), mask_v(7)}; + float e [8]; + + s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667); + s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608); + mask.x = _mm256_loadu_ps ((float *)m); + + u.x = _mm256_blendv_ps (s1.x, s2.x, mask.x); + + for (i = 0; i < 8; i++) + e[i] = (m[i] & (1ULL << 31)) ? s2.a[i] : s1.a[i]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-1.c new file mode 100644 index 000000000..e0cddd1a9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u; + union128 s; + float e [8]; + + s.x = _mm_set_ps(24.43, 68.346, 43.35, 546.46); + u.x = _mm256_broadcast_ps (&s.x); + + for (i = 0; i < 4; i++) + e[i+4] = e[i] = s.a[i]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-2.c new file mode 100644 index 000000000..eb4ec579b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-2.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256d u; + union128d s; + double e [4]; + + s.x = _mm_set_pd(24.43, 68.346); + u.x = _mm256_broadcast_pd (&s.x); + + e[0] = e[2] = s.a[0]; + e[1] = e[3] = s.a[1]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastsd-1.c new file mode 100644 index 000000000..329405f31 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastsd-1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + double s = 39678; + union256d u; + double e [4]; + + u.x = _mm256_broadcast_sd (&s); + + for (i = 0; i < 4; i++) + e[i] = s; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-1.c new file mode 100644 index 000000000..d6bf2ce61 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + float s = 39678.3452; + union256 u; + float e [8]; + + u.x = _mm256_broadcast_ss (&s); + + for (i = 0; i < 8; i++) + e[i] = s; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-2.c new file mode 100644 index 000000000..56723cb28 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-2.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + float s = 39678.3452; + union128 u; + float e [4]; + + u.x = _mm_broadcast_ss (&s); + + for (i = 0; i < 4; i++) + e[i] = s; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c new file mode 100644 index 000000000..f9646a10d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c @@ -0,0 +1,79 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ +/* { dg-options "-O2 -mavx -std=c99" } */ + +#include "avx-check.h" +#include <math.h> + +double s1[2]={2134.3343,6678.346}; +double s2[2]={41124.234,6678.346}; +long long e[2]; + +union +{ + double d[2]; + long long ll[2]; +}d; + +void check(unsigned imm, char *id) +{ + if(checkVl(d.ll, e, 2)){ + printf("mm_cmp_pd(%s: 0x%x) FAILED\n", id, imm); + } +} + +#define CMP(imm, rel) \ + for (i = 0; i < 2; i++) e[i] = rel ? -1 : 0; \ + source1 = _mm_loadu_pd(s1); \ + source2 = _mm_loadu_pd(s2); \ + dest = _mm_cmp_pd(source1, source2, imm); \ + _mm_storeu_pd(d.d, dest); \ + check(imm, "" #imm ""); + +static void +avx_test () +{ + __m128d source1, source2, dest; + int i; + + d.ll[0] = e[0] = 222; + d.ll[1] = e[1] = -33; + + CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]); + CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]); + CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]); + CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i])); + CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]); + CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]); + CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]); + CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i])); + + CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]); + CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]); + CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]); + + CMP(_CMP_FALSE_OQ, 0); + CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]); + CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]); + CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]); + CMP(_CMP_TRUE_UQ, 1); + + CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]); + CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]); + CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]); + CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i])); + CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]); + CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]); + CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]); + CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i])); + CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]); + CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]); + CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]); + CMP(_CMP_FALSE_OS, 0); + CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]); + CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]); + CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]); + CMP(_CMP_TRUE_US, 1); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c new file mode 100644 index 000000000..1c169f5ac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c @@ -0,0 +1,76 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ +/* { dg-options "-O2 -mavx -std=c99" } */ + +#include "avx-check.h" +#include <math.h> + +double s1[4]={2134.3343,6678.346,453.345635,54646.464356}; +double s2[4]={41124.234,6678.346,8653.65635,856.43576}; +long long e[4]; + +union +{ + double d[4]; + long long ll[4]; +}d; + +void check(unsigned imm, char *id) +{ + if(checkVl(d.ll, e, 4)){ + printf("mm256_cmp_pd(%s: 0x%x) FAILED\n", id, imm); + } +} + +#define CMP(imm, rel) \ + for (i = 0; i < 4; i++) e[i] = rel ? -1 : 0; \ + source1 = _mm256_loadu_pd(s1); \ + source2 = _mm256_loadu_pd(s2); \ + dest = _mm256_cmp_pd(source1, source2, imm); \ + _mm256_storeu_pd(d.d, dest); \ + check(imm, "" #imm ""); + +static void +avx_test () +{ + __m256d source1, source2, dest; + int i; + + CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]); + CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]); + CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]); + CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i])); + CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]); + CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]); + CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]); + CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i])); + + CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]); + CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]); + CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]); + + CMP(_CMP_FALSE_OQ, 0); + CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]); + CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]); + CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]); + CMP(_CMP_TRUE_UQ, 1); + + CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]); + CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]); + CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]); + CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i])); + CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]); + CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]); + CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]); + CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i])); + CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]); + CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]); + CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]); + CMP(_CMP_FALSE_OS, 0); + CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]); + CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]); + CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]); + CMP(_CMP_TRUE_US, 1); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c new file mode 100644 index 000000000..888f9eb28 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c @@ -0,0 +1,75 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ +/* { dg-options "-O2 -mavx -std=c99" } */ + +#include "avx-check.h" +#include <math.h> + +float s1[4]={2134.3343,6678.346,453.345635,54646.464356}; +float s2[4]={41124.234,6678.346,8653.65635,856.43576}; +int e[4]; + +union +{ + float f[4]; + int i[4]; +}d; + +void check(unsigned imm, char *id) +{ + if(checkVi(d.i, e, 4)){ + printf("mm_cmp_ps(0x%x, %s) FAILED\n", imm, id); + } +} + +static void +avx_test () +{ + __m128 source1, source2, dest; + int i; + +#define CMP(imm, rel) \ + for (i = 0; i < 4; i++) e[i] = rel ? -1 : 0; \ + source1 = _mm_loadu_ps(s1); \ + source2 = _mm_loadu_ps(s2); \ + dest = _mm_cmp_ps(source1, source2, imm); \ + _mm_storeu_ps(d.f, dest); \ + check(imm, "" #imm ""); + + CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]); + CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]); + CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]); + CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i])); + CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]); + CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]); + CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]); + CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i])); + + CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]); + CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]); + CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]); + + CMP(_CMP_FALSE_OQ, 0); + CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]); + CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]); + CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]); + CMP(_CMP_TRUE_UQ, 1); + + CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]); + CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]); + CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]); + CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i])); + CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]); + CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]); + CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]); + CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i])); + CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]); + CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]); + CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]); + CMP(_CMP_FALSE_OS, 0); + CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]); + CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]); + CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]); + CMP(_CMP_TRUE_US, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c new file mode 100644 index 000000000..b82abb6dc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c @@ -0,0 +1,75 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ +/* { dg-options "-O2 -mavx -std=c99" } */ + +#include "avx-check.h" +#include <math.h> + +float s1[8]={2134.3343,6678.346,453.345635,54646.464356,456,678567,123,2346}; +float s2[8]={41124.234,6678.346,8653.65635,856.43576,7456,134,539,54674}; +int e[8]; + +union +{ + float f[8]; + int i[8]; +}d; + +void check(unsigned imm, char *id) +{ + if(checkVi(d.i, e, 8)){ + printf("mm256_cmp_ps(0x%x, %s) FAILED\n", imm, id); + } +} + +static void +avx_test () +{ + __m256 source1, source2, dest; + int i; + +#define CMP(imm, rel) \ + for (i = 0; i < 8; i++) e[i] = rel ? -1 : 0; \ + source1 = _mm256_loadu_ps(s1); \ + source2 = _mm256_loadu_ps(s2); \ + dest = _mm256_cmp_ps(source1, source2, imm); \ + _mm256_storeu_ps(d.f, dest); \ + check(imm, "" #imm ""); + + CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]); + CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]); + CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]); + CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i])); + CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]); + CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]); + CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]); + CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i])); + + CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]); + CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]); + CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]); + + CMP(_CMP_FALSE_OQ, 0); + CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]); + CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]); + CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]); + CMP(_CMP_TRUE_UQ, 1); + + CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]); + CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]); + CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]); + CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i])); + CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]); + CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]); + CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]); + CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i])); + CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]); + CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]); + CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]); + CMP(_CMP_FALSE_OS, 0); + CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]); + CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]); + CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]); + CMP(_CMP_TRUE_US, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c new file mode 100644 index 000000000..9b6d58028 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c @@ -0,0 +1,72 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ +/* { dg-options "-O2 -mavx -std=c99" } */ + +#include "avx-check.h" +#include <math.h> + +double s1[] = {2134.3343, 6678.346}; +double s2[] = {41124.234, 6678.346}; +long long dd[] = {1, 2}, d[2]; +union{long long l[2]; double d[2];} e; + +void check(unsigned imm, char *id) +{ + if(checkVl(d, e.l, 2)){ + printf("mm_cmp_sd(%s: 0x%x) FAILED\n", id, imm); + } +} + +#define CMP(imm, rel) \ + e.l[0] = rel ? -1 : 0; \ + dest = _mm_loadu_pd((double*)dd); \ + source1 = _mm_loadu_pd(s1); \ + source2 = _mm_loadu_pd(s2); \ + dest = _mm_cmp_sd(source1, source2, imm); \ + _mm_storeu_pd((double*) d, dest); \ + check(imm, "" #imm ""); + +static void +avx_test () +{ + __m128d source1, source2, dest; + + e.d[1] = s1[1]; + + CMP(_CMP_EQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]); + CMP(_CMP_LT_OS, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]); + CMP(_CMP_LE_OS, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]); + CMP(_CMP_UNORD_Q, isunordered(s1[0], s2[0])); + CMP(_CMP_NEQ_UQ, isunordered(s1[0], s2[0]) || s1[0] != s2[0]); + CMP(_CMP_NLT_US, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]); + CMP(_CMP_NLE_US, isunordered(s1[0], s2[0]) || s1[0] > s2[0]); + CMP(_CMP_ORD_Q, !isunordered(s1[0], s2[0])); + + CMP(_CMP_EQ_UQ, isunordered(s1[0], s2[0]) || s1[0] == s2[0]); + CMP(_CMP_NGE_US, isunordered(s1[0], s2[0]) || s1[0] < s2[0]); + CMP(_CMP_NGT_US, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]); + + CMP(_CMP_FALSE_OQ, 0); + CMP(_CMP_NEQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]); + CMP(_CMP_GE_OS, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]); + CMP(_CMP_GT_OS, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]); + CMP(_CMP_TRUE_UQ, 1); + + CMP(_CMP_EQ_OS, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]); + CMP(_CMP_LT_OQ, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]); + CMP(_CMP_LE_OQ, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]); + CMP(_CMP_UNORD_S, isunordered(s1[0], s2[0])); + CMP(_CMP_NEQ_US, isunordered(s1[0], s2[0]) || s1[0] != s2[0]); + CMP(_CMP_NLT_UQ, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]); + CMP(_CMP_NLE_UQ, isunordered(s1[0], s2[0]) || s1[0] > s2[0]); + CMP(_CMP_ORD_S, !isunordered(s1[0], s2[0])); + CMP(_CMP_EQ_US, isunordered(s1[0], s2[0]) || s1[0] == s2[0]); + CMP(_CMP_NGE_UQ, isunordered(s1[0], s2[0]) || s1[0] < s2[0]); + CMP(_CMP_NGT_UQ, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]); + CMP(_CMP_FALSE_OS, 0); + CMP(_CMP_NEQ_OS, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]); + CMP(_CMP_GE_OQ, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]); + CMP(_CMP_GT_OQ, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]); + CMP(_CMP_TRUE_US, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c new file mode 100644 index 000000000..0dd1b0922 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c @@ -0,0 +1,74 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-require-effective-target c99_runtime } */ +/* { dg-options "-O2 -mavx -std=c99" } */ + +#include "avx-check.h" +#include <math.h> + +float s1[]={2134.3343, 6678.346, 453.345635, 54646.464356}; +float s2[]={41124.234, 6678.346, 8653.65635, 856.43576}; +int dd[] = {1, 2, 3, 4}; +float d[4]; +union{int i[4]; float f[4];} e; + +void check(unsigned imm, char *id) +{ + if(checkVi((int*)d, e.i, 4)){ + printf("mm_cmp_ss(0x%x, %s) FAILED\n", imm, id); + } +} + +static void +avx_test () +{ + __m128 source1, source2, dest; + int i; + +#define CMP(imm, rel) \ + e.i[0] = rel ? -1 : 0; \ + dest = _mm_loadu_ps((float*)dd); \ + source1 = _mm_loadu_ps(s1); \ + source2 = _mm_loadu_ps(s2); \ + dest = _mm_cmp_ss(source1, source2, imm); \ + _mm_storeu_ps(d, dest); \ + check(imm, "" #imm ""); + + for(i = 1; i < 4; i++) e.f[i] = s1[i]; + + CMP(_CMP_EQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]); + CMP(_CMP_LT_OS, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]); + CMP(_CMP_LE_OS, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]); + CMP(_CMP_UNORD_Q, isunordered(s1[0], s2[0])); + CMP(_CMP_NEQ_UQ, isunordered(s1[0], s2[0]) || s1[0] != s2[0]); + CMP(_CMP_NLT_US, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]); + CMP(_CMP_NLE_US, isunordered(s1[0], s2[0]) || s1[0] > s2[0]); + CMP(_CMP_ORD_Q, !isunordered(s1[0], s2[0])); + + CMP(_CMP_EQ_UQ, isunordered(s1[0], s2[0]) || s1[0] == s2[0]); + CMP(_CMP_NGE_US, isunordered(s1[0], s2[0]) || s1[0] < s2[0]); + CMP(_CMP_NGT_US, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]); + + CMP(_CMP_FALSE_OQ, 0); + CMP(_CMP_NEQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]); + CMP(_CMP_GE_OS, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]); + CMP(_CMP_GT_OS, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]); + CMP(_CMP_TRUE_UQ, 1); + + CMP(_CMP_EQ_OS, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]); + CMP(_CMP_LT_OQ, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]); + CMP(_CMP_LE_OQ, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]); + CMP(_CMP_UNORD_S, isunordered(s1[0], s2[0])); + CMP(_CMP_NEQ_US, isunordered(s1[0], s2[0]) || s1[0] != s2[0]); + CMP(_CMP_NLT_UQ, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]); + CMP(_CMP_NLE_UQ, isunordered(s1[0], s2[0]) || s1[0] > s2[0]); + CMP(_CMP_ORD_S, !isunordered(s1[0], s2[0])); + CMP(_CMP_EQ_US, isunordered(s1[0], s2[0]) || s1[0] == s2[0]); + CMP(_CMP_NGE_UQ, isunordered(s1[0], s2[0]) || s1[0] < s2[0]); + CMP(_CMP_NGT_UQ, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]); + CMP(_CMP_FALSE_OS, 0); + CMP(_CMP_NEQ_OS, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]); + CMP(_CMP_GE_OQ, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]); + CMP(_CMP_GT_OQ, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]); + CMP(_CMP_TRUE_US, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-1.c new file mode 100644 index 000000000..419249b46 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-comisd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-2.c new file mode 100644 index 000000000..9f757ef04 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-comisd-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-3.c new file mode 100644 index 000000000..3bb5453c2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-3.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-comisd-3.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-4.c new file mode 100644 index 000000000..f5c7a5d3b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-4.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-comisd-4.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-5.c new file mode 100644 index 000000000..314cb09ee --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-5.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-comisd-5.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-6.c new file mode 100644 index 000000000..72f54138f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomisd-6.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-comisd-6.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-1.c new file mode 100644 index 000000000..6b214fd11 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-comiss-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-2.c new file mode 100644 index 000000000..f83b977a4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-comiss-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-3.c new file mode 100644 index 000000000..a2db9e91c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-3.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-comiss-3.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-4.c new file mode 100644 index 000000000..530dfc0c5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-4.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-comiss-4.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-5.c new file mode 100644 index 000000000..b149736b3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-5.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-comiss-5.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-6.c new file mode 100644 index 000000000..45e94daf3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcomiss-6.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-comiss-6.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-1.c new file mode 100644 index 000000000..5d08be902 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvtdq2pd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-256-1.c new file mode 100644 index 000000000..4b39ffe9a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union128i_d s1; + union256d u; + double e [4]; + + s1.x = _mm_set_epi32 (2134.3343,1234.635654,453.345635,54646.464356); + u.x = _mm256_cvtepi32_pd (s1.x); + + for (i = 0; i < 4; i++) + e[i] = (double)s1.a[i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtdq2ps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtdq2ps-1.c new file mode 100644 index 000000000..1e2ad6254 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtdq2ps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvtdq2ps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-1.c new file mode 100644 index 000000000..752497514 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvtpd2dq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-256-1.c new file mode 100644 index 000000000..30e93af92 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d s1; + union128i_d u; + int e [4]; + + s1.x = _mm256_set_pd (2.78, 7777768.82, 23.67, 536.46); + u.x = _mm256_cvtpd_epi32 (s1.x); + + for (i = 0; i < 4; i++) + e[i] = (int)(s1.a[i] + 0.5); + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-1.c new file mode 100644 index 000000000..5bc43d561 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvtpd2ps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-256-1.c new file mode 100644 index 000000000..987f2b263 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d s1; + union128 u; + float e [4]; + + s1.x = _mm256_set_pd (2.43, 68.46, 23.35, 536.46); + u.x = _mm256_cvtpd_ps (s1.x); + + for (i = 0; i < 4; i++) + e[i] = (float)s1.a[i]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-1.c new file mode 100644 index 000000000..36d90a265 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvtps2dq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-256-1.c new file mode 100644 index 000000000..47ec12b8d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 s1; + union256i_d u; + int e [8]; + + s1.x = _mm256_set_ps (2.78, 77768.82, 23.67, 536.46, 4564.6575, 568.1263, 9889.2422, 7352.4563); + u.x = _mm256_cvtps_epi32 (s1.x); + + for (i = 0; i < 8; i++) + e[i] = (int)(s1.a[i] + 0.5); + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-1.c new file mode 100644 index 000000000..114a71976 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvtps2pd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-256-1.c new file mode 100644 index 000000000..9d48998a3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union128 s1; + union256d u; + double e [4]; + + s1.x = _mm_set_ps (2.43, 68.46, 23.35, 536.46); + u.x = _mm256_cvtps_pd (s1.x); + + for (i = 0; i < 4; i++) + e[i] = (double)s1.a[i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-1.c new file mode 100644 index 000000000..53c61a2ea --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvtsd2si-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c new file mode 100644 index 000000000..f462c6365 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c @@ -0,0 +1,8 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvtsd2si-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsd2ss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsd2ss-1.c new file mode 100644 index 000000000..c0e224d06 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsd2ss-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvtsd2ss-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-1.c new file mode 100644 index 000000000..35da346d6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvtsi2sd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c new file mode 100644 index 000000000..36f411e59 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c @@ -0,0 +1,8 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvtsi2sd-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-1.c new file mode 100644 index 000000000..12ac36c72 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-cvtsi2ss-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c new file mode 100644 index 000000000..8dc0b35c1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c @@ -0,0 +1,8 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-cvtsi2ss-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtss2sd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtss2sd-1.c new file mode 100644 index 000000000..0f6365c35 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtss2sd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvtss2sd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-1.c new file mode 100644 index 000000000..3a51ff168 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-cvtss2si-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c new file mode 100644 index 000000000..b9afab7f6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c @@ -0,0 +1,8 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-cvtss2si-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-1.c new file mode 100644 index 000000000..f27160a6b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvttpd2dq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-256-1.c new file mode 100644 index 000000000..16edf8ac7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d s1; + union128i_d u; + int e [4]; + + s1.x = _mm256_set_pd (2.43, 68.78, 23.61, 536.46); + u.x = _mm256_cvttpd_epi32 (s1.x); + + for (i = 0; i < 4; i++) + e[i] = (int)s1.a[i]; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-1.c new file mode 100644 index 000000000..f8ab025db --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvttps2dq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-256-1.c new file mode 100644 index 000000000..0a580f015 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 s1; + union256i_d u; + int e [8]; + + s1.x = _mm256_set_ps (45.64, 4564.56, 2.3, 5.5, 57.57, 89.34, 54.12, 954.67); + u.x = _mm256_cvttps_epi32 (s1.x); + + for (i = 0; i < 8; i++) + e[i] = (int)s1.a[i]; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-1.c new file mode 100644 index 000000000..b9963d4ab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvttsd2si-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c new file mode 100644 index 000000000..84bdb9f3a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c @@ -0,0 +1,8 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-cvttsd2si-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-1.c new file mode 100644 index 000000000..94c94c1d6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-cvttss2si-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c new file mode 100644 index 000000000..b3c68eaf6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c @@ -0,0 +1,8 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-cvttss2si-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivpd-1.c new file mode 100644 index 000000000..57ddfd1f7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-divpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivpd-256-1.c new file mode 100644 index 000000000..1840e3d56 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivpd-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576); + u.x = _mm256_div_pd (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] / s2.a[i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivps-1.c new file mode 100644 index 000000000..d4fcaebdf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-divps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivps-256-1.c new file mode 100644 index 000000000..3ff4c7ee2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivps-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u, s1, s2; + float e[8]; + + s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4); + s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9); + u.x = _mm256_div_ps (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i] / s2.a[i]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivsd-1.c new file mode 100644 index 000000000..faca3ed1c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivsd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-divsd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivss-1.c new file mode 100644 index 000000000..f5740eba4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdivss-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-divss-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdppd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdppd-1.c new file mode 100644 index 000000000..7d04cc4bc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdppd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-dppd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdppd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdppd-2.c new file mode 100644 index 000000000..6e30faf45 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdppd-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-dppd-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdpps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdpps-1.c new file mode 100644 index 000000000..75ba0be5f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdpps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-dpps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdpps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdpps-2.c new file mode 100644 index 000000000..b54b90969 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vdpps-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-dpps-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-1.c new file mode 100644 index 000000000..4919d640f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-1.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef OFFSET +#define OFFSET 1 +#endif + +#if OFFSET < 0 || OFFSET > 1 +#error OFFSET must be within [0..1] +#endif + +void static +avx_test (void) +{ + union256d s1; + union128d u; + double e [2]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + u.x = _mm256_extractf128_pd (s1.x, OFFSET); + + __builtin_memcpy (e, s1.a + OFFSET * 2, sizeof e); + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-2.c new file mode 100644 index 000000000..db26e181c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-2.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef OFFSET +#define OFFSET 1 +#endif + +#if OFFSET < 0 || OFFSET > 1 +#error OFFSET must be within [0..1] +#endif + +void static +avx_test (void) +{ + union256 s1; + union128 u; + float e [4]; + + s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4); + u.x = _mm256_extractf128_ps (s1.x, OFFSET); + + __builtin_memcpy (e, s1.a + OFFSET * 4, sizeof e); + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-3.c new file mode 100644 index 000000000..b7d4a3731 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-3.c @@ -0,0 +1,7 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define OFFSET 0 + +#include "avx-vextractf128-256-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-4.c new file mode 100644 index 000000000..973fa58b1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-4.c @@ -0,0 +1,7 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define OFFSET 0 + +#include "avx-vextractf128-256-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractps-1.c new file mode 100644 index 000000000..4215c34dc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vextractps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-extractps.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhaddpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhaddpd-1.c new file mode 100644 index 000000000..7809c850c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhaddpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse3-haddpd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhaddpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhaddpd-256-1.c new file mode 100644 index 000000000..b9245a368 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhaddpd-256-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576); + u.x = _mm256_hadd_pd (s1.x, s2.x); + + e[0] = s1.a[0] + s1.a[1]; + e[1] = s2.a[0] + s2.a[1]; + e[2] = s1.a[2] + s1.a[3]; + e[3] = s2.a[2] + s2.a[3]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhaddps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhaddps-1.c new file mode 100644 index 000000000..73dcfb6c4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhaddps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse3-haddps.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhaddps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhaddps-256-1.c new file mode 100644 index 000000000..fbc58238a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhaddps-256-1.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4); + s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9); + u.x = _mm256_hadd_ps (s1.x, s2.x); + + e[0] = s1.a[0] + s1.a[1]; + e[1] = s1.a[2] + s1.a[3]; + e[2] = s2.a[0] + s2.a[1]; + e[3] = s2.a[2] + s2.a[3]; + e[4] = s1.a[4] + s1.a[5]; + e[5] = s1.a[6] + s1.a[7]; + e[6] = s2.a[4] + s2.a[5]; + e[7] = s2.a[6] + s2.a[7]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhsubpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhsubpd-1.c new file mode 100644 index 000000000..68d14327a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhsubpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse3-hsubpd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhsubpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhsubpd-256-1.c new file mode 100644 index 000000000..df710d7f0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhsubpd-256-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576); + u.x = _mm256_hsub_pd (s1.x, s2.x); + + e[0] = s1.a[0] - s1.a[1]; + e[1] = s2.a[0] - s2.a[1]; + e[2] = s1.a[2] - s1.a[3]; + e[3] = s2.a[2] - s2.a[3]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhsubps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhsubps-1.c new file mode 100644 index 000000000..2ddd2c0c8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhsubps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse3-hsubps.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhsubps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhsubps-256-1.c new file mode 100644 index 000000000..aa601c8a7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vhsubps-256-1.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4); + s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9); + u.x = _mm256_hsub_ps (s1.x, s2.x); + + e[0] = s1.a[0] - s1.a[1]; + e[1] = s1.a[2] - s1.a[3]; + e[2] = s2.a[0] - s2.a[1]; + e[3] = s2.a[2] - s2.a[3]; + e[4] = s1.a[4] - s1.a[5]; + e[5] = s1.a[6] - s1.a[7]; + e[6] = s2.a[4] - s2.a[5]; + e[7] = s2.a[6] - s2.a[7]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-1.c new file mode 100644 index 000000000..2390e5c7e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-1.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef OFFSET +#define OFFSET 1 +#endif + +#if OFFSET < 0 || OFFSET > 1 +#error OFFSET must be within [0..1] +#endif + +void static +avx_test (void) +{ + int i; + union256d u, s1; + union128d s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm_set_pd (68543.731254, 3452.578238); + u.x = _mm256_insertf128_pd (s1.x, s2.x, OFFSET); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i]; + + for (i=0; i < 2; i++) + e[i + (OFFSET * 2)] = s2.a[i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-2.c new file mode 100644 index 000000000..ce0b23bbf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-2.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef OFFSET +#define OFFSET 0 +#endif + +#if OFFSET < 0 || OFFSET > 1 +#error OFFSET must be within [0..1] +#endif + +void static +avx_test (void) +{ + int i; + union256 u, s1; + union128 s2; + float e [8]; + + s1.x = _mm256_set_ps (39.467, 45.789, 78.342, 67.892, 76.678, 12.963, 29.746, 24.753); + s2.x = _mm_set_ps (57.493, 38.395, 22.479, 31.614); + u.x = _mm256_insertf128_ps (s1.x, s2.x, OFFSET); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i]; + + for (i=0; i < 4; i++) + e[i + (OFFSET * 4)] = s2.a[i]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-3.c new file mode 100644 index 000000000..89834d554 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-3.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef OFFSET +#define OFFSET 0 +#endif + +#if OFFSET < 0 || OFFSET > 1 +#error OFFSET must be within [0..1] +#endif + +void static +avx_test (void) +{ + int i; + union256i_d u, s1; + union128i_d s2; + int e [8]; + + s1.x = _mm256_set_epi32 (39467, 45789, 78342, 67892, 76678, 12963, 29746, 24753); + s2.x = _mm_set_epi32 (57493, 38395, 22479, 31614); + u.x = _mm256_insertf128_si256 (s1.x, s2.x, OFFSET); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i]; + + for (i=0; i < 4; i++) + e[i + (OFFSET * 4)] = s2.a[i]; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertps-1.c new file mode 100644 index 000000000..ad1f33308 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-insertps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertps-2.c new file mode 100644 index 000000000..7b93174aa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertps-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-insertps-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertps-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertps-3.c new file mode 100644 index 000000000..515ee418c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertps-3.c @@ -0,0 +1,8 @@ +/* { dg-do run { target ia32 } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx -mtune=geode" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-insertps-3.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertps-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertps-4.c new file mode 100644 index 000000000..527b070f6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vinsertps-4.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-insertps-4.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vlddqu-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vlddqu-1.c new file mode 100644 index 000000000..7ecea79e8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vlddqu-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse3-lddqu.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vlddqu-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vlddqu-256-1.c new file mode 100644 index 000000000..82c0ed580 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vlddqu-256-1.c @@ -0,0 +1,17 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int e[8]={ 23, 67, 53, 6, 4, 6, 85, 234}; + union256i_d u; + + u.x = _mm256_lddqu_si256 ((__m256i *) e); + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovdqu.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovdqu.c new file mode 100644 index 000000000..24b5bba77 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovdqu.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-maskmovdqu.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c new file mode 100644 index 000000000..6204ebd28 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 7 +#endif + +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) + +void static +avx_test (void) +{ + int i; + long long m[2] = {mask_v(0), mask_v(1)}; + double s[2] = {1.1, 2.2}; + union128d u; + union128i_q mask; + double e[2] = {0.0}; + + mask.x = _mm_loadu_si128 ((__m128i *)m); + u.x = _mm_maskload_pd (s, mask.x); + + for (i = 0 ; i < 2; i++) + e[i] = m[i] ? s[i] : 0; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c new file mode 100644 index 000000000..6bc620755 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 6 +#endif + +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) + +void static +avx_test (void) +{ + int i; + long long m[2] = {mask_v(0), mask_v(1)}; + double s[2] = {1.1, 2.2}; + double e[2] = {0.0}; + double d[2] = {0.0}; + union128d src; + union128i_q mask; + + src.x = _mm_loadu_pd (s); + mask.x = _mm_loadu_si128 ((__m128i *)m); + _mm_maskstore_pd (d, mask.x, src.x); + + for (i = 0 ; i < 2; i++) + e[i] = m[i] ? s[i] : 0; + + if (checkVd (d, e, 2)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c new file mode 100644 index 000000000..e591c05c8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 7 +#endif + +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) + +void static +avx_test (void) +{ + int i; + long long m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)}; + double s[4] = {1.1, 2.2, 3.3, 4.4}; + union256d u; + union256i_q mask; + double e [4] = {0.0}; + + mask.x = _mm256_loadu_si256 ((__m256i *)m); + u.x = _mm256_maskload_pd (s, mask.x); + + for (i = 0 ; i < 4; i++) + e[i] = m[i] ? s[i] : 0; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c new file mode 100644 index 000000000..5df2f94ee --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 6 +#endif + +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) + +void static +avx_test (void) +{ + int i; + long long m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)}; + double s[4] = {1.1, 2.2, 3.3, 4.4}; + double e [4] = {0.0}; + double d [4] = {0.0}; + union256d src; + union256i_q mask; + + src.x = _mm256_loadu_pd (s); + mask.x = _mm256_loadu_si256 ((__m256i *)m); + _mm256_maskstore_pd (d, mask.x, src.x); + + for (i = 0 ; i < 4; i++) + e[i] = m[i] ? s[i] : 0; + + if (checkVd (d, e, 4)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c new file mode 100644 index 000000000..360a04dba --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 134 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) + +void static +avx_test (void) +{ + int i; + int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)}; + float s[4] = {1,2,3,4}; + union128 u; + union128i_d mask; + float e[4] = {0.0}; + + mask.x = _mm_loadu_si128 ((__m128i *)m); + u.x = _mm_maskload_ps (s, mask.x); + + for (i = 0 ; i < 4; i++) + e[i] = m[i] ? s[i] : 0; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c new file mode 100644 index 000000000..3dde96557 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 214 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) + +void static +avx_test (void) +{ + int i; + int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)}; + float s[4] = {1,2,3,4}; + union128 src; + union128i_d mask; + float e[4] = {0.0}; + float d[4] = {0.0}; + + src.x = _mm_loadu_ps (s); + mask.x = _mm_loadu_si128 ((__m128i *)m); + _mm_maskstore_ps (d, mask.x, src.x); + + for (i = 0 ; i < 4; i++) + e[i] = m[i] ? s[i] : 0; + + if (checkVf (d, e, 4)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c new file mode 100644 index 000000000..647ce3f6e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 134 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) + +void static +avx_test (void) +{ + int i; + int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)}; + float s[8] = {1,2,3,4,5,6,7,8}; + union256 u; + union256i_d mask; + float e [8] = {0.0}; + + mask.x = _mm256_loadu_si256 ((__m256i *)m); + u.x = _mm256_maskload_ps (s, mask.x); + + for (i = 0 ; i < 8; i++) + e[i] = m[i] ? s[i] : 0; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c new file mode 100644 index 000000000..016904d46 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 214 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) + +void static +avx_test (void) +{ + int i; + int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)}; + float s[8] = {1,2,3,4,5,6,7,8}; + union256 src; + union256i_d mask; + float e [8] = {0.0}; + float d [8] = {0.0}; + + src.x = _mm256_loadu_ps (s); + mask.x = _mm256_loadu_si256 ((__m256i *)m); + _mm256_maskstore_ps (d, mask.x, src.x); + + for (i = 0 ; i < 8; i++) + e[i] = m[i] ? s[i] : 0; + + if (checkVf (d, e, 8)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxpd-1.c new file mode 100644 index 000000000..981e2a5b6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-maxpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxpd-256-1.c new file mode 100644 index 000000000..7b9c91c03 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxpd-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576); + u.x = _mm256_max_pd (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] > s2.a[i] ? s1.a[i] : s2.a[i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxps-1.c new file mode 100644 index 000000000..e4c41450d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-maxps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxps-256-1.c new file mode 100644 index 000000000..44bb7ed9c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxps-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4); + s2.x = _mm256_set_ps (1.17, 24567.16, 3.15, 4567.14, 5.13, 65467.12, 788.11, 8.9); + u.x = _mm256_max_ps (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i] > s2.a[i] ? s1.a[i] : s2.a[i]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxsd-1.c new file mode 100644 index 000000000..e24410cd1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxsd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-maxsd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxss-1.c new file mode 100644 index 000000000..afe5d0adb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmaxss-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-maxss-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminpd-1.c new file mode 100644 index 000000000..a7eb64972 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-minpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminpd-256-1.c new file mode 100644 index 000000000..555e029bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminpd-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576); + u.x = _mm256_min_pd (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] < s2.a[i] ? s1.a[i] : s2.a[i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminps-1.c new file mode 100644 index 000000000..dfb07ba23 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-minps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminps-256-1.c new file mode 100644 index 000000000..19ac83a72 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminps-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4); + s2.x = _mm256_set_ps (1.17, 24567.16, 3.15, 4567.14, 5.13, 65467.12, 788.11, 8.9); + u.x = _mm256_min_ps (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i] < s2.a[i] ? s1.a[i] : s2.a[i]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminsd-1.c new file mode 100644 index 000000000..5aa1d9aa0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminsd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-minsd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminss-1.c new file mode 100644 index 000000000..c2e6f2799 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vminss-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-minss-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovapd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovapd-1.c new file mode 100644 index 000000000..5d97a5d2f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovapd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movapd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovapd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovapd-2.c new file mode 100644 index 000000000..9856d2907 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovapd-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movapd-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c new file mode 100644 index 000000000..d91212283 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256d +__attribute__((noinline, unused)) +test (double *e) +{ + return _mm256_load_pd (e); +} + +void static +avx_test (void) +{ + union256d u; + double e [4] __attribute__ ((aligned (8))) = {41124.234,2344.2354,8653.65635,856.43576}; + + u.x = test (e); + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c new file mode 100644 index 000000000..96a664ac1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static void +__attribute__((noinline, unused)) +test (double *e, __m256d a) +{ + return _mm256_store_pd (e, a); +} + +void static +avx_test (void) +{ + union256d u; + double e [4] __attribute__ ((aligned (8))) = {0.0}; + + u.x = _mm256_set_pd (39578.467285, 7856.342941, 85632.783567, 47563.234215); + + test (e, u.x); + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovaps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovaps-1.c new file mode 100644 index 000000000..a10894c35 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovaps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movaps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovaps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovaps-2.c new file mode 100644 index 000000000..ad0cf47c4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovaps-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movaps-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-1.c new file mode 100644 index 000000000..74681c326 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256 +__attribute__((noinline, unused)) +test (float *e) +{ + return _mm256_load_ps (e); +} + +void static +avx_test (void) +{ + union256 u; + float e [8] __attribute__ ((aligned (32))) = {24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4}; + + u.x = test (e); + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-2.c new file mode 100644 index 000000000..dbd5227c0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static void +__attribute__((noinline, unused)) +test (float *e, __m256 a) +{ + return _mm256_store_ps (e, a); +} + +void static +avx_test (void) +{ + union256 u; + float e [8] __attribute__ ((aligned (32))) = {0.0}; + + u.x = _mm256_set_ps (1.17, 24567.16, 3.15, 4567.14, 5.13, 65467.12, 788.11, 8.9); + + test (e, u.x); + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovd-1.c new file mode 100644 index 000000000..cdaec13cf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c new file mode 100644 index 000000000..02b0d2229 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movd-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovddup-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovddup-1.c new file mode 100644 index 000000000..4db42e137 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovddup-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -mfpmath=sse" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse3-movddup.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovddup-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovddup-256-1.c new file mode 100644 index 000000000..a971dbf4f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovddup-256-1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u, s1; + double e [4]; + + s1.x = _mm256_set_pd (39578.467285, 7856.342941, 85632.783567, 47563.234215); + u.x = _mm256_movedup_pd (s1.x); + + for (i = 0; i < 2; i++) + e[2*i] = e[2*i+1] = s1.a[2*i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqa-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqa-1.c new file mode 100644 index 000000000..b14aeaff9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqa-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movdqa-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqa-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqa-2.c new file mode 100644 index 000000000..94a758d2e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqa-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movdqa-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-1.c new file mode 100644 index 000000000..abe62880e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256i +__attribute__ ((noinline, unused)) +test (__m256i *p) +{ + return _mm256_load_si256 (p); +} + +void static +avx_test (void) +{ + union256i_d u; + int e [8] __attribute__ ((aligned (32))) = {23, 67, 53, 6, 4, 6, 85, 234}; + + u.x = test ((__m256i *)e); + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-2.c new file mode 100644 index 000000000..41f3ed0e6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-2.c @@ -0,0 +1,18 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256i_d u; + int e [8] __attribute__ ((aligned (32))) = {0}; + + u.x = _mm256_set_epi32(23, 67, 53, 6, 4, 6, 85, 234); + _mm256_store_si256 ((__m256i *)e, u.x); + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqu-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqu-1.c new file mode 100644 index 000000000..7785b40ab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqu-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movdqu-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqu-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqu-2.c new file mode 100644 index 000000000..f0eead700 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqu-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movdqu-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-1.c new file mode 100644 index 000000000..849df7bc3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-1.c @@ -0,0 +1,17 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256i_d u; + int e [8] = {23, 67, 53, 6, 4, 6, 85, 234}; + + u.x = _mm256_loadu_si256 ((__m256i *) e); + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-2.c new file mode 100644 index 000000000..eb0af202c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-2.c @@ -0,0 +1,18 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256i_d u; + int e [8] = {0}; + + u.x = _mm256_set_epi32(23, 67, 53, 6, 4, 6, 85, 234); + _mm256_storeu_si256 ((__m256i *)e, u.x); + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhlps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhlps-1.c new file mode 100644 index 000000000..25beca971 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhlps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movhlps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhpd-1.c new file mode 100644 index 000000000..246275cd2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movhpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhpd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhpd-2.c new file mode 100644 index 000000000..1cfdf59c2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhpd-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movhpd-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhps-1.c new file mode 100644 index 000000000..8cf1eec8d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movhps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhps-2.c new file mode 100644 index 000000000..c835f1512 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovhps-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movhps-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovlhps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovlhps-1.c new file mode 100644 index 000000000..8f8234b31 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovlhps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movlhps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovlpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovlpd-1.c new file mode 100644 index 000000000..64d90c6cb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovlpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movlpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovlpd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovlpd-2.c new file mode 100644 index 000000000..081956a9d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovlpd-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movlpd-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-1.c new file mode 100644 index 000000000..07eb85185 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movmskpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-256-1.c new file mode 100644 index 000000000..71353c44d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-256-1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + int d; + union256d s1; + double source[4] = {-45, -3, -34.56, 35}; + int e = 0; + + s1.x = _mm256_loadu_pd (source); + d = _mm256_movemask_pd (s1.x); + + for (i = 0; i < 4; i++) + if (source[i] < 0) + e |= (1 << i); + + if (checkVi (&d, &e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovmskps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovmskps-1.c new file mode 100644 index 000000000..df4d1e78d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovmskps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movmskps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovmskps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovmskps-256-1.c new file mode 100644 index 000000000..4b81d0413 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovmskps-256-1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + int d; + union256 s1; + float source[8] = {-45, -3, -34.56, 35, 5.46,46, -464.3, 56}; + int e = 0; + + s1.x = _mm256_loadu_ps (source); + d = _mm256_movemask_ps (s1.x); + + for (i = 0; i < 8; i++) + if (source[i] < 0) + e |= (1 << i); + + if (checkVi (&d, &e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntdq-1.c new file mode 100644 index 000000000..166d46f20 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntdq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movntdq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntdq-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntdq-256-1.c new file mode 100644 index 000000000..5caf34e6d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntdq-256-1.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static void +__attribute__((noinline)) +test (__m256i *p, __m256i s) +{ + return _mm256_stream_si256 (p, s); +} + +static void +avx_test (void) +{ + union256i_d u; + int e[8] __attribute__ ((aligned(32))) = {1,1,1,1,1,1,1,1}; + + u.x = _mm256_set_epi32 (2434, 6845, 3789, 4683, + 4623, 2236, 8295, 1084); + + test ((__m256i *)e, u.x); + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntdqa-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntdqa-1.c new file mode 100644 index 000000000..c884d1e5e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntdqa-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-movntdqa.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntpd-1.c new file mode 100644 index 000000000..d547a2a9e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntpd-1.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movntpd-1.c" + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntpd-256-1.c new file mode 100644 index 000000000..f17deafaf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntpd-256-1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static void +__attribute__((noinline)) +test (double *p, __m256d s) +{ + return _mm256_stream_pd (p, s); +} + +static void +avx_test (void) +{ + union256d u; + double e[4] __attribute__ ((aligned(32))) = {1,1,1,1}; + + u.x = _mm256_set_pd (2134.3343, 1234.635654, -13443.35, 43.35345); + test (e, u.x); + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntps-1.c new file mode 100644 index 000000000..b9732f26d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movntps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntps-256-1.c new file mode 100644 index 000000000..9f79403f4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovntps-256-1.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static void +__attribute__((noinline)) +test (float *p, __m256 s) +{ + return _mm256_stream_ps (p, s); +} + +static void +avx_test (void) +{ + union256 u; + float e[8] __attribute__ ((aligned(32))); + + u.x = _mm256_set_ps (24.43, 68.346, -43.35, 546.46, + 46.9, -2.78, 82.9, -0.4); + test (e, u.x); + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovq-1.c new file mode 100644 index 000000000..44d202308 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c new file mode 100644 index 000000000..8306d39cc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c @@ -0,0 +1,8 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movq-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c new file mode 100644 index 000000000..a6d624749 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c @@ -0,0 +1,8 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movq-3.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovsd-1.c new file mode 100644 index 000000000..185784419 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovsd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movsd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovsd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovsd-2.c new file mode 100644 index 000000000..672b25bfd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovsd-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movsd-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovshdup-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovshdup-1.c new file mode 100644 index 000000000..ee995e3a7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovshdup-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -mfpmath=sse" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse3-movshdup.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovshdup-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovshdup-256-1.c new file mode 100644 index 000000000..a4b57a0c4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovshdup-256-1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u, s1; + float e[8]; + + s1.x = _mm256_set_ps (134.3, 1234.54, 45.335, 646.456, 43.54, 473.34, 78, 89.54); + u.x = _mm256_movehdup_ps (s1.x); + + for (i = 0; i < 4; i++) + e[2*i] = e[2*i+1] = s1.a[2*i+1]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovsldup-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovsldup-1.c new file mode 100644 index 000000000..67ea717ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovsldup-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -mfpmath=sse" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse3-movsldup.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovsldup-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovsldup-256-1.c new file mode 100644 index 000000000..52127bec2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovsldup-256-1.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u, s1; + float e[8]; + + s1.x = _mm256_set_ps (134.3, 1234.54, 45.335, 646.456, 43.54, 473.34, 78, 89.54); + u.x = _mm256_moveldup_ps (s1.x); + + for (i = 0; i < 4; i++) + e[2*i] = e[2*i+1] = s1.a[2*i]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovss-1.c new file mode 100644 index 000000000..ff983e6b3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovss-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movss-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovss-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovss-2.c new file mode 100644 index 000000000..e9a8bdc59 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovss-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movss-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovss-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovss-3.c new file mode 100644 index 000000000..b73e2af06 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovss-3.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movss-3.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovupd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovupd-1.c new file mode 100644 index 000000000..67f08744a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovupd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movupd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovupd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovupd-2.c new file mode 100644 index 000000000..cb6f27763 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovupd-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-movupd-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-1.c new file mode 100644 index 000000000..8683a78da --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256d +__attribute__((noinline, unused)) +test (double *e) +{ + return _mm256_loadu_pd (e); +} + +void static +avx_test (void) +{ + union256d u; + double e [4] = {41124.234,2344.2354,8653.65635,856.43576}; + + u.x = test (e); + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-2.c new file mode 100644 index 000000000..4cbd0e7e2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static void +__attribute__((noinline, unused)) +test (double *e, __m256d a) +{ + return _mm256_storeu_pd (e, a); +} + +void static +avx_test (void) +{ + union256d u; + double e [4] = {0.0}; + + u.x = _mm256_set_pd (39578.467285, 7856.342941, 85632.783567, 47563.234215); + + test (e, u.x); + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovups-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovups-1.c new file mode 100644 index 000000000..5b9a98b05 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovups-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movups-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovups-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovups-2.c new file mode 100644 index 000000000..e5668a29a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovups-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-movups-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovups-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovups-256-1.c new file mode 100644 index 000000000..87d840998 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovups-256-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static __m256 +__attribute__((noinline, unused)) +test (float *e) +{ + return _mm256_loadu_ps (e); +} + +void static +avx_test (void) +{ + union256 u; + float e [8] = {24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4}; + + u.x = test (e); + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovups-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovups-256-2.c new file mode 100644 index 000000000..c1781979a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmovups-256-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static void +__attribute__((noinline, unused)) +test (float *e, __m256 a) +{ + return _mm256_storeu_ps (e, a); +} + +void static +avx_test (void) +{ + union256 u; + float e [8] = {0.0}; + + u.x = _mm256_set_ps (1.17, 24567.16, 3.15, 4567.14, 5.13, 65467.12, 788.11, 8.9); + + test (e, u.x); + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmpsadbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmpsadbw-1.c new file mode 100644 index 000000000..403423e66 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmpsadbw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-mpsadbw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulpd-1.c new file mode 100644 index 000000000..0fa0f1ad7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-mulpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulpd-256-1.c new file mode 100644 index 000000000..c6d9c4770 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulpd-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576); + u.x = _mm256_mul_pd (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] * s2.a[i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulps-1.c new file mode 100644 index 000000000..bb29e1945 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-mulps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulps-256-1.c new file mode 100644 index 000000000..518a9477d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulps-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4); + s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9); + u.x = _mm256_mul_ps (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i] * s2.a[i]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulsd-1.c new file mode 100644 index 000000000..16adcde80 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulsd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-mulsd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulss-1.c new file mode 100644 index 000000000..9ff6e3d14 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vmulss-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-mulss-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vorpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vorpd-1.c new file mode 100644 index 000000000..221849ff1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vorpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-orpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vorpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vorpd-256-1.c new file mode 100644 index 000000000..ca60e24fc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vorpd-256-1.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u, s1, s2; + + union + { + double d[4]; + long long ll[4]; + }source1, source2, e; + + s1.x = _mm256_set_pd (34545, 95567, 23443, 5675); + s2.x = _mm256_set_pd (674, 57897, 93459, 45624); + + _mm256_storeu_pd (source1.d, s1.x); + _mm256_storeu_pd (source2.d, s2.x); + + u.x = _mm256_or_pd (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e.ll[i] = source1.ll[i] | source2.ll[i]; + + if (check_union256d (u, e.d)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vorps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vorps-1.c new file mode 100644 index 000000000..fd501dd15 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vorps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-orps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vorps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vorps-256-1.c new file mode 100644 index 000000000..ef1c51b1d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vorps-256-1.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + + union256 u, s1, s2; + + union + { + float f[8]; + int i[8]; + }source1, source2, e; + + s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667); + s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608); + + _mm256_storeu_ps (source1.f, s1.x); + _mm256_storeu_ps (source2.f, s2.x); + + u.x = _mm256_or_ps (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e.i[i] = source1.i[i] | source2.i[i]; + + if (check_union256 (u, e.f)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpabsb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpabsb-1.c new file mode 100644 index 000000000..bd5b1fbe9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpabsb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-pabsb.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpabsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpabsd-1.c new file mode 100644 index 000000000..3ea84d808 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpabsd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-pabsd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpabsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpabsw-1.c new file mode 100644 index 000000000..6de79a5b6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpabsw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-pabsw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpackssdw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpackssdw-1.c new file mode 100644 index 000000000..f302ce716 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpackssdw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-packssdw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpacksswb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpacksswb-1.c new file mode 100644 index 000000000..14fd680a5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpacksswb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-packsswb-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpackusdw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpackusdw-1.c new file mode 100644 index 000000000..81991d951 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpackusdw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-packusdw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpackuswb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpackuswb-1.c new file mode 100644 index 000000000..d06f3c779 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpackuswb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-packuswb-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddb-1.c new file mode 100644 index 000000000..fa06c1e30 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-paddb-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddd-1.c new file mode 100644 index 000000000..fc2ee2932 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-paddd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddq-1.c new file mode 100644 index 000000000..bb913be9d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-paddq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddsb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddsb-1.c new file mode 100644 index 000000000..56dc00b73 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddsb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-paddsb-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddsw-1.c new file mode 100644 index 000000000..c326420e6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddsw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-paddsw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddusb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddusb-1.c new file mode 100644 index 000000000..a83bf6b7e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddusb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-paddusb-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddusw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddusw-1.c new file mode 100644 index 000000000..8cbf06092 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddusw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-paddusw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddw-1.c new file mode 100644 index 000000000..caaa46666 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpaddw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-paddw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpalignr-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpalignr-1.c new file mode 100644 index 000000000..1a60b467f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpalignr-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-palignr.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpand-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpand-1.c new file mode 100644 index 000000000..22e05701c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpand-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pand-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpandn-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpandn-1.c new file mode 100644 index 000000000..fbd7e25ed --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpandn-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pandn-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpavgb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpavgb-1.c new file mode 100644 index 000000000..1474d2b1f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpavgb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pavgb-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpavgw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpavgw-1.c new file mode 100644 index 000000000..1c7c3c89d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpavgw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pavgw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpblendvb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpblendvb-1.c new file mode 100644 index 000000000..001799776 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpblendvb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pblendvb.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpblendw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpblendw-1.c new file mode 100644 index 000000000..241dbcc6a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpblendw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pblendw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpclmulqdq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpclmulqdq.c new file mode 100644 index 000000000..9b015abcd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpclmulqdq.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target vpclmul } */ +/* { dg-options "-O2 -mpclmul -mavx" } */ + +#define CHECK_H "pclmul-avx-check.h" +#define TEST pclmul_avx_test + +#include "pclmulqdq.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpeqb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpeqb-1.c new file mode 100644 index 000000000..9cd2bbcc1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpeqb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pcmpeqb-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpeqd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpeqd-1.c new file mode 100644 index 000000000..b1d1dd2d6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpeqd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pcmpeqd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpeqq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpeqq-1.c new file mode 100644 index 000000000..541b52c4b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpeqq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pcmpeqq.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpeqw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpeqw-1.c new file mode 100644 index 000000000..0e0397abd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpeqw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pcmpeqw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-1.c new file mode 100644 index 000000000..806000f9f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_2-pcmpestri-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-2.c new file mode 100644 index 000000000..6d683ef89 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_2-pcmpestri-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-1.c new file mode 100644 index 000000000..95b2bdc0c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_2-pcmpestrm-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-2.c new file mode 100644 index 000000000..b2f6ad33d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_2-pcmpestrm-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpgtb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpgtb-1.c new file mode 100644 index 000000000..ed9fd4d21 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpgtb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pcmpgtb-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpgtd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpgtd-1.c new file mode 100644 index 000000000..344741eef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpgtd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pcmpgtd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpgtq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpgtq-1.c new file mode 100644 index 000000000..1332215a9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpgtq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_2-pcmpgtq.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpgtw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpgtw-1.c new file mode 100644 index 000000000..c4f2007e0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpgtw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pcmpgtw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-1.c new file mode 100644 index 000000000..4cb13535d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_2-pcmpistri-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-2.c new file mode 100644 index 000000000..ec2af713d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_2-pcmpistri-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-1.c new file mode 100644 index 000000000..7a6a4d4d1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_2-pcmpistrm-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-2.c new file mode 100644 index 000000000..82857d813 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_2-pcmpistrm-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-1.c new file mode 100644 index 000000000..99abca189 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-1.c @@ -0,0 +1,63 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#define CONTROL 0xCC + +void static +avx_test (void) +{ + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (1, 2, 3, 4, 5, 6, 7, 8); + s2.x = _mm256_set_ps (9, 10, 11, 12, 13, 14, 15, 16); + u.x = _mm256_permute2f128_ps (s1.x, s2.x, CONTROL); + + switch (CONTROL & 0x3) + { + case 0: + __builtin_memcpy (e, s1.a, 16); + break; + case 1: + __builtin_memcpy (e, s1.a+4, 16); + break; + case 2: + __builtin_memcpy (e, s2.a, 16); + break; + case 3: + __builtin_memcpy (e, s2.a+4, 16); + break; + default: + abort (); + } + + switch ((CONTROL & 0xc)>>2) + { + case 0: + __builtin_memcpy (e+4, s1.a, 16); + break; + case 1: + __builtin_memcpy (e+4, s1.a+4, 16); + break; + case 2: + __builtin_memcpy (e+4, s2.a, 16); + break; + case 3: + __builtin_memcpy (e+4, s2.a+4, 16); + break; + default: + abort (); + } + + if (CONTROL & (1<<3)) + __builtin_memset (e, 0, 16); + + if (CONTROL & (1<<7)) + __builtin_memset (e+4, 0, 16); + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-2.c new file mode 100644 index 000000000..db9c65bce --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-2.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef IMM8 +# define IMM8 99 +#endif + + +void static +avx_test () +{ + union256d source1, source2, u; + double s1[4]={1, 2, 3, 4}; + double s2[4]={5, 6, 7, 8}; + double e[4]; + + source1.x = _mm256_loadu_pd(s1); + source2.x = _mm256_loadu_pd(s2); + u.x = _mm256_permute2f128_pd(source1.x, source2.x, IMM8); + + if(IMM8 & 8) e[0] = e[1] = 0; + else{ + e[0] = (IMM8 & 2 ? s2 : s1)[(IMM8 & 1) * 2]; + e[1] = (IMM8 & 2 ? s2 : s1)[(IMM8 & 1) * 2 + 1]; + } + if(IMM8 & 128) e[3] = e[3] = 0; + else{ + unsigned m = (IMM8 >> 4) & 3; + e[2] = (m & 2 ? s2 : s1)[(m & 1) * 2]; + e[3] = (m & 2 ? s2 : s1)[(m & 1) * 2 + 1]; + } + + if (check_union256d (u, e)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-3.c new file mode 100644 index 000000000..7b00c4b76 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-3.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef IMM8 +# define IMM8 100 +#endif + +void static +avx_test () +{ + union256i_q source1, source2, u; + long long s1[4]={1, 2, 3, 4}; + long long s2[4]={5, 6, 7, 8}; + long long e[4]; + + source1.x = _mm256_loadu_si256((__m256i*)s1); + source2.x = _mm256_loadu_si256((__m256i*)s2); + u.x = _mm256_permute2f128_si256(source1.x, source2.x, IMM8); + + if(IMM8 & 8) e[0] = e[1] = 0; + else{ + e[0] = (IMM8 & 2 ? s2 : s1)[(IMM8 & 1) * 2]; + e[1] = (IMM8 & 2 ? s2 : s1)[(IMM8 & 1) * 2 + 1]; + } + if(IMM8 & 128) e[3] = e[3] = 0; + else{ + unsigned m = (IMM8 >> 4) & 3; + e[2] = (m & 2 ? s2 : s1)[(m & 1) * 2]; + e[3] = (m & 2 ? s2 : s1)[(m & 1) * 2 + 1]; + } + + if (check_union256i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilpd-1.c new file mode 100644 index 000000000..6379cdb4a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilpd-1.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef CTRL +#define CTRL 1 +#endif + +void static +avx_test () +{ + union128d u, src; + double s[2] = {9674.67456, 13543.9788}; + double e[2]; + + src.x=_mm_loadu_pd(s); + u.x=_mm_permute_pd(src.x, CTRL); + + e[0] = s[ (CTRL & 0x01)]; + e[1] = s[((CTRL & 0x02) >> 1)]; + + if (check_union128d (u, e)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilpd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilpd-2.c new file mode 100644 index 000000000..a6d7a0d67 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilpd-2.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef CTRL +#define CTRL 2 +#endif + +#define mask_v(pos) (((CTRL & (1ULL << (pos))) >> (pos)) << 1) + +void static +avx_test () +{ + union128d u, src; + union128i_q ctl; + + double s[2] = {9674.67456, 13543.9788}; + long long m[2] = {mask_v(0), mask_v(1)}; + double e[2]; + + src.x = _mm_loadu_pd(s); + ctl.x = _mm_loadu_si128((__m128i*) m); + u.x = _mm_permutevar_pd(src.x, ctl.x); + + e[0] = s[((m[0] & 0x02) >> 1)]; + e[1] = s[((m[1] & 0x02) >> 1)]; + + if (check_union128d (u, e)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-1.c new file mode 100644 index 000000000..ca93474b5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#define CONTROL 5 + +void static +avx_test (void) +{ + union256d u, s1; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + u.x = _mm256_permute_pd (s1.x, CONTROL); + + e[0] = (CONTROL&0x01) ? s1.a[1] : s1.a[0]; + e[1] = (CONTROL&0x02) ? s1.a[1] : s1.a[0]; + e[2] = (CONTROL&0x04) ? s1.a[3] : s1.a[2]; + e[3] = (CONTROL&0x08) ? s1.a[3] : s1.a[2]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-2.c new file mode 100644 index 000000000..1cd5c3a62 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef CTRL +#define CTRL 6 +#endif + +#define mask_v(pos) (((CTRL & (1ULL << (pos))) >> (pos)) << 1) + +void static +avx_test () +{ + union256d u, src; + union256i_q ctl; + + double s[4] = {39578.467285, 7856.342941, 9674.67456, 13543.9788}; + long long m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)}; + double e[4] = {0.0}; + + src.x = _mm256_loadu_pd(s); + ctl.x = _mm256_loadu_si256((__m256i*) m); + u.x = _mm256_permutevar_pd(src.x, ctl.x); + + e[0] = s[0 + ((m[0] & 0x02) >> 1)]; + e[1] = s[0 + ((m[1] & 0x02) >> 1)]; + e[2] = s[2 + ((m[2] & 0x02) >> 1)]; + e[3] = s[2 + ((m[3] & 0x02) >> 1)]; + + if (check_union256d (u, e)) + abort (); +} + + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilps-1.c new file mode 100644 index 000000000..146f55567 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilps-1.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef CTRL +#define CTRL 11 +#endif + +void static +avx_test () +{ + union128 u, s; + float e[4]; + + s.x = _mm_set_ps (1, 2, 3, 4); + u.x = _mm_permute_ps(s.x, CTRL); + + e[0] = s.a[ (CTRL & 0x03)]; + e[1] = s.a[((CTRL & 0x0c) >> 2)]; + e[2] = s.a[((CTRL & 0x30) >> 4)]; + e[3] = s.a[((CTRL & 0xc0) >> 6)]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilps-2.c new file mode 100644 index 000000000..ca0fbae4a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilps-2.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef CTRL +#define CTRL 233 +#endif + +#define mask_v(pos) ((CTRL & (0x3 << (pos))) >> (pos)) + +void static +avx_test () +{ + union128 u, s; + union128i_q ctl; + int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)}; + float e[4]; + + s.x = _mm_set_ps (1, 2, 3, 4); + ctl.x = _mm_loadu_si128((__m128i*) m); + u.x = _mm_permutevar_ps(s.x, ctl.x); + + e[0] = s.a[0 + (m[0] & 0x03)]; + e[1] = s.a[0 + (m[1] & 0x03)]; + e[2] = s.a[0 + (m[2] & 0x03)]; + e[3] = s.a[0 + (m[3] & 0x03)]; + + if (check_union128 (u, e)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-1.c new file mode 100644 index 000000000..b9291498d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-1.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef CTRL +#define CTRL 129 +#endif + +void static +avx_test () +{ + union256 src, u; + float e[8] = {0.0}; + + src.x = _mm256_set_ps (1, 2, 3, 4, 5, 6, 7, 8); + u.x = _mm256_permute_ps(src.x, CTRL); + + e[0] = src.a[0 + (CTRL & 0x03)]; + e[1] = src.a[0 + ((CTRL & 0x0c) >> 2)]; + e[2] = src.a[0 + ((CTRL & 0x30) >> 4)]; + e[3] = src.a[0 + ((CTRL & 0xc0) >> 6)]; + e[4] = src.a[4 + (CTRL & 0x03)]; + e[5] = src.a[4 + ((CTRL & 0x0c) >> 2)]; + e[6] = src.a[4 + ((CTRL & 0x30) >> 4)]; + e[7] = src.a[4 + ((CTRL & 0xc0) >> 6)]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-2.c new file mode 100644 index 000000000..9890410b4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-2.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef CTRL +#define CTRL 233 +#endif + +#define mask_v(pos) ((CTRL & (0x3 << (pos))) >> (pos)) + +void static +avx_test () +{ + union256 u, s; + union256i_q ctl; + int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)}; + float e[8]; + + s.x = _mm256_set_ps (1, 2, 3, 4, 5, 6, 7, 8); + ctl.x = _mm256_loadu_si256((__m256i*) m); + u.x = _mm256_permutevar_ps(s.x, ctl.x); + + e[0] = s.a[0 + (m[0] & 0x03)]; + e[1] = s.a[0 + (m[1] & 0x03)]; + e[2] = s.a[0 + (m[2] & 0x03)]; + e[3] = s.a[0 + (m[3] & 0x03)]; + e[4] = s.a[4 + (m[4] & 0x03)]; + e[5] = s.a[4 + (m[5] & 0x03)]; + e[6] = s.a[4 + (m[6] & 0x03)]; + e[7] = s.a[4 + (m[7] & 0x03)]; + + if (check_union256 (u, e)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpextrb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpextrb-1.c new file mode 100644 index 000000000..4e1c64428 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpextrb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pextrb.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpextrd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpextrd-1.c new file mode 100644 index 000000000..bc67a2845 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpextrd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pextrd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c new file mode 100644 index 000000000..59e70b2d8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pextrq.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpextrw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpextrw-1.c new file mode 100644 index 000000000..7751ded98 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpextrw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pextrw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphaddd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphaddd-1.c new file mode 100644 index 000000000..d0aee2139 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphaddd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-phaddd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphaddsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphaddsw-1.c new file mode 100644 index 000000000..b58978aeb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphaddsw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-phaddsw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphaddw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphaddw-1.c new file mode 100644 index 000000000..cdf17f694 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphaddw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-phaddw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphminposuw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphminposuw-1.c new file mode 100644 index 000000000..288651c95 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphminposuw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-phminposuw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphminposuw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphminposuw-2.c new file mode 100644 index 000000000..3ae122c7e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphminposuw-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O3 -mavx -mno-avx2" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-phminposuw-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphminposuw-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphminposuw-3.c new file mode 100644 index 000000000..4a37ba542 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphminposuw-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mno-avx2" } */ + +#include "avx-vphminposuw-2.c" + +/* { dg-final { scan-assembler "vphminposuw\[^\n\r\]*xmm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphsubd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphsubd-1.c new file mode 100644 index 000000000..b1be419cb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphsubd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-phsubd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphsubsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphsubsw-1.c new file mode 100644 index 000000000..477523e30 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphsubsw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-phsubsw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphsubw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphsubw-1.c new file mode 100644 index 000000000..55893a672 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vphsubw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-phsubw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpinsrb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpinsrb-1.c new file mode 100644 index 000000000..b3b63581d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpinsrb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pinsrb.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpinsrd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpinsrd-1.c new file mode 100644 index 000000000..69c9bef3c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpinsrd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pinsrd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c new file mode 100644 index 000000000..595fc1baa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pinsrq.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpinsrw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpinsrw-1.c new file mode 100644 index 000000000..5e1a7cb91 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpinsrw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pinsrw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaddubsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaddubsw-1.c new file mode 100644 index 000000000..adc476300 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaddubsw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-pmaddubsw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxsb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxsb-1.c new file mode 100644 index 000000000..74b5a331f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxsb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmaxsb.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxsd-1.c new file mode 100644 index 000000000..832e25e7f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxsd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmaxsd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxsw-1.c new file mode 100644 index 000000000..55e362e69 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxsw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pmaxsw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxub-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxub-1.c new file mode 100644 index 000000000..0f647cbe1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxub-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pmaxub-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxud-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxud-1.c new file mode 100644 index 000000000..afd29dbb4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxud-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmaxud.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxuw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxuw-1.c new file mode 100644 index 000000000..74b4177ca --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmaxuw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmaxuw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminsb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminsb-1.c new file mode 100644 index 000000000..e44ca611f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminsb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pminsb.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminsd-1.c new file mode 100644 index 000000000..54e18ed53 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminsd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pminsd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminsw-1.c new file mode 100644 index 000000000..ce65712f4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminsw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pminsw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminub-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminub-1.c new file mode 100644 index 000000000..d7b77bc62 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminub-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pminub-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminud-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminud-1.c new file mode 100644 index 000000000..bbc069e78 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminud-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pminud.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminuw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminuw-1.c new file mode 100644 index 000000000..9b253555e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpminuw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pminuw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovmskb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovmskb-1.c new file mode 100644 index 000000000..0b3e8aaee --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovmskb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pmovmskb-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxbd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxbd-1.c new file mode 100644 index 000000000..b3a57b044 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxbd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmovsxbd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxbq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxbq-1.c new file mode 100644 index 000000000..a9aba16bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxbq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmovsxbq.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxbw-1.c new file mode 100644 index 000000000..a3f2efe36 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxbw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmovsxbw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxdq-1.c new file mode 100644 index 000000000..6f2940533 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxdq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmovsxdq.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxwd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxwd-1.c new file mode 100644 index 000000000..8e186e382 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxwd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmovsxwd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxwq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxwq-1.c new file mode 100644 index 000000000..90c2d1d5e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovsxwq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmovsxwq.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxbd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxbd-1.c new file mode 100644 index 000000000..3f4556ce8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxbd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmovzxbd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxbq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxbq-1.c new file mode 100644 index 000000000..719c7271e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxbq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmovzxbq.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxbw-1.c new file mode 100644 index 000000000..ad5fe4e7d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxbw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmovzxbw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxdq-1.c new file mode 100644 index 000000000..7490902b8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxdq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmovzxdq.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxwd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxwd-1.c new file mode 100644 index 000000000..5447155d5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxwd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmovzxwd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxwq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxwq-1.c new file mode 100644 index 000000000..b8239f221 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmovzxwq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmovzxwq.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmuldq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmuldq-1.c new file mode 100644 index 000000000..527d3cbdb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmuldq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmuldq.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmulhrsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmulhrsw-1.c new file mode 100644 index 000000000..121252ec6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmulhrsw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-pmulhrsw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmulhuw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmulhuw-1.c new file mode 100644 index 000000000..f3127a9db --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmulhuw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pmulhuw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmulhw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmulhw-1.c new file mode 100644 index 000000000..c36b489c7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmulhw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pmulhw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmulld-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmulld-1.c new file mode 100644 index 000000000..63df55d79 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmulld-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-pmulld.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmullw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmullw-1.c new file mode 100644 index 000000000..649dcad62 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmullw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pmullw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmuludq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmuludq-1.c new file mode 100644 index 000000000..e7c1cebdc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpmuludq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pmuludq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpor-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpor-1.c new file mode 100644 index 000000000..cda694f00 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpor-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-por-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsadbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsadbw-1.c new file mode 100644 index 000000000..6f76c9632 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsadbw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psadbw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpshufb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpshufb-1.c new file mode 100644 index 000000000..5ab106c3f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpshufb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-pshufb.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpshufd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpshufd-1.c new file mode 100644 index 000000000..543bcdfcb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpshufd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pshufd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpshufhw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpshufhw-1.c new file mode 100644 index 000000000..23b79c653 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpshufhw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pshufhw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpshuflw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpshuflw-1.c new file mode 100644 index 000000000..268b5d244 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpshuflw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pshuflw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsignb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsignb-1.c new file mode 100644 index 000000000..9677c6834 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsignb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-psignb.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsignd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsignd-1.c new file mode 100644 index 000000000..84b16b73a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsignd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-psignd.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsignw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsignw-1.c new file mode 100644 index 000000000..daf47e601 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsignw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "ssse3-psignw.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpslld-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpslld-1.c new file mode 100644 index 000000000..778662dbd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpslld-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pslld-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpslld-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpslld-2.c new file mode 100644 index 000000000..12754ed78 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpslld-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pslld-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpslldq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpslldq-1.c new file mode 100644 index 000000000..aea5b7865 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpslldq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pslldq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsllq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsllq-1.c new file mode 100644 index 000000000..37c152649 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsllq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psllq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsllq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsllq-2.c new file mode 100644 index 000000000..0cc298df9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsllq-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psllq-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsllw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsllw-1.c new file mode 100644 index 000000000..ebb610c31 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsllw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psllw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsllw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsllw-2.c new file mode 100644 index 000000000..62a989dc9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsllw-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psllw-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrad-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrad-1.c new file mode 100644 index 000000000..2293c42b5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrad-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psrad-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrad-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrad-2.c new file mode 100644 index 000000000..53f4f09c2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrad-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psrad-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsraw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsraw-1.c new file mode 100644 index 000000000..525163fcc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsraw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psraw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsraw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsraw-2.c new file mode 100644 index 000000000..90c8df0f2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsraw-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psraw-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrld-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrld-1.c new file mode 100644 index 000000000..a143a65c4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrld-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psrld-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrld-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrld-2.c new file mode 100644 index 000000000..e9e1e3f2a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrld-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psrld-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrldq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrldq-1.c new file mode 100644 index 000000000..a8cec081e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrldq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psrldq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrlq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrlq-1.c new file mode 100644 index 000000000..d7a57bff7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrlq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psrlq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrlq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrlq-2.c new file mode 100644 index 000000000..efa870818 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrlq-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psrlq-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrlw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrlw-1.c new file mode 100644 index 000000000..e132c2da1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrlw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psrlw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrlw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrlw-2.c new file mode 100644 index 000000000..ec4a85dce --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsrlw-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psrlw-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubb-1.c new file mode 100644 index 000000000..e66624f22 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psubb-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubd-1.c new file mode 100644 index 000000000..1e9214dbd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psubd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubq-1.c new file mode 100644 index 000000000..b7c22be7c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psubq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubsb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubsb-1.c new file mode 100644 index 000000000..fa71d6112 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubsb-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psubsb-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubsw-1.c new file mode 100644 index 000000000..b3fbad0ed --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubsw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psubsw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubw-1.c new file mode 100644 index 000000000..a83140e19 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpsubw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-psubw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-1.c new file mode 100644 index 000000000..c70752d36 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-ptest-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-2.c new file mode 100644 index 000000000..cb6b5520b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-ptest-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-256-1.c new file mode 100644 index 000000000..ebc2673a4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-256-1.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int s1i[8] = {0, 5463, 86456, 0, 1234, 0, 62445, 34352}; + int s2i[8] = {0, 1223, 0, 0, 0, 1, 0, 0}; + int d; + int e; + int i; + union256i_d s1, s2; + + s1.x = _mm256_loadu_si256 ((__m256i*)s1i); + s2.x = _mm256_loadu_si256 ((__m256i*)s2i); + d = _mm256_testz_si256 (s1.x, s2.x); + + e = 1; + for (i = 0; i < 8; i++) + if ((s1i[i] & s2i[i]) != 0) + e = 0; + + if (d != e) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-256-2.c new file mode 100644 index 000000000..f85344a9a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-256-2.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int s1i[8] = {0, 0, 0, 0, 0, 0, 0, 0}; + int s2i[8] = {1, 2, 3, 4, 5, 6, 7, 8}; + int d; + int e; + int i; + union256i_d s1, s2; + + s1.x = _mm256_loadu_si256 ((__m256i*)s1i); + s2.x = _mm256_loadu_si256 ((__m256i*)s2i); + d = _mm256_testc_si256 (s1.x, s2.x); + + e = 1; + for (i = 0; i < 8; i++) + if ((~s1i[i] & s2i[i]) != 0) + e = 0; + + if (d != e) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-256-3.c new file mode 100644 index 000000000..cccbbef4e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-256-3.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int s1i[8] = {0, 0, 0, 0, 0, 0, 0, 0}; + int s2i[8] = {1, 2, 3, 4, 5, 6, 7, 8}; + int d; + int c = 1, z = 1, e = 0xf; + int i; + union256i_d s1, s2; + + s1.x = _mm256_loadu_si256 ((__m256i*)s1i); + s2.x = _mm256_loadu_si256 ((__m256i*)s2i); + d = _mm256_testnzc_si256 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + if ((s1.a[i] & s2.a[i])) + z = 0; + if ((~s1.a[i] & s2.a[i])) + c = 0; + } + + e = (z == 0 && c == 0) ? 1 : 0; + + if (d != e) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-3.c new file mode 100644 index 000000000..1b875a75f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vptest-3.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-ptest-3.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckhbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckhbw-1.c new file mode 100644 index 000000000..3c76aa3f1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckhbw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-punpckhbw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckhdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckhdq-1.c new file mode 100644 index 000000000..a853d7014 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckhdq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-punpckhdq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckhqdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckhqdq-1.c new file mode 100644 index 000000000..8b86c7649 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckhqdq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-punpckhqdq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckhwd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckhwd-1.c new file mode 100644 index 000000000..0e4e051d4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckhwd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-punpckhwd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpcklbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpcklbw-1.c new file mode 100644 index 000000000..ad856cf6a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpcklbw-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-punpcklbw-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckldq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckldq-1.c new file mode 100644 index 000000000..2acd87929 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpckldq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-punpckldq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpcklqdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpcklqdq-1.c new file mode 100644 index 000000000..bd378a34f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpcklqdq-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-punpcklqdq-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpcklwd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpcklwd-1.c new file mode 100644 index 000000000..07f2be177 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpunpcklwd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-punpcklwd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpxor-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpxor-1.c new file mode 100644 index 000000000..dfc46537b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vpxor-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-pxor-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vrcpps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vrcpps-1.c new file mode 100644 index 000000000..45673de43 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vrcpps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-rcpps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vrcpps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vrcpps-256-1.c new file mode 100644 index 000000000..16b3051b0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vrcpps-256-1.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union256 u, s1; + float e[8] = {0.0}; + + s1.x = _mm256_set_ps (1.0, 2.0, 13.0, 14.0, 56.89, 73.3, 4.78, 45.64); + u.x = _mm256_rcp_ps (s1.x); + + for (i = 0; i < 8; i++) { + __m128 tmp = _mm_load_ss (&s1.a[i]); + tmp = _mm_rcp_ss (tmp); + _mm_store_ss (&e[i], tmp); + } + + if (check_union256 (u, e)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-1.c new file mode 100644 index 000000000..c8b0ec1ef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-roundpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-2.c new file mode 100644 index 000000000..e29ac5562 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-roundpd-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-1.c new file mode 100644 index 000000000..71da7523a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-1.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#define iRoundMode 0x7 + +void static +avx_test (void) +{ + union256d u, s1; + double source [4] = {2134.3343,1234.635654,453.345635,54646.464356}; + double e[4] = {0.0}; + int i; + + s1.x = _mm256_loadu_pd (source); + u.x = _mm256_round_pd (s1.x, iRoundMode); + + for (i = 0; i < 4; i++) + { + __m128d tmp = _mm_load_sd (&s1.a[i]); + tmp = _mm_round_sd (tmp, tmp, iRoundMode); + _mm_store_sd (&e[i], tmp); + } + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-2.c new file mode 100644 index 000000000..a61d7730c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-2.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256d u, s1; + double source [4] = {2134.3343,1234.635654,453.345635,54646.464356}; + double e[4] = {0.0}; + int i; + + s1.x = _mm256_loadu_pd (source); + u.x = _mm256_floor_pd (s1.x); + + for (i = 0; i < 4; i++) + { + __m128d tmp = _mm_load_sd (&s1.a[i]); + tmp = _mm_floor_sd (tmp, tmp); + _mm_store_sd (&e[i], tmp); + } + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-3.c new file mode 100644 index 000000000..f4f3e77dd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-3.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256d u, s1; + double source [4] = {2134.3343,1234.635654,453.345635,54646.464356}; + double e[4] = {0.0}; + int i; + + s1.x = _mm256_loadu_pd (source); + u.x = _mm256_ceil_pd (s1.x); + + for (i = 0; i < 4; i++) + { + __m128d tmp = _mm_load_sd (&s1.a[i]); + tmp = _mm_ceil_sd (tmp, tmp); + _mm_store_sd (&e[i], tmp); + } + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-3.c new file mode 100644 index 000000000..6d9326f6a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundpd-3.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse4_1-roundpd-3.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundps-256-1.c new file mode 100644 index 000000000..d33248e24 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vroundps-256-1.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256 u, s1; + float source [8] = {2134.3343,1234.635654,453.345635,54646.464356,895833.346347,56343,234234.34563,2345434.67832}; + float e [8] = {2134.0,1234.0,453.0,54646.0,895833.0,56343,234234.0,2345434.0}; + + s1.x = _mm256_loadu_ps (source); + u.x = _mm256_round_ps (s1.x, 1); + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-1.c new file mode 100644 index 000000000..2db1650dd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-rsqrtps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-256-1.c new file mode 100644 index 000000000..19a933c5d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-256-1.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union256 u, s1; + float e[8] = {0.0}; + + s1.x = _mm256_set_ps (1.0, 2.0, 13.0, 14.0, 56.89, 73.3, 4.78, 45.64); + u.x = _mm256_rsqrt_ps (s1.x); + + for (i = 0; i < 8; i++) { + __m128 tmp = _mm_load_ss (&s1.a[i]); + tmp = _mm_rsqrt_ss (tmp); + _mm_store_ss (&e[i], tmp); + } + + if (check_union256 (u, e)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vshufpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vshufpd-1.c new file mode 100644 index 000000000..a6f00ea8b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vshufpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-shufpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vshufpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vshufpd-256-1.c new file mode 100644 index 000000000..828f6804f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vshufpd-256-1.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 10 +#endif + +void static +avx_test (void) +{ + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576); + u.x = _mm256_shuffle_pd (s1.x, s2.x, MASK); + + e[0] = (MASK & (1 << 0)) ? s1.a[1] : s1.a[0]; + e[1] = (MASK & (1 << 1)) ? s2.a[1] : s2.a[0]; + e[2] = (MASK & (1 << 2)) ? s1.a[3] : s1.a[2]; + e[3] = (MASK & (1 << 3)) ? s2.a[3] : s2.a[2]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vshufps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vshufps-1.c new file mode 100644 index 000000000..97d85706d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vshufps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-shufps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vshufps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vshufps-256-1.c new file mode 100644 index 000000000..f939357d4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vshufps-256-1.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +#ifndef MASK +#define MASK 203 +#endif + +float select4(const float *src, unsigned int control) +{ + switch(control) { + case 0: + return src[0]; + case 1: + return src[1]; + case 2: + return src[2]; + case 3: + return src[3]; + } + return -1; +} + + +void static +avx_test (void) +{ + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8); + s2.x = _mm256_set_ps (2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8); + u.x = _mm256_shuffle_ps (s1.x, s2.x, MASK); + + + e[0] = select4(s1.a, (MASK >> 0) & 0x3); + e[1] = select4(s1.a, (MASK >> 2) & 0x3); + e[2] = select4(s2.a, (MASK >> 4) & 0x3); + e[3] = select4(s2.a, (MASK >> 6) & 0x3); + e[4] = select4(s1.a+4, (MASK >> 0) & 0x3); + e[5] = select4(s1.a+4, (MASK >> 2) & 0x3); + e[6] = select4(s2.a+4, (MASK >> 4) & 0x3); + e[7] = select4(s2.a+4, (MASK >> 6) & 0x3); + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-1.c new file mode 100644 index 000000000..dc098c910 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-sqrtpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-256-1.c new file mode 100644 index 000000000..d611bbd12 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-256-1.c @@ -0,0 +1,18 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256d u, s1; + double e [4] = {0x1.d3881b2c32ed7p+7, 0x1.54abaed51711cp+4, 0x1.19195c08a8d23p+5, 0x1.719741d6c0b0bp+5}; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + u.x = _mm256_sqrt_pd (s1.x); + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsqrtps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsqrtps-1.c new file mode 100644 index 000000000..deb88947f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsqrtps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-sqrtps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsqrtps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsqrtps-256-1.c new file mode 100644 index 000000000..d5cd77f5d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsqrtps-256-1.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256 u, s1; + float e[8] = {0x1.7edeccp+10, 0x1.e3fa46p+8, 0x1.dabbcep+7, 0x1.d93e0cp+9,\ + 0x1.d3881cp+7, 0x1.54abbp+4, 0x1.19195cp+5, 0x1.719742p+5}; + + s1.x = _mm256_set_ps (2134.3343,1234.635654,453.345635,54646.464356, \ + 895833.346347,56343,234234.34563,2345434.67832); + u.x = _mm256_sqrt_ps (s1.x); + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubpd-1.c new file mode 100644 index 000000000..2af33fc6a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-subpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubpd-256-1.c new file mode 100644 index 000000000..ce4ddcaa1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubpd-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576); + u.x = _mm256_sub_pd (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] - s2.a[i]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubps-1.c new file mode 100644 index 000000000..59aa92847 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-subps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubps-256-1.c new file mode 100644 index 000000000..de4337cb6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubps-256-1.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + int i; + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4); + s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9); + u.x = _mm256_sub_ps (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i] - s2.a[i]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubsd-1.c new file mode 100644 index 000000000..58cf4cb32 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubsd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-subsd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubss-1.c new file mode 100644 index 000000000..719aa6f15 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vsubss-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-subss-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-1.c new file mode 100644 index 000000000..6b52d786b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */ +/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */ +/* { dg-message " from " "include chain" { target default_packed } 0 } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union128d source1, source2; + + double s1[2] = {30, -5463}; + double s2[2] = {20, 1223}; + int d[1]; + int e[1]; + + source1.x = _mm_loadu_pd(s1); + source2.x = _mm_loadu_pd(s2); + + d[0] = _mm_testz_pd(source1.x, source2.x); + + e[0] = 1; + for (i = 0; i < 2; i++) + { + union ieee754_double u1, u2; + u1.d = s1[i]; + u2.d = s2[i]; + if (u1.bits.sign && u2.bits.sign) { + e[0] = 0; + } + } + + if (checkVi(d, e, 1)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-2.c new file mode 100644 index 000000000..57dfeeb7d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-2.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */ +/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */ +/* { dg-message " from " "include chain" { target default_packed } 0 } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union128d source1, source2; + + double s1[2] = {0, -5463}; + double s2[2] = {0, -1223}; + int d[1]; + int e[1]; + + source1.x = _mm_loadu_pd(s1); + source2.x = _mm_loadu_pd(s2); + + d[0] = _mm_testc_pd(source1.x, source2.x); + + e[0] = 1; + for (i = 0; i < 2; i++) { + union ieee754_double u1, u2; + u1.d = s1[i]; + u2.d = s2[i]; + if (!u1.bits.sign && u2.bits.sign) + e[0] = 0; + } + + if (checkVi(d, e, 1)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-1.c new file mode 100644 index 000000000..050f140f7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-1.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */ +/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */ +/* { dg-message " from " "include chain" { target default_packed } 0 } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union256d source1, source2; + + double s1[4] = {0, -5463, 86456, 0}; + double s2[4] = {0, -1223, 0, 1}; + int d[1]; + int e[1]; + + source1.x = _mm256_loadu_pd(s1); + source2.x = _mm256_loadu_pd(s2); + d[0] = _mm256_testz_pd(source1.x, source2.x); + + e[0] = 1; + for (i = 0; i < 4; i++) { + union ieee754_double u1, u2; + u1.d = s1[i]; + u2.d = s2[i]; + if (u1.bits.sign && u2.bits.sign) { + e[0] = 0; + } + } + + if (checkVi(d, e, 1)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-2.c new file mode 100644 index 000000000..0954f1dd8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-2.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */ +/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */ +/* { dg-message " from " "include chain" { target default_packed } 0 } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union256d source1, source2; + + double s1[4] = {0, -5463, 86456, 0}; + double s2[4] = {0, -1223, 0, 1}; + int d[1]; + int e[1]; + + source1.x = _mm256_loadu_pd(s1); + source2.x = _mm256_loadu_pd(s2); + d[0] = _mm256_testc_pd(source1.x, source2.x); + + e[0] = 1; + for (i = 0; i < 4; i++) { + union ieee754_double u1, u2; + u1.d = s1[i]; + u2.d = s2[i]; + if (!u1.bits.sign && u2.bits.sign) { + e[0] = 0; + } + } + + if (checkVi(d, e, 1)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-3.c new file mode 100644 index 000000000..8a6e32e41 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-3.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */ +/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */ +/* { dg-message " from " "include chain" { target default_packed } 0 } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union256d source1, source2; + + double s1[4] = {0, -5463, 86456, 0}; + double s2[4] = {0, -1223, 0, 1}; + int d[1]; + int e[1]; + int c=1; + int z=1; + + source1.x = _mm256_loadu_pd(s1); + source2.x = _mm256_loadu_pd(s2); + d[0] = _mm256_testnzc_pd(source1.x, source2.x); + + e[0] = 1; + for (i = 0; i < 4; i++) { + union ieee754_double u1, u2; + u1.d = s1[i]; + u2.d = s2[i]; + if (u1.bits.sign && u2.bits.sign) + z = 0; + + if (!u1.bits.sign && u2.bits.sign) + c = 0; + } + e[0] = (c==0 && z==0) ? 1:0; + + if (checkVi(d, e, 1)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-3.c new file mode 100644 index 000000000..74c5dc868 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestpd-3.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */ +/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */ +/* { dg-message " from " "include chain" { target default_packed } 0 } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union128d source1, source2; + + double s1[2] = {0, -5463}; + double s2[2] = {0, -1223}; + int d[1]; + int e[1]; + int c = 1; + int z = 1; + + source1.x = _mm_loadu_pd(s1); + source2.x = _mm_loadu_pd(s2); + + d[0] = _mm_testnzc_pd(source1.x, source2.x); + + e[0] = 1; + for (i = 0; i < 2; i++) { + union ieee754_double u1, u2; + u1.d = s1[i]; + u2.d = s2[i]; + if (u1.bits.sign && u2.bits.sign) + z = 0; + if (!u1.bits.sign && u2.bits.sign) + c = 0; + + } + + e[0] = (c==0 && z==0) ? 1:0; + + if (checkVi(d, e, 1)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-1.c new file mode 100644 index 000000000..fb0c802fb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-1.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */ +/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */ +/* { dg-message " from " "include chain" { target default_packed } 0 } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union128 source1, source2; + float s1[4] = {0, -5463, 86456, 0}; + float s2[4] = {0, -1223, 0, 0}; + int d[1]; + int e[1]; + + source1.x = _mm_loadu_ps(s1); + source2.x = _mm_loadu_ps(s2); + d[0] = _mm_testz_ps(source1.x, source2.x); + + e[0] = 1; + for (i = 0; i < 4; i++) { + union ieee754_float u1, u2; + u1.d = s1[i]; + u2.d = s2[i]; + if (u1.bits.sign && u2.bits.sign) + e[0] = 0; + } + + if (checkVi (d, e, 1)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-2.c new file mode 100644 index 000000000..7482dae4e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-2.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */ +/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */ +/* { dg-message " from " "include chain" { target default_packed } 0 } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union128 source1, source2; + float s1[4] = {0, -5463, 86456, 0}; + float s2[4] = {0, -1223, 0, 0}; + int d[1]; + int e[1]; + + source1.x = _mm_loadu_ps(s1); + source2.x = _mm_loadu_ps(s2); + d[0] = _mm_testc_ps(source1.x, source2.x); + + e[0] = 1; + for (i = 0; i < 4; i++) { + union ieee754_float u1, u2; + u1.d = s1[i]; + u2.d = s2[i]; + if (!u1.bits.sign && u2.bits.sign) + e[0] = 0; + } + + if (checkVi (d, e, 1)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-256-1.c new file mode 100644 index 000000000..6362c4183 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-256-1.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */ +/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */ +/* { dg-message " from " "include chain" { target default_packed } 0 } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union256 source1, source2; + + float s1[8] = {0, -5463, 86456, 0, 1234, 0, 62445, 34352}; + float s2[8] = {0, -1223, 0, 0, 0, 1, 0, 0}; + int d[1]; + int e[1]; + + source1.x = _mm256_loadu_ps(s1); + source2.x = _mm256_loadu_ps(s2); + d[0] = _mm256_testz_ps(source1.x, source2.x); + + e[0] = 1; + for (i = 0; i < 8; i++) { + union ieee754_float u1, u2; + u1.d = s1[i]; + u2.d = s2[i]; + if (u1.bits.sign && u2.bits.sign) + e[0] = 0; + } + + if (checkVi (d, e, 1)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-256-2.c new file mode 100644 index 000000000..de23ab2e9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-256-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */ +/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */ +/* { dg-message " from " "include chain" { target default_packed } 0 } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union256 source1, source2; + + float s1[8] = {0, -5463, 86456, 0, 1234, 0, 62445, 34352}; + float s2[8] = {0, -1223, 0, 0, 0, 1, 0, 0}; + int d[1]; + int e[1]; + + source1.x = _mm256_loadu_ps(s1); + source2.x = _mm256_loadu_ps(s2); + d[0] = _mm256_testc_ps(source1.x, source2.x); + + e[0] = 1; + for (i = 0; i < 8; i++) { + union ieee754_float u1, u2; + u1.d = s1[i]; + u2.d = s2[i]; + if (!u1.bits.sign && u2.bits.sign) + e[0] = 0; + } + + if (checkVi (d, e, 1)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-256-3.c new file mode 100644 index 000000000..717e5bb28 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-256-3.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */ +/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */ +/* { dg-message " from " "include chain" { target default_packed } 0 } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union256 source1, source2; + int c = 1; + int z = 1; + + float s1[8] = {0, -5463, 86456, 0, 1234, 0, 62445, 34352}; + float s2[8] = {0, -1223, 0, 0, 0, 1, 0, 0}; + int d[1]; + int e[1]; + + source1.x = _mm256_loadu_ps(s1); + source2.x = _mm256_loadu_ps(s2); + d[0] = _mm256_testnzc_ps(source1.x, source2.x); + + e[0] = 1; + for (i = 0; i < 8; i++) { + union ieee754_float u1, u2; + u1.d = s1[i]; + u2.d = s2[i]; + if (!u1.bits.sign && u2.bits.sign) + c = 0; + if (u1.bits.sign && u2.bits.sign) + z = 0; + } + e[0] = (c==0 && z==0)?1:0; + + if (checkVi (d, e, 1)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-3.c new file mode 100644 index 000000000..61f58a6b3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vtestps-3.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */ +/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */ +/* { dg-message " from " "include chain" { target default_packed } 0 } */ + +#include "avx-check.h" + +static void +avx_test () +{ + int i; + union128 source1, source2; + float s1[4] = {0, -5463, 86456, 0}; + float s2[4] = {0, -1223, 0, 0}; + int d[1]; + int e[1]; + int c=1; + int z=1; + + source1.x = _mm_loadu_ps(s1); + source2.x = _mm_loadu_ps(s2); + d[0] = _mm_testnzc_ps(source1.x, source2.x); + + e[0] = 1; + for (i = 0; i < 4; i++) { + union ieee754_float u1, u2; + u1.d = s1[i]; + u2.d = s2[i]; + if (!u1.bits.sign && u2.bits.sign) + c = 0; + if (u1.bits.sign && u2.bits.sign) + z = 0; + + } + e[0] = (c == 0 && z == 0) ? 1:0; + + if (checkVi (d, e, 1)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-1.c new file mode 100644 index 000000000..d4efd212d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-ucomisd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-2.c new file mode 100644 index 000000000..d55f31007 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-ucomisd-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-3.c new file mode 100644 index 000000000..e2ba869ff --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-3.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-ucomisd-3.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-4.c new file mode 100644 index 000000000..961759909 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-4.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-ucomisd-4.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-5.c new file mode 100644 index 000000000..9034519af --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-5.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-ucomisd-5.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-6.c new file mode 100644 index 000000000..cc9d0e925 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomisd-6.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-ucomisd-6.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-1.c new file mode 100644 index 000000000..c0ba7a3a6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-ucomiss-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-2.c new file mode 100644 index 000000000..ea4b80e10 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-ucomiss-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-3.c new file mode 100644 index 000000000..bd82bb92a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-3.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-ucomiss-3.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-4.c new file mode 100644 index 000000000..a58395a12 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-4.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-ucomiss-4.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-5.c new file mode 100644 index 000000000..198933cd5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-5.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-ucomiss-5.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-6.c new file mode 100644 index 000000000..db48b7a30 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vucomiss-6.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-ucomiss-6.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-1.c new file mode 100644 index 000000000..4b7191ce0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-unpckhpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-256-1.c new file mode 100644 index 000000000..5da332d45 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-256-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576); + u.x = _mm256_unpackhi_pd (s1.x, s2.x); + + e[0] = s1.a[1]; + e[1] = s2.a[1]; + e[2] = s1.a[3]; + e[3] = s2.a[3]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpckhps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpckhps-1.c new file mode 100644 index 000000000..e5a0f3e1e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpckhps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-unpckhps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpckhps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpckhps-256-1.c new file mode 100644 index 000000000..be6fbb6f9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpckhps-256-1.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4); + s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9); + u.x = _mm256_unpackhi_ps (s1.x, s2.x); + + e[0] = s1.a[2]; + e[1] = s2.a[2]; + e[2] = s1.a[3]; + e[3] = s2.a[3]; + e[4] = s1.a[6]; + e[5] = s2.a[6]; + e[6] = s1.a[7]; + e[7] = s2.a[7]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-1.c new file mode 100644 index 000000000..9e0cb05ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-unpcklpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-256-1.c new file mode 100644 index 000000000..0f7e390cf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-256-1.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256d u, s1, s2; + double e [4]; + + s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356); + s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576); + u.x = _mm256_unpacklo_pd (s1.x, s2.x); + + e[0] = s1.a[0]; + e[1] = s2.a[0]; + e[2] = s1.a[2]; + e[3] = s2.a[2]; + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpcklps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpcklps-1.c new file mode 100644 index 000000000..c2380a47e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpcklps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mfpmath=sse -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-unpcklps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpcklps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpcklps-256-1.c new file mode 100644 index 000000000..bf0e31892 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vunpcklps-256-1.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union256 u, s1, s2; + float e [8]; + + s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4); + s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9); + u.x = _mm256_unpacklo_ps (s1.x, s2.x); + + e[0] = s1.a[0]; + e[1] = s2.a[0]; + e[2] = s1.a[1]; + e[3] = s2.a[1]; + e[4] = s1.a[4]; + e[5] = s2.a[4]; + e[6] = s1.a[5]; + e[7] = s2.a[5]; + + if (check_union256 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vxorpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vxorpd-1.c new file mode 100644 index 000000000..435bf042a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vxorpd-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse2-xorpd-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vxorpd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vxorpd-256-1.c new file mode 100644 index 000000000..4896ee01e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vxorpd-256-1.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union + { + double d[4]; + long long l[4]; + }source1, source2, e; + + int i; + union256d u, s1, s2; + + s1.x = _mm256_set_pd (34545.123, 95567.456, 23443.09876, 5675.543); + s2.x = _mm256_set_pd (674, 57897.332187, 93459, 45624.112); + _mm256_storeu_pd (source1.d, s1.x); + _mm256_storeu_pd (source2.d, s2.x); + + u.x = _mm256_xor_pd (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e.l[i] = source1.l[i] ^ source2.l[i]; + + if (check_union256d (u, e.d)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vxorps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vxorps-1.c new file mode 100644 index 000000000..e203a7f57 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vxorps-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#define CHECK_H "avx-check.h" +#define TEST avx_test + +#include "sse-xorps-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vxorps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vxorps-256-1.c new file mode 100644 index 000000000..007704846 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vxorps-256-1.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +void static +avx_test (void) +{ + union { + float f[8]; + int i[8]; + }source1, source2, e; + + int i; + union256 u, s1, s2; + + s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667); + s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608); + + _mm256_storeu_ps (source1.f, s1.x); + _mm256_storeu_ps (source2.f, s2.x); + + u.x = _mm256_xor_ps (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e.i[i] = source1.i[i] ^ source2.i[i]; + + if (check_union256 (u, e.f)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroall-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroall-1.c new file mode 100644 index 000000000..996357a7e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroall-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static void +avx_test (void) +{ + __m256i src; +#ifdef __x86_64__ + char reg_save[16][32]; + char d[16][32]; +#else + char reg_save[8][32]; + char d[8][32]; +#endif + + int s[8] = {1, 2, 3, 4, 5, 6, 7, 8}; + + __builtin_memset (d, 0, sizeof d); + __builtin_memset (reg_save, -1, sizeof reg_save); + + src = _mm256_loadu_si256 ((__m256i*) s); + + _mm256_zeroall (); + + __asm__ __volatile__ ("vmovdqu %%ymm0,%0":"=m"(reg_save[0])); + __asm__ __volatile__ ("vmovdqu %%ymm1,%0":"=m"(reg_save[1])); + __asm__ __volatile__ ("vmovdqu %%ymm2,%0":"=m"(reg_save[2])); + __asm__ __volatile__ ("vmovdqu %%ymm3,%0":"=m"(reg_save[3])); + __asm__ __volatile__ ("vmovdqu %%ymm4,%0":"=m"(reg_save[4])); + __asm__ __volatile__ ("vmovdqu %%ymm5,%0":"=m"(reg_save[5])); + __asm__ __volatile__ ("vmovdqu %%ymm6,%0":"=m"(reg_save[6])); + __asm__ __volatile__ ("vmovdqu %%ymm7,%0":"=m"(reg_save[7])); +#ifdef __x86_64__ + __asm__ __volatile__ ("vmovdqu %%ymm8,%0":"=m"(reg_save[8])); + __asm__ __volatile__ ("vmovdqu %%ymm9,%0":"=m"(reg_save[9])); + __asm__ __volatile__ ("vmovdqu %%ymm10,%0":"=m"(reg_save[10])); + __asm__ __volatile__ ("vmovdqu %%ymm11,%0":"=m"(reg_save[11])); + __asm__ __volatile__ ("vmovdqu %%ymm12,%0":"=m"(reg_save[12])); + __asm__ __volatile__ ("vmovdqu %%ymm13,%0":"=m"(reg_save[13])); + __asm__ __volatile__ ("vmovdqu %%ymm14,%0":"=m"(reg_save[14])); + __asm__ __volatile__ ("vmovdqu %%ymm15,%0":"=m"(reg_save[15])); +#endif + + if (__builtin_memcmp (reg_save, d, sizeof d)) + abort (); + + _mm256_storeu_si256 ((__m256i*) d, src); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroall-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroall-2.c new file mode 100644 index 000000000..f49a0da42 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroall-2.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx" } */ + +#include "avx-check.h" + +static int s[4] = {234566, 8723467, 6576856, 19832468}; +static int d[4] = {1,1,1,1}; + +static void +avx_test (void) +{ + __m128i src; + + src = _mm_loadu_si128 ((__m128i*) s); + _mm256_zeroall (); + _mm_storeu_si128 ((__m128i*) d, src); + + if (__builtin_memcmp (d, s, sizeof (d))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-1.c new file mode 100644 index 000000000..73ce795f3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-1.c @@ -0,0 +1,56 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -mtune=generic" } */ + +#include "avx-check.h" + +#ifdef __x86_64__ +#define LEN 16 +#else +#define LEN 8 +#endif + +static void +avx_test (void) +{ + __m256i src; + + char reg_save[LEN][32]; + int i, j; + + int s[8] = {1, 2, 3, 4, 5, 6, 7, 8}; + int d[8] = {11, 22, 33, 44, 55, 66, 77, 88}; + + __builtin_memset (reg_save, -1, sizeof reg_save); + + src = _mm256_loadu_si256 ((__m256i*) s); + + _mm256_zeroupper (); + + __asm__ __volatile__ ("vmovdqu %%ymm0,%0":"=m"(reg_save[0])); + __asm__ __volatile__ ("vmovdqu %%ymm1,%0":"=m"(reg_save[1])); + __asm__ __volatile__ ("vmovdqu %%ymm2,%0":"=m"(reg_save[2])); + __asm__ __volatile__ ("vmovdqu %%ymm3,%0":"=m"(reg_save[3])); + __asm__ __volatile__ ("vmovdqu %%ymm4,%0":"=m"(reg_save[4])); + __asm__ __volatile__ ("vmovdqu %%ymm5,%0":"=m"(reg_save[5])); + __asm__ __volatile__ ("vmovdqu %%ymm6,%0":"=m"(reg_save[6])); + __asm__ __volatile__ ("vmovdqu %%ymm7,%0":"=m"(reg_save[7])); +#ifdef __x86_64__ + __asm__ __volatile__ ("vmovdqu %%ymm8,%0":"=m"(reg_save[8])); + __asm__ __volatile__ ("vmovdqu %%ymm9,%0":"=m"(reg_save[9])); + __asm__ __volatile__ ("vmovdqu %%ymm10,%0":"=m"(reg_save[10])); + __asm__ __volatile__ ("vmovdqu %%ymm11,%0":"=m"(reg_save[11])); + __asm__ __volatile__ ("vmovdqu %%ymm12,%0":"=m"(reg_save[12])); + __asm__ __volatile__ ("vmovdqu %%ymm13,%0":"=m"(reg_save[13])); + __asm__ __volatile__ ("vmovdqu %%ymm14,%0":"=m"(reg_save[14])); + __asm__ __volatile__ ("vmovdqu %%ymm15,%0":"=m"(reg_save[15])); +#endif + + for (i = 0; i < LEN; i++) + for (j = 16; j < 32; j++) + if (reg_save[i][j]) + abort (); + + _mm256_storeu_si256 ((__m256i*) d, src); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-10.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-10.c new file mode 100644 index 000000000..5007753a0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-10.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */ + +#include <immintrin.h> + +extern float x, y; + +void +foo () +{ + x = y; + _mm256_zeroupper (); + _mm256_zeroupper (); + _mm256_zeroupper (); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 3 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-11.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-11.c new file mode 100644 index 000000000..507f94543 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-11.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */ + +#include <immintrin.h> + +extern float x, y; + +void +foo () +{ + x = y; + _mm256_zeroall (); + _mm256_zeroupper (); + _mm256_zeroupper (); + _mm256_zeroupper (); +} + +/* { dg-final { scan-assembler-times "\\*avx_vzeroall" 1 } } */ +/* { dg-final { scan-assembler-times "avx_vzeroupper" 3 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c new file mode 100644 index 000000000..e694d4048 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */ + +#include <immintrin.h> + +extern __m256 x, y; + +void +foo () +{ + _mm256_zeroall (); + _mm256_zeroupper (); + x = y; + _mm256_zeroupper (); + _mm256_zeroupper (); + _mm256_zeroupper (); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 } } */ +/* { dg-final { scan-assembler-times "\\*avx_vzeroall" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-13.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-13.c new file mode 100644 index 000000000..cff5f8878 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-13.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx -mno-vzeroupper -dp" } */ + +#include <immintrin.h> + +extern __m256 x, y; + +void +foo () +{ + x = y; +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-14.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-14.c new file mode 100644 index 000000000..a31b4a2a6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-14.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mtune=generic -dp" } */ + +#include <immintrin.h> + +extern __m256 x, y; + +void +foo () +{ + x = y; +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-15.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-15.c new file mode 100644 index 000000000..803936eef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-15.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mtune=generic -dp" } */ + +#include <immintrin.h> + +extern __m256 x, y; +extern void (*bar) (void); + +void +foo () +{ + x = y; + bar (); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c new file mode 100644 index 000000000..bc6e0d23c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mavx -mabi=ms -mtune=generic -dp" } */ + +typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__)); + +extern __m256 x; + +extern __m256 __attribute__ ((sysv_abi)) bar (__m256); + +void +foo (void) +{ + bar (x); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ +/* { dg-final { scan-assembler-times "\\*call_value_rex64_ms_sysv" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c new file mode 100644 index 000000000..5d3aa4839 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mavx -mabi=ms -mtune=generic -dp" } */ + +typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__)); + +extern __m256 x; + +extern __m256 __attribute__ ((sysv_abi)) (*bar) (__m256); + +void +foo (void) +{ + bar (x); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ +/* { dg-final { scan-assembler-times "\\*call_value_rex64_ms_sysv" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c new file mode 100644 index 000000000..06307525d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O0 -mavx -mabi=ms -mtune=generic -dp" } */ + +typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__)); + +extern __m256 x; + +extern void __attribute__ ((sysv_abi)) bar (__m256); + +void +foo (void) +{ + bar (x); +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ +/* { dg-final { scan-assembler-times "\\*call_rex64_ms_sysv" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c new file mode 100644 index 000000000..ae2f8611e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mtune=generic -dp" } */ + +void feat_s3_cep_dcep (int cepsize_used, float **mfc, float **feat) +{ + float *f; + float *w, *_w; + int i; + __builtin_memcpy (feat[0], mfc[0], cepsize_used * sizeof(float)); + f = feat[0] + cepsize_used; + w = mfc[2]; + _w = mfc[-2]; + for (i = 0; i < cepsize_used; i++) + f[i] = w[i] - _w[i]; +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-2.c new file mode 100644 index 000000000..66df90f14 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-2.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -mtune=generic" } */ + +#include "avx-check.h" + +static int s[4] = {234566, 8723467, 6576856, 19832468}; +static int d[4] = {1,1,1,1}; + +static void +avx_test (void) +{ + __m128i src; + + src = _mm_loadu_si128 ((__m128i*) s); + _mm256_zeroupper (); + _mm_storeu_si128 ((__m128i*) d, src); + + if (__builtin_memcmp (d, s, sizeof (d))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-20.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-20.c new file mode 100644 index 000000000..33010839e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-20.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mtune=generic -dp" } */ + +extern void free (void *); +void +bar (void *ncstrp) +{ + if(ncstrp==((void *)0)) + return; + free(ncstrp); +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-21.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-21.c new file mode 100644 index 000000000..6dea0552f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-21.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mtune=generic -dp" } */ + +extern void exit (int) __attribute__ ((__noreturn__)); + +int +foo (int i) +{ + if (i == 0) + exit (1); + return 0; +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-22.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-22.c new file mode 100644 index 000000000..b4e4a5806 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-22.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mtune=generic -dp" } */ + +extern void exit (int) __attribute__ ((__noreturn__)); +extern void bar (void); + +int +foo (int i) +{ + if (i == 0) + { + bar (); + exit (1); + } + return 0; +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-23.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-23.c new file mode 100644 index 000000000..66df800e9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-23.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mtune=generic -dp" } */ + +extern void fatal (void) __attribute__ ((__noreturn__)); +extern void exit (int) __attribute__ ((__noreturn__)); + +void +fatal (void) +{ + exit (1); +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-24.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-24.c new file mode 100644 index 000000000..4fdd37446 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-24.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mtune=generic -dp" } */ + +typedef struct bitmap_element_def { + struct bitmap_element_def *next; + unsigned int indx; +} bitmap_element; +typedef struct bitmap_head_def { + bitmap_element *first; + bitmap_element *current; + unsigned int indx; +} bitmap_head; +typedef struct bitmap_head_def *bitmap; +typedef const struct bitmap_head_def *const_bitmap; +extern void bar (void) __attribute__ ((__noreturn__)); +unsigned char +bitmap_and_compl_into (bitmap a, const_bitmap b) +{ + bitmap_element *a_elt = a->first; + const bitmap_element *b_elt = b->first; + if (a == b) + { + if ((!(a)->first)) + return 0; + else + return 1; + } + while (a_elt && b_elt) + { + if (a_elt->indx < b_elt->indx) + a_elt = a_elt->next; + } + if (a->indx == a->current->indx) + bar (); + return 0; +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-25.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-25.c new file mode 100644 index 000000000..5ef49c7d3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-25.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx -mtune=generic -dp" } */ + +#include <immintrin.h> + +extern __m256 x, y; + +void +foo () +{ + x = y; +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-26.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-26.c new file mode 100644 index 000000000..96e9190fa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-26.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mavx -mtune=generic -dp" } */ + +#include <immintrin.h> + +extern __m256 x, y; +extern void (*bar) (void); + +void +foo () +{ + x = y; + bar (); +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-27.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-27.c new file mode 100644 index 000000000..7fa5de437 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-27.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mtune=generic -dp" } */ + +typedef struct objc_class *Class; +typedef struct objc_object +{ + Class class_pointer; +} *id; + +typedef const struct objc_selector *SEL; +typedef void * retval_t; +typedef void * arglist_t; + +extern retval_t __objc_forward (id object, SEL sel, arglist_t args); + +double +__objc_double_forward (id rcv, SEL op, ...) +{ + void *args, *res; + + args = __builtin_apply_args (); + res = __objc_forward (rcv, op, args); + __builtin_return (res); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-3.c new file mode 100644 index 000000000..8053d787f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-3.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -mavx -mvzeroupper" } */ + +#include "avx-check.h" + +int s[8] = {1, 2, 3, 4, 5, 6, 7, 8}; +int d[8] = {11, 22, 33, 44, 55, 66, 77, 88}; + +void +__attribute__((noinline)) +foo () +{ + int i; + for (i = 0; i < ARRAY_SIZE (d); i++) + d[i] = s[i] + 0x1000; +} + +static void +__attribute__((noinline)) +bar (__m256i src) +{ + foo (); + _mm256_storeu_si256 ((__m256i*) d, src); + if (__builtin_memcmp (d, s, sizeof (d))) + abort (); +} + +static void +avx_test (void) +{ + __m256i src = _mm256_loadu_si256 ((__m256i*) s); + bar (src); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-4.c new file mode 100644 index 000000000..467661760 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-4.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */ +/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ + +typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__)); + +extern void bar2 (__m256); +extern __m256 y; + +void +foo () +{ + bar2 (y); +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-5.c new file mode 100644 index 000000000..ba08978ab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-5.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */ +/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ + +#include <immintrin.h> + +extern void bar2 (__m256); +extern __m256 y; + +void +foo () +{ + bar2 (y); + _mm256_zeroupper (); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-6.c new file mode 100644 index 000000000..ada87bd31 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-6.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */ + +#include <immintrin.h> + +extern __m256 x, y; + +void +foo () +{ + x = y; + _mm256_zeroall (); +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c new file mode 100644 index 000000000..ab6d68779 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */ + +#include <immintrin.h> + +extern __m256 x, y; + +void +foo () +{ + x = y; + _mm256_zeroupper (); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-8.c new file mode 100644 index 000000000..bb370c5b4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */ + +#include <immintrin.h> + +extern __m256 x, y; + +void +foo () +{ + x = y; + _mm256_zeroall (); + _mm256_zeroupper (); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c new file mode 100644 index 000000000..974e1626a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */ + +#include <immintrin.h> + +extern __m256 x, y; + +void +foo () +{ + _mm256_zeroupper (); + x = y; + _mm256_zeroupper (); + _mm256_zeroupper (); + _mm256_zeroupper (); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-check.h new file mode 100644 index 000000000..424335dbb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-check.h @@ -0,0 +1,47 @@ +#include <stdlib.h> +#include "cpuid.h" +#include "m256-check.h" +#include "avx-os-support.h" + +static void avx2_test (void); + +static void __attribute__ ((noinline)) do_test (void) +{ + avx2_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run AVX2 test only if host has AVX2 support. */ + if ((ecx & bit_OSXSAVE) == (bit_OSXSAVE)) + { + if (__get_cpuid_max (0, NULL) < 7) + return 0; + + __cpuid_count (7, 0, eax, ebx, ecx, edx); + + if ((avx_os_support ()) && ((ebx & bit_AVX2) == bit_AVX2)) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + return 0; + } +#ifdef DEBUG + printf ("SKIPPED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-cvt-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-cvt-1.c new file mode 100644 index 000000000..9626a0666 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-cvt-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mavx2" } */ +/* { dg-require-effective-target avx2 } */ + +#ifndef CHECK_H +#define CHECK_H "avx2-check.h" +#endif + +#ifndef TEST +#define TEST avx2_test +#endif + +#include "sse2-cvt-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-cvt-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-cvt-2.c new file mode 100644 index 000000000..4826e9b6d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-cvt-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx2 -mtune=generic -fdump-tree-vect-details" } */ + +#include "avx2-cvt-1.c" + +/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 6 "vect" } } */ +/* { dg-final { scan-assembler "vcvttpd2dq(y\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*YMMWORD PTR)" } } */ +/* { dg-final { scan-assembler "vcvtdq2ps\[^\n\r\]*ymm" } } */ +/* { dg-final { scan-assembler "vcvtps2pd\[^\n\r\]*(%xmm\[^\n\r\]*%ymm|ymm\[^\n\r\]*xmm)" } } */ +/* { dg-final { scan-assembler "vcvttps2dq\[^\n\r\]*ymm" } } */ +/* { dg-final { scan-assembler "vcvtdq2pd\[^\n\r\]*(%xmm\[^\n\r\]*%ymm|ymm\[^\n\r\]*xmm)" } } */ +/* { dg-final { scan-assembler "vcvtpd2ps(y\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*YMMWORD PTR)" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-gather-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-gather-1.c new file mode 100644 index 000000000..7ed567dc4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-gather-1.c @@ -0,0 +1,215 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include "avx2-check.h" + +#define N 1024 +float vf1[N+16], vf2[N]; +double vd1[N+16], vd2[N]; +int k[N]; +long l[N]; +short n[N]; + +__attribute__((noinline, noclone)) void +f1 (void) +{ + int i; + for (i = 0; i < N; i++) + vf2[i] = vf1[k[i]]; +} + +__attribute__((noinline, noclone)) void +f2 (void) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vf1[k[i]]; +} + +__attribute__((noinline, noclone)) void +f3 (int x) +{ + int i; + for (i = 0; i < N; i++) + vf2[i] = vf1[k[i] + x]; +} + +__attribute__((noinline, noclone)) void +f4 (int x) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vf1[k[i] + x]; +} + +__attribute__((noinline, noclone)) void +f5 (void) +{ + int i; + for (i = 0; i < N; i++) + vd2[i] = vd1[k[i]]; +} + +__attribute__((noinline, noclone)) void +f6 (void) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vd1[k[i]]; +} + +__attribute__((noinline, noclone)) void +f7 (int x) +{ + int i; + for (i = 0; i < N; i++) + vd2[i] = vd1[k[i] + x]; +} + +__attribute__((noinline, noclone)) void +f8 (int x) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vd1[k[i] + x]; +} + +__attribute__((noinline, noclone)) void +f9 (void) +{ + int i; + for (i = 0; i < N; i++) + vf2[i] = vf1[l[i]]; +} + +__attribute__((noinline, noclone)) void +f10 (void) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vf1[l[i]]; +} + +__attribute__((noinline, noclone)) void +f11 (long x) +{ + int i; + for (i = 0; i < N; i++) + vf2[i] = vf1[l[i] + x]; +} + +__attribute__((noinline, noclone)) void +f12 (long x) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vf1[l[i] + x]; +} + +__attribute__((noinline, noclone)) void +f13 (void) +{ + int i; + for (i = 0; i < N; i++) + vd2[i] = vd1[l[i]]; +} + +__attribute__((noinline, noclone)) void +f14 (void) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vd1[l[i]]; +} + +__attribute__((noinline, noclone)) void +f15 (long x) +{ + int i; + for (i = 0; i < N; i++) + vd2[i] = vd1[l[i] + x]; +} + +__attribute__((noinline, noclone)) void +f16 (long x) +{ + int i; + for (i = 0; i < N; i++) + n[i] = (int) vd1[l[i] + x]; +} + +static void +avx2_test (void) +{ + int i; + + for (i = 0; i < N + 16; i++) + { + asm (""); + vf1[i] = 17.0f + i; + vd1[i] = 19.0 + i; + } + for (i = 0; i < N; i++) + { + asm (""); + k[i] = (i * 731) & (N - 1); + l[i] = (i * 657) & (N - 1); + } + + f1 (); + f2 (); + for (i = 0; i < N; i++) + if (vf2[i] != ((i * 731) & (N - 1)) + 17 + || n[i] != ((i * 731) & (N - 1)) + 17) + abort (); + + f3 (12); + f4 (14); + for (i = 0; i < N; i++) + if (vf2[i] != ((i * 731) & (N - 1)) + 17 + 12 + || n[i] != ((i * 731) & (N - 1)) + 17 + 14) + abort (); + + f5 (); + f6 (); + for (i = 0; i < N; i++) + if (vd2[i] != ((i * 731) & (N - 1)) + 19 + || n[i] != ((i * 731) & (N - 1)) + 19) + abort (); + + f7 (7); + f8 (9); + for (i = 0; i < N; i++) + if (vd2[i] != ((i * 731) & (N - 1)) + 19 + 7 + || n[i] != ((i * 731) & (N - 1)) + 19 + 9) + abort (); + + f9 (); + f10 (); + for (i = 0; i < N; i++) + if (vf2[i] != ((i * 657) & (N - 1)) + 17 + || n[i] != ((i * 657) & (N - 1)) + 17) + abort (); + + f11 (2); + f12 (4); + for (i = 0; i < N; i++) + if (vf2[i] != ((i * 657) & (N - 1)) + 17 + 2 + || n[i] != ((i * 657) & (N - 1)) + 17 + 4) + abort (); + + f13 (); + f14 (); + for (i = 0; i < N; i++) + if (vd2[i] != ((i * 657) & (N - 1)) + 19 + || n[i] != ((i * 657) & (N - 1)) + 19) + abort (); + + f15 (13); + f16 (15); + for (i = 0; i < N; i++) + if (vd2[i] != ((i * 657) & (N - 1)) + 19 + 13 + || n[i] != ((i * 657) & (N - 1)) + 19 + 15) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-gather-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-gather-2.c new file mode 100644 index 000000000..8a7fe95a2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-gather-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx2 -fdump-tree-vect-details" } */ + +#include "avx2-gather-1.c" + +/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 16 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-gather-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-gather-3.c new file mode 100644 index 000000000..fb6289c0e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-gather-3.c @@ -0,0 +1,167 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2 -ffast-math" } */ + +#include "avx2-check.h" + +#define N 1024 +float f[N]; +double d[N]; +int k[N]; +float *l[N]; +double *n[N]; +int **m[N]; +long **o[N]; +long q[N]; +long *r[N]; +int *s[N]; + +__attribute__((noinline, noclone)) float +f1 (void) +{ + int i; + float g = 0.0; + for (i = 0; i < N / 2; i++) + g += f[k[i]]; + return g; +} + +__attribute__((noinline, noclone)) float +f2 (float *p) +{ + int i; + float g = 0.0; + for (i = 0; i < N / 2; i++) + g += p[k[i]]; + return g; +} + +__attribute__((noinline, noclone)) float +f3 (void) +{ + int i; + float g = 0.0; + for (i = 0; i < N / 2; i++) + g += *l[i]; + return g; +} + +__attribute__((noinline, noclone)) int +f4 (void) +{ + int i; + int g = 0; + for (i = 0; i < N / 2; i++) + g += **m[i]; + return g; +} + +__attribute__((noinline, noclone)) double +f5 (void) +{ + int i; + double g = 0.0; + for (i = 0; i < N / 2; i++) + g += d[k[i]]; + return g; +} + +__attribute__((noinline, noclone)) double +f6 (double *p) +{ + int i; + double g = 0.0; + for (i = 0; i < N / 2; i++) + g += p[k[i]]; + return g; +} + +__attribute__((noinline, noclone)) double +f7 (void) +{ + int i; + double g = 0.0; + for (i = 0; i < N / 2; i++) + g += *n[i]; + return g; +} + +__attribute__((noinline, noclone)) int +f8 (void) +{ + int i; + int g = 0; + for (i = 0; i < N / 2; i++) + g += **o[i]; + return g; +} + +__attribute__((noinline, noclone)) float +f9 (void) +{ + int i; + float g = 0.0; + for (i = 0; i < N / 2; i++) + g += f[q[i]]; + return g; +} + +__attribute__((noinline, noclone)) float +f10 (float *p) +{ + int i; + float g = 0.0; + for (i = 0; i < N / 2; i++) + g += p[q[i]]; + return g; +} + +__attribute__((noinline, noclone)) double +f11 (void) +{ + int i; + double g = 0.0; + for (i = 0; i < N / 2; i++) + g += d[q[i]]; + return g; +} + +__attribute__((noinline, noclone)) double +f12 (double *p) +{ + int i; + double g = 0.0; + for (i = 0; i < N / 2; i++) + g += p[q[i]]; + return g; +} + +static void +avx2_test (void) +{ + int i; + + for (i = 0; i < N; i++) + { + asm (""); + f[i] = -256.0f + i; + d[i] = -258.0 + i; + k[i] = (i * 731) & (N - 1); + q[i] = (i * 657) & (N - 1); + l[i] = &f[(i * 239) & (N - 1)]; + n[i] = &d[(i * 271) & (N - 1)]; + r[i] = &q[(i * 323) & (N - 1)]; + s[i] = &k[(i * 565) & (N - 1)]; + m[i] = &s[(i * 13) & (N - 1)]; + o[i] = &r[(i * 19) & (N - 1)]; + } + + if (f1 () != 136448.0f || f2 (f) != 136448.0f || f3 () != 130304.0) + abort (); + if (f4 () != 261376 || f5 () != 135424.0 || f6 (d) != 135424.0) + abort (); + if (f7 () != 129280.0 || f8 () != 259840L || f9 () != 130816.0f) + abort (); + if (f10 (f) != 130816.0f || f11 () != 129792.0 || f12 (d) != 129792.0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-gather-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-gather-4.c new file mode 100644 index 000000000..440a9c9b1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-gather-4.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include "avx2-check.h" + +#define N 1024 +int a[N], b[N], c[N], d[N]; + +__attribute__((noinline, noclone)) void +foo (float *__restrict p, float *__restrict q, float *__restrict r, + long s1, long s2, long s3) +{ + int i; + for (i = 0; i < N; i++) + p[i] = q[a[i] * s1 + b[i] * s2 + s3] * r[c[i] * s1 + d[i] * s2 + s3]; +} + +static void +avx2_test (void) +{ + int i; + float e[N], f[N], g[N]; + for (i = 0; i < N; i++) + { + a[i] = (i * 7) & (N / 8 - 1); + b[i] = (i * 13) & (N / 8 - 1); + c[i] = (i * 23) & (N / 8 - 1); + d[i] = (i * 5) & (N / 8 - 1); + e[i] = 16.5 + i; + f[i] = 127.5 - i; + } + foo (g, e, f, 3, 2, 4); + for (i = 0; i < N; i++) + if (g[i] != (float) ((20.5 + a[i] * 3 + b[i] * 2) + * (123.5 - c[i] * 3 - d[i] * 2))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-1.c new file mode 100644 index 000000000..ae3b1d577 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i32gather_epi32 (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-2.c new file mode 100644 index 000000000..7d3f3474d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherd (int *s1, int *s2, int scale, int *r) +{ + int i; + + for (i = 0; i < 4; ++i) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union128i_d res; + int s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm_i32gather_epi32 (s1, idx.x, 2); + + compute_i32gatherd (s1, idx.a, 2, res_ref); + + if (check_union128i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-3.c new file mode 100644 index 000000000..fc8fedea0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i32gather_epi32 (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-4.c new file mode 100644 index 000000000..2cc3a792e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-4.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherd (int *src, int *s1, int *s2, int *mask, int scale, int *r) +{ + int i; + + for (i = 0; i < 4; ++i) + if ((mask[i] >> 31) & 1) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union128i_d res, src, mask; + int s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((int *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm_mask_i32gather_epi32 (src.x, s1, idx.x, mask.x, 2); + + compute_i32gatherd (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-1.c new file mode 100644 index 000000000..afc73b9b1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +int *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i32gather_epi32 (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-2.c new file mode 100644 index 000000000..e5bcbee1f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherd256 (int *s1, int *s2, int scale, int *r) +{ + int i; + + for (i = 0; i < 8; ++i) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union256i_d idx; + union256i_d res; + int s1[8], res_ref[8] = { 0 }; + + for (i = 0; i < 8; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_i32gather_epi32 (s1, idx.x, 2); + + compute_i32gatherd256 (s1, idx.a, 2, res_ref); + + if (check_union256i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-3.c new file mode 100644 index 000000000..d0c864294 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256i x; +int *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i32gather_epi32 (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-4.c new file mode 100644 index 000000000..a80530912 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherd256 (int *src, + int *s1, int *s2, int *mask, int scale, int *r) +{ + int i; + + for (i = 0; i < 8; ++i) + if ((mask[i] >> 31) & 1) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union256i_d idx; + union256i_d res, src, mask; + int s1[8], res_ref[8] = { 0 }; + + for (i = 0; i < 8; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + mask.a[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_mask_i32gather_epi32 (src.x, s1, idx.x, mask.x, 2); + + compute_i32gatherd256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union256i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-1.c new file mode 100644 index 000000000..860cac448 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdpd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i32gather_pd (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-2.c new file mode 100644 index 000000000..475f623ec --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd (double *s1, int *s2, int scale, double *r) +{ + int i; + + for (i = 0; i < 2; ++i) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union128d res; + double s1[2], res_ref[2] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm_i32gather_pd (s1, idx.x, 2); + + compute_i32gatherpd (s1, idx.a, 2, res_ref); + + if (check_union128d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-3.c new file mode 100644 index 000000000..5e1d4864b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdpd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i32gather_pd (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-4.c new file mode 100644 index 000000000..12c533f9d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd (double *src, + double *s1, int *s2, double *mask, int scale, double *r) +{ + int i; + + for (i = 0; i < 2; ++i) + if ((((long long *) mask)[i] >> 63) & 1) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union128d res, src, mask; + double s1[2], res_ref[2] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((long long *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm_mask_i32gather_pd (src.x, s1, idx.x, mask.x, 2); + + compute_i32gatherpd (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-1.c new file mode 100644 index 000000000..00b6a35c5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i32gather_pd (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-2.c new file mode 100644 index 000000000..a45801ba9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd256 (double *s1, int *s2, int scale, double *r) +{ + int i; + + for (i = 0; i < 4; ++i) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union256d res; + double s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_i32gather_pd (s1, idx.x, 2); + + compute_i32gatherpd256 (s1, idx.a, 2, res_ref); + + if (check_union256d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-3.c new file mode 100644 index 000000000..336fb299b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i32gather_pd (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-4.c new file mode 100644 index 000000000..f24acbd7f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-4.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd256 (double *src, + double *s1, + int *s2, double *mask, int scale, double *r) +{ + int i; + + for (i = 0; i < 4; ++i) + if ((((long long *) mask)[i] >> 63) & 1) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union256d res, src, mask; + double s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((long long *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, divide by 2 + to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_mask_i32gather_pd (src.x, s1, idx.x, mask.x, 2); + + compute_i32gatherpd256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union256d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-1.c new file mode 100644 index 000000000..c43687c4d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +float *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i32gather_ps (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-2.c new file mode 100644 index 000000000..1174ddad5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherps (float *s1, int *s2, int scale, float *r) +{ + int i; + + for (i = 0; i < 4; ++i) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union128 res; + float s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm_i32gather_ps (s1, idx.x, 2); + + compute_i32gatherps (s1, idx.a, 2, res_ref); + + if (check_union128 (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-3.c new file mode 100644 index 000000000..76b46fb23 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +float *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i32gather_ps (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-4.c new file mode 100644 index 000000000..94b9213d6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherps (float *src, + float *s1, int *s2, float *mask, int scale, float *r) +{ + int i; + + for (i = 0; i < 4; ++i) + if ((((int *) mask)[i] >> 31) & 1) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_d idx; + union128 res, src, mask; + float s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((int *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm_mask_i32gather_ps (src.x, s1, idx.x, mask.x, 2); + + compute_i32gatherps (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128 (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-1.c new file mode 100644 index 000000000..f09a0ff32 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdps\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256 x; +float *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i32gather_ps (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-2.c new file mode 100644 index 000000000..654c6f676 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherps256 (float *s1, int *s2, int scale, float *r) +{ + int i; + + for (i = 0; i < 8; ++i) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union256i_d idx; + union256 res; + float s1[8], res_ref[8] = { 0 }; + + for (i = 0; i < 8; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_i32gather_ps (s1, idx.x, 2); + + compute_i32gatherps256 (s1, idx.a, 2, res_ref); + + if (check_union256 (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-3.c new file mode 100644 index 000000000..34b7b8d72 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherdps\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256 x; +float *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i32gather_ps (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-4.c new file mode 100644 index 000000000..07c2abacb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherps256 (float *src, + float *s1, int *s2, float *mask, int scale, float *r) +{ + int i; + + for (i = 0; i < 8; ++i) + if ((((int *) mask)[i] >> 31) & 1) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union256i_d idx; + union256 res, src, mask; + float s1[8], res_ref[8] = { 0 }; + + for (i = 0; i < 8; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((int *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_mask_i32gather_ps (src.x, s1, idx.x, mask.x, 2); + + compute_i32gatherps256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union256 (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-1.c new file mode 100644 index 000000000..0b250e5dd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdq\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +long long int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i32gather_epi64 (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-2.c new file mode 100644 index 000000000..54838e710 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd (long long *s1, int *s2, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 2; ++i) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + long long i; + union128i_d idx; + union128i_q res; + long long s1[2], res_ref[2] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm_i32gather_epi64 ((long long int *) s1, idx.x, 2); + + compute_i32gatherpd (s1, idx.a, 2, res_ref); + + if (check_union128i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-3.c new file mode 100644 index 000000000..d87400c77 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdq\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +long long int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i32gather_epi64 (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-4.c new file mode 100644 index 000000000..4770d0ada --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-4.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd (long long *src, + long long *s1, + int *s2, long long *mask, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 2; ++i) + if ((mask[i] >> 63) & 1) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + long long i; + union128i_d idx; + union128i_q res, src, mask; + long long s1[2], res_ref[2] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + mask.a[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = + _mm_mask_i32gather_epi64 (src.x, (long long int *) s1, idx.x, mask.x, 2); + + compute_i32gatherpd (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-1.c new file mode 100644 index 000000000..e8651438a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +long long int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i32gather_epi64 (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-2.c new file mode 100644 index 000000000..85e576797 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd256 (long long *s1, int *s2, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 4; ++i) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + long long i; + union128i_d idx; + union256i_q res; + long long s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_i32gather_epi64 ((long long int *) s1, idx.x, 2); + + compute_i32gatherpd256 (s1, idx.a, 2, res_ref); + + if (check_union256i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-3.c new file mode 100644 index 000000000..7b6f4491a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherdq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256i x; +long long int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i32gather_epi64 (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-4.c new file mode 100644 index 000000000..3eab9be5c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-4.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i32gatherpd256 (long long *src, + long long *s1, + int *s2, long long *mask, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 4; ++i) + if ((mask[i] >> 63) & 1) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + long long i; + union128i_d idx; + union256i_q res, src, mask; + long long s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + mask.a[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, divide by 2 + to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_mask_i32gather_epi64 (src.x, + (long long int *) s1, + idx.x, mask.x, 2); + + compute_i32gatherpd256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union256i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-1.c new file mode 100644 index 000000000..f2ade8415 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i64gather_epi32 (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-2.c new file mode 100644 index 000000000..f475a4a73 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps (int *s1, long long *s2, int scale, int *r) +{ + int i; + + for (i = 0; i < 2; ++i) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_q idx; + union128i_d res; + int s1[2], res_ref[4] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (8 - (i + 1) * 4) >> 1; + } + + res.x = _mm_i64gather_epi32 (s1, idx.x, 2); + + compute_i64gatherps (s1, idx.a, 2, res_ref); + + if (check_union128i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-3.c new file mode 100644 index 000000000..265713da5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i64gather_epi32 (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-4.c new file mode 100644 index 000000000..77c8747f0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps (int *src, + int *s1, long long *s2, int *mask, int scale, int *r) +{ + int i; + + for (i = 0; i < 2; ++i) + if ((mask[i] >> 31) & 1) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_q idx; + union128i_d res, src, mask; + int s1[2], res_ref[4] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + mask.a[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (8 - (i + 1) * 4) >> 1; + } + + res.x = _mm_mask_i64gather_epi32 (src.x, s1, idx.x, mask.x, 2); + + compute_i64gatherps (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-1.c new file mode 100644 index 000000000..ccc16e523 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i64gather_epi32 (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-2.c new file mode 100644 index 000000000..0f88b20b2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps256 (int *s1, long long *s2, int scale, int *r) +{ + int i; + + for (i = 0; i < 4; ++i) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union256i_q idx; + union128i_d res; + int s1[8], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_i64gather_epi32 (s1, idx.x, 2); + + compute_i64gatherps256 (s1, idx.a, 2, res_ref); + + if (check_union128i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-3.c new file mode 100644 index 000000000..815e70828 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i64gather_epi32 (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-4.c new file mode 100644 index 000000000..6c4bdd60a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-4.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps256 (int *src, + int *s1, long long *s2, int *mask, int scale, int *r) +{ + int i; + + for (i = 0; i < 4; ++i) + if ((mask[i] >> 31) & 1) + r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union256i_q idx; + union128i_d res, src, mask; + int s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1973 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + mask.a[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_mask_i64gather_epi32 (src.x, s1, idx.x, mask.x, 2); + + compute_i64gatherps256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128i_d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-1.c new file mode 100644 index 000000000..895b248c7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqpd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i64gather_pd (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-2.c new file mode 100644 index 000000000..5a119712e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-2.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherpd (double *s1, long long *s2, int scale, double *r) +{ + int i; + + for (i = 0; i < 2; ++i) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_q idx; + union128d res; + double s1[2], res_ref[2] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm_i64gather_pd (s1, idx.x, 2); + + compute_i64gatherpd (s1, idx.a, 2, res_ref); + + if (check_union128d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-3.c new file mode 100644 index 000000000..436ffe90a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqpd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128d x; +double *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i64gather_pd (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-4.c new file mode 100644 index 000000000..61cb1f8d0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-4.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherpd (double *src, + double *s1, + long long int *s2, double *mask, int scale, double *r) +{ + int i; + + for (i = 0; i < 2; ++i) + if ((((long long *) mask)[i] >> 63) & 1) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_q idx; + union128d res, src, mask; + double s1[2], res_ref[2] = { 0, 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((long long *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm_mask_i64gather_pd (src.x, s1, idx.x, mask.x, 2); + + compute_i64gatherpd (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-1.c new file mode 100644 index 000000000..bc22f02e5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256d x; +double *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i64gather_pd (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-2.c new file mode 100644 index 000000000..99e192d75 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherpd256 (double *s1, long long int *s2, int scale, double *r) +{ + int i; + + for (i = 0; i < 4; ++i) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union256i_q idx; + union256d res; + double s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_i64gather_pd (s1, idx.x, 2); + + compute_i64gatherpd256 (s1, idx.a, 2, res_ref); + + if (check_union256d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-3.c new file mode 100644 index 000000000..505722a8a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256d x; +double *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i64gather_pd (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-4.c new file mode 100644 index 000000000..09a5f8a14 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-4.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherpd256 (double *src, + double *s1, + long long int *s2, double *mask, int scale, double *r) +{ + int i; + + for (i = 0; i < 4; ++i) + if ((((long long *) mask)[i] >> 63) & 1) + r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union256i_q idx; + union256d res, src, mask; + double s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((long long *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_mask_i64gather_pd (src.x, s1, idx.x, mask.x, 2); + + compute_i64gatherpd256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union256d (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-1.c new file mode 100644 index 000000000..c7d7c0787 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +float *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i64gather_ps (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-2.c new file mode 100644 index 000000000..527e4e812 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps (float *s1, long long *s2, int scale, float *r) +{ + int i; + + for (i = 0; i < 2; ++i) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union128i_q idx; + union128 res; + float s1[2], res_ref[4] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (8 - (i + 1) * 4) >> 1; + } + + res.x = _mm_i64gather_ps (s1, idx.x, 2); + + compute_i64gatherps (s1, idx.a, 2, res_ref); + + if (check_union128 (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-3.c new file mode 100644 index 000000000..ca7162ad9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +float *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i64gather_ps (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-4.c new file mode 100644 index 000000000..ada4e49ff --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-4.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps (float *src, + float *s1, + long long *s2, float *mask, int scale, float *r) +{ + int i; + + for (i = 0; i < 2; ++i) + if ((((int *) mask)[i] >> 31) & 1) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union128i_q idx; + union128 res, src, mask; + float s1[2], res_ref[4] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((int *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (8 - (i + 1) * 4) >> 1; + } + + res.x = _mm_mask_i64gather_ps (src.x, s1, idx.x, mask.x, 2); + + compute_i64gatherps (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128 (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-1.c new file mode 100644 index 000000000..6612e9940 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +float *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i64gather_ps (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-2.c new file mode 100644 index 000000000..d2fe7c1fb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps256 (float *s1, long long *s2, int scale, float *r) +{ + int i; + + for (i = 0; i < 4; ++i) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + int i; + union256i_q idx; + union128 res; + float s1[8], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_i64gather_ps (s1, idx.x, 2); + + compute_i64gatherps256 (s1, idx.a, 2, res_ref); + + if (check_union128 (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-3.c new file mode 100644 index 000000000..f05e4a208 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vgatherqps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +float *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i64gather_ps (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-4.c new file mode 100644 index 000000000..8185cd839 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-4.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherps256 (float *src, + float *s1, + long long *s2, float *mask, int scale, float *r) +{ + int i; + + for (i = 0; i < 4; ++i) + if ((((int *) mask)[i] >> 31) & 1) + r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + int i; + union256i_q idx; + union128 res, src, mask; + float s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 2.718281828459045 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((int *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 4) >> 1; + } + + res.x = _mm256_mask_i64gather_ps (src.x, s1, idx.x, mask.x, 2); + + compute_i64gatherps256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128 (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-1.c new file mode 100644 index 000000000..8f9752d2c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqq\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +long long int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_i64gather_epi64 (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-2.c new file mode 100644 index 000000000..a2d7a9968 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherpd (long long *s1, long long *s2, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 2; ++i) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + long long i; + union128i_q idx; + union128i_q res; + long long s1[2], res_ref[2] = { 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm_i64gather_epi64 ((long long int *) s1, idx.x, 2); + + compute_i64gatherpd (s1, idx.a, 2, res_ref); + + if (check_union128i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-3.c new file mode 100644 index 000000000..c1c31c728 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqq\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +long long int *base; +__m128i idx; + +void extern +avx2_test (void) +{ + x = _mm_mask_i64gather_epi64 (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-4.c new file mode 100644 index 000000000..cbc8e31f1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-4.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherpd (long long *src, + long long *s1, + long long *s2, long long *mask, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 2; ++i) + if ((mask[i] >> 63) & 1) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + long long i; + union128i_q idx; + union128i_q res, src, mask; + long long s1[2], res_ref[2] = { 0, 0 }; + + for (i = 0; i < 2; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + mask.a[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = + _mm_mask_i64gather_epi64 (src.x, (long long int *) s1, idx.x, mask.x, 2); + + compute_i64gatherpd (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union128i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-1.c new file mode 100644 index 000000000..c873cb954 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +long long int *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_i64gather_epi64 (base, idx, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-2.c new file mode 100644 index 000000000..3ac3e2e01 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherq256 (long long *s1, long long *s2, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 4; ++i) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); +} + +void static +avx2_test (void) +{ + long long i; + union256i_q idx; + union256i_q res; + long long s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (32 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_i64gather_epi64 ((long long int *) s1, idx.x, 2); + + compute_i64gatherq256 (s1, idx.a, 2, res_ref); + + if (check_union256i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-3.c new file mode 100644 index 000000000..f60ad2274 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpgatherqq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256i x; +long long int *base; +__m256i idx; + +void extern +avx2_test (void) +{ + x = _mm256_mask_i64gather_epi64 (x, base, idx, x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-4.c new file mode 100644 index 000000000..355c8c2b0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-4.c @@ -0,0 +1,55 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_i64gatherq256 (long long *src, + long long *s1, + long long *s2, + long long *mask, int scale, long long *r) +{ + long long i; + + for (i = 0; i < 4; ++i) + if ((mask[i] >> 63) & 1) + r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale); + else + r[i] = src[i]; +} + +void static +avx2_test (void) +{ + long long i; + union256i_q idx; + union256i_q res, src, mask; + long long s1[4], res_ref[4] = { 0 }; + + for (i = 0; i < 4; ++i) + { + /* Set some stuff */ + s1[i] = 1983 * (i + 1) * (i + 2); + + /* Set src as something different from s1 */ + src.a[i] = -s1[i]; + + /* Mask out evens */ + ((long long *) mask.a)[i] = i % 2 ? 0 : -1; + + /* About to gather in reverse order, + divide by 2 to demonstrate scale */ + idx.a[i] = (16 - (i + 1) * 8) >> 1; + } + + res.x = _mm256_mask_i64gather_epi64 (src.x, + (long long int *) s1, + idx.x, mask.x, 2); + + compute_i64gatherq256 (src.a, s1, idx.a, mask.a, 2, res_ref); + + if (check_union256i_q (res, res_ref) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-1.c new file mode 100644 index 000000000..740e14163 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx2" } */ +/* { dg-final { scan-assembler "mpsadbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + /* imm = 13 is arbitrary here */ + x = _mm256_mpsadbw_epu8 (x, x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-2.c new file mode 100644 index 000000000..18118e442 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-2.c @@ -0,0 +1,132 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define msk0 0xC0 +#define msk1 0x01 +#define msk2 0xF2 +#define msk3 0x03 +#define msk4 0x84 +#define msk5 0x05 +#define msk6 0xE6 +#define msk7 0x67 + + +static void +compute_mpsadbw (int *i1, int *i2, int mask, int *r) +{ + unsigned char s[4]; + int i, j; + int offs1, offs2; + unsigned char *v1 = (char *) i1; + unsigned char *v2 = (char *) i2; + unsigned short *ret = (unsigned short *) r; + + memset (ret, 0, 32); + + /* Lower part */ + offs2 = 4 * (mask & 3); + for (i = 0; i < 4; i++) + s[i] = v2[offs2 + i]; + + offs1 = 4 * ((mask & 4) >> 2); + for (j = 0; j < 8; j++) + for (i = 0; i < 4; i++) + ret[j] += abs (v1[offs1 + j + i] - s[i]); + + /* Higher part */ + offs2 = 4 * ((mask >> 3) & 3) + 16; + for (i = 0; i < 4; i++) + s[i] = v2[offs2 + i]; + + offs1 = 4 * ((mask & 0x20) >> 5) + 16; + for (j = 0; j < 8; j++) + for (i = 0; i < 4; i++) + ret[j + 8] += abs (v1[offs1 + j + i] - s[i]); +} + +static void +avx2_test (void) +{ + union256i_d val1, val2, val3[8], res[8]; + int tmp[8]; + unsigned char masks[8]; + int i, j; + + val1.a[0] = 0x35251505; + val1.a[1] = 0x75655545; + val1.a[2] = 0xB5A59585; + val1.a[3] = 0xF5E5D5C5; + + val1.a[4] = 0x35251505; + val1.a[5] = 0x75655545; + val1.a[6] = 0xB5A59585; + val1.a[7] = 0xF5E5D5C5; + + val2.a[0] = 0x31211101; + val2.a[1] = 0x71615141; + val2.a[2] = 0xB1A19181; + val2.a[3] = 0xF1E1D1C1; + + val2.a[4] = 0x31211101; + val2.a[5] = 0x71615141; + val2.a[6] = 0xB1A19181; + val2.a[7] = 0xF1E1D1C1; + + for (i = 0; i < 8; i++) + switch (i % 3) + { + case 1: + val3[i].a[0] = 0xF1E1D1C1; + val3[i].a[1] = 0xB1A19181; + val3[i].a[2] = 0x71615141; + val3[i].a[3] = 0x31211101; + break; + default: + val3[i].x = val2.x; + break; + } + + /* Check mpsadbw imm8, ymm, ymm. */ + res[0].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk0); + res[1].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk1); + res[2].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk2); + res[3].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk3); + res[4].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk4); + res[5].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk5); + res[6].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk6); + res[7].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk7); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + masks[4] = msk4; + masks[5] = msk5; + masks[6] = msk6; + masks[7] = msk7; + + for (i = 0; i < 8; i++) + { + compute_mpsadbw (val1.a, val2.a, masks[i], tmp); + if (check_union256i_d (res[i], tmp)) + abort (); + } + + /* Check mpsadbw imm8, m256, ymm. */ + for (i = 0; i < 8; i++) + { + res[i].x = _mm256_mpsadbw_epu8 (val1.x, val3[i].x, msk4); + masks[i] = msk4; + } + + for (i = 0; i < 8; i++) + { + compute_mpsadbw (val1.a, val3[i].a, masks[i], tmp); + if (check_union256i_d (res[i], tmp)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-mul-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-mul-1.c new file mode 100644 index 000000000..0351fbb7c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-mul-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#ifndef CHECK_H +#define CHECK_H "avx2-check.h" +#endif + +#ifndef TEST +#define TEST avx2_test +#endif + +#include "sse2-mul-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-pr51581-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-pr51581-1.c new file mode 100644 index 000000000..74d507fd9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-pr51581-1.c @@ -0,0 +1,9 @@ +/* PR tree-optimization/51581 */ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -mavx2 -fno-vect-cost-model" } */ +/* { dg-require-effective-target avx2 } */ + +#define CHECK_H "avx2-check.h" +#define TEST avx2_test + +#include "avx-pr51581-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-pr51581-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-pr51581-2.c new file mode 100644 index 000000000..bf063c2ef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-pr51581-2.c @@ -0,0 +1,9 @@ +/* PR tree-optimization/51581 */ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -mavx2 -fno-vect-cost-model" } */ +/* { dg-require-effective-target avx2 } */ + +#define CHECK_H "avx2-check.h" +#define TEST avx2_test + +#include "avx-pr51581-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-1.c new file mode 100644 index 000000000..80964e39d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vbroadcastsd\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +__m128d x; +__m256d y; + +void extern +avx2_test (void) +{ + y = _mm256_broadcastsd_pd (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-2.c new file mode 100644 index 000000000..ee323f5af --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-2.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union128d s1; + union256d res; + double res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + s1.a[0] = i * 3.14; + + res.x = _mm256_broadcastsd_pd (s1.x); + + for (j = 0; j < 4; j++) + memcpy (res_ref + j, s1.a, 8); + + fail += check_union256d (res, res_ref); + } + + if (fail != 0) + abort (); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-1.c new file mode 100644 index 000000000..7805e3ddb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vbroadcasti128\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_broadcastsi128_si256 (y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-2.c new file mode 100644 index 000000000..ef1d370ab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-2.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union128i_q s1; + union256i_q res; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 2; j++) + s1.a[j] = j * i; + + res.x = _mm256_broadcastsi128_si256 (s1.x); + + memcpy (res_ref, s1.a, 16); + memcpy (res_ref + 2, s1.a, 16); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-1.c new file mode 100644 index 000000000..d9d47e2a9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vbroadcastss\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; + +void extern +avx2_test (void) +{ + x = _mm_broadcastss_ps (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-2.c new file mode 100644 index 000000000..1637e703b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union128 s1, res; + float res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + s1.a[0] = i * 3.14; + + res.x = _mm_broadcastss_ps (s1.x); + + for (j = 0; j < 4; j++) + memcpy (res_ref + j, s1.a, 4); + + fail += check_union128 (res, res_ref); + } + + if (fail != 0) + abort (); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-1.c new file mode 100644 index 000000000..dfac3916b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vbroadcastss\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128 x; +__m256 y; + +void extern +avx2_test (void) +{ + y = _mm256_broadcastss_ps (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-2.c new file mode 100644 index 000000000..9f90e2e85 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-2.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union128 s1; + union256 res; + float res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + s1.a[0] = i * 3.14; + + res.x = _mm256_broadcastss_ps (s1.x); + + for (j = 0; j < 8; j++) + memcpy (res_ref + j, s1.a, 4); + + fail += check_union256 (res, res_ref); + } + + if (fail != 0) + abort (); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vextracti128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vextracti128-1.c new file mode 100644 index 000000000..a032e3c9b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vextracti128-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vextracti128\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + y = _mm256_extracti128_si256 (x, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vextracti128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vextracti128-2.c new file mode 100644 index 000000000..7d3c561a1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vextracti128-2.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_q s1; + union128i_q res; + long long int res_ref[2]; + int j; + + for (j = 0; j < 4; j++) + s1.a[j] = j * j; + + res.x = _mm256_extracti128_si256 (s1.x, 0); + + memset (res_ref, 0, 16); + memcpy (res_ref, s1.a, 16); + + if (check_union128i_q (res, res_ref)) + abort (); + + res.x = _mm256_extracti128_si256 (s1.x, 1); + + memset (res_ref, 0, 16); + memcpy (res_ref, s1.a + 2, 16); + + if (check_union128i_q (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vinserti128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vinserti128-1.c new file mode 100644 index 000000000..2d0f7c51a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vinserti128-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vinserti128\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_inserti128_si256 (x, y, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vinserti128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vinserti128-2.c new file mode 100644 index 000000000..f6361cd47 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vinserti128-2.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_q s1, res; + union128i_q s2; + long long int res_ref[4]; + int j; + + for (j = 0; j < 4; j++) + s1.a[j] = j * j; + + for (j = 0; j < 2; j++) + s2.a[j] = j * j * j; + + res.x = _mm256_inserti128_si256 (s1.x, s2.x, 0); + + memcpy (res_ref, s1.a, 32); + memcpy (res_ref, s2.a, 16); + + if (check_union256i_q (res, res_ref)) + abort (); + + res.x = _mm256_inserti128_si256 (s1.x, s2.x, 1); + + memcpy (res_ref, s1.a, 32); + memcpy (res_ref + 2, s2.a, 16); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-1.c new file mode 100644 index 000000000..4c44f082d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vmovntdqa\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m256i *y; + +void extern +avx2_test (void) +{ + x = _mm256_stream_load_si256 (y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-2.c new file mode 100644 index 000000000..f1eda70bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_q s1, res; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + s1.a[j] = j * i; + + res.x = _mm256_stream_load_si256 (&s1.x); + + fail += check_union256i_q (res, s1.a); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-1.c new file mode 100644 index 000000000..0607a886c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpabsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_abs_epi8 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-2.c new file mode 100644 index 000000000..05db8a407 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "ssse3-vals.h" +#include "avx2-check.h" + +/* Routine to manually compute the results */ +static void +compute_pabs256 (int *i1, char *r) +{ + char *b1 = (char *) i1; + int i; + + for (i = 0; i < 32; i++) + if (b1[i] < 0) + r[i] = -b1[i]; + else + r[i] = b1[i]; +} + +static void +avx2_test (void) +{ + int i; + char ck[32]; + int fail = 0; + + union256i_b s, d; + + for (i = 0; i < 256; ++i) + { + /* Recompute the results for 256-bits */ + compute_pabs256 (&vals[i], ck); + + s.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + + /* Run the 256-bit tests */ + d.x = _mm256_abs_epi8 (s.x); + + fail += check_union256i_b (d, ck); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-1.c new file mode 100644 index 000000000..396077ff1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpabsd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_abs_epi32 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-2.c new file mode 100644 index 000000000..4c88024b5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "ssse3-vals.h" +#include "avx2-check.h" + +/* Routine to manually compute the results */ +static void +compute_pabs256 (int *i1, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + if (i1[i] < 0) + r[i] = -i1[i]; + else + r[i] = i1[i]; +} + +static void +avx2_test (void) +{ + int i; + int ck[8]; + int fail = 0; + + union256i_d s, d; + + for (i = 0; i < 256; ++i) + { + /* Recompute the results for 256-bits */ + compute_pabs256 (&vals[i], ck); + + s.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + + /* Run the 256-bit tests */ + d.x = _mm256_abs_epi32 (s.x); + + fail += check_union256i_d (d, ck); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-1.c new file mode 100644 index 000000000..2dc7692ce --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpabsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_abs_epi16 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-2.c new file mode 100644 index 000000000..fa4efd298 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "ssse3-vals.h" +#include "avx2-check.h" + +/* Routine to manually compute the results */ +static void +compute_pabs256 (int *i1, short *r) +{ + short *b1 = (short *) i1; + int i; + + for (i = 0; i < 16; i++) + if (b1[i] < 0) + r[i] = -b1[i]; + else + r[i] = b1[i]; +} + +static void +avx2_test (void) +{ + int i; + short ck[16]; + int fail = 0; + + union256i_w s, d; + + for (i = 0; i < 256; ++i) + { + /* Using only first 2 bytes of int */ + /* Recompute the results for 256-bits */ + compute_pabs256 (&vals[i], ck); + + s.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + + /* Run the 256-bit tests */ + d.x = _mm256_abs_epi16 (s.x); + + fail += check_union256i_w (d, ck); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-1.c new file mode 100644 index 000000000..6d5667a64 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpackssdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_packs_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-2.c new file mode 100644 index 000000000..16f0d23f6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static short +int_to_short (int iVal) +{ + short sVal; + + if (iVal < -32768) + sVal = -32768; + else if (iVal > 32767) + sVal = 32767; + else + sVal = iVal; + + return sVal; +} + +void static +avx2_test (void) +{ + union256i_d s1, s2; + union256i_w u; + short e[16]; + int i; + + s1.x = _mm256_set_epi32 (1, 2, 3, 4, 65000, 20, 30, 90); + + s2.x = _mm256_set_epi32 (88, 44, 33, 22, 11, 98, 76, -65000); + + u.x = _mm256_packs_epi32 (s1.x, s2.x); + + for (i = 0; i < 4; i++) + { + e[i] = int_to_short (s1.a[i]); + e[i + 4] = int_to_short (s2.a[i]); + e[i + 8] = int_to_short (s1.a[i + 4]); + e[i + 12] = int_to_short (s2.a[i + 4]); + } + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-1.c new file mode 100644 index 000000000..00faf844a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpacksswb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_packs_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-2.c new file mode 100644 index 000000000..8b2a1c111 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static char +short_to_byte (short iVal) +{ + char sVal; + + if (iVal < -128) + sVal = -128; + else if (iVal > 127) + sVal = 127; + else + sVal = iVal; + + return sVal; +} + +void static +avx2_test (void) +{ + union256i_w s1, s2; + union256i_b u; + char e[32]; + int i; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 6500, 20, 30, 90, + 88, 44, 33, 22, 11, 98, 78, -1000); + + s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, -650, + 1, 2, 3, 4, 6500, 20, 30, 90); + + u.x = _mm256_packs_epi16 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + e[i] = short_to_byte (s1.a[i]); + e[i + 8] = short_to_byte (s2.a[i]); + e[i + 16] = short_to_byte (s1.a[i + 8]); + e[i + 24] = short_to_byte (s2.a[i + 8]); + } + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-1.c new file mode 100644 index 000000000..1f0a7ff9d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpackusdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_packus_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-2.c new file mode 100644 index 000000000..afc102610 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static unsigned short +int_to_ushort (int iVal) +{ + unsigned short sVal; + + if (iVal < 0) + sVal = 0; + else if (iVal > 65536) + sVal = 65535; + else + sVal = iVal; + + return sVal; +} + +void static +avx2_test (void) +{ + union256i_d s1, s2; + union256i_w u; + unsigned short e[16]; + int i; + + s1.x = _mm256_set_epi32 (1, 2, 3, 4, -65000, 20, 30, 90); + + s2.x = _mm256_set_epi32 (88, 44, 33, 22, 11, 98, 76, 120000); + + u.x = _mm256_packus_epi32 (s1.x, s2.x); + + for (i = 0; i < 4; i++) + { + e[i] = int_to_ushort (s1.a[i]); + e[i + 4] = int_to_ushort (s2.a[i]); + e[i + 8] = int_to_ushort (s1.a[i + 4]); + e[i + 12] = int_to_ushort (s2.a[i + 4]); + } + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-1.c new file mode 100644 index 000000000..7b30a6666 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpackuswb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_packus_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-2.c new file mode 100644 index 000000000..abeee3e6d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static unsigned char +short_to_ubyte (short iVal) +{ + unsigned char sVal; + + if (iVal < 0) + sVal = 0; + else if (iVal > 255) + sVal = 255; + else + sVal = iVal; + + return sVal; +} + +void static +avx2_test (void) +{ + union256i_w s1, s2; + union256i_b u; + char e[32]; + int i; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 6500, 20, 30, 90, + 88, 44, 33, 22, 11, 98, 78, -1000); + + s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, -650, + 1, 2, 3, 4, 6500, 20, 30, 90); + + u.x = _mm256_packus_epi16 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + e[i] = short_to_ubyte (s1.a[i]); + e[i + 8] = short_to_ubyte (s2.a[i]); + e[i + 16] = short_to_ubyte (s1.a[i + 8]); + e[i + 24] = short_to_ubyte (s2.a[i + 8]); + } + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddb-1.c new file mode 100644 index 000000000..b6ceef16f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_add_epi8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddb-2.c new file mode 100644 index 000000000..8abeb50c0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddb-2.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + char e[32]; + unsigned i; + + s1.x = _mm256_set_epi8 (10, 74, 50, 4, 6, 99, 1, 4, 87, 83, 84, + 29, 81, 79, 1, 3, 1, 5, 2, 47, 20, 2, 72, + 92, 9, 4, 23, 17, 99, 43, 72, 17); + + s2.x = _mm256_set_epi8 (88, 44, 33, 20, 56, 99, 2, 90, 38, 4, 200, + 17, 3, 39, 2, 37, 27, 95, 17, 74, 72, 43, + 27, 112, 71, 50, 32, 72, 84, 17, 27, 96); + + u.x = _mm256_add_epi8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c new file mode 100644 index 000000000..238f02092 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE char +#define BIN_OP(a, b) ((a) + (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpaddb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddd-1.c new file mode 100644 index 000000000..14142ec0a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_add_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddd-2.c new file mode 100644 index 000000000..c3b196196 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddd-2.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_d u, s1, s2; + int e[8]; + unsigned i; + + s1.x = _mm256_set_epi32 (100, 74, 50000, 4, 6999, 39999, 1000, 4); + s2.x = _mm256_set_epi32 (88, 44, 33, 220, 4556, 2999, 2, 9000000); + + u.x = _mm256_add_epi32 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c new file mode 100644 index 000000000..c57ef8fea --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE int +#define BIN_OP(a, b) ((a) + (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddq-1.c new file mode 100644 index 000000000..9fcf9aaad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_add_epi64 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddq-2.c new file mode 100644 index 000000000..03b011f3f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddq-2.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_q u, s1, s2; + long long e[4]; + unsigned i; + + s1.x = _mm256_set_epi64x (100, 74, 50000, 4); + s2.x = _mm256_set_epi64x (88, 44, 33, 220); + + u.x = _mm256_add_epi64 (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union256i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c new file mode 100644 index 000000000..801bd39d8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE long long int +#define BIN_OP(a, b) ((a) + (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpaddq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-1.c new file mode 100644 index 000000000..77978d936 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_adds_epi8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-2.c new file mode 100644 index 000000000..d07a6a781 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-2.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + char e[32]; + int i, tmp; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, + 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, + -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20, + 30, 90, -80, -40, -100, -15, 98, 25, 98, 7); + + u.x = _mm256_adds_epi8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + { + tmp = s1.a[i] + s2.a[i]; + + if (tmp > 127) + tmp = 127; + if (tmp < -128) + tmp = -128; + + e[i] = tmp; + } + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-1.c new file mode 100644 index 000000000..128f5309f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_adds_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-2.c new file mode 100644 index 000000000..19bbe0a77 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_w u, s1, s2; + short e[16]; + int i, tmp; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, -80, + -40, -100, -15, 98, 25, 98, 7); + + s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, -100, + -34, -78, -39, 6, 3, 4, 5, 119); + + u.x = _mm256_adds_epi16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + { + tmp = s1.a[i] + s2.a[i]; + + if (tmp > 32767) + tmp = 32767; + if (tmp < -32768) + tmp = -32768; + + e[i] = tmp; + } + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-1.c new file mode 100644 index 000000000..f6cf4019c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddusb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_adds_epu8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-2.c new file mode 100644 index 000000000..68ad4f03f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + unsigned char e[32]; + unsigned i, tmp; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, 80, 40, 100, 15, + 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, 76, + 200, 34, 78, 39, 6, 3, 4, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 33, 220, 11, 98, 76, 100, 34, 78, 39, + 6, 3, 4, 5, 219, 1, 2, 3, 4, 10, 20, 30, 90, + 80, 40, 100, 15, 98, 25, 98, 7); + + u.x = _mm256_adds_epu8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + { + tmp = (unsigned char) s1.a[i] + (unsigned char) s2.a[i]; + + if (tmp > 255) + tmp = 255; + + e[i] = tmp; + } + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-1.c new file mode 100644 index 000000000..a4c1dd9bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddusw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_adds_epu16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-2.c new file mode 100644 index 000000000..937b93c21 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-2.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_w u, s1, s2; + unsigned short e[32]; + unsigned i, tmp; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, + 65531, 40, 100, 15, 98, 25, 98, 7); + + s2.x = _mm256_set_epi16 (88, 44, 33, 220, 11, 98, 76, 100, + 34, 78, 39, 6, 3, 4, 5, 219); + + u.x = _mm256_adds_epu16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + { + tmp = (unsigned short) s1.a[i] + (unsigned short) s2.a[i]; + + if (tmp > 65535) + tmp = 65535; + + e[i] = tmp; + } + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddw-1.c new file mode 100644 index 000000000..052e3a352 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpaddw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_add_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddw-2.c new file mode 100644 index 000000000..f7dbf2053 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddw-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_w u, s1, s2; + short e[16]; + unsigned i; + + s1.x = _mm256_set_epi16 (100, 74, 50000, 4, 6999, 39999, 1000, 4, + 874, 2783, 29884, 2904, 2889, 3279, 1, 3); + s2.x = _mm256_set_epi16 (88, 44, 33, 220, 4556, 2999, 2, 9000, + 238, 194, 274, 17, 3, 5739, 2, 379); + + u.x = _mm256_add_epi16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c new file mode 100644 index 000000000..facee9f2d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE short +#define BIN_OP(a, b) ((a) + (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpaddw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-1.c new file mode 100644 index 000000000..a87a207d4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx2" } */ +/* { dg-final { scan-assembler "vpalignr\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + /* imm = 13 is arbitrary here */ + x = _mm256_alignr_epi8 (x, x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-2.c new file mode 100644 index 000000000..5be64c0cf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-2.c @@ -0,0 +1,177 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "ssse3-vals.h" +#include "avx2-check.h" + +/* Test the 256-bit form */ +static void +avx2_test_palignr256 (__m256i t1, __m256i t2, unsigned int imm, __m256i * r) +{ + switch (imm) + { + case 0: + *r = _mm256_alignr_epi8 (t1, t2, 0); + break; + case 1: + *r = _mm256_alignr_epi8 (t1, t2, 1); + break; + case 2: + *r = _mm256_alignr_epi8 (t1, t2, 2); + break; + case 3: + *r = _mm256_alignr_epi8 (t1, t2, 3); + break; + case 4: + *r = _mm256_alignr_epi8 (t1, t2, 4); + break; + case 5: + *r = _mm256_alignr_epi8 (t1, t2, 5); + break; + case 6: + *r = _mm256_alignr_epi8 (t1, t2, 6); + break; + case 7: + *r = _mm256_alignr_epi8 (t1, t2, 7); + break; + case 8: + *r = _mm256_alignr_epi8 (t1, t2, 8); + break; + case 9: + *r = _mm256_alignr_epi8 (t1, t2, 9); + break; + case 10: + *r = _mm256_alignr_epi8 (t1, t2, 10); + break; + case 11: + *r = _mm256_alignr_epi8 (t1, t2, 11); + break; + case 12: + *r = _mm256_alignr_epi8 (t1, t2, 12); + break; + case 13: + *r = _mm256_alignr_epi8 (t1, t2, 13); + break; + case 14: + *r = _mm256_alignr_epi8 (t1, t2, 14); + break; + case 15: + *r = _mm256_alignr_epi8 (t1, t2, 15); + break; + case 16: + *r = _mm256_alignr_epi8 (t1, t2, 16); + break; + case 17: + *r = _mm256_alignr_epi8 (t1, t2, 17); + break; + case 18: + *r = _mm256_alignr_epi8 (t1, t2, 18); + break; + case 19: + *r = _mm256_alignr_epi8 (t1, t2, 19); + break; + case 20: + *r = _mm256_alignr_epi8 (t1, t2, 20); + break; + case 21: + *r = _mm256_alignr_epi8 (t1, t2, 21); + break; + case 22: + *r = _mm256_alignr_epi8 (t1, t2, 22); + break; + case 23: + *r = _mm256_alignr_epi8 (t1, t2, 23); + break; + case 24: + *r = _mm256_alignr_epi8 (t1, t2, 24); + break; + case 25: + *r = _mm256_alignr_epi8 (t1, t2, 25); + break; + case 26: + *r = _mm256_alignr_epi8 (t1, t2, 26); + break; + case 27: + *r = _mm256_alignr_epi8 (t1, t2, 27); + break; + case 28: + *r = _mm256_alignr_epi8 (t1, t2, 28); + break; + case 29: + *r = _mm256_alignr_epi8 (t1, t2, 29); + break; + case 30: + *r = _mm256_alignr_epi8 (t1, t2, 30); + break; + case 31: + *r = _mm256_alignr_epi8 (t1, t2, 31); + break; + default: + *r = _mm256_alignr_epi8 (t1, t2, 32); + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result_256 (int *i1, int *i2, unsigned int imm, int *r) +{ + char buf[32]; + char *bout = (char *) r; + int i; + + /* Fill lowers 128 bit of ymm */ + memcpy (&buf[0], i2, 16); + memcpy (&buf[16], i1, 16); + + for (i = 0; i < 16; i++) + if (imm >= 32 || imm + i >= 32) + bout[i] = 0; + else + bout[i] = buf[imm + i]; + + /* Fill higher 128 bit of ymm */ + bout += 16; + memcpy (&buf[0], i2 + 4, 16); + memcpy (&buf[16], i1 + 4, 16); + + for (i = 0; i < 16; i++) + if (imm >= 32 || imm + i >= 32) + bout[i] = 0; + else + bout[i] = buf[imm + i]; +} + +static void +avx2_test (void) +{ + int i; + int ck[8]; + int r[8]; + unsigned int imm; + int fail = 0; + + union256i_q s1, s2, d; + + for (i = 0; i < 256; i += 16) + for (imm = 0; imm < 100; imm++) + { + /* Recompute the results for 256-bits */ + compute_correct_result_256 (&vals[i + 0], &vals[i + 8], imm, ck); + + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 0]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + /* Run the 256-bit tests */ + avx2_test_palignr256 (s1.x, s2.x, imm, &d.x); + + _mm256_storeu_si256 ((__m256i *) r, d.x); + + fail += checkVi (r, ck, 8); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpand-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpand-1.c new file mode 100644 index 000000000..e77e36982 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpand-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpand\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_and_si256 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpand-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpand-2.c new file mode 100644 index 000000000..ffd3404e5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpand-2.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + int i; + union256i_q u, s1, s2; + int source1[8] = { 34545, 95567, 23443, 5675, 2323, 67, 2345, 45667 }; + int source2[8] = { 674, 57897, 93459, 45624, 54674, 1237, 67436, 79608 }; + int d[8]; + int e[8]; + + s1.x = _mm256_loadu_si256 ((__m256i *) source1); + s2.x = _mm256_loadu_si256 ((__m256i *) source2); + u.x = _mm256_and_si256 (s1.x, s2.x); + + _mm256_storeu_si256 ((__m256i *) d, u.x); + + for (i = 0; i < 8; i++) + e[i] = source1[i] & source2[i]; + + if (checkVi (d, e, 8)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c new file mode 100644 index 000000000..67ca4a7cd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE unsigned +#define BIN_OP(a, b) ((a) & (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpand\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpandn-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpandn-1.c new file mode 100644 index 000000000..b06889884 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpandn-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpandn\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_andnot_si256 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpandn-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpandn-2.c new file mode 100644 index 000000000..06d3cbd23 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpandn-2.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + int i; + union256i_q u, s1, s2; + int source1[8] = { 34545, 95567, 23443, 5675, 2323, 67, 2345, 45667 }; + int source2[8] = { 674, 57897, 93459, 45624, 54674, 1237, 67436, 79608 }; + int d[8]; + int e[8]; + + s1.x = _mm256_loadu_si256 ((__m256i *) source1); + s2.x = _mm256_loadu_si256 ((__m256i *) source2); + u.x = _mm256_andnot_si256 (s1.x, s2.x); + + _mm256_storeu_si256 ((__m256i *) d, u.x); + + for (i = 0; i < 8; i++) + e[i] = (~source1[i]) & source2[i]; + + if (checkVi (d, e, 8)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpavgb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpavgb-1.c new file mode 100644 index 000000000..a7abd6751 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpavgb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpavgb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_avg_epu8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpavgb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpavgb-2.c new file mode 100644 index 000000000..8519e9bc3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpavgb-2.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + unsigned char e[32]; + int tmp; + int i; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, + 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, + -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20, + 30, 90, -80, -40, -100, -15, 98, 25, 98, 7); + + u.x = _mm256_avg_epu8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + e[i] = ((unsigned char) s1.a[i] + (unsigned char) s2.a[i] + 1) >> 1; + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpavgw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpavgw-1.c new file mode 100644 index 000000000..dc68b8a6b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpavgw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpavgw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_avg_epu16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpavgw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpavgw-2.c new file mode 100644 index 000000000..d222a9d4a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpavgw-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_w u, s1, s2; + unsigned short e[32]; + int i; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, 80, + 40, 100, 15, 98, 25, 98, 7); + s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, 100, + 34, 78, 39, 6, 3, 4, 5, 119); + + u.x = _mm256_avg_epu16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = (s1.a[i] + s2.a[i] + 1) >> 1; + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-1.c new file mode 100644 index 000000000..92f7e1b8e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpblendd\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_blend_epi32 (x, x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-2.c new file mode 100644 index 000000000..44732cc6f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 20 + +#undef MASK +#define MASK 0xf1 + +static void +init_pblendd128 (int *src1, int *src2, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 4; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed + 20) * sign; + sign = -sign; + } +} + +static void +calc_pblendd128 (int *src1, int *src2, unsigned int mask, int *dst) +{ + int i; + + memcpy (dst, src1, 16); + for (i = 0; i < 4; i++) + if (mask & (1 << i)) + dst[i] = src2[i]; +} + +static void +avx2_test (void) +{ + union128i_d src1, src2, dst; + int dst_ref[4]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pblendd128 (src1.a, src2.a, i); + + dst.x = _mm_blend_epi32 (src1.x, src2.x, MASK); + calc_pblendd128 (src1.a, src2.a, MASK, dst_ref); + + if (check_union128i_d (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-1.c new file mode 100644 index 000000000..ab7498854 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpblendd\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_blend_epi32 (x, x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-2.c new file mode 100644 index 000000000..fc5e3f7be --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 20 + +#undef MASK +#define MASK 0xf1 + +static void +init_pblendd256 (int *src1, int *src2, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 8; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed + 20) * sign; + sign = -sign; + } +} + +static void +calc_pblendd256 (int *src1, int *src2, unsigned int mask, int *dst) +{ + int i; + + memcpy (dst, src1, 32); + for (i = 0; i < 8; i++) + if (mask & (1 << i)) + dst[i] = src2[i]; +} + +static void +avx2_test (void) +{ + union256i_d src1, src2, dst; + int dst_ref[8]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pblendd256 (src1.a, src2.a, i); + + dst.x = _mm256_blend_epi32 (src1.x, src2.x, MASK); + calc_pblendd256 (src1.a, src2.a, MASK, dst_ref); + + if (check_union256i_d (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-1.c new file mode 100644 index 000000000..09ff4bcca --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpblendvb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_blendv_epi8 (x, x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-2.c new file mode 100644 index 000000000..c0e1d71ea --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-2.c @@ -0,0 +1,56 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 20 + +static void +init_pblendb (char *src1, char *src2, char *mask, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 32; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed + 20) * sign; + sign = -sign; + + if (sign > 0) + mask[i] = 1 << 7; + else + mask[i] = 0; + } +} + +static void +calc_pblendb (char *src1, char *src2, char *mask, char *dst) +{ + int i; + + memcpy (dst, src1, 32); + for (i = 0; i < 32; i++) + if (mask[i] & (1 << 7)) + dst[i] = src2[i]; +} + +static void +avx2_test (void) +{ + union256i_b src1, src2, mask, dst; + char dst_ref[32]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pblendb (src1.a, src2.a, mask.a, i); + + dst.x = _mm256_blendv_epi8 (src1.x, src2.x, mask.x); + calc_pblendb (src1.a, src2.a, mask.a, dst_ref); + + if (check_union256i_b (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendw-1.c new file mode 100644 index 000000000..7bbb93e4a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpblendw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_blend_epi16 (x, x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendw-2.c new file mode 100644 index 000000000..0500d351e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpblendw-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 20 + +#undef MASK +#define MASK 0xfe + +static void +init_pblendw (short *src1, short *src2, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 16; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed + 20) * sign; + sign = -sign; + } +} + +static void +calc_pblendw (short *src1, short *src2, unsigned int mask, short *dst) +{ + int i; + + memcpy (dst, src1, 32); + for (i = 0; i < 16; i++) + if (mask & (1 << (i % 8))) + dst[i] = src2[i]; +} + +static void +avx2_test (void) +{ + union256i_w src1, src2, dst; + short dst_ref[16]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pblendw (src1.a, src2.a, i); + + dst.x = _mm256_blend_epi16 (src1.x, src2.x, MASK); + calc_pblendw (src1.a, src2.a, MASK, dst_ref); + + if (check_union256i_w (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-1.c new file mode 100644 index 000000000..14b9a7c09 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastb\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_broadcastb_epi8 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-2.c new file mode 100644 index 000000000..927755b2a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastb128 (char *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 16; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastb128 (char *src, char *dst) +{ + int i; + + for (i = 0; i < 16; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_b src, dst; + char dst_ref[16]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastb128 (src.a, i); + + dst.x = _mm_broadcastb_epi8 (src.x); + calc_pbroadcastb128 (src.a, dst_ref); + + if (check_union128i_b (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-1.c new file mode 100644 index 000000000..8e1247aac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i y; + +void extern +avx2_test (void) +{ + y = _mm256_broadcastb_epi8 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-2.c new file mode 100644 index 000000000..9b0e56469 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-2.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastb256 (char *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 16; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastb256 (char *src, char *dst) +{ + int i; + + for (i = 0; i < 32; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_b src; + union256i_b dst; + char dst_ref[32]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastb256 (src.a, i); + + dst.x = _mm256_broadcastb_epi8 (src.x); + calc_pbroadcastb256 (src.a, dst_ref); + + if (check_union256i_b (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-1.c new file mode 100644 index 000000000..8a396678e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_broadcastd_epi32 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-2.c new file mode 100644 index 000000000..c9d2b46d2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastd128 (int *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 4; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastd128 (int *src, int *dst) +{ + int i; + + for (i = 0; i < 4; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_d src, dst; + int dst_ref[4]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastd128 (src.a, i); + + dst.x = _mm_broadcastd_epi32 (src.x); + calc_pbroadcastd128 (src.a, dst_ref); + + if (check_union128i_d (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-1.c new file mode 100644 index 000000000..57f1bc78e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i y; + +void extern +avx2_test (void) +{ + y = _mm256_broadcastd_epi32 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-2.c new file mode 100644 index 000000000..fe009da1a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-2.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastd256 (int *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 4; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastd256 (int *src, int *dst) +{ + int i; + + for (i = 0; i < 8; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_d src; + union256i_d dst; + int dst_ref[8]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastd256 (src.a, i); + + dst.x = _mm256_broadcastd_epi32 (src.x); + calc_pbroadcastd256 (src.a, dst_ref); + + if (check_union256i_d (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-1.c new file mode 100644 index 000000000..6714ae7ff --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastq\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_broadcastq_epi64 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-2.c new file mode 100644 index 000000000..e6446de7d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastq128 (long long int *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 2; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastq128 (long long int *src, long long int *dst) +{ + int i; + + for (i = 0; i < 2; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_q src, dst; + long long int dst_ref[2]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastq128 (src.a, i); + + dst.x = _mm_broadcastq_epi64 (src.x); + calc_pbroadcastq128 (src.a, dst_ref); + + if (check_union128i_q (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-1.c new file mode 100644 index 000000000..bf1532b1e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i y; + +void extern +avx2_test (void) +{ + y = _mm256_broadcastq_epi64 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-2.c new file mode 100644 index 000000000..470263156 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-2.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastq256 (long long int *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 2; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastq256 (long long int *src, long long int *dst) +{ + int i; + + for (i = 0; i < 4; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_q src; + union256i_q dst; + long long int dst_ref[4]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastq256 (src.a, i); + + dst.x = _mm256_broadcastq_epi64 (src.x); + calc_pbroadcastq256 (src.a, dst_ref); + + if (check_union256i_q (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-1.c new file mode 100644 index 000000000..ff5ee8741 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastw\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_broadcastw_epi16 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-2.c new file mode 100644 index 000000000..e8673a9dd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastw128 (short *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 8; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastw128 (short *src, short *dst) +{ + int i; + + for (i = 0; i < 8; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_w src, dst; + short dst_ref[8]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastw128 (src.a, i); + + dst.x = _mm_broadcastw_epi16 (src.x); + calc_pbroadcastw128 (src.a, dst_ref); + + if (check_union128i_w (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-1.c new file mode 100644 index 000000000..14462a19b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpbroadcastw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i y; + +void extern +avx2_test (void) +{ + y = _mm256_broadcastw_epi16 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-2.c new file mode 100644 index 000000000..bac748fef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-2.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_pbroadcastw256 (short *src, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 8; i++) + { + src[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_pbroadcastw256 (short *src, short *dst) +{ + int i; + + for (i = 0; i < 16; i++) + dst[i] = src[0]; +} + +static void +avx2_test (void) +{ + union128i_w src; + union256i_w dst; + short dst_ref[16]; + int i; + + for (i = 0; i < NUM; i++) + { + init_pbroadcastw256 (src.a, i); + + dst.x = _mm256_broadcastw_epi16 (src.x); + calc_pbroadcastw256 (src.a, dst_ref); + + if (check_union256i_w (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-1.c new file mode 100644 index 000000000..063cb5750 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpeqb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpeq_epi8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-2.c new file mode 100644 index 000000000..87a8fa42c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-2.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_b u, s1, s2; + char e[32]; + int i; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, + 76, -100, -34, -78, -39, 6, 3, 25, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 3, 22, 11, 98, 76, -100, -34, -78, + -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20, + 30, 90, -80, -40, -100, -15, 98, 25, 98, 7); + + u.x = _mm256_cmpeq_epi8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + e[i] = (s1.a[i] == s2.a[i]) ? -1 : 0; + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-1.c new file mode 100644 index 000000000..002b69686 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpeqd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpeq_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-2.c new file mode 100644 index 000000000..0cc10458f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-2.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_d u, s1, s2; + int e[8]; + int i; + + s1.x = _mm256_set_epi32 (1, 2, 3, 4, 10, 20, 30, 90000); + + s2.x = _mm256_set_epi32 (88, 44, 3, 22, 11, 98, 76, -100); + + u.x = _mm256_cmpeq_epi32 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = (s1.a[i] == s2.a[i]) ? -1 : 0; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-1.c new file mode 100644 index 000000000..196e3c311 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpeqq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpeq_epi64 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-2.c new file mode 100644 index 000000000..4abe78198 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-2.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_q u, s1, s2; + long long int e[4]; + int i; + + s1.x = _mm256_set_epi64x (1, 2, 3, 4); + + s2.x = _mm256_set_epi64x (88, 44, 3, 220000); + + u.x = _mm256_cmpeq_epi64 (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = (s1.a[i] == s2.a[i]) ? -1 : 0; + + if (check_union256i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-1.c new file mode 100644 index 000000000..1efa29143 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpeqw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpeq_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-2.c new file mode 100644 index 000000000..9fb38de2c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-2.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_w u, s1, s2; + short e[16]; + int i; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + 76, -100, -34, -78, -31000); + + s2.x = _mm256_set_epi16 (88, 44, 3, 22, 11, 98, 76, -100, -34, -78, + 30, 90, -80, -40, -100, -15); + + u.x = _mm256_cmpeq_epi16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = (s1.a[i] == s2.a[i]) ? -1 : 0; + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-1.c new file mode 100644 index 000000000..d8b35bba7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpgtb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpgt_epi8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-2.c new file mode 100644 index 000000000..b76077c20 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-2.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_b u, s1, s2; + char e[32]; + int i; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, + 76, -100, -34, -78, -39, 6, 3, 25, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 3, 22, 11, 98, 76, -100, -34, -78, + -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20, + 30, 90, -80, -40, -100, -15, 98, 25, 98, 7); + + u.x = _mm256_cmpgt_epi8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + e[i] = (s1.a[i] > s2.a[i]) ? -1 : 0; + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-1.c new file mode 100644 index 000000000..75e4b24e6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpgtd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpgt_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-2.c new file mode 100644 index 000000000..371bd79fa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-2.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_d u, s1, s2; + int e[8]; + int i; + + s1.x = _mm256_set_epi32 (1, 2, 3, 4, 10, 20, 30, 90000); + + s2.x = _mm256_set_epi32 (88, 44, 3, 22, 11, 98, 76, -100); + + u.x = _mm256_cmpgt_epi32 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = (s1.a[i] > s2.a[i]) ? -1 : 0; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c new file mode 100644 index 000000000..7a983808b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpgtq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpgt_epi64 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-2.c new file mode 100644 index 000000000..8d5cf3ee8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-2.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_q u, s1, s2; + long long int e[4]; + int i; + + s1.x = _mm256_set_epi64x (1, 2, 3, 4); + + s2.x = _mm256_set_epi64x (88, 44, 3, 220000); + + u.x = _mm256_cmpgt_epi64 (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = (s1.a[i] > s2.a[i]) ? -1 : 0; + + if (check_union256i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-1.c new file mode 100644 index 000000000..f2ed47298 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpcmpgtw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_cmpgt_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-2.c new file mode 100644 index 000000000..490878f8b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-2.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_w u, s1, s2; + short e[16]; + int i; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + 76, -100, -34, -78, -31000); + + s2.x = _mm256_set_epi16 (88, 44, 3, 22, 11, 98, 76, -100, -34, -78, + 30, 90, -80, -40, -100, -15); + + u.x = _mm256_cmpgt_epi16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = (s1.a[i] > s2.a[i]) ? -1 : 0; + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-1.c new file mode 100644 index 000000000..518ff333b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vperm2i128\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_permute2x128_si256 (x, x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-2.c new file mode 100644 index 000000000..96f32b8f0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-2.c @@ -0,0 +1,84 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +#define MASK 0xf1 + +static void +init_perm2i128 (unsigned long long *src1, unsigned long long *src2, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 4; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed) * seed * sign; + sign = -sign; + } +} + +static void +calc_perm2i128 (unsigned long long *src1, + unsigned long long *src2, + unsigned int mask, unsigned long long *dst) +{ + int i, temp; + + temp = mask & 3; + + switch (temp) + { + case 0: + memcpy (dst, src1, 16); + case 1: + memcpy (dst, src1 + 2, 16); + case 2: + memcpy (dst, src2, 16); + case 3: + memcpy (dst, src1 + 2, 16); + } + + temp = (mask >> 4) & 3; + + switch (temp) + { + case 0: + memcpy (dst + 2, src1, 16); + case 1: + memcpy (dst + 2, src1 + 2, 16); + case 2: + memcpy (dst + 2, src2, 16); + case 3: + memcpy (dst + 2, src1 + 2, 16); + } + + if ((mask >> 3) & 1) + memset (dst, 0, 16); + + if ((mask >> 7) & 1) + memset (dst + 2, 0, 16); +} + +static void +avx2_test (void) +{ + union256i_q src1, src2, dst; + unsigned long long dst_ref[4]; + int i; + + for (i = 0; i < NUM; i++) + { + init_perm2i128 (src1.a, src2.a, i); + + dst.x = _mm256_permute2x128_si256 (src1.x, src2.x, MASK); + calc_perm2i128 (src1.a, src2.a, MASK, dst_ref); + + if (check_union256i_q (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermd-1.c new file mode 100644 index 000000000..939f33895 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpermd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_permutevar8x32_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermd-2.c new file mode 100644 index 000000000..a663337e9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermd-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_permd (int *src1, int *src2, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 8; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed + 20) * sign; + sign = -sign; + } +} + +static void +calc_permd (int *src1, int *src2, int *dst) +{ + int i; + unsigned temp; + + memcpy (dst, src1, 32); + for (i = 0; i < 8; i++) + { + temp = src2[i]; + dst[i] = src1[temp & 7]; + } +} + +static void +avx2_test (void) +{ + union256i_d src1, src2, dst; + int dst_ref[8]; + int i; + + for (i = 0; i < NUM; i++) + { + init_permd (src1.a, src2.a, i); + + dst.x = _mm256_permutevar8x32_epi32 (src1.x, src2.x); + calc_permd (src1.a, src2.a, dst_ref); + + if (check_union256i_d (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermpd-1.c new file mode 100644 index 000000000..62ca67cc4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermpd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpermpd\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +__m256d x; + +void extern +avx2_test (void) +{ + x = _mm256_permute4x64_pd (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermpd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermpd-2.c new file mode 100644 index 000000000..1097e5cd1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermpd-2.c @@ -0,0 +1,55 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define MASK 0x1a + +#define NUM 10 + +static void +init_permpd (double *src1, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 4; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_permpd (double *src1, int mask, double *dst) +{ + int i; + unsigned temp; + + memcpy (dst, src1, 32); + for (i = 0; i < 4; i++) + { + temp = mask >> (i * 2); + dst[i] = src1[temp & 3]; + } +} + +static void +avx2_test (void) +{ + union256d src1, dst; + double dst_ref[4]; + int i; + + for (i = 0; i < NUM; i++) + { + init_permpd (src1.a, i); + + dst.x = _mm256_permute4x64_pd (src1.x, MASK); + calc_permpd (src1.a, MASK, dst_ref); + + if (check_union256d (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermps-1.c new file mode 100644 index 000000000..bf436599d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermps-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpermps\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m256 x; +__m256i y; + +void extern +avx2_test (void) +{ + x = _mm256_permutevar8x32_ps (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermps-2.c new file mode 100644 index 000000000..4190189a8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermps-2.c @@ -0,0 +1,55 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +static void +init_permps (float *src1, int *src2, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 8; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + src2[i] = (i + seed + 20) * sign; + sign = -sign; + } +} + +static void +calc_permps (float *src1, int *src2, float *dst) +{ + int i; + unsigned temp; + + memcpy (dst, src1, 32); + for (i = 0; i < 8; i++) + { + temp = src2[i]; + dst[i] = src1[temp & 7]; + } +} + +static void +avx2_test (void) +{ + union256 src1, dst; + union256i_d src2; + float dst_ref[8]; + int i; + + for (i = 0; i < NUM; i++) + { + init_permps (src1.a, src2.a, i); + + dst.x = _mm256_permutevar8x32_ps (src1.x, src2.x); + calc_permps (src1.a, src2.a, dst_ref); + + if (check_union256 (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermq-1.c new file mode 100644 index 000000000..533af89a9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpermq\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_permute4x64_epi64 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermq-2.c new file mode 100644 index 000000000..2d8c34402 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpermq-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include <string.h> + +#define NUM 10 + +#define MASK 0xf1 + +static void +init_permq (unsigned long long *src1, int seed) +{ + int i, sign = 1; + + for (i = 0; i < 4; i++) + { + src1[i] = (i + seed) * (i + seed) * sign; + sign = -sign; + } +} + +static void +calc_permq (unsigned long long *src1, unsigned int mask, + unsigned long long *dst) +{ + int i, temp; + + for (i = 0; i < 4; i++) + { + temp = (mask >> (2 * i)) & 3; + dst[i] = src1[temp]; + } +} + +static void +avx2_test (void) +{ + union256i_q src1, dst; + unsigned long long dst_ref[4]; + int i; + + for (i = 0; i < NUM; i++) + { + init_permq (src1.a, i); + + dst.x = _mm256_permute4x64_epi64 (src1.x, MASK); + calc_permq (src1.a, MASK, dst_ref); + + if (check_union256i_q (dst, dst_ref)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddd-1.c new file mode 100644 index 000000000..2fb0fd7f2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vphaddd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_hadd_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddd-2.c new file mode 100644 index 000000000..0d686cb4f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddd-2.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static void +compute_phaddd256 (int *i1, int *i2, int *r) +{ + int i; + + for (i = 0; i < 2; i++) + r[i + 0] = i1[2 * i] + i1[2 * i + 1]; + + for (i = 0; i < 2; i++) + r[i + 2] = i2[2 * i] + i2[2 * i + 1]; + + for (i = 0; i < 2; i++) + r[i + 4] = i1[2 * i + 4] + i1[2 * i + 5]; + + for (i = 0; i < 2; i++) + r[i + 6] = i2[2 * i + 4] + i2[2 * i + 5]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j; + int fail = 0; + + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_hadd_epi32 (s1.x, s2.x); + + compute_phaddd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-1.c new file mode 100644 index 000000000..dbedf69de --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vphaddsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_hadds_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-2.c new file mode 100644 index 000000000..371984776 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-2.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static short +signed_saturate_to_word (int x) +{ + if (x > (int) 0x7fff) + return 0x7fff; + + if (x < (int) 0xffff8000) + return 0x8000; + + return (short) x; +} + +static void +compute_phaddsw256 (short *i1, short *i2, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i + 0] = signed_saturate_to_word (i1[2 * i] + i1[2 * i + 1]); + + for (i = 0; i < 4; i++) + r[i + 4] = signed_saturate_to_word (i2[2 * i] + i2[2 * i + 1]); + + for (i = 0; i < 4; i++) + r[i + 8] = signed_saturate_to_word (i1[2 * i + 8] + i1[2 * i + 9]); + + for (i = 0; i < 4; i++) + r[i + 12] = signed_saturate_to_word (i2[2 * i + 8] + i2[2 * i + 9]); +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j; + int fail = 0; + + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_hadds_epi16 (s1.x, s2.x); + + compute_phaddsw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddw-1.c new file mode 100644 index 000000000..c0bdac2f9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vphaddw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_hadd_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddw-2.c new file mode 100644 index 000000000..8811e99d6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphaddw-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static void +compute_phaddw256 (short *i1, short *i2, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i + 0] = i1[2 * i] + i1[2 * i + 1]; + + for (i = 0; i < 4; i++) + r[i + 4] = i2[2 * i] + i2[2 * i + 1]; + + for (i = 0; i < 4; i++) + r[i + 8] = i1[2 * i + 8] + i1[2 * i + 9]; + + for (i = 0; i < 4; i++) + r[i + 12] = i2[2 * i + 8] + i2[2 * i + 9]; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i; + int fail = 0; + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_hadd_epi16 (s1.x, s2.x); + + compute_phaddw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubd-1.c new file mode 100644 index 000000000..d4ede9db0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vphsubd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_hsub_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubd-2.c new file mode 100644 index 000000000..ba4936792 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubd-2.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static void +compute_phsubd256 (int *i1, int *i2, int *r) +{ + int i; + + for (i = 0; i < 2; i++) + r[i + 0] = i1[2 * i] - i1[2 * i + 1]; + + for (i = 0; i < 2; i++) + r[i + 2] = i2[2 * i] - i2[2 * i + 1]; + + for (i = 0; i < 2; i++) + r[i + 4] = i1[2 * i + 4] - i1[2 * i + 5]; + + for (i = 0; i < 2; i++) + r[i + 6] = i2[2 * i + 4] - i2[2 * i + 5]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j; + int fail = 0; + + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_hsub_epi32 (s1.x, s2.x); + + compute_phsubd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-1.c new file mode 100644 index 000000000..d941f44b3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vphsubsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_hsubs_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-2.c new file mode 100644 index 000000000..1ed099090 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-2.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static short +signed_saturate_to_word (int x) +{ + if (x > (int) 0x7fff) + return 0x7fff; + + if (x < (int) 0xffff8000) + return 0x8000; + + return (short) x; +} + +static void +compute_phsubsw256 (short *i1, short *i2, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i + 0] = signed_saturate_to_word (i1[2 * i] - i1[2 * i + 1]); + + for (i = 0; i < 4; i++) + r[i + 4] = signed_saturate_to_word (i2[2 * i] - i2[2 * i + 1]); + + for (i = 0; i < 4; i++) + r[i + 8] = signed_saturate_to_word (i1[2 * i + 8] - i1[2 * i + 9]); + + for (i = 0; i < 4; i++) + r[i + 12] = signed_saturate_to_word (i2[2 * i + 8] - i2[2 * i + 9]); +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i; + int fail = 0; + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_hsubs_epi16 (s1.x, s2.x); + + compute_phsubsw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubw-1.c new file mode 100644 index 000000000..f336fad48 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vphsubw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vphsubw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_hsub_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-1.c new file mode 100644 index 000000000..6ab19103d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaddubsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_maddubs_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-2.c new file mode 100644 index 000000000..5761d8f44 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-2.c @@ -0,0 +1,59 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static short +signed_saturate_to_word (int x) +{ + if (x > (int) 0x7fff) + return 0x7fff; + + if (x < (int) 0xffff8000) + return 0x8000; + + return (short) x; +} + +static void +compute_pmaddubsw256 (short *i1, short *i2, short *r) +{ + unsigned char *ub1 = (unsigned char *) i1; + char *sb2 = (char *) i2; + short *sout = (short *) r; + int t0; + int i; + + for (i = 0; i < 16; i++) + { + t0 = ((int) ub1[2 * i] * (int) sb2[2 * i] + + (int) ub1[2 * i + 1] * (int) sb2[2 * i + 1]); + sout[i] = signed_saturate_to_word (t0); + } +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i; + int fail = 0; + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_maddubs_epi16 (s1.x, s2.x); + + compute_pmaddubsw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-1.c new file mode 100644 index 000000000..97de707ba --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaddwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_madd_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-2.c new file mode 100644 index 000000000..d539d3943 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" +#include "ssse3-vals.h" + +static void +compute_pmaddwd256 (short *i1, short *i2, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = ((int) i1[2 * i] * (int) i2[2 * i] + + (int) i1[2 * i + 1] * (int) i2[2 * i + 1]); +} + +static void +avx2_test (void) +{ + union256i_w s1, s2; + union256i_d res; + int res_ref[8]; + int i; + int fail = 0; + + for (i = 0; i < 256; i += 16) + { + s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]); + s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]); + + res.x = _mm256_madd_epi16 (s1.x, s2.x); + + compute_pmaddwd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-1.c new file mode 100644 index 000000000..917de5136 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovd\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *y; + +void extern +avx2_test (void) +{ + x = _mm_maskload_epi32 (y, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-2.c new file mode 100644 index 000000000..9bc3f31be --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-2.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 134 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) + +void static +avx2_test (void) +{ + int i; + int m[4] = { mask_v (0), mask_v (1), mask_v (2), mask_v (3) }; + int s[4] = { 1, 2, 3, 4 }; + union128i_d u, mask; + int e[4] = { 0 }; + + mask.x = _mm_loadu_si128 ((__m128i *) m); + u.x = _mm_maskload_epi32 (s, mask.x); + + for (i = 0; i < 4; i++) + e[i] = m[i] ? s[i] : 0; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-1.c new file mode 100644 index 000000000..aa9438c93 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovd\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +int *y; + +void extern +avx2_test (void) +{ + x = _mm256_maskload_epi32 (y, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-2.c new file mode 100644 index 000000000..b5a82bddd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-2.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 134 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) + +void static +avx2_test (void) +{ + int i; + int m[8] = + { mask_v (0), mask_v (1), mask_v (2), mask_v (3), mask_v (4), mask_v (5), +mask_v (6), mask_v (7) }; + int s[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; + union256i_d u, mask; + int e[8] = { 0 }; + + mask.x = _mm256_loadu_si256 ((__m256i *) m); + u.x = _mm256_maskload_epi32 (s, mask.x); + + for (i = 0; i < 8; i++) + e[i] = m[i] ? s[i] : 0; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-1.c new file mode 100644 index 000000000..24768b8f8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovq\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +__m128i x; +long long int *y; + +void extern +avx2_test (void) +{ + x = _mm_maskload_epi64 (y, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-2.c new file mode 100644 index 000000000..ca7abadca --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-2.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 7 +#endif + +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) + +void static +avx2_test (void) +{ + int i; + long long m[2] = { mask_v (0), mask_v (1) }; + long long s[2] = { 1, 2 }; + union128i_q u, mask; + long long e[2] = { 0 }; + + mask.x = _mm_loadu_si128 ((__m128i *) m); + u.x = _mm_maskload_epi64 (s, mask.x); + + for (i = 0; i < 2; i++) + e[i] = m[i] ? s[i] : 0; + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-1.c new file mode 100644 index 000000000..9b824eb57 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovq\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +long long int *y; + +void extern +avx2_test (void) +{ + x = _mm256_maskload_epi64 (y, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-2.c new file mode 100644 index 000000000..c74d15304 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-2.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 7 +#endif + +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) + +void static +avx2_test (void) +{ + int i; + long long m[4] = { mask_v (0), mask_v (1), mask_v (2), mask_v (3) }; + long long s[4] = { 1, 2, 3, 4 }; + union256i_q u, mask; + long long e[4] = { 0 }; + + mask.x = _mm256_loadu_si256 ((__m256i *) m); + u.x = _mm256_maskload_epi64 (s, mask.x); + + for (i = 0; i < 4; i++) + e[i] = m[i] ? s[i] : 0; + + if (check_union256i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-1.c new file mode 100644 index 000000000..0731d1ae1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovd\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +__m128i x; +int *y; + +void extern +avx2_test (void) +{ + _mm_maskstore_epi32 (y, x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-2.c new file mode 100644 index 000000000..89b54f594 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-2.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 214 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) + +void static +avx2_test (void) +{ + int i; + int m[4] = { mask_v (0), mask_v (1), mask_v (2), mask_v (3) }; + int s[4] = { 1, 2, 3, 4 }; + union128i_d src, mask; + int e[4] = { 0 }; + int d[4] = { 0 }; + + src.x = _mm_loadu_si128 ((__m128i *) s); + mask.x = _mm_loadu_si128 ((__m128i *) m); + _mm_maskstore_epi32 (d, mask.x, src.x); + + for (i = 0; i < 4; i++) + e[i] = m[i] ? s[i] : 0; + + if (checkVi (d, e, 4)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-1.c new file mode 100644 index 000000000..4e2944de0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovd\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +int *y; + +void extern +avx2_test (void) +{ + _mm256_maskstore_epi32 (y, x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-2.c new file mode 100644 index 000000000..7b66a0897 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-2.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 214 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31) + +void static +avx2_test (void) +{ + int i; + int m[8] = + { mask_v (0), mask_v (1), mask_v (2), mask_v (3), mask_v (4), mask_v (5), +mask_v (6), mask_v (7) }; + int s[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; + union256i_d src, mask; + int e[8] = { 0 }; + int d[8] = { 0 }; + + src.x = _mm256_loadu_si256 ((__m256i *) s); + mask.x = _mm256_loadu_si256 ((__m256i *) m); + _mm256_maskstore_epi32 (d, mask.x, src.x); + + for (i = 0; i < 8; i++) + e[i] = m[i] ? s[i] : 0; + + if (checkVi (d, e, 8)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-1.c new file mode 100644 index 000000000..f1075bf25 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovq\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +__m128i x; +long long int *y; + +void extern +avx2_test (void) +{ + _mm_maskstore_epi64 (y, x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-2.c new file mode 100644 index 000000000..bd9e39470 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-2.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 6 +#endif + +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) + +void static +avx2_test (void) +{ + int i; + long long m[2] = { mask_v (0), mask_v (1) }; + long long s[2] = { 1, 2 }; + long long e[2] = { 0 }; + long long d[2] = { 0 }; + union128i_q src, mask; + + src.x = _mm_loadu_si128 ((__m128i *) s); + mask.x = _mm_loadu_si128 ((__m128i *) m); + _mm_maskstore_epi64 (d, mask.x, src.x); + + for (i = 0; i < 2; i++) + e[i] = m[i] ? s[i] : 0; + + if (checkVl (d, e, 2)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-1.c new file mode 100644 index 000000000..0d0520b81 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaskmovq\[ \\t\]+\[^\n\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +long long int *y; + +void extern +avx2_test (void) +{ + _mm256_maskstore_epi64 (y, x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-2.c new file mode 100644 index 000000000..091791ac6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-2.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +#ifndef MASK +#define MASK 6 +#endif + +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63) + +void static +avx2_test (void) +{ + int i; + long long m[4] = { mask_v (0), mask_v (1), mask_v (2), mask_v (3) }; + long long s[4] = { 1, 2, 3, 4 }; + long long e[4] = { 0 }; + long long d[4] = { 0 }; + union256i_q src, mask; + + src.x = _mm256_loadu_si256 ((__m256i *) s); + mask.x = _mm256_loadu_si256 ((__m256i *) m); + _mm256_maskstore_epi64 (d, mask.x, src.x); + + for (i = 0; i < 4; i++) + e[i] = m[i] ? s[i] : 0; + + if (checkVl (d, e, 4)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-1.c new file mode 100644 index 000000000..2cbbcff9d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaxsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_max_epi8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-2.c new file mode 100644 index 000000000..4b1b1dd2f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmaxsb256 (char *s1, char *s2, char *r) +{ + int i; + + for (i = 0; i < 32; i++) + r[i] = s1[i] > s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_b s1, s2, res; + char res_ref[32]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (i + 20) * sign; + sign = -sign; + } + + res.x = _mm256_max_epi8 (s1.x, s2.x); + + compute_pmaxsb256 (s1.a, s2.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-1.c new file mode 100644 index 000000000..1b227e614 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaxsd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_max_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-2.c new file mode 100644 index 000000000..e488a6ea1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmaxsd256 (int *s1, int *s2, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s1[i] > s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (i + 2000) * sign; + sign = -sign; + } + + res.x = _mm256_max_epi32 (s1.x, s2.x); + + compute_pmaxsd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-1.c new file mode 100644 index 000000000..8fb2d29cd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaxsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_max_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-2.c new file mode 100644 index 000000000..6ada1cd23 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmaxsw256 (short *s1, short *s2, short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = s1[i] > s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (i + 2000) * sign; + sign = -sign; + } + + res.x = _mm256_max_epi16 (s1.x, s2.x); + + compute_pmaxsw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-1.c new file mode 100644 index 000000000..6d0fe9828 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaxub\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_max_epu8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-2.c new file mode 100644 index 000000000..f0654e032 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmaxub256 (unsigned char *s1, unsigned char *s2, unsigned char *r) +{ + int i; + + for (i = 0; i < 32; i++) + r[i] = s1[i] > s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_b s1, s2, res; + unsigned char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = i + 200; + } + + res.x = _mm256_max_epu8 (s1.x, s2.x); + + compute_pmaxub256 ((unsigned char *) s1.a, + (unsigned char *) s2.a, (unsigned char *) res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-1.c new file mode 100644 index 000000000..5784148c7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaxud\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_max_epu32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-2.c new file mode 100644 index 000000000..a61314d19 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmaxud256 (unsigned int *s1, unsigned int *s2, unsigned int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s1[i] > s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + unsigned int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i; + s2.a[j] = i + 2000; + } + + res.x = _mm256_max_epu32 (s1.x, s2.x); + + compute_pmaxud256 ((unsigned *) s1.a, (unsigned *) s2.a, + (unsigned *) res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-1.c new file mode 100644 index 000000000..dbadc254c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmaxuw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_max_epu16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-2.c new file mode 100644 index 000000000..2631f0cf0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmaxuw256 (unsigned short *s1, unsigned short *s2, unsigned short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = s1[i] > s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + unsigned short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i; + s2.a[j] = i + 2000; + } + + res.x = _mm256_max_epu16 (s1.x, s2.x); + + compute_pmaxuw256 ((unsigned short *) s1.a, + (unsigned short *) s2.a, (unsigned short *) res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsb-1.c new file mode 100644 index 000000000..35cbdb312 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpminsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_min_epi8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsb-2.c new file mode 100644 index 000000000..2dc5b109f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsb-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pminsb256 (char *s1, char *s2, char *r) +{ + int i; + + for (i = 0; i < 32; i++) + r[i] = s1[i] < s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_b s1, s2, res; + char res_ref[32]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (i + 20) * sign; + sign = -sign; + } + + res.x = _mm256_min_epi8 (s1.x, s2.x); + + compute_pminsb256 (s1.a, s2.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsd-1.c new file mode 100644 index 000000000..97c99f24c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpminsd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_min_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsd-2.c new file mode 100644 index 000000000..e2c69e7e8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsd-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pminsd256 (int *s1, int *s2, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s1[i] < s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (i + 2000) * sign; + sign = -sign; + } + + res.x = _mm256_min_epi32 (s1.x, s2.x); + + compute_pminsd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsw-1.c new file mode 100644 index 000000000..43f5c72ac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpminsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_min_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsw-2.c new file mode 100644 index 000000000..05be8ce90 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminsw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pminsw256 (short *s1, short *s2, short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = s1[i] < s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (i + 2000) * sign; + sign = -sign; + } + + res.x = _mm256_min_epi16 (s1.x, s2.x); + + compute_pminsw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminub-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminub-1.c new file mode 100644 index 000000000..44663e8ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminub-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpminub\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_min_epu8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminub-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminub-2.c new file mode 100644 index 000000000..16c5f7628 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminub-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pminub256 (unsigned char *s1, unsigned char *s2, unsigned char *r) +{ + int i; + + for (i = 0; i < 32; i++) + r[i] = s1[i] < s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_b s1, s2, res; + unsigned char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = i + 200; + } + + res.x = _mm256_min_epu8 (s1.x, s2.x); + + compute_pminub256 ((unsigned char *) s1.a, + (unsigned char *) s2.a, (unsigned char *) res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminud-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminud-1.c new file mode 100644 index 000000000..d6acb8b47 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminud-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpminud\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_min_epu32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminud-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminud-2.c new file mode 100644 index 000000000..97ff74226 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminud-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pminud256 (unsigned int *s1, unsigned int *s2, unsigned int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s1[i] < s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + unsigned int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i; + s2.a[j] = i + 2000; + } + + res.x = _mm256_min_epu32 (s1.x, s2.x); + + compute_pminud256 ((unsigned *) s1.a, (unsigned *) s2.a, + (unsigned *) res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminuw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminuw-1.c new file mode 100644 index 000000000..c018a49c9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminuw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpminuw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_min_epu16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminuw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminuw-2.c new file mode 100644 index 000000000..7de87d00d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpminuw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pminuw256 (unsigned short *s1, unsigned short *s2, unsigned short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = s1[i] < s2[i] ? s1[i] : s2[i]; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + unsigned short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i; + s2.a[j] = i + 2000; + } + + res.x = _mm256_min_epu16 (s1.x, s2.x); + + compute_pminuw256 ((unsigned short *) s1.a, + (unsigned short *) s2.a, (unsigned short *) res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-1.c new file mode 100644 index 000000000..1a37b1bef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovmskb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +int res; + +void extern +avx2_test (void) +{ + res = _mm256_movemask_epi8 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-2.c new file mode 100644 index 000000000..e5a9c10e1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovmskb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include "avx2-check.h" + +static void +avx2_test (void) +{ + union256i_b s; + int res, res_ref; + int i, e = 0; + + s.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + 15, 98, 25, 98, 7, 1, 2, 3, 4, 10, 20, 30, 90, + -80, -40, -100, -15, 98, 25, 98, 7); + + res = _mm256_movemask_epi8 (s.x); + + for (i = 0; i < 32; i++) + if (s.a[i] & (1 << 7)) + res_ref = res_ref | (1 << i); + + if (res != res_ref) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-1.c new file mode 100644 index 000000000..d438248b5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovsxbd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepi8_epi32 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-2.c new file mode 100644 index 000000000..3b641b0ca --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movsxbd (char *s, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_b s; + union256i_d res; + int res_ref[8]; + + s.x = _mm_set_epi8 (1, 2, 3, 4, 20, -50, 6, 8, 1, 2, 3, 4, -20, 5, 6, 8); + + res.x = _mm256_cvtepi8_epi32 (s.x); + + compute_movsxbd (s.a, res_ref); + + if (check_union256i_d (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-1.c new file mode 100644 index 000000000..12c817ffb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovsxbq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepi8_epi64 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-2.c new file mode 100644 index 000000000..23aae5bdb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movsxbq (char *s, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_b s; + union256i_q res; + long long int res_ref[4]; + + s.x = _mm_set_epi8 (1, 2, 3, 4, 20, -50, 6, 8, 1, 2, 3, 4, -20, 5, 6, 8); + + res.x = _mm256_cvtepi8_epi64 (s.x); + + compute_movsxbq (s.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-1.c new file mode 100644 index 000000000..bf98e3154 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovsxbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepi8_epi16 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-2.c new file mode 100644 index 000000000..d1c02ea86 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movsxbw (char *s, short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_b s; + union256i_w res; + short res_ref[16]; + + s.x = _mm_set_epi8 (1, 2, 3, 4, 20, -50, 6, 8, 1, 2, 3, 4, -20, 5, 6, 8); + + res.x = _mm256_cvtepi8_epi16 (s.x); + + compute_movsxbw (s.a, res_ref); + + if (check_union256i_w (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-1.c new file mode 100644 index 000000000..9c72c41e1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovsxdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepi32_epi64 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-2.c new file mode 100644 index 000000000..7e87f316f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movsxdq (int *s, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_d s; + union256i_q res; + long long int res_ref[4]; + + s.x = _mm_set_epi32 (1, -2, 3, 4); + + res.x = _mm256_cvtepi32_epi64 (s.x); + + compute_movsxdq (s.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-1.c new file mode 100644 index 000000000..39627ced8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovsxwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepi16_epi32 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-2.c new file mode 100644 index 000000000..5a95e376e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movsxwd (short *s, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_w s; + union256i_d res; + int res_ref[8]; + + s.x = _mm_set_epi16 (1, -2, 3, 4, 200, 5000, -6, 8); + + res.x = _mm256_cvtepi16_epi32 (s.x); + + compute_movsxwd (s.a, res_ref); + + if (check_union256i_d (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-1.c new file mode 100644 index 000000000..9fa613b34 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovsxwq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepi16_epi64 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-2.c new file mode 100644 index 000000000..f096de577 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movsxwq (short *s, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_w s; + union256i_q res; + long long int res_ref[4]; + + s.x = _mm_set_epi16 (1, 2, 3, 4, -200, 50, 6, 8); + + res.x = _mm256_cvtepi16_epi64 (s.x); + + compute_movsxwq (s.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-1.c new file mode 100644 index 000000000..bde8c134d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovzxbd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepu8_epi32 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-2.c new file mode 100644 index 000000000..7a212c89d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movzxbd (unsigned char *s, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_b s; + union256i_d res; + int res_ref[8]; + + s.x = _mm_set_epi8 (1, 2, 3, 4, 20, 50, 6, 8, 1, 2, 3, 4, 200, 5, 6, 8); + + res.x = _mm256_cvtepu8_epi32 (s.x); + + compute_movzxbd (s.a, res_ref); + + if (check_union256i_d (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-1.c new file mode 100644 index 000000000..da8e0584a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovzxbq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepu8_epi64 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-2.c new file mode 100644 index 000000000..c09c21d67 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movzxbq (unsigned char *s, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_b s; + union256i_q res; + long long int res_ref[4]; + + s.x = _mm_set_epi8 (1, 2, 3, 4, 20, 150, 6, 8, 1, 2, 3, 4, 20, 5, 6, 8); + + res.x = _mm256_cvtepu8_epi64 (s.x); + + compute_movzxbq (s.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-1.c new file mode 100644 index 000000000..f7a926de1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovzxbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepu8_epi16 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-2.c new file mode 100644 index 000000000..5ef4b1535 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movzxbw (unsigned char *s, short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_b s; + union256i_w res; + short res_ref[16]; + + s.x = _mm_set_epi8 (1, 2, 3, 4, 200, 50, 6, 8, 1, 2, 3, 4, 200, 5, 6, 8); + + res.x = _mm256_cvtepu8_epi16 (s.x); + + compute_movzxbw (s.a, res_ref); + + if (check_union256i_w (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-1.c new file mode 100644 index 000000000..3f0c400c3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovzxdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepu32_epi64 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-2.c new file mode 100644 index 000000000..20986b644 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movzxdq (unsigned *s, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_d s; + union256i_q res; + long long int res_ref[4]; + + s.x = _mm_set_epi32 (1, 2, 3, 4); + + res.x = _mm256_cvtepu32_epi64 (s.x); + + compute_movzxdq (s.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-1.c new file mode 100644 index 000000000..902cd6df8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovzxwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepu16_epi32 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-2.c new file mode 100644 index 000000000..b4d2b2da6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movzxwd (unsigned short *s, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_w s; + union256i_d res; + int res_ref[8]; + + s.x = _mm_set_epi16 (1, 2, 3, 4, 200, 5000, 6, 8); + + res.x = _mm256_cvtepu16_epi32 (s.x); + + compute_movzxwd (s.a, res_ref); + + if (check_union256i_d (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-1.c new file mode 100644 index 000000000..4eaa65aeb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmovzxwq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; +__m256i res; + +void extern +avx2_test (void) +{ + res = _mm256_cvtepu16_epi64 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-2.c new file mode 100644 index 000000000..8a9250aec --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-2.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_movzxwq (unsigned short *s, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s[i]; +} + +static void +avx2_test (void) +{ + union128i_w s; + union256i_q res; + long long int res_ref[4]; + + s.x = _mm_set_epi16 (1, 2, 3, 4, 200, 5000, 6, 8); + + res.x = _mm256_cvtepu16_epi64 (s.x); + + compute_movzxwq (s.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-1.c new file mode 100644 index 000000000..e1c232da3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmuldq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mul_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-2.c new file mode 100644 index 000000000..b67f25fc4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmuldq256 (int *s1, int *s2, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s1[i * 2] * s2[i * 2]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2; + union256i_q res; + long long int res_ref[4]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = i * j * sign; + s2.a[j] = (j + 20) * sign; + sign = -sign; + } + + res.x = _mm256_mul_epi32 (s1.x, s2.x); + compute_pmuldq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-1.c new file mode 100644 index 000000000..7c6692b81 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmulhrsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mulhrs_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-2.c new file mode 100644 index 000000000..c6d874222 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmulhrsw256 (short *s1, short *s2, short *r) +{ + int i; + int t0; + + for (i = 0; i < 16; i++) + { + t0 = (((int) s1[i] * (int) s2[i]) >> 14) + 1; + r[i] = (short) (t0 >> 1); + } +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = i * j * sign; + s2.a[j] = (j + 20) * sign; + sign = -sign; + } + + res.x = _mm256_mulhrs_epi16 (s1.x, s2.x); + + compute_pmulhrsw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-1.c new file mode 100644 index 000000000..d9a2fa7ce --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmulhuw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mulhi_epu16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-2.c new file mode 100644 index 000000000..734b20cfb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmulhuw256 (unsigned short *s1, unsigned short *s2, unsigned short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = (s1[i] * s2[i]) >> 16; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + unsigned short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = i * j; + s2.a[j] = j + 20; + } + + res.x = _mm256_mulhi_epu16 (s1.x, s2.x); + + compute_pmulhuw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-1.c new file mode 100644 index 000000000..a626f1919 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmulhw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mulhi_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-2.c new file mode 100644 index 000000000..ea0bde2be --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmulhw256 (short *s1, short *s2, short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = (s1[i] * s2[i]) >> 16; +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = i * j * sign; + s2.a[j] = (j + 20) * sign; + sign = -sign; + } + + res.x = _mm256_mulhi_epi16 (s1.x, s2.x); + + compute_pmulhw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulld-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulld-1.c new file mode 100644 index 000000000..4e2e5250f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulld-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmulld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mullo_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulld-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulld-2.c new file mode 100644 index 000000000..74443a24d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulld-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmulld256 (int *s1, int *s2, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + r[i] = (int) ((long long int) s1[i] * (long long int) s2[i]); +} + +static void +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = i * j * sign; + s2.a[j] = (j + 20) * sign; + sign = -sign; + } + + res.x = _mm256_mullo_epi32 (s1.x, s2.x); + + compute_pmulld256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c new file mode 100644 index 000000000..b2d539ba4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE int +#define BIN_OP(a, b) ((a) * (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpmulld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmullw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmullw-1.c new file mode 100644 index 000000000..61cc75884 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmullw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmullw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mullo_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmullw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmullw-2.c new file mode 100644 index 000000000..81d05ccab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmullw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmullw256 (short *s1, short *s2, short *r) +{ + int i; + + for (i = 0; i < 16; i++) + r[i] = (short) ((int) s1[i] * (int) s2[i]); +} + +static void +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = i * j * sign; + s2.a[j] = (j + 20) * sign; + sign = -sign; + } + + res.x = _mm256_mullo_epi16 (s1.x, s2.x); + + compute_pmullw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c new file mode 100644 index 000000000..46d173fc3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE short +#define BIN_OP(a, b) ((a) * (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpmullw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-1.c new file mode 100644 index 000000000..4fa1bf155 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpmuludq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_mul_epu32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-2.c new file mode 100644 index 000000000..619b7358e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +static void +compute_pmuludq256 (unsigned int *s1, unsigned int *s2, unsigned long long *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s1[i * 2] * s2[i * 2]; +} + +static void +avx2_test (void) +{ + union256i_d s1, s2; + union256i_q res; + unsigned long long res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = i * j; + s2.a[j] = j + 20; + } + + res.x = _mm256_mul_epu32 (s1.x, s2.x); + + compute_pmuludq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpop-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpop-check.h new file mode 100644 index 000000000..143b54dae --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpop-check.h @@ -0,0 +1,53 @@ +#include "avx2-check.h" + +#define SIZE 256 + +TYPE a[SIZE]; +TYPE b[SIZE]; +TYPE c[SIZE]; +volatile TYPE c_ref[SIZE]; + +__attribute__ ((__noinline__)) +void +gen_pop () +{ + int i; + for (i = 0; i < SIZE; ++i) +#ifdef BIN_OP + c[i] = BIN_OP (a[i], b[i]); +#else /* Must be UN_OP */ + c[i] = UN_OP (a[i]); +#endif /* BIN_OP */ +} + +void +check_pop () +{ + int i; + for (i = 0; i < SIZE; ++i) +#ifdef BIN_OP + c_ref[i] = BIN_OP (a[i], b[i]); +#else /* Must be UN_OP */ + c_ref[i] = UN_OP (a[i]); +#endif /* BIN_OP */ +} + +void static +avx2_test (void) +{ + int i, j; + for (i = 0; i < 4; ++i ) + { + for ( j = 0; j < SIZE; ++j ) + { + a[i] = i * i + i; + b[i] = i * i * i; + } + + gen_pop (); + check_pop (); + + if (memcmp (c, c_ref, SIZE * sizeof (TYPE))) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpor-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpor-1.c new file mode 100644 index 000000000..2e0f46d21 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpor-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpor\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_or_si256 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpor-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpor-2.c new file mode 100644 index 000000000..fd5da8335 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpor-2.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include "avx2-check.h" + +static void +compute_por256 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s1[i] | s2[i]; +} + +void static +avx2_test (void) +{ + union256i_q s1, s2, res; + long long int res_ref[4]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = i * j * sign; + s2.a[j] = (j + 20) * sign; + sign = -sign; + } + + res.x = _mm256_or_si256 (s1.x, s2.x); + compute_por256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-1.c new file mode 100644 index 000000000..1cd56661c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsadbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sad_epu8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-2.c new file mode 100644 index 000000000..392613659 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-2.c @@ -0,0 +1,57 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_sadbw256 (unsigned char *s1, unsigned char *s2, unsigned short *r) +{ + int i; + unsigned char tmp[32]; + + for (i = 0; i < 32; i++) + tmp[i] = s1[i] > s2[i] ? s1[i] - s2[i] : s2[i] - s1[i]; + + memset (r, 0, 32); + + for (i = 0; i < 8; i++) + r[0] += tmp[i]; + + for (i = 8; i < 16; i++) + r[4] += tmp[i]; + + for (i = 16; i < 24; i++) + r[8] += tmp[i]; + + for (i = 24; i < 32; i++) + r[12] += tmp[i]; +} + +void static +avx2_test (void) +{ + union256i_b s1, s2; + union256i_w res; + unsigned short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_sad_epu8 (s1.x, s2.x);; + compute_sadbw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufb-1.c new file mode 100644 index 000000000..b94563d0c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpshufb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_shuffle_epi8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufb-2.c new file mode 100644 index 000000000..ee9149395 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufb-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_pshufb256 (char *s1, char *s2, char *r) +{ + int i; + char select; + + for (i = 0; i < 16; i++) + { + select = s2[i]; + if (select & 0x80) + r[i] = 0; + else + r[i] = s1[select & 0xf]; + + select = s2[i + 16]; + if (select & 0x80) + r[i + 16] = 0; + else + r[i + 16] = s1[16 + (select & 0xf)]; + } +} + +void static +avx2_test (void) +{ + union256i_b s1, s2, res; + char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_shuffle_epi8 (s1.x, s2.x); + compute_pshufb256 (s1.a, s2.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufd-1.c new file mode 100644 index 000000000..cdfde4654 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpshufd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_shuffle_epi32 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufd-2.c new file mode 100644 index 000000000..e799ed789 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufd-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0xec + +static void +compute_pshufd256 (int *s1, unsigned char imm, int *r) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = s1[((N & (0x3 << (2 * i))) >> (2 * i))]; + + for (i = 0; i < 4; i++) + r[i + 4] = s1[((N & (0x3 << (2 * i))) >> (2 * i)) + 4]; +} + +void static +avx2_test (void) +{ + union256i_d s1, res; + int res_ref[8]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i * sign; + sign = -sign; + } + + res.x = _mm256_shuffle_epi32 (s1.x, N); + compute_pshufd256 (s1.a, N, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-1.c new file mode 100644 index 000000000..fa3f809da --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpshufhw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_shufflehi_epi16 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-2.c new file mode 100644 index 000000000..a27ed03b3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-2.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0xec + +static void +compute_pshuflw256 (short *s1, unsigned char imm, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + { + r[i] = s1[(imm >> (2 * i)) & 3]; + r[i + 8] = s1[((imm >> (2 * i)) & 3) + 8]; + } + + for (i = 4; i < 8; i++) + { + r[i] = s1[i]; + r[i + 8] = s1[i + 8]; + } +} + +void static +avx2_test (void) +{ + union256i_w s1, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 1; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i * sign; + sign = -sign; + } + + res.x = _mm256_shufflelo_epi16 (s1.x, N); + compute_pshuflw256 (s1.a, N, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-1.c new file mode 100644 index 000000000..24e75625f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpshuflw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_shufflelo_epi16 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-2.c new file mode 100644 index 000000000..144197348 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-2.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0xec + +static void +compute_pshufhw256 (short *s1, unsigned char imm, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + { + r[i] = s1[i]; + r[i + 8] = s1[i + 8]; + } + + for (i = 4; i < 8; i++) + { + r[i] = s1[((imm >> (2 * (i - 4))) & 3) + 4]; + r[i + 8] = s1[((imm >> (2 * (i - 4))) & 3) + 12]; + } +} + +void static +avx2_test (void) +{ + union256i_w s1, res; + short res_ref[16]; + int i, j, sign = 1; + int fail = 0; + + for (i = 1; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i * sign; + sign = -sign; + } + + res.x = _mm256_shufflehi_epi16 (s1.x, N); + compute_pshufhw256 (s1.a, N, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignb-1.c new file mode 100644 index 000000000..6cd7ca6e8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsignb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sign_epi8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignb-2.c new file mode 100644 index 000000000..5e3d819fe --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignb-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psignb256 (char *s1, char *s2, char *r) +{ + int i; + + for (i = 0; i < 32; i++) + if (s2[i] < 0) + r[i] = -s1[i]; + else if (s2[i] == 0) + r[i] = 0; + else + r[i] = s1[i]; +} + +void static +avx2_test (void) +{ + union256i_b s1, s2, res; + char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_sign_epi8 (s1.x, s2.x); + compute_psignb256 (s1.a, s2.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignd-1.c new file mode 100644 index 000000000..dab81a3b1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsignd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sign_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignd-2.c new file mode 100644 index 000000000..14e61b014 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignd-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psignd256 (int *s1, int *s2, int *r) +{ + int i; + + for (i = 0; i < 8; i++) + if (s2[i] < 0) + r[i] = -s1[i]; + else if (s2[i] == 0) + r[i] = 0; + else + r[i] = s1[i]; +} + +void static +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_sign_epi32 (s1.x, s2.x); + compute_psignd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignw-1.c new file mode 100644 index 000000000..cae04c081 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsignw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sign_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignw-2.c new file mode 100644 index 000000000..bb96a1d53 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsignw-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psignw256 (short int *s1, short int *s2, short int *r) +{ + int i; + + for (i = 0; i < 16; i++) + if (s2[i] < 0) + r[i] = -s1[i]; + else if (s2[i] == 0) + r[i] = 0; + else + r[i] = s1[i]; +} + +void static +avx2_test (void) +{ + union256i_w s1, s2, res; + short int res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_sign_epi16 (s1.x, s2.x); + compute_psignw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslld-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslld-1.c new file mode 100644 index 000000000..5140d7ae0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslld-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpslld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_sll_epi32 (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslld-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslld-2.c new file mode 100644 index 000000000..84c68feb5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslld-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_pslld256 (int *s1, long long int *s2, int *r) +{ + int i; + long long int count = s2[0]; + + memset (r, 0, 32); + + if (count < 32) + for (i = 0; i < 8; ++i) + r[i] = s1[i] << count; +} + + +void static +avx2_test (void) +{ + union256i_d s1, res; + union128i_q s2; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_sll_epi32 (s1.x, s2.x); + + compute_pslld256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslldi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslldi-1.c new file mode 100644 index 000000000..9cea0f675 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslldi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpslld\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_slli_epi32 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslldi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslldi-2.c new file mode 100644 index 000000000..dfd7d9a03 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslldi-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_pslldi256 (int *s1, int *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 64) + for (i = 0; i < 8; ++i) + r[i] = s1[i] << N; +} + + +void static +avx2_test (void) +{ + union256i_d s1, res; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + s1.a[j] = j * i; + + res.x = _mm256_slli_epi32 (s1.x, N); + + compute_pslldi256 (s1.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslldq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslldq-1.c new file mode 100644 index 000000000..5a85a7982 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslldq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpslldq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +extern volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_slli_si256 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslldq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslldq-2.c new file mode 100644 index 000000000..7bfb5b185 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpslldq-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_pslldq256 (char *s1, char *r) +{ + int i; + + memset (r, 0, 32); + + for (i = 0; i < 16 - N; i++) + r[i + N] = s1[i]; + + for (i = 0; i < 16 - N; i++) + r[i + 16 + N] = s1[i + 16]; +} + + +void static +avx2_test (void) +{ + union256i_b s1, res; + char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + s1.a[j] = j * i; + + res.x = _mm256_slli_si256 (s1.x, N); + + compute_pslldq256 (s1.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllq-1.c new file mode 100644 index 000000000..53417a1ac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsllq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_sll_epi64 (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllq-2.c new file mode 100644 index 000000000..c0ac89bfe --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllq-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psllq256 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + long long int count = s2[0]; + + memset (r, 0, 32); + + if (count < 64) + for (i = 0; i < 4; ++i) + r[i] = s1[i] << count; +} + +void static +avx2_test (void) +{ + union256i_q s1, res; + union128i_q s2; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_sll_epi64 (s1.x, s2.x); + + compute_psllq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-1.c new file mode 100644 index 000000000..2851be5e2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsllq\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_slli_epi64 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-2.c new file mode 100644 index 000000000..9ef49bdb9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psllqi256 (long long int *s1, long long int *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 64) + for (i = 0; i < 4; ++i) + r[i] = s1[i] << N; +} + + +void static +avx2_test (void) +{ + union256i_q s1, res; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + s1.a[j] = j * i; + + res.x = _mm256_slli_epi64 (s1.x, N); + + compute_psllqi256 (s1.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-1.c new file mode 100644 index 000000000..b57afc4af --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsllvd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_sllv_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-2.c new file mode 100644 index 000000000..5ab83ae20 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psllvd128 (int *s1, int *s2, int *r) +{ + int i, count; + + for (i = 0; i < 4; ++i) + { + count = s2[i]; + r[i] = s1[i] << count; + } +} + +void static +avx2_test (void) +{ + union128i_d s1, s2, res; + int res_ref[4]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm_sllv_epi32 (s1.x, s2.x); + + compute_psllvd128 (s1.a, s2.a, res_ref); + + fail += check_union128i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-1.c new file mode 100644 index 000000000..59063d5c4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsllvd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sllv_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-2.c new file mode 100644 index 000000000..407a8f3c5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psllvd256 (int *s1, int *s2, int *r) +{ + int i, count; + + for (i = 0; i < 8; ++i) + { + count = s2[i]; + r[i] = s1[i] << count; + } +} + +void static +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j, sign = 1;; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm256_sllv_epi32 (s1.x, s2.x); + + compute_psllvd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-1.c new file mode 100644 index 000000000..245aa5508 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsllvq\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_sllv_epi64 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-2.c new file mode 100644 index 000000000..422ddf5bf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psllvq128 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + long long int count; + + for (i = 0; i < 2; ++i) + { + count = s2[i]; + r[i] = s1[i] << count; + } +} + +void static +avx2_test (void) +{ + union128i_q s1, s2, res; + long long int res_ref[2]; + int i, j, sign = 2; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 2; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm_sllv_epi64 (s1.x, s2.x); + + compute_psllvq128 (s1.a, s2.a, res_ref); + + fail += check_union128i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-1.c new file mode 100644 index 000000000..caae3f2fa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsllvq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sllv_epi64 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-2.c new file mode 100644 index 000000000..c41597b16 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psllvq256 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + long long int count; + + for (i = 0; i < 4; ++i) + { + count = s2[i]; + r[i] = s1[i] << count; + } +} + +void static +avx2_test (void) +{ + union256i_q s1, s2, res; + long long int res_ref[4]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm256_sllv_epi64 (s1.x, s2.x); + + compute_psllvq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllw-1.c new file mode 100644 index 000000000..2fbc43f48 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllw-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsllw\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_sll_epi16 (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllw-2.c new file mode 100644 index 000000000..1b26330dd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllw-2.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psllw256 (short *s1, long long int *s2, short *r) +{ + int i; + int count = s2[0]; + + memset (r, 0, 32); + + if (count < 16) + for (i = 0; i < 16; ++i) + r[i] = s1[i] << count; +} + +void static +avx2_test (void) +{ + union256i_w s1, res; + union128i_q s2; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_sll_epi16 (s1.x, s2.x); + + compute_psllw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + + if (fail) + { + for (j = 0; j < 16; ++j) + printf ("%d <->%d\n", res.a[j], res_ref[j]); + abort (); + } + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-1.c new file mode 100644 index 000000000..10bd08c34 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsllw\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_slli_epi16 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-2.c new file mode 100644 index 000000000..f1d3e1109 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psllwi256 (short *s1, short *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 16) + for (i = 0; i < 16; ++i) + r[i] = s1[i] << N; +} + + +void static +avx2_test (void) +{ + union256i_w s1, res; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + s1.a[j] = j * i; + + res.x = _mm256_slli_epi16 (s1.x, N); + + compute_psllwi256 (s1.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrad-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrad-1.c new file mode 100644 index 000000000..673398e3d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrad-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrad\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_sra_epi32 (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrad-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrad-2.c new file mode 100644 index 000000000..39a579e4f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrad-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrad256 (int *s1, long long int *s2, int *r) +{ + int i; + long long int count = s2[0]; + + memset (r, 0, 32); + + if (count < 32) + for (i = 0; i < 8; ++i) + r[i] = s1[i] >> count; +} + + +void static +avx2_test (void) +{ + union256i_d s1, res; + union128i_q s2; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_sra_epi32 (s1.x, s2.x); + + compute_psrad256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c new file mode 100644 index 000000000..97affb4bb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE unsigned +#define UN_OP(a) ((a) >> (5)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsrld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsradi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsradi-1.c new file mode 100644 index 000000000..f6bb71a57 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsradi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsrad\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srai_epi32 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsradi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsradi-2.c new file mode 100644 index 000000000..b9cfc7afa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsradi-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psradi256 (int *s1, int *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 32) + for (i = 0; i < 8; ++i) + r[i] = s1[i] >> N; +} + + +void static +avx2_test (void) +{ + union256i_d s1, res; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + s1.a[j] = j * i; + + res.x = _mm256_srai_epi16 (s1.x, N); + + compute_psradi256 (s1.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-1.c new file mode 100644 index 000000000..a20a8868a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsravd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_srav_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-2.c new file mode 100644 index 000000000..8438d9a44 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psravd128 (int *s1, int *s2, int *r) +{ + int i, count; + + for (i = 0; i < 4; ++i) + { + count = s2[i]; + r[i] = s1[i] >> count; + } +} + +void static +avx2_test (void) +{ + union128i_d s1, s2, res; + int res_ref[4]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm_srav_epi32 (s1.x, s2.x); + + compute_psravd128 (s1.a, s2.a, res_ref); + + fail += check_union128i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-1.c new file mode 100644 index 000000000..6adf3049b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsravd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srav_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-2.c new file mode 100644 index 000000000..0be75205b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psravd256 (int *s1, int *s2, int *r) +{ + int i, count; + + for (i = 0; i < 8; ++i) + { + count = s2[i]; + r[i] = s1[i] >> count; + } +} + +void static +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm256_srav_epi32 (s1.x, s2.x); + + compute_psravd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsraw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsraw-1.c new file mode 100644 index 000000000..2b1c3584b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsraw-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsraw\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_sra_epi16 (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsraw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsraw-2.c new file mode 100644 index 000000000..66fe8a95c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsraw-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psraw256 (short *s1, long long int *s2, short *r) +{ + int i; + long long int count = s2[0]; + + memset (r, 0, 32); + + if (count < 16) + for (i = 0; i < 16; ++i) + r[i] = s1[i] >> count; +} + + +void static +avx2_test (void) +{ + union256i_w s1, res; + union128i_q s2; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_sra_epi16 (s1.x, s2.x); + + compute_psraw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c new file mode 100644 index 000000000..e7112565b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE short +#define UN_OP(a) ((a) >> (5)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsraw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-1.c new file mode 100644 index 000000000..e8558c35d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsraw\[ \\t\]+\[^\n\]*" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srai_epi16 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-2.c new file mode 100644 index 000000000..c135833a4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psrawi256 (short *s1, short *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 16) + for (i = 0; i < 16; ++i) + r[i] = s1[i] >> N; +} + + +void static +avx2_test (void) +{ + union256i_w s1, res; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + s1.a[j] = j * i; + + res.x = _mm256_srai_epi16 (s1.x, N); + + compute_psrawi256 (s1.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrld-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrld-1.c new file mode 100644 index 000000000..5c0605cdd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrld-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_srl_epi32 (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrld-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrld-2.c new file mode 100644 index 000000000..1fab08cd8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrld-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrld256 (int *s1, long long int *s2, int *r) +{ + int i; + long long int count = s2[0]; + + memset (r, 0, 32); + + if (count < 32) + for (i = 0; i < 8; ++i) + r[i] = s1[i] >> count; +} + +void static +avx2_test (void) +{ + union256i_d s1, res; + union128i_q s2; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_srl_epi32 (s1.x, s2.x); + + compute_psrld256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c new file mode 100644 index 000000000..97affb4bb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE unsigned +#define UN_OP(a) ((a) >> (5)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsrld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-1.c new file mode 100644 index 000000000..feac4c920 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsrld\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srli_epi32 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-2.c new file mode 100644 index 000000000..0f109feb3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-2.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psrldi256 (int *s1, int *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 64) + for (i = 0; i < 8; ++i) + r[i] = s1[i] >> N; +} + +void static +avx2_test (void) +{ + union256i_d s1, res; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + s1.a[j] = j * i; + + res.x = _mm256_srli_epi32 (s1.x, N); + + compute_psrldi256 (s1.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-1.c new file mode 100644 index 000000000..dd804e04f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrldq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +extern volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srli_si256 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-2.c new file mode 100644 index 000000000..4c2850903 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psrldq256 (char *s1, char *r) +{ + int i; + + memset (r, 0, 32); + + for (i = 0; i < 16 - N; i++) + r[i] = s1[i + N]; + + for (i = 0; i < 16 - N; i++) + r[i + 16] = s1[i + N + 16]; +} + + +void static +avx2_test (void) +{ + union256i_b s1, res; + char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + s1.a[j] = j * i; + + res.x = _mm256_srli_si256 (s1.x, N); + + compute_psrldq256 (s1.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-1.c new file mode 100644 index 000000000..c19d067a7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrlq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_srl_epi64 (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-2.c new file mode 100644 index 000000000..e02da78f6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrlq256 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + long long int count = s2[0]; + + memset (r, 0, 32); + + if (count < 64) + for (i = 0; i < 4; ++i) + r[i] = s1[i] >> count; +} + +void static +avx2_test (void) +{ + union256i_q s1, res; + union128i_q s2; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_srl_epi64 (s1.x, s2.x); + + compute_psrlq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-1.c new file mode 100644 index 000000000..3cab1dc0e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsrlq\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srli_epi64 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-2.c new file mode 100644 index 000000000..1aa23fedc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-2.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psrlqi256 (long long int *s1, long long int *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 64) + for (i = 0; i < 4; ++i) + r[i] = s1[i] >> N; +} + +void static +avx2_test (void) +{ + union256i_q s1, res; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + s1.a[j] = j * i; + + res.x = _mm256_srli_epi64 (s1.x, N); + + compute_psrlqi256 (s1.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-1.c new file mode 100644 index 000000000..d4d035842 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrlvd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_srlv_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-2.c new file mode 100644 index 000000000..c7674c02c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrlvd128 (int *s1, int *s2, int *r) +{ + int i, count; + + for (i = 0; i < 4; ++i) + { + count = s2[i]; + r[i] = ((unsigned) s1[i]) >> count; + } +} + + +void static +avx2_test (void) +{ + union128i_d s1, s2, res; + int res_ref[4]; + int i, j, sign; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm_srlv_epi32 (s1.x, s2.x); + + compute_psrlvd128 (s1.a, s2.a, res_ref); + + fail += check_union128i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-1.c new file mode 100644 index 000000000..ce76c8f80 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrlvd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srlv_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-2.c new file mode 100644 index 000000000..e3c3c4841 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrlvd256 (int *s1, int *s2, int *r) +{ + int i, count; + + for (i = 0; i < 8; ++i) + { + count = s2[i]; + r[i] = ((unsigned) s1[i]) >> count; + } +} + +void static +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm256_srlv_epi32 (s1.x, s2.x); + + compute_psrlvd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-1.c new file mode 100644 index 000000000..64d7c28ef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrlvq\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +__m128i x; + +void extern +avx2_test (void) +{ + x = _mm_srlv_epi64 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-2.c new file mode 100644 index 000000000..842559ff2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrlvq128 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + long long int count; + + for (i = 0; i < 2; ++i) + { + count = s2[i]; + r[i] = ((unsigned long long int) s1[i]) >> count; + } +} + +void static +avx2_test (void) +{ + union128i_q s1, s2, res; + long long int res_ref[2]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 2; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm_srlv_epi64 (s1.x, s2.x); + + compute_psrlvq128 (s1.a, s2.a, res_ref); + + fail += check_union128i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-1.c new file mode 100644 index 000000000..4e00736e8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrlvq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srlv_epi64 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-2.c new file mode 100644 index 000000000..e006d7c27 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrlvq256 (long long int *s1, long long int *s2, long long int *r) +{ + int i; + long long int count; + + for (i = 0; i < 4; ++i) + { + count = s2[i]; + r[i] = ((unsigned long long) s1[i]) >> count; + } +} + +void static +avx2_test (void) +{ + union256i_q s1, s2, res; + long long int res_ref[4]; + int i, j, sign = 1; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i * sign; + s2.a[j] = (j + i) >> 2; + sign = -sign; + } + + res.x = _mm256_srlv_epi64 (s1.x, s2.x); + + compute_psrlvq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-1.c new file mode 100644 index 000000000..f69edbc69 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsrlw\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; +__m128i y; + +void extern +avx2_test (void) +{ + x = _mm256_srl_epi16 (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-2.c new file mode 100644 index 000000000..fb7526c0e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-2.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +static void +compute_psrlw256 (short *s1, long long int *s2, short *r) +{ + int i; + int count = s2[0]; + + memset (r, 0, 32); + + if (count < 16) + for (i = 0; i < 16; ++i) + r[i] = s1[i] >> count; +} + +void static +avx2_test (void) +{ + union256i_w s1, res; + union128i_q s2; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + s1.a[j] = j * i; + + s2.a[0] = i; + + res.x = _mm256_srl_epi16 (s1.x, s2.x); + + compute_psrlw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + + if (fail) + { + for (j = 0; j < 16; ++j) + printf ("%d <->%d\n", res.a[j], res_ref[j]); + abort (); + } + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c new file mode 100644 index 000000000..67f3afc41 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE unsigned short +#define UN_OP(a) ((a) >> (5)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsrlw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-1.c new file mode 100644 index 000000000..823d81eb4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O3" } */ +/* { dg-final { scan-assembler "vpsrlw\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_srli_epi16 (x, 13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-2.c new file mode 100644 index 000000000..9baf2dadc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-2.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O3 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_psrlwi256 (short *s1, short *r) +{ + int i; + + memset (r, 0, 32); + + if (N < 16) + for (i = 0; i < 16; ++i) + r[i] = s1[i] >> N; +} + +void static +avx2_test (void) +{ + union256i_w s1, res; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + s1.a[j] = j * i; + + res.x = _mm256_srli_epi16 (s1.x, N); + + compute_psrlwi256 (s1.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubb-1.c new file mode 100644 index 000000000..e5ccd6be8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sub_epi8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubb-2.c new file mode 100644 index 000000000..14da9e02c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubb-2.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + char e[32]; + unsigned i; + + s1.x = _mm256_set_epi8 (10, 74, 50, 4, 6, 99, 1, 4, 87, 83, 84, + 29, 81, 79, 1, 3, 1, 5, 2, 47, 20, 2, 72, + 92, 9, 4, 23, 17, 99, 43, 72, 17); + + s2.x = _mm256_set_epi8 (88, 44, 33, 20, 56, 99, 2, 90, 38, 4, 200, + 17, 3, 39, 2, 37, 27, 95, 17, 74, 72, 43, + 27, 112, 71, 50, 32, 72, 84, 17, 27, 96); + + u.x = _mm256_sub_epi8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + e[i] = s1.a[i] - s2.a[i]; + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c new file mode 100644 index 000000000..843128b4f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE char +#define BIN_OP(a, b) ((a) - (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsubb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubd-1.c new file mode 100644 index 000000000..150f4cbcf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sub_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubd-2.c new file mode 100644 index 000000000..74a6fec01 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubd-2.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_d u, s1, s2; + int e[8]; + unsigned i; + + s1.x = _mm256_set_epi32 (100, 74, 50000, 4, 6999, 39999, 1000, 4); + s2.x = _mm256_set_epi32 (88, 44, 33, 220, 4556, 2999, 2, 9000000); + + u.x = _mm256_sub_epi32 (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i] - s2.a[i]; + + if (check_union256i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c new file mode 100644 index 000000000..f8f399f6b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE int +#define BIN_OP(a, b) ((a) - (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubq-1.c new file mode 100644 index 000000000..9460b0d84 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_sub_epi64 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubq-2.c new file mode 100644 index 000000000..aa869252a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubq-2.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_q u, s1, s2; + long long e[4]; + unsigned i; + + s1.x = _mm256_set_epi64x (100, 74, 50000, 4); + s2.x = _mm256_set_epi64x (88, 44, 33, 220); + + u.x = _mm256_sub_epi64 (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] - s2.a[i]; + + if (check_union256i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c new file mode 100644 index 000000000..0a23a280e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE long long int +#define BIN_OP(a, b) ((a) - (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsubq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-1.c new file mode 100644 index 000000000..ad1b986f7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_subs_epi8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-2.c new file mode 100644 index 000000000..5f33f6b89 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-2.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + char e[32]; + int i, tmp; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100, + -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, + 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, + -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20, + 30, 90, -80, -40, -100, -15, 98, 25, 98, 7); + + u.x = _mm256_subs_epi8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + { + tmp = s1.a[i] - s2.a[i]; + + if (tmp > 127) + tmp = 127; + if (tmp < -128) + tmp = -128; + + e[i] = tmp; + } + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-1.c new file mode 100644 index 000000000..c02d27551 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_subs_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-2.c new file mode 100644 index 000000000..2f2fc7d60 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_w u, s1, s2; + short e[16]; + int i, tmp; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, -80, + -40, -100, -15, 98, 25, 98, 7); + + s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, -100, + -34, -78, -39, 6, 3, 4, 5, 119); + + u.x = _mm256_subs_epi16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + { + tmp = s1.a[i] - s2.a[i]; + + if (tmp > 32767) + tmp = 32767; + if (tmp < -32768) + tmp = -32768; + + e[i] = tmp; + } + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-1.c new file mode 100644 index 000000000..917ffa9a8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubusb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_subs_epu8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-2.c new file mode 100644 index 000000000..bffb5b6f5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_b u, s1, s2; + unsigned char e[32]; + int i, tmp; + + s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, 80, 40, 100, 15, + 98, 25, 98, 7, 88, 44, 33, 22, 11, 98, 76, + 200, 34, 78, 39, 6, 3, 4, 5, 119); + + s2.x = _mm256_set_epi8 (88, 44, 33, 220, 11, 98, 76, 100, 34, 78, 39, + 6, 3, 4, 5, 219, 1, 2, 3, 4, 10, 20, 30, 90, + 80, 40, 100, 15, 98, 25, 98, 7); + + u.x = _mm256_subs_epu8 (s1.x, s2.x); + + for (i = 0; i < 32; i++) + { + tmp = (unsigned char) s1.a[i] - (unsigned char) s2.a[i]; + + if (tmp < 0) + tmp = 0; + + e[i] = tmp; + } + + if (check_union256i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-1.c new file mode 100644 index 000000000..bc0e3df63 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpsubusw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_subs_epu16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-2.c new file mode 100644 index 000000000..7fd16400a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-2.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + union256i_w u, s1, s2; + unsigned short e[16]; + int i, tmp; + + s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, + 65531, 40, 100, 15, 98, 25, 98, 7); + + s2.x = _mm256_set_epi16 (88, 44, 33, 220, 11, 98, 76, 100, + 34, 78, 39, 6, 3, 4, 5, 219); + + u.x = _mm256_subs_epu16 (s1.x, s2.x); + + for (i = 0; i < 16; i++) + { + tmp = (unsigned short) s1.a[i] - (unsigned short) s2.a[i]; + + if (tmp < 0) + tmp = 0; + + e[i] = tmp; + } + + if (check_union256i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c new file mode 100644 index 000000000..1cb90b5a8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */ +/* { dg-require-effective-target avx2 } */ + + +#define TYPE short +#define BIN_OP(a, b) ((a) - (b)) + +#include "avx2-vpop-check.h" + +/* { dg-final { scan-assembler-times "vpsubw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-1.c new file mode 100644 index 000000000..2c7c9bd11 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpckhbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpackhi_epi8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-2.c new file mode 100644 index 000000000..3d3f84934 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-2.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpckhbw256 (char *s1, char *s2, char *r) +{ + int i; + + for (i = 0; i < 8; i++) + { + r[2 * i] = s1[i + 8]; + r[2 * i + 1] = s2[i + 8]; + + r[2 * i + 16] = s1[i + 24]; + r[2 * i + 16 + 1] = s2[i + 24]; + } +} + +void static +avx2_test (void) +{ + union256i_b s1, s2, res; + char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpackhi_epi8 (s1.x, s2.x); + + compute_punpckhbw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-1.c new file mode 100644 index 000000000..e1e65eae3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpckhdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpackhi_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-2.c new file mode 100644 index 000000000..34499f01a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-2.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpckhwd256 (int *s1, int *s2, int *r) +{ + int i; + + for (i = 0; i < 2; i++) + { + r[2 * i] = s1[i + 2]; + r[2 * i + 1] = s2[i + 2]; + + r[2 * i + 4] = s1[i + 2 + 4]; + r[2 * i + 4 + 1] = s2[i + 2 + 4]; + } +} + +void static +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpackhi_epi32 (s1.x, s2.x); + + compute_punpckhwd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-1.c new file mode 100644 index 000000000..a8a5f37ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpckhqdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpackhi_epi64 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-2.c new file mode 100644 index 000000000..4668571c4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-2.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpckhqdq256 (long long int *s1, long long int *s2, long long int *r) +{ + r[0] = s1[1]; + r[1] = s2[1]; + r[2] = s1[3]; + r[3] = s2[3]; +} + +void static +avx2_test (void) +{ + union256i_q s1, s2, res; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpackhi_epi64 (s1.x, s2.x); + + compute_punpckhqdq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-1.c new file mode 100644 index 000000000..1ab034407 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpckhwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpackhi_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-2.c new file mode 100644 index 000000000..59c4ed89c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-2.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpckhwd256 (short *s1, short *s2, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + { + r[2 * i] = s1[i + 4]; + r[2 * i + 1] = s2[i + 4]; + + r[2 * i + 8] = s1[i + 4 + 8]; + r[2 * i + 8 + 1] = s2[i + 4 + 8]; + } +} + +void static +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpackhi_epi16 (s1.x, s2.x); + + compute_punpckhwd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-1.c new file mode 100644 index 000000000..45db9a41e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpcklbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpacklo_epi8 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-2.c new file mode 100644 index 000000000..49e41212f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-2.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpcklbw256 (char *s1, char *s2, char *r) +{ + int i; + + for (i = 0; i < 8; i++) + { + r[2 * i] = s1[i]; + r[2 * i + 1] = s2[i]; + + r[2 * i + 16] = s1[i + 16]; + r[2 * i + 16 + 1] = s2[i + 16]; + } +} + +void static +avx2_test (void) +{ + union256i_b s1, s2, res; + char res_ref[32]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 32; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpacklo_epi8 (s1.x, s2.x); + + compute_punpcklbw256 (s1.a, s2.a, res_ref); + + fail += check_union256i_b (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-1.c new file mode 100644 index 000000000..aff815b29 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpckldq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpacklo_epi32 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-2.c new file mode 100644 index 000000000..aba5e8092 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-2.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpcklwd256 (int *s1, int *s2, int *r) +{ + int i; + + for (i = 0; i < 2; i++) + { + r[2 * i] = s1[i]; + r[2 * i + 1] = s2[i]; + + r[2 * i + 4] = s1[i + 4]; + r[2 * i + 4 + 1] = s2[i + 4]; + } +} + +void static +avx2_test (void) +{ + union256i_d s1, s2, res; + int res_ref[8]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 8; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpacklo_epi32 (s1.x, s2.x); + + compute_punpcklwd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_d (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-1.c new file mode 100644 index 000000000..e8dd06da8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpcklqdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpacklo_epi64 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-2.c new file mode 100644 index 000000000..1c6db718a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-2.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpcklqdq256 (long long int *s1, long long int *s2, long long int *r) +{ + r[0] = s1[0]; + r[1] = s2[0]; + r[2] = s1[2]; + r[3] = s2[2]; +} + +void static +avx2_test (void) +{ + union256i_q s1, s2, res; + long long int res_ref[4]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 4; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpacklo_epi64 (s1.x, s2.x); + + compute_punpcklqdq256 (s1.a, s2.a, res_ref); + + fail += check_union256i_q (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-1.c new file mode 100644 index 000000000..6bcdf9bf9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpunpcklwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_unpacklo_epi16 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-2.c new file mode 100644 index 000000000..9f6f9c0d6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-2.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx2 } */ +/* { dg-options "-O2 -mavx2" } */ + +#include <string.h> +#include "avx2-check.h" + +#define N 0x5 + +static void +compute_punpcklwd256 (short *s1, short *s2, short *r) +{ + int i; + + for (i = 0; i < 4; i++) + { + r[2 * i] = s1[i]; + r[2 * i + 1] = s2[i]; + + r[2 * i + 8] = s1[i + 8]; + r[2 * i + 8 + 1] = s2[i + 8]; + } +} + +void static +avx2_test (void) +{ + union256i_w s1, s2, res; + short res_ref[16]; + int i, j; + int fail = 0; + + for (i = 0; i < 10; i++) + { + for (j = 0; j < 16; j++) + { + s1.a[j] = j * i; + s2.a[j] = j + 20; + } + + res.x = _mm256_unpacklo_epi16 (s1.x, s2.x); + + compute_punpcklwd256 (s1.a, s2.a, res_ref); + + fail += check_union256i_w (res, res_ref); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpxor-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpxor-1.c new file mode 100644 index 000000000..cfd43b0fc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpxor-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler "vpxor\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include <immintrin.h> + +volatile __m256i x; + +void extern +avx2_test (void) +{ + x = _mm256_xor_si256 (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpxor-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpxor-2.c new file mode 100644 index 000000000..be3264498 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vpxor-2.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx2" } */ +/* { dg-require-effective-target avx2 } */ + +#include "avx2-check.h" + +void static +avx2_test (void) +{ + int i; + union256i_q u, s1, s2; + int source1[8] = { 34545, 95567, 23443, 5675, 2323, 67, 2345, 45667 }; + int source2[8] = { 674, 57897, 93459, 45624, 54674, 1237, 67436, 79608 }; + int d[8]; + int e[8]; + + s1.x = _mm256_loadu_si256 ((__m256i *) source1); + s2.x = _mm256_loadu_si256 ((__m256i *) source2); + u.x = _mm256_xor_si256 (s1.x, s2.x); + + _mm256_storeu_si256 ((__m256i *) d, u.x); + + for (i = 0; i < 8; i++) + e[i] = source1[i] ^ source2[i]; + + if (checkVi (d, e, 8)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vshift-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vshift-1.c new file mode 100644 index 000000000..15f20c836 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx2-vshift-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mavx2" } */ +/* { dg-require-effective-target avx2 } */ + +#ifndef CHECK_H +#define CHECK_H "avx2-check.h" +#endif + +#ifndef TEST +#define TEST avx2_test +#endif + +#include "xop-vshift-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c new file mode 100644 index 000000000..e7eef6d7a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */ + +#define N 1024 + +float a[N], b[N+3], c[N]; + +void +avx_test (void) +{ + int i; + + for (i = 0; i < N; i++) + c[i] = a[i] * b[i+3]; +} + +/* { dg-final { scan-assembler-not "avx_loadups256" } } */ +/* { dg-final { scan-assembler "sse_loadups" } } */ +/* { dg-final { scan-assembler "vinsertf128" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c new file mode 100644 index 000000000..2947d9eab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c @@ -0,0 +1,28 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */ + +#define N 1024 + +char **ep; +char **fp; + +void +avx_test (void) +{ + int i; + char **ap; + char **bp; + char **cp; + + ap = ep; + bp = fp; + for (i = 128; i >= 0; i--) + { + *ap++ = *cp++; + *bp++ = 0; + } +} + +/* { dg-final { scan-assembler-not "avx_loaddqu256" } } */ +/* { dg-final { scan-assembler "sse2_loaddqu" } } */ +/* { dg-final { scan-assembler "vinsert.128" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c new file mode 100644 index 000000000..b0e0e79bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load -mtune=generic" } */ + +#define N 1024 + +double a[N], b[N+3], c[N]; + +void +avx_test (void) +{ + int i; + + for (i = 0; i < N; i++) + c[i] = a[i] * b[i+3]; +} + +/* { dg-final { scan-assembler-not "avx_loadupd256" } } */ +/* { dg-final { scan-assembler "sse2_loadupd" } } */ +/* { dg-final { scan-assembler "vinsertf128" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c new file mode 100644 index 000000000..e0eb92b57 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -dp -mavx -mno-avx256-split-unaligned-load -mno-avx256-split-unaligned-store" } */ + +#define N 1024 + +float a[N+3], b[N]; + +void +avx_test (void) +{ + int i; + + for (i = 0; i < N; i++) + b[i] = a[i+3] * 2; +} + +/* { dg-final { scan-assembler "avx_loadups256" } } */ +/* { dg-final { scan-assembler-not "sse_loadups" } } */ +/* { dg-final { scan-assembler-not "vinsertf128" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-5.c new file mode 100644 index 000000000..153b66f82 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-5.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */ + +#include "avx-check.h" + +#define N 8 + +float a[N+3] = { -1, -1, -1, 24.43, 68.346, 43.35, + 546.46, 46.79, 82.78, 82.7, 9.4 }; +float b[N]; +float c[N]; + +void +foo (void) +{ + int i; + + for (i = 0; i < N; i++) + b[i] = a[i+3] * 2; +} + +__attribute__ ((noinline)) +float +bar (float x) +{ + return x * 2; +} + +void +avx_test (void) +{ + int i; + + foo (); + + for (i = 0; i < N; i++) + c[i] = bar (a[i+3]); + + for (i = 0; i < N; i++) + if (b[i] != c[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-6.c new file mode 100644 index 000000000..2fa984cc4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-6.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */ + +#include "avx-check.h" + +#define N 4 + +double a[N+3] = { -1, -1, -1, 24.43, 68.346, 43.35, 546.46 }; +double b[N]; +double c[N]; + +void +foo (void) +{ + int i; + + for (i = 0; i < N; i++) + b[i] = a[i+3] * 2; +} + +__attribute__ ((noinline)) +double +bar (double x) +{ + return x * 2; +} + +void +avx_test (void) +{ + int i; + + foo (); + + for (i = 0; i < N; i++) + c[i] = bar (a[i+3]); + + for (i = 0; i < N; i++) + if (b[i] != c[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c new file mode 100644 index 000000000..ad16a5329 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */ + +#include "avx-check.h" + +#define N 128 + +char **ep; +char **fp; +char **mp; +char **lp; + +__attribute__ ((noinline)) +void +foo (void) +{ + mp = (char **) malloc (N); + lp = (char **) malloc (N); + ep = (char **) malloc (N); + fp = (char **) malloc (N); +} + +void +avx_test (void) +{ + int i; + char **ap, **bp, **cp, **dp; + char *str = "STR"; + + foo (); + + cp = mp; + dp = lp; + + for (i = N; i >= 0; i--) + { + *cp++ = str; + *dp++ = str; + } + + ap = ep; + bp = fp; + cp = mp; + dp = lp; + + for (i = N; i >= 0; i--) + { + *ap++ = *cp++; + *bp++ = *dp++; + } + + for (i = N; i >= 0; i--) + { + if (strcmp (*--ap, "STR") != 0) + abort (); + if (strcmp (*--bp, "STR") != 0) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c new file mode 100644 index 000000000..1a53ba14a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store" } */ + +#define N 1024 + +float a[N], b[N+3], c[N], d[N]; + +void +avx_test (void) +{ + int i; + + for (i = 0; i < N; i++) + b[i+3] = a[i] * 10.0; + + for (i = 0; i < N; i++) + d[i] = c[i] * 20.0; +} + +/* { dg-final { scan-assembler-not "avx_storeups256" } } */ +/* { dg-final { scan-assembler "vmovups.*\\*movv4sf_internal/3" } } */ +/* { dg-final { scan-assembler "vextractf128" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c new file mode 100644 index 000000000..977662beb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c @@ -0,0 +1,28 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store" } */ + +#define N 1024 + +char **ep; +char **fp; + +void +avx_test (void) +{ + int i; + char **ap; + char **bp; + char **cp; + + ap = ep; + bp = fp; + for (i = 128; i >= 0; i--) + { + *ap++ = *cp++; + *bp++ = 0; + } +} + +/* { dg-final { scan-assembler-not "avx_storedqu256" } } */ +/* { dg-final { scan-assembler "vmovdqu.*\\*movv16qi_internal/3" } } */ +/* { dg-final { scan-assembler "vextract.128" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c new file mode 100644 index 000000000..26c993be7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store -mtune=generic" } */ + +#define N 1024 + +double a[N], b[N+3], c[N], d[N]; + +void +avx_test (void) +{ + int i; + + for (i = 0; i < N; i++) + b[i+3] = a[i] * 10.0; + + for (i = 0; i < N; i++) + d[i] = c[i] * 20.0; +} + +/* { dg-final { scan-assembler-not "avx_storeupd256" } } */ +/* { dg-final { scan-assembler "vmovupd.*\\*movv2df_internal/3" } } */ +/* { dg-final { scan-assembler "vextractf128" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c new file mode 100644 index 000000000..6d734faa2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -dp -mavx -mno-avx256-split-unaligned-load -mno-avx256-split-unaligned-store" } */ + +#define N 1024 + +float a[N], b[N+3], c[N]; + +void +avx_test (void) +{ + int i; + + for (i = 0; i < N; i++) + b[i+3] = a[i] * c[i]; +} + +/* { dg-final { scan-assembler "avx_storeups256" } } */ +/* { dg-final { scan-assembler-not "sse_storeups" } } */ +/* { dg-final { scan-assembler-not "\\*avx_movv4sf_internal/3" } } */ +/* { dg-final { scan-assembler-not "vextractf128" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-5.c new file mode 100644 index 000000000..642da3cf0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-5.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store" } */ + +#include "avx-check.h" + +#define N 8 + +float a[N] = { 24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4 }; +float b[N+3]; +float c[N+3]; + +void +foo (void) +{ + int i; + + for (i = 0; i < N; i++) + b[i+3] = a[i] * 2; +} + +__attribute__ ((noinline)) +float +bar (float x) +{ + return x * 2; +} + +void +avx_test (void) +{ + int i; + + foo (); + + for (i = 0; i < N; i++) + c[i+3] = bar (a[i]); + + for (i = 0; i < N; i++) + if (b[i+3] != c[i+3]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-6.c new file mode 100644 index 000000000..a0de7a56f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-6.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store" } */ + +#include "avx-check.h" + +#define N 4 + +double a[N] = { 24.43, 68.346, 43.35, 546.46 }; +double b[N+3]; +double c[N+3]; + +void +foo (void) +{ + int i; + + for (i = 0; i < N; i++) + b[i+3] = a[i] * 2; +} + +__attribute__ ((noinline)) +double +bar (double x) +{ + return x * 2; +} + +void +avx_test (void) +{ + int i; + + foo (); + + for (i = 0; i < N; i++) + c[i+3] = bar (a[i]); + + for (i = 0; i < N; i++) + if (b[i+3] != c[i+3]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c new file mode 100644 index 000000000..4272dc3cd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store" } */ + +#include "avx-check.h" + +#define N 128 + +char **ep; +char **fp; + +__attribute__ ((noinline)) +void +foo (void) +{ + ep = (char **) malloc (N); + fp = (char **) malloc (N); +} + +void +avx_test (void) +{ + int i; + char **ap, **bp; + char *str = "STR"; + + foo (); + + ap = ep; + bp = fp; + + for (i = N; i >= 0; i--) + { + *ap++ = str; + *bp++ = str; + } + + for (i = N; i >= 0; i--) + { + if (strcmp (*--ap, "STR") != 0) + abort (); + if (strcmp (*--bp, "STR") != 0) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avxfp-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avxfp-1.c new file mode 100644 index 000000000..70bc8f1ed --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avxfp-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mfpmath=sse" } */ +/* { dg-final { scan-assembler "vmaxsd" } } */ +/* { dg-final { scan-assembler "vminsd" } } */ +double x; +t() +{ + x=x>5?x:5; +} + +double x; +q() +{ + x=x<5?x:5; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avxfp-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avxfp-2.c new file mode 100644 index 000000000..c34a1bd7c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/avxfp-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mfpmath=sse" } */ +/* { dg-final { scan-assembler "vmaxsd" } } */ +/* { dg-final { scan-assembler "vminsd" } } */ +double x; +q() +{ + x=x<5?5:x; +} + +double x; +q1() +{ + x=x>5?5:x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bitfield1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bitfield1.c new file mode 100644 index 000000000..00b7bfd71 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bitfield1.c @@ -0,0 +1,55 @@ +// Test for bitfield alignment in structs on IA-32 +// { dg-do run } +// { dg-require-effective-target ia32 } +// { dg-options "-O2" } +// { dg-options "-mno-align-double -mno-ms-bitfields" { target i?86-*-interix* i?86-*-cygwin* i?86-*-mingw*} } + +extern void abort (void); +extern void exit (int); + +struct A +{ + char a; + long long b : 61; + char c; +} a, a4[4]; + +struct B +{ + char d; + struct A e; + char f; +} b; + +struct C +{ + char g; + union U + { + char u1; + long long u2; + long long u3 : 64; + } h; + char i; +} c; + +int main (void) +{ + if (&a.c - &a.a != 12) + abort (); + if (sizeof (a) != 16) + abort (); + if (sizeof (a4) != 4 * 16) + abort (); + if (sizeof (b) != 2 * 4 + 16) + abort (); + if (__alignof__ (b.e) != 4) + abort (); + if (&c.i - &c.g != 12) + abort (); + if (sizeof (c) != 16) + abort (); + if (__alignof__ (c.h) != 4) + abort (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bitfield2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bitfield2.c new file mode 100644 index 000000000..e40059892 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bitfield2.c @@ -0,0 +1,23 @@ +// Test for bitfield alignment in structs on IA-32 +// { dg-do run } +// { dg-require-effective-target ia32 } +// { dg-options "-O2" } +// { dg-options "-mno-align-double -mno-ms-bitfields" { target i?86-*-interix* i?86-*-cygwin* i?86-*-mingw* } } + +extern void abort (void); +extern void exit (int); + +struct X { + char a; + long long : 0; + char b; +} x; + +int main () { + if (&x.b - &x.a != 4) + abort (); + if (sizeof (x) != 5) + abort (); + + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bitfield3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bitfield3.c new file mode 100644 index 000000000..1a161597c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bitfield3.c @@ -0,0 +1,25 @@ +// Test for bitfield alignment in structs on IA-32 +// { dg-do run } +// { dg-options "-O2" } +// { dg-additional-options "-mno-align-double -mno-ms-bitfields" { target *-*-interix* } } +// { dg-additional-options "-mno-ms-bitfields" { target *-*-mingw* } } + +extern void abort (void); +extern void exit (int); + +struct X { + int : 32; +}; + +struct Y { + int i : 32; +}; + +int main () { + if (__alignof__(struct X) != 1) + abort (); + if (__alignof__(struct Y) != 4) + abort (); + + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-1.c new file mode 100644 index 000000000..dc964ba3d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-1.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi " } */ +/* { dg-final { scan-assembler "andn\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "bextr\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "blsi\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "blsmsk\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "blsr\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "tzcntl\[^\\n]*(%|)eax" } } */ + +#include <x86intrin.h> + +unsigned int +func_andn32 (unsigned int X, unsigned int Y) +{ + return __andn_u32(X, Y); +} + +unsigned int +func_bextr32 (unsigned int X, unsigned int Y) +{ + return __bextr_u32(X, Y); +} + +unsigned int +func_blsi32 (unsigned int X) +{ + return __blsi_u32(X); +} + +unsigned int +func_blsmsk32 (unsigned int X) +{ + return __blsmsk_u32(X); +} + +unsigned int +func_blsr32 (unsigned int X) +{ + return __blsr_u32(X); +} + +unsigned int +func_tzcnt32 (unsigned int X) +{ + return __tzcnt_u32(X); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-2.c new file mode 100644 index 000000000..56f73876d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-2.c @@ -0,0 +1,46 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mbmi " } */ +/* { dg-final { scan-assembler "andn\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "bextr\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "blsi\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "blsmsk\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "blsr\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "tzcntq\[^\\n]*(%|)rax" } } */ + +#include <x86intrin.h> + +unsigned long long +func_andn64 (unsigned long long X, unsigned long long Y) +{ + return __andn_u64 (X, Y); +} + +unsigned long long +func_bextr64 (unsigned long long X, unsigned long long Y) +{ + return __bextr_u64 (X, Y); +} + +unsigned long long +func_blsi64 (unsigned long long X) +{ + return __blsi_u64 (X); +} + +unsigned long long +func_blsmsk64 (unsigned long long X) +{ + return __blsmsk_u64 (X); +} + +unsigned long long +func_blsr64 (unsigned long long X) +{ + return __blsr_u64 (X); +} + +unsigned long long +func_tzcnt64 (unsigned long long X) +{ + return __tzcnt_u64 (X); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-3.c new file mode 100644 index 000000000..ddc5e0f66 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi " } */ +/* { dg-final { scan-assembler "tzcntw\[^\\n]*(%|)ax" } } */ + +#include <x86intrin.h> + +unsigned short +func_tzcnt16 (unsigned short X) +{ + return __tzcnt_u16(X); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-4.c new file mode 100644 index 000000000..e0a116162 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-4.c @@ -0,0 +1,13 @@ +/* { dg-do link } */ +/* { dg-options "-O2 -mbmi" } */ + +#include <x86intrin.h> + +/* Test that a constant operand 0 to tzcnt gets folded. */ +extern void link_error(void); +int main() +{ + if (__tzcnt_u32(0) != 32) + link_error(); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-5.c new file mode 100644 index 000000000..546a593c8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-5.c @@ -0,0 +1,13 @@ +/* { dg-do link { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mbmi" } */ + +#include <x86intrin.h> + +/* Test that a constant operand 0 to tzcnt gets folded. */ +extern void link_error(void); +int main() +{ + if (__tzcnt_u64(0) != 64) + link_error(); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-6.c new file mode 100644 index 000000000..a4489e0b5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-6.c @@ -0,0 +1,13 @@ +/* { dg-do link } */ +/* { dg-options "-O2 -mbmi" } */ + +#include <x86intrin.h> + +/* Test that a constant operand 0 to tzcnt gets folded. */ +extern void link_error(void); +int main() +{ + if (__tzcnt_u16(0) != 16) + link_error(); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-andn-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-andn-1.c new file mode 100644 index 000000000..bf0685ad3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-andn-1.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { bmi && { ! ia32 } } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +long long calc_andn_u64 (long long src1, + long long src2, + long long dummy) +{ + return (~src1 + dummy) & (src2); +} + +static void +bmi_test() +{ + unsigned i; + + long long src = 0xfacec0ffeefacec0; + long long res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_andn_u64 (src, src+i, 0); + res = __andn_u64 (src, src+i); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c new file mode 100644 index 000000000..a7ee07653 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-andn-1.c" + +/* { dg-final { scan-assembler-times "bmi_andn_di" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-andn-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-andn-2.c new file mode 100644 index 000000000..bb998f3af --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-andn-2.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { bmi } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +long long calc_andn_u32 (int src1, int src2, int dummy) +{ + return (~src1+dummy) & (src2); +} + +static void +bmi_test() +{ + unsigned i; + + int src = 0xfacec0ff; + int res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_andn_u32 (src, src+i, 0); + res = __andn_u32 (src, src+i); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c new file mode 100644 index 000000000..72fe02639 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-andn-2.c" + +/* { dg-final { scan-assembler-times "bmi_andn_si" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-bextr-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-bextr-1.c new file mode 100644 index 000000000..4abe63e54 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-bextr-1.c @@ -0,0 +1,49 @@ +/* { dg-do run { target { bmi && { ! ia32 } } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +long long calc_bextr_u64 (unsigned long long src1, + unsigned long long src2) +{ + long long res = 0; + unsigned char start = (src2 & 0xff); + unsigned char len = (int) ((src2 >> 8) & 0xff); + if (start < 64) { + unsigned i; + unsigned last = (start+len) < 64 ? start+len : 64; + + src1 >>= start; + for (i=start; i<last; ++i) { + res |= (src1 & 1) << (i-start); + src1 >>= 1; + } + } + + return res; +} + +static void +bmi_test () +{ + unsigned i; + unsigned char start, len; + unsigned long long src1 = 0xfacec0ffeefacec0; + unsigned long long res, res_ref, src2; + + for (i=0; i<5; ++i) { + start = (i * 1983) % 64; + len = i + (i * 1983) % 64; + + src1 = src1 * 3; + src2 = start | (((long long)len) << 8); + + res_ref = calc_bextr_u64 (src1, src2); + res = __bextr_u64 (src1, src2); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c new file mode 100644 index 000000000..4ccfbdc98 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-bextr-1.c" + +/* { dg-final { scan-assembler-times "bmi_bextr_di" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-bextr-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-bextr-2.c new file mode 100644 index 000000000..2ce625966 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-bextr-2.c @@ -0,0 +1,49 @@ +/* { dg-do run { target { bmi } } } */ +/* { dg-require-effective-target bmi } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +unsigned calc_bextr_u32 (unsigned src1, unsigned src2) +{ + unsigned res = 0; + unsigned char start = (src2 & 0xff); + unsigned char len = (int) ((src2 >> 8) & 0xff); + if (start < 32) { + unsigned i; + unsigned last = (start+len) < 32 ? start+len : 32; + + src1 >>= start; + for (i=start; i<last; ++i) { + res |= (src1 & 1) << (i-start); + src1 >>= 1; + } + } + + return res; +} + +static void +bmi_test () +{ + unsigned i; + unsigned char start, len; + unsigned src1 = 0xfacec0ff; + unsigned res, res_ref, src2; + + for (i=0; i<5; ++i) { + start = (i * 1983) % 32; + len = i + (i * 1983) % 32; + + src1 = src1 * 3; + src2 = start | (((unsigned)len) << 8); + + res_ref = calc_bextr_u32 (src1, src2); + res = __bextr_u32 (src1, src2); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c new file mode 100644 index 000000000..282a3e400 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-bextr-2.c" + +/* { dg-final { scan-assembler-times "bmi_bextr_si" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsi-1.c new file mode 100644 index 000000000..e7f2c896d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsi-1.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { bmi && { ! ia32 } } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +/* To fool compiler, so it not generate blsi here. */ +long long calc_blsi_u64 (long long src1, long long src2) +{ + return (-src1) & (src2); +} + +static void +bmi_test() +{ + unsigned i; + + long long src = 0xfacec0ffeefacec0; + long long res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_blsi_u64 (src, src); + res = __blsi_u64 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c new file mode 100644 index 000000000..e9e0ecb67 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-blsi-1.c" + +/* { dg-final { scan-assembler-times "bmi_blsi_di" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsi-2.c new file mode 100644 index 000000000..b6633a980 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsi-2.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { bmi } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +/* To fool compiler, so it not generate blsi here. */ +int calc_blsi_u32 (int src1, int src2) +{ + return (-src1) & (src2); +} + +static void +bmi_test() +{ + unsigned i; + int src = 0xfacec0ff; + int res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_blsi_u32 (src, src); + res = __blsi_u32 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c new file mode 100644 index 000000000..be9ca3f63 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-blsi-2.c" + +/* { dg-final { scan-assembler-times "bmi_blsi_si" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1.c new file mode 100644 index 000000000..5498007c3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { bmi && { ! ia32 } } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +/* Trick compiler in order not to generate target insn here. */ +long long calc_blsmsk_u64 (long long src1, long long src2) +{ + return (src1-1) ^ (src2); +} + +static void +bmi_test () +{ + unsigned i; + long long src = 0xfacec0ffeefacec0; + long long res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_blsmsk_u64 (src, src); + res = __blsmsk_u64 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c new file mode 100644 index 000000000..4e6cb7b36 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-blsmsk-1.c" + +/* { dg-final { scan-assembler-times "bmi_blsmsk_di" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2.c new file mode 100644 index 000000000..be0ebf900 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { bmi } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +/* Trick compiler in order not to generate target insn here. */ +int calc_blsmsk_u32 (int src1, int src2) +{ + return (src1-1) ^ (src2); +} + +static void +bmi_test () +{ + unsigned i; + int src = 0xfacec0ff; + int res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_blsmsk_u32 (src, src); + res = __blsmsk_u32 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c new file mode 100644 index 000000000..f6f6babff --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-blsmsk-2.c" + +/* { dg-final { scan-assembler-times "bmi_blsmsk_si" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsr-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsr-1.c new file mode 100644 index 000000000..68e01f39f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsr-1.c @@ -0,0 +1,29 @@ +/* { dg-do run { target { bmi && { ! ia32 } } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +long long calc_blsr_u64 (long long src1, long long src2) +{ + return (src1-1) & (src2); +} + +static void +bmi_test() +{ + unsigned i; + long long src = 0xfacec0ffeefacec0; + long long res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_blsr_u64 (src, src); + res = __blsr_u64 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c new file mode 100644 index 000000000..79241ca8f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-blsr-1.c" + +/* { dg-final { scan-assembler-times "bmi_blsr_di" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsr-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsr-2.c new file mode 100644 index 000000000..b3fc4e5e9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsr-2.c @@ -0,0 +1,29 @@ +/* { dg-do run { target { bmi } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +int calc_blsr_u32 (int src1, int src2) +{ + return (src1-1) & (src2); +} + +static void +bmi_test () +{ + unsigned i; + int src = 0xfacec0ff; + int res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_blsr_u32 (src, src); + res = __blsr_u32 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c new file mode 100644 index 000000000..d88c16e4d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi -fno-inline -dp" } */ + +#include "bmi-blsr-2.c" + +/* { dg-final { scan-assembler-times "bmi_blsr_si" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-check.h new file mode 100644 index 000000000..8fad38ad0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-check.h @@ -0,0 +1,39 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void bmi_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + bmi_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (__get_cpuid_max (0, NULL) < 7) + return 0; + + __cpuid_count (7, 0, eax, ebx, ecx, edx); + + /* Run BMI test only if host has BMI support. */ + if (ebx & bit_BMI) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1.c new file mode 100644 index 000000000..a9fce15ce --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1.c @@ -0,0 +1,37 @@ +/* { dg-do run { target { bmi && { ! ia32 } } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +long long calc_tzcnt_u64 (long long src) +{ + int i; + int res = 0; + + while ( (res<64) && ((src&1) == 0)) { + ++res; + src >>= 1; + } + + return res; +} + +static void +bmi_test () +{ + unsigned i; + long long src = 0xfacec0ffeefacec0; + long long res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_tzcnt_u64 (src); + res = __tzcnt_u64 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c new file mode 100644 index 000000000..e283c3154 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include "bmi-tzcnt-1.c" + +/* { dg-final { scan-assembler-times "tzcntq" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2.c new file mode 100644 index 000000000..1a9235b59 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2.c @@ -0,0 +1,36 @@ +/* { dg-do run { target { bmi } } } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include <x86intrin.h> + +#include "bmi-check.h" + +int calc_tzcnt_u32 (int src) +{ + int i; + int res = 0; + + while ( (res<32) && ((src&1) == 0)) { + ++res; + src >>= 1; + } + return res; +} + +static void +bmi_test () +{ + unsigned i; + int src = 0xfacec0ff; + int res, res_ref; + + for (i=0; i<5; ++i) { + src = i + src << i; + + res_ref = calc_tzcnt_u32 (src); + res = __tzcnt_u32 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c new file mode 100644 index 000000000..2cdb3f443 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi -fno-inline" } */ + +#include "bmi-tzcnt-2.c" + +/* { dg-final { scan-assembler-times "tzcntl" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1.c new file mode 100644 index 000000000..68df8b71d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned +calc_bzhi_u32 (unsigned a, int l) +{ + unsigned res = a; + int i; + for (i = 0; i < 32 - l; ++i) + res &= ~(1 << (31 - i)); + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned src = 0xce7ace0f; + unsigned res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_bzhi_u32 (src, i * 2); + res = _bzhi_u32 (src, i * 2); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c new file mode 100644 index 000000000..05be7a837 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-bzhi32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_bzhi_si3" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1.c new file mode 100644 index 000000000..1ffe135b4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_bzhi_u64 (unsigned long long a, int l) +{ + unsigned long long res = a; + int i; + for (i = 0; i < 64 - l; ++i) + res &= ~(1LL << (63 - i)); + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned long long src = 0xce7ace0ce7ace0ff; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_bzhi_u64 (src, i * 2); + res = _bzhi_u64 (src, i * 2); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c new file mode 100644 index 000000000..dc4a94cc3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-bzhi64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_bzhi_di3" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-check.h new file mode 100644 index 000000000..c933a49f2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-check.h @@ -0,0 +1,39 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void bmi2_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + bmi2_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (__get_cpuid_max (0, NULL) < 7) + return 0; + + __cpuid_count (7, 0, eax, ebx, ecx, edx); + + /* Run BMI2 test only if host has BMI2 support. */ + if (ebx & bit_BMI2) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1.c new file mode 100644 index 000000000..5e6028781 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1.c @@ -0,0 +1,47 @@ +/* { dg-do run { target { bmi2 && { ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_mul_u32 (unsigned volatile a, unsigned b) +{ + unsigned long long res = 0; + int i; + for (i = 0; i < b; ++i) + res += a; + + return res; +} + +__attribute__((noinline, regparm (2))) +unsigned long long +gen_mulx (unsigned a, unsigned b) +{ + unsigned long long res; + + res = (unsigned long long)a * b; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned a = 0xce7ace0; + unsigned b = 0xfacefff; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + a = a * (i + 1); + b = b / (i + 1); + + res_ref = calc_mul_u32 (a, b); + res = gen_mulx (a, b); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1a.c new file mode 100644 index 000000000..cf3bb085c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ia32 } } } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-mulx32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_umulsidi3_1" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2.c new file mode 100644 index 000000000..7c99b2dae --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2.c @@ -0,0 +1,47 @@ +/* { dg-do run { target { bmi2 && { ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_mul_u32 (unsigned volatile a, unsigned b) +{ + unsigned long long res = 0; + int i; + for (i = 0; i < b; ++i) + res += a; + + return res; +} + +__attribute__((noinline, regparm (2))) +unsigned calc_mulx_u32 (unsigned x, unsigned y, unsigned *res_h) +{ + return (unsigned) _mulx_u32 (x, y, res_h); +} + +static void +bmi2_test () +{ + unsigned i; + unsigned a = 0xce7ace0; + unsigned b = 0xfacefff; + unsigned res_l, res_h; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + a = a * (i + 1); + b = b / (i + 1); + + res_ref = calc_mul_u32 (a, b); + res_l = calc_mulx_u32 (a, b, &res_h); + + res = ((unsigned long long) res_h << 32) | res_l; + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2a.c new file mode 100644 index 000000000..356d593c7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ia32 } } } */ +/* { dg-options "-O2 -mbmi2" } */ + +#include "bmi2-mulx32-2.c" + +/* { dg-final { scan-assembler-times "mulx\[ \\t\]+\[^\n\]*" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1.c new file mode 100644 index 000000000..68449466c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1.c @@ -0,0 +1,36 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned __int128 +calc_mul_u64 (unsigned long long volatile a, unsigned long long b) +{ + unsigned __int128 res = 0; + int i; + for (i = 0; i < b; ++i) + res += (unsigned __int128) a; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned long long a = 0xce7ace0ce7ace0; + unsigned long long b = 0xface; + unsigned __int128 res, res_ref; + + for (i=0; i<5; ++i) { + a = a * (i + 1); + b = b / (i + 1); + + res_ref = calc_mul_u64 (a, b); + res = (unsigned __int128) a * b; + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1a.c new file mode 100644 index 000000000..592d713e9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-mulx64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_umulditi3_1" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2.c new file mode 100644 index 000000000..55b355462 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2.c @@ -0,0 +1,51 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned __int128 +calc_mul_u64 (unsigned long long volatile a, unsigned long long b) +{ + unsigned __int128 res = 0; + int i; + for (i = 0; i < b; ++i) + res += (unsigned __int128) a; + + return res; +} + +__attribute__((noinline)) +unsigned long long +calc_mulx_u64 (unsigned long long x, + unsigned long long y, + unsigned long long *res_h) +{ + return _mulx_u64 (x, y, res_h); +} + + +static void +bmi2_test () +{ + unsigned i; + unsigned long long a = 0xce7ace0ce7ace0; + unsigned long long b = 0xface; + unsigned long long res_l, res_h; + unsigned __int128 res, res_ref; + + for (i=0; i<5; ++i) { + a = a * (i + 1); + b = b / (i + 1); + + res_ref = calc_mul_u64 (a, b); + + res_l = calc_mulx_u64 (a, b, &res_h); + + res = ((unsigned __int128) res_h << 64) | res_l; + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2a.c new file mode 100644 index 000000000..d8b3e0ecc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi2" } */ + +#include "bmi2-mulx64-2.c" + +/* { dg-final { scan-assembler-times "mulx\[ \\t\]+\[^\n\]*" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1.c new file mode 100644 index 000000000..5aecf5717 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned +calc_pdep_u32 (unsigned a, int mask) +{ + unsigned res = 0; + int i, k = 0; + + for (i = 0; i < 32; ++i) + if (mask & (1 << i)) { + res |= ((a & (1 << k)) >> k) << i; + ++k; + } + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned src = 0xce7acc; + unsigned res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_pdep_u32 (src, i * 3); + res = _pdep_u32 (src, i * 3); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c new file mode 100644 index 000000000..87888fcff --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-pdep32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_pdep_si3" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1.c new file mode 100644 index 000000000..f718b2f35 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1.c @@ -0,0 +1,38 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_pdep_u64 (unsigned long long a, unsigned long long mask) +{ + unsigned long long res = 0; + unsigned long long i, k = 0; + + for (i = 0; i < 64; ++i) + if (mask & (1LL << i)) { + res |= ((a & (1LL << k)) >> k) << i; + ++k; + } + return res; +} + +static void +bmi2_test () +{ + unsigned long long i; + unsigned long long src = 0xce7acce7acce7ac; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_pdep_u64 (src, ~(i * 3)); + res = _pdep_u64 (src, ~(i * 3)); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c new file mode 100644 index 000000000..8163c4062 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-pdep64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_pdep_di3" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pext32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pext32-1.c new file mode 100644 index 000000000..7fe78378e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pext32-1.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned +calc_pext_u32 (unsigned a, unsigned mask) +{ + unsigned res = 0; + int i, k = 0; + + for (i = 0; i < 32; ++i) + if (mask & (1 << i)) { + res |= ((a & (1 << i)) >> i) << k; + ++k; + } + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned src = 0xce7acc; + unsigned res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_pext_u32 (src, ~(i * 3)); + res = _pext_u32 (src, ~(i * 3)); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c new file mode 100644 index 000000000..c4a6deeca --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-pext32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_pext_si3" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pext64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pext64-1.c new file mode 100644 index 000000000..685074966 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pext64-1.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2" } */ + +#include <x86intrin.h> +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_pext_u64 (unsigned long long a, unsigned long long mask) +{ + unsigned long long res = 0; + int i, k = 0; + + for (i = 0; i < 64; ++i) + if (mask & (1LL << i)) { + res |= ((a & (1LL << i)) >> i) << k; + ++k; + } + + return res; +} + +static void +bmi2_test () +{ + unsigned long long i; + unsigned long long src = 0xce7acce7acce7ac; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_pext_u64 (src, ~(i * 3)); + res = _pext_u64 (src, ~(i * 3)); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c new file mode 100644 index 000000000..aaf06c1f2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-pext64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_pext_di3" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1.c new file mode 100644 index 000000000..d7f6f3b62 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1.c @@ -0,0 +1,36 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned +calc_rorx_u32 (unsigned a, int l) +{ + unsigned volatile res = a; + int i; + for (i = 0; i < l; ++i) + res = (res >> 1) | ((res & 1) << 31); + + return res; +} + +#define SHIFT_VAL 0x0e + +static void +bmi2_test () +{ + unsigned i; + unsigned src = 0xce7ace0; + unsigned res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_rorx_u32 (src, SHIFT_VAL); + res = (src >> SHIFT_VAL) | (src << (32 - SHIFT_VAL)); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1a.c new file mode 100644 index 000000000..bb3b28d6c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-rorx32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_rorxsi3_1" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1.c new file mode 100644 index 000000000..ccd60c28a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1.c @@ -0,0 +1,36 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_rorx_u64 (unsigned long long a, int l) +{ + unsigned long long volatile res = a; + int i; + for (i = 0; i < l; ++i) + res = (res >> 1) | ((res&1)<< 63); + + return res; +} + +#define SHIFT_VAL 0x1e + +static void +bmi2_test () +{ + unsigned i; + unsigned long long src = 0xce7ace0ce7ace0; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_rorx_u64 (src, SHIFT_VAL); + res = (src >> SHIFT_VAL) | (src << (64 - SHIFT_VAL)); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1a.c new file mode 100644 index 000000000..2a7a7a08c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-rorx64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_rorxdi3_1" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1.c new file mode 100644 index 000000000..8224b6f60 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +int +calc_sarx_u32 (int a, int l) +{ + int volatile res = a; + int i; + for (i = 0; i < l; ++i) + res >>= 1; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + int src = 0xfce7ace0; + int res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_sarx_u32 (src, i + 1); + res = src >> (i + 1); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1a.c new file mode 100644 index 000000000..f10d60b3e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-sarx32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_ashrsi3" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1.c new file mode 100644 index 000000000..a43b2025d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +long long +calc_sarx_u64 (long long a, int l) +{ + long long volatile res = a; + int i; + for (i = 0; i < l; ++i) + res >>= 1; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + long long src = 0xfce7ace0ce7ace0; + long long res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_sarx_u64 (src, i + 1); + res = src >> (i + 1); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1a.c new file mode 100644 index 000000000..bcf0fd44c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-sarx64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_ashrdi3" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1.c new file mode 100644 index 000000000..0bf970282 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +int +calc_shlx_u32 (int a, int l) +{ + int volatile res = a; + int i; + for (i = 0; i < l; ++i) + res <<= 1; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + int src = 0xfce7ace0; + int res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_shlx_u32 (src, i + 1); + res = src << (i + 1); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1a.c new file mode 100644 index 000000000..215e5d3d7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-shlx32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_ashlsi3" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1.c new file mode 100644 index 000000000..2d2ec155e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { bmi2 } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned +calc_shrx_u32 (unsigned a, int l) +{ + unsigned volatile res = a; + int i; + for (i = 0; i < l; ++i) + res >>= 1; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned src = 0xce7ace0; + unsigned res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_shrx_u32 (src, i + 1); + res = src >> (i + 1); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1a.c new file mode 100644 index 000000000..24c53d458 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-shrx32-1.c" + +/* { dg-final { scan-assembler-times "bmi2_lshrsi3" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1.c new file mode 100644 index 000000000..81d232e76 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { bmi2 && { ! ia32 } } } } */ +/* { dg-options "-mbmi2 -O2 -dp" } */ + +#include "bmi2-check.h" + +__attribute__((noinline)) +unsigned long long +calc_shrx_u64 (unsigned long long a, int l) +{ + unsigned long long volatile res = a; + int i; + for (i = 0; i < l; ++i) + res >>= 1; + + return res; +} + +static void +bmi2_test () +{ + unsigned i; + unsigned long long src = 0xce7ace0ce7ace0; + unsigned long long res, res_ref; + + for (i = 0; i < 5; ++i) { + src = src * (i + 1); + + res_ref = calc_shrx_u64 (src, i + 1); + res = src >> (i + 1); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1a.c new file mode 100644 index 000000000..783043935 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi2 -dp" } */ + +#include "bmi2-shrx64-1.c" + +/* { dg-final { scan-assembler-times "bmi2_lshrdi3" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/branch-cost1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/branch-cost1.c new file mode 100644 index 000000000..ed873fa71 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/branch-cost1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-gimple -mbranch-cost=0" } */ + +extern int doo (void); + +int +foo (int a, int b) +{ + if (a && b) + return doo (); + return 0; +} + +/* { dg-final { scan-tree-dump-times "if " 2 "gimple" } } */ +/* { dg-final { scan-tree-dump-not " & " "gimple" } } */ +/* { dg-final { cleanup-tree-dump "gimple" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/branch-cost2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/branch-cost2.c new file mode 100644 index 000000000..4d754d57b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/branch-cost2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-gimple -mbranch-cost=2" } */ + +extern int doo (void); + +int +foo (int a, int b) +{ + if (a && b) + return doo (); + return 0; +} + +/* { dg-final { scan-tree-dump-times "if " 1 "gimple" } } */ +/* { dg-final { scan-tree-dump-times " & " 1 "gimple" } } */ +/* { dg-final { cleanup-tree-dump "gimple" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/branch-cost3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/branch-cost3.c new file mode 100644 index 000000000..3b69f503f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/branch-cost3.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-gimple -mbranch-cost=2" } */ + +extern int doo (void); + +int +foo (_Bool a, _Bool b) +{ + if (a && b) + return doo (); + return 0; +} + +/* { dg-final { scan-tree-dump-times "if " 1 "gimple" } } */ +/* { dg-final { scan-tree-dump-times " & " 1 "gimple" } } */ +/* { dg-final { cleanup-tree-dump "gimple" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/branch-cost4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/branch-cost4.c new file mode 100644 index 000000000..5904b0da2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/branch-cost4.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-gimple -mbranch-cost=0" } */ + +extern int doo (void); + +int +foo (_Bool a, _Bool b) +{ + if (a && b) + return doo (); + return 0; +} + +/* { dg-final { scan-tree-dump-times "if " 2 "gimple" } } */ +/* { dg-final { scan-tree-dump-not " & " "gimple" } } */ +/* { dg-final { cleanup-tree-dump "gimple" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/brokensqrt.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/brokensqrt.c new file mode 100644 index 000000000..836d3b37d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/brokensqrt.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */ +/* { dg-require-effective-target sse } */ +#include "sse-check.h" + +extern float sqrtf (float); +float __attribute__((noinline)) broken (float a, float b) +{ + return sqrtf (a / b); +} + +extern void abort (void); +extern void *memcpy (void *, const void *, __SIZE_TYPE__); +static void +sse_test (void) +{ + int i; + float x; + char buf[sizeof (float)]; + x = broken (0.0f, 10000.0f); + /* A convoluted way to check for the correct result (zero) for all + floating point formats. + We can't use ==, !=, or range checks, or isinf/isnan/isunordered, + because all of these will not do the right thing under -ffast-math, + as they can assume that neither nan nor inf are returned. */ + memcpy (&buf, &x, sizeof (float)); + for (i = 0; i < sizeof (float); i++) + if (buf[i] != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bt-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bt-1.c new file mode 100644 index 000000000..3727155d6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bt-1.c @@ -0,0 +1,15 @@ +/* PR target/36473 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=core2" } */ + +extern void foo (void); + +int test(int x, int n) +{ + if (x & ( 0x01 << n )) + foo (); + + return 0; +} + +/* { dg-final { scan-assembler "btl\[ \t\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bt-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bt-2.c new file mode 100644 index 000000000..34fa829e4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bt-2.c @@ -0,0 +1,16 @@ +/* PR target/36473 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=core2" } */ + +extern void foo (void); + +int test(long x, long n) +{ + if (x & ( (long)0x01 << n )) + foo (); + + return 0; +} + +/* { dg-final { scan-assembler "btl\[ \t\]" { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler "btq\[ \t\]" { target lp64 } } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bt-mask-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bt-mask-1.c new file mode 100644 index 000000000..bdcfd558a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bt-mask-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=core2" } */ + +void foo (void); + +int test (int x, int n) +{ + n &= 0x1f; + + if (x & (0x01 << n)) + foo (); + + return 0; +} + +/* { dg-final { scan-assembler-not "and\[lq\]\[ \t\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bt-mask-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bt-mask-2.c new file mode 100644 index 000000000..babfc2bcd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/bt-mask-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=core2" } */ + +void foo (void); + +int test (long x, long n) +{ + n &= 0x3f; + + if (x & ((long)0x01 << n)) + foo (); + + return 0; +} + +/* { dg-final { scan-assembler-not "and\[lq\]\[ \t\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c new file mode 100644 index 000000000..badfe03a9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c @@ -0,0 +1,42 @@ +/* __builtin_apply_args () and __builtin_return () built-in functions does + not function properly when -mmmx is used in compile flags. + __builtin_apply_args () saves all registers that pass arguments to a + function, including %mm0-%mm3, to a memory block, and __builtin_return () + restores %mm0, from a return memory block, as it can be used as a + function return register. Unfortunatelly, when MMX registers are touched, + i387 FPU switches to MMX mode, and no FP operation is possible until emms + instruction is issued. */ + +/* This test case is adapted from gcc.dg/builtin-apply4.c. */ + +/* { dg-do run { xfail { ! *-*-darwin* } } } */ +/* { dg-options "-O2 -mmmx" } */ +/* { dg-require-effective-target ia32 } */ + +#include "mmx-check.h" + +extern void abort (void); + +double +foo (double arg) +{ + if (arg != 116.0) + abort (); + + return arg + 1.0; +} + +inline double +bar (double arg) +{ + foo (arg); + __builtin_return (__builtin_apply ((void (*)()) foo, + __builtin_apply_args (), 16)); +} + +static void +mmx_test (void) +{ + if (bar (116.0) != 117.0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-assume-aligned-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-assume-aligned-1.c new file mode 100644 index 000000000..4acf48bdc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-assume-aligned-1.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse2 -mno-avx" } */ + +void +test1 (double *out1, double *out2, double *out3, double *in1, + double *in2, int len) +{ + int i; + double *__restrict o1 = __builtin_assume_aligned (out1, 16); + double *__restrict o2 = __builtin_assume_aligned (out2, 16); + double *__restrict o3 = __builtin_assume_aligned (out3, 16); + double *__restrict i1 = __builtin_assume_aligned (in1, 16); + double *__restrict i2 = __builtin_assume_aligned (in2, 16); + for (i = 0; i < len; ++i) + { + o1[i] = i1[i] * i2[i]; + o2[i] = i1[i] + i2[i]; + o3[i] = i1[i] - i2[i]; + } +} + +void +test2 (double *out1, double *out2, double *out3, double *in1, + double *in2, int len) +{ + int i, align = 32, misalign = 16; + out1 = __builtin_assume_aligned (out1, align, misalign); + out2 = __builtin_assume_aligned (out2, align, 16); + out3 = __builtin_assume_aligned (out3, 32, misalign); + in1 = __builtin_assume_aligned (in1, 32, 16); + in2 = __builtin_assume_aligned (in2, 32, 0); + for (i = 0; i < len; ++i) + { + out1[i] = in1[i] * in2[i]; + out2[i] = in1[i] + in2[i]; + out3[i] = in1[i] - in2[i]; + } +} + +/* { dg-final { scan-assembler-not "movhpd" } } */ +/* { dg-final { scan-assembler-not "movlpd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c new file mode 100644 index 000000000..0f94025c5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "builtin_bswap" } } */ + +long foo (long a) +{ + long b; + +#if __LP64__ + b = __builtin_bswap64 (a); +#else + b = __builtin_bswap32 (a); +#endif + + return b; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-bswap-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-bswap-2.c new file mode 100644 index 000000000..818aa76b9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-bswap-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=nocona" } */ +/* { dg-final { scan-assembler-not "bswap\[ \t\]" } } */ + +int foo(int x) +{ + int t = __builtin_bswap32 (x); + return __builtin_bswap32 (t); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-bswap-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-bswap-3.c new file mode 100644 index 000000000..d5d612f60 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-bswap-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "bswapdi2" } } */ + +long long foo (long long x) +{ + return __builtin_bswap64 (x); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-bswap-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-bswap-4.c new file mode 100644 index 000000000..65198aee8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-bswap-4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "bswap\[ \t\]" } } */ + +short foo (short x) +{ + return __builtin_bswap16 (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-copysign.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-copysign.c new file mode 100644 index 000000000..175b931c7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-copysign.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define TEST_SET(MODE, CEXT) \ +MODE test1##CEXT(MODE a) { return -a; } \ +MODE test2##CEXT(MODE a) { return __builtin_fabs##CEXT(a); } \ +MODE test3##CEXT(MODE a) { return __builtin_copysign##CEXT(a, 0.0); } \ +MODE test4##CEXT(MODE a) { return __builtin_copysign##CEXT(a, -1.0); } \ +MODE test5##CEXT(MODE a, MODE b) { return __builtin_copysign##CEXT(a, b); } + +TEST_SET (float, f) +TEST_SET (double, ) +TEST_SET (long double, l) +TEST_SET (__float128, q) diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-unreachable.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-unreachable.c new file mode 100644 index 000000000..91923a2df --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin-unreachable.c @@ -0,0 +1,13 @@ +/* This should return 1 without setting up a stack frame or + jumping. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -fomit-frame-pointer" } */ +int h (char *p) +{ + if (*p) + __builtin_unreachable (); + return p ? 1 : 0; +} +/* { dg-final { scan-assembler-not "%e\[bs\]p" } } */ +/* { dg-final { scan-assembler-not "\[\\t \]+j" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin_target.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin_target.c new file mode 100644 index 000000000..c40983e6b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/builtin_target.c @@ -0,0 +1,284 @@ +/* This test checks if the __builtin_cpu_is and __builtin_cpu_supports calls + are recognized. It also independently uses CPUID to get cpu type and + features supported and checks if the builtins correctly identify the + platform. The code to do the identification is adapted from + libgcc/config/i386/cpuinfo.c. */ + +/* { dg-do run } */ + +#include <assert.h> +#include "cpuid.h" + +/* Check if the Intel CPU model and sub-model are identified. */ +static void +check_intel_cpu_model (unsigned int family, unsigned int model, + unsigned int brand_id) +{ + /* Parse family and model only if brand ID is 0. */ + if (brand_id == 0) + { + switch (family) + { + case 0x5: + /* Pentium. */ + break; + case 0x6: + switch (model) + { + case 0x1c: + case 0x26: + /* Atom. */ + assert (__builtin_cpu_is ("atom")); + break; + case 0x1a: + case 0x1e: + case 0x1f: + case 0x2e: + /* Nehalem. */ + assert (__builtin_cpu_is ("corei7")); + assert (__builtin_cpu_is ("nehalem")); + break; + case 0x25: + case 0x2c: + case 0x2f: + /* Westmere. */ + assert (__builtin_cpu_is ("corei7")); + assert (__builtin_cpu_is ("westmere")); + break; + case 0x2a: + /* Sandy Bridge. */ + assert (__builtin_cpu_is ("corei7")); + assert (__builtin_cpu_is ("sandybridge")); + break; + case 0x17: + case 0x1d: + /* Penryn. */ + case 0x0f: + /* Merom. */ + assert (__builtin_cpu_is ("core2")); + break; + default: + break; + } + break; + default: + /* We have no idea. */ + break; + } + } +} + +/* Check if the AMD CPU model and sub-model are identified. */ +static void +check_amd_cpu_model (unsigned int family, unsigned int model) +{ + switch (family) + { + /* AMD Family 10h. */ + case 0x10: + switch (model) + { + case 0x2: + /* Barcelona. */ + assert (__builtin_cpu_is ("amdfam10h")); + assert (__builtin_cpu_is ("barcelona")); + break; + case 0x4: + /* Shanghai. */ + assert (__builtin_cpu_is ("amdfam10h")); + assert (__builtin_cpu_is ("shanghai")); + break; + case 0x8: + /* Istanbul. */ + assert (__builtin_cpu_is ("amdfam10h")); + assert (__builtin_cpu_is ("istanbul")); + break; + default: + break; + } + break; + /* AMD Family 15h. */ + case 0x15: + assert (__builtin_cpu_is ("amdfam15h")); + /* Bulldozer version 1. */ + if ( model <= 0xf) + assert (__builtin_cpu_is ("bdver1")); + /* Bulldozer version 2. */ + if (model >= 0x10 && model <= 0x1f) + assert (__builtin_cpu_is ("bdver2")); + break; + default: + break; + } +} + +/* Check if the ISA features are identified. */ +static void +check_features (unsigned int ecx, unsigned int edx, + int max_cpuid_level) +{ + if (edx & bit_CMOV) + assert (__builtin_cpu_supports ("cmov")); + if (edx & bit_MMX) + assert (__builtin_cpu_supports ("mmx")); + if (edx & bit_SSE) + assert (__builtin_cpu_supports ("sse")); + if (edx & bit_SSE2) + assert (__builtin_cpu_supports ("sse2")); + if (ecx & bit_POPCNT) + assert (__builtin_cpu_supports ("popcnt")); + if (ecx & bit_SSE3) + assert (__builtin_cpu_supports ("sse3")); + if (ecx & bit_SSSE3) + assert (__builtin_cpu_supports ("ssse3")); + if (ecx & bit_SSE4_1) + assert (__builtin_cpu_supports ("sse4.1")); + if (ecx & bit_SSE4_2) + assert (__builtin_cpu_supports ("sse4.2")); + if (ecx & bit_AVX) + assert (__builtin_cpu_supports ("avx")); + + /* Get advanced features at level 7 (eax = 7, ecx = 0). */ + if (max_cpuid_level >= 7) + { + unsigned int eax, ebx, ecx, edx; + __cpuid_count (7, 0, eax, ebx, ecx, edx); + if (ebx & bit_AVX2) + assert (__builtin_cpu_supports ("avx2")); + } +} + +static int __attribute__ ((noinline)) +__get_cpuid_output (unsigned int __level, + unsigned int *__eax, unsigned int *__ebx, + unsigned int *__ecx, unsigned int *__edx) +{ + return __get_cpuid (__level, __eax, __ebx, __ecx, __edx); +} + +static int +check_detailed () +{ + unsigned int eax, ebx, ecx, edx; + + int max_level; + unsigned int vendor; + unsigned int model, family, brand_id; + unsigned int extended_model, extended_family; + + /* Assume cpuid insn present. Run in level 0 to get vendor id. */ + if (!__get_cpuid_output (0, &eax, &ebx, &ecx, &edx)) + return 0; + + vendor = ebx; + max_level = eax; + + if (max_level < 1) + return 0; + + if (!__get_cpuid_output (1, &eax, &ebx, &ecx, &edx)) + return 0; + + model = (eax >> 4) & 0x0f; + family = (eax >> 8) & 0x0f; + brand_id = ebx & 0xff; + extended_model = (eax >> 12) & 0xf0; + extended_family = (eax >> 20) & 0xff; + + if (vendor == signature_INTEL_ebx) + { + assert (__builtin_cpu_is ("intel")); + /* Adjust family and model for Intel CPUs. */ + if (family == 0x0f) + { + family += extended_family; + model += extended_model; + } + else if (family == 0x06) + model += extended_model; + check_intel_cpu_model (family, model, brand_id); + check_features (ecx, edx, max_level); + } + else if (vendor == signature_AMD_ebx) + { + assert (__builtin_cpu_is ("amd")); + /* Adjust model and family for AMD CPUS. */ + if (family == 0x0f) + { + family += extended_family; + model += (extended_model << 4); + } + check_amd_cpu_model (family, model); + check_features (ecx, edx, max_level); + } + + return 0; +} + +static int +quick_check () +{ + /* Check CPU Features. */ + assert (__builtin_cpu_supports ("cmov") >= 0); + + assert (__builtin_cpu_supports ("mmx") >= 0); + + assert (__builtin_cpu_supports ("popcnt") >= 0); + + assert (__builtin_cpu_supports ("sse") >= 0); + + assert (__builtin_cpu_supports ("sse2") >= 0); + + assert (__builtin_cpu_supports ("sse3") >= 0); + + assert (__builtin_cpu_supports ("ssse3") >= 0); + + assert (__builtin_cpu_supports ("sse4.1") >= 0); + + assert (__builtin_cpu_supports ("sse4.2") >= 0); + + assert (__builtin_cpu_supports ("avx") >= 0); + + assert (__builtin_cpu_supports ("avx2") >= 0); + + /* Check CPU type. */ + assert (__builtin_cpu_is ("amd") >= 0); + + assert (__builtin_cpu_is ("intel") >= 0); + + assert (__builtin_cpu_is ("atom") >= 0); + + assert (__builtin_cpu_is ("core2") >= 0); + + assert (__builtin_cpu_is ("corei7") >= 0); + + assert (__builtin_cpu_is ("nehalem") >= 0); + + assert (__builtin_cpu_is ("westmere") >= 0); + + assert (__builtin_cpu_is ("sandybridge") >= 0); + + assert (__builtin_cpu_is ("amdfam10h") >= 0); + + assert (__builtin_cpu_is ("barcelona") >= 0); + + assert (__builtin_cpu_is ("shanghai") >= 0); + + assert (__builtin_cpu_is ("istanbul") >= 0); + + assert (__builtin_cpu_is ("amdfam15h") >= 0); + + assert (__builtin_cpu_is ("bdver1") >= 0); + + assert (__builtin_cpu_is ("bdver2") >= 0); + + return 0; +} + +int main () +{ + __builtin_cpu_init (); + quick_check (); + check_detailed (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cadd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cadd.c new file mode 100644 index 000000000..7a39c67ed --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cadd.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8" } */ +/* { dg-final { scan-assembler "sbb" } } */ + +extern void abort (void); + +/* Conditional increment is best done using sbb $-1, val. */ +int t[]={0,0,0,0,1,1,1,1,1,1}; +q() +{ + int sum=0; + int i; + for (i=0;i<10;i++) + if (t[i]) + sum++; + if (sum != 6) + abort (); +} +main() +{ + int i; + for (i=0;i<10000000;i++) + q(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/call-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/call-1.c new file mode 100644 index 000000000..bd7c569c6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/call-1.c @@ -0,0 +1,39 @@ +/* PR optimization/11304 */ +/* Originator: <manuel.serrano@sophia.inria.fr> */ +/* { dg-do run } */ +/* { dg-options "-O -fomit-frame-pointer" } */ + +/* Verify that %eax is always restored after a call. */ + +extern void abort(void); + +volatile int r; + +void set_eax(int val) +{ + __asm__ __volatile__ ("mov %0, %%eax" : : "m" (val)); +} + +void foo(int val) +{ + r = val; +} + +int bar(int x) +{ + if (x) + { + set_eax(0); + return x; + } + + foo(x); +} + +int main(void) +{ + if (bar(1) != 1) + abort(); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cleanup-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cleanup-1.c new file mode 100644 index 000000000..1a47fcb03 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cleanup-1.c @@ -0,0 +1,240 @@ +/* { dg-do run { target *-*-linux* } } */ +/* { dg-options "-fexceptions -fnon-call-exceptions -fasynchronous-unwind-tables -O2" } */ +/* Test complex CFA value expressions. */ + +#include <unwind.h> +#include <stdlib.h> +#include <string.h> +#include <stdio.h> +#include <unistd.h> + +static _Unwind_Reason_Code +force_unwind_stop (int version, _Unwind_Action actions, + _Unwind_Exception_Class exc_class, + struct _Unwind_Exception *exc_obj, + struct _Unwind_Context *context, + void *stop_parameter) +{ + if (actions & _UA_END_OF_STACK) + abort (); + return _URC_NO_REASON; +} + +static void +force_unwind () +{ + struct _Unwind_Exception *exc = malloc (sizeof (*exc)); + memset (&exc->exception_class, 0, sizeof (exc->exception_class)); + exc->exception_cleanup = 0; + + _Unwind_ForcedUnwind (exc, force_unwind_stop, 0); + abort (); +} + +int count; + +static void +counter (void *p __attribute__((unused))) +{ + ++count; +} + +static void +handler (void *p __attribute__((unused))) +{ + if (count != 2) + abort (); + _exit (0); +} + +static int __attribute__((noinline)) +fn5 (void) +{ + char dummy __attribute__((cleanup (counter))); + force_unwind (); + return 0; +} + +void +bar (void) +{ + char dummy __attribute__((cleanup (counter))); + fn5 (); +} + +void __attribute__((noinline)) +foo (int x) +{ + char buf[256]; +#ifdef __i386__ + __asm ( + "testl %0, %0\n\t" + "jnz 1f\n\t" + ".subsection 1\n\t" + ".type _L_mutex_lock_%=, @function\n" +"_L_mutex_lock_%=:\n" +"1:\t" "leal %1, %%ecx\n" +"2:\t" "call bar\n" +"3:\t" "jmp 18f\n" +"4:\t" ".size _L_mutex_lock_%=, .-_L_mutex_lock_%=\n\t" + ".previous\n\t" + ".section .eh_frame,\"a\",@progbits\n" +"5:\t" ".long 7f-6f # Length of Common Information Entry\n" +"6:\t" ".long 0x0 # CIE Identifier Tag\n\t" + ".byte 0x1 # CIE Version\n\t" + ".ascii \"zR\\0\" # CIE Augmentation\n\t" + ".uleb128 0x1 # CIE Code Alignment Factor\n\t" + ".sleb128 -4 # CIE Data Alignment Factor\n\t" + ".byte 0x8 # CIE RA Column\n\t" + ".uleb128 0x1 # Augmentation size\n\t" + ".byte 0x1b # FDE Encoding (pcrel sdata4)\n\t" + ".byte 0xc # DW_CFA_def_cfa\n\t" + ".uleb128 0x4\n\t" + ".uleb128 0x0\n\t" + ".align 4\n" +"7:\t" ".long 17f-8f # FDE Length\n" +"8:\t" ".long 8b-5b # FDE CIE offset\n\t" + ".long 1b-. # FDE initial location\n\t" + ".long 4b-1b # FDE address range\n\t" + ".uleb128 0x0 # Augmentation size\n\t" + ".byte 0x16 # DW_CFA_val_expression\n\t" + ".uleb128 0x8\n\t" + ".uleb128 10f-9f\n" +"9:\t" ".byte 0x78 # DW_OP_breg8\n\t" + ".sleb128 3b-1b\n" +"10:\t" ".byte 0x40 + (2b-1b) # DW_CFA_advance_loc\n\t" + ".byte 0x16 # DW_CFA_val_expression\n\t" + ".uleb128 0x8\n\t" + ".uleb128 12f-11f\n" +"11:\t" ".byte 0x78 # DW_OP_breg8\n\t" + ".sleb128 3b-2b\n" +"12:\t" ".byte 0x40 + (3b-2b-1) # DW_CFA_advance_loc\n\t" + ".byte 0x16 # DW_CFA_val_expression\n\t" + ".uleb128 0x8\n\t" + ".uleb128 16f-13f\n" +"13:\t" ".byte 0x78 # DW_OP_breg8\n\t" + ".sleb128 15f-14f\n\t" + ".byte 0x0d # DW_OP_const4s\n" +"14:\t" ".4byte 3b-.\n\t" + ".byte 0x1c # DW_OP_minus\n\t" + ".byte 0x0d # DW_OP_const4s\n" +"15:\t" ".4byte 18f-.\n\t" + ".byte 0x22 # DW_OP_plus\n" +"16:\t" ".align 4\n" +"17:\t" ".previous\n" +"18:" + : : "r" (x), "m" (x), "r" (buf) + : "memory", "eax", "edx", "ecx"); +#elif defined __x86_64__ + __asm ( + "testl %0, %0\n\t" + "jnz 1f\n\t" + ".subsection 1\n\t" + ".type _L_mutex_lock_%=, @function\n" +"_L_mutex_lock_%=:\n" +"1:\t" "leaq %1, %%rdi\n" +"2:\t" "subq $128, %%rsp\n" +"3:\t" "call bar\n" +"4:\t" "addq $128, %%rsp\n" +"5:\t" "jmp 24f\n" +"6:\t" ".size _L_mutex_lock_%=, .-_L_mutex_lock_%=\n\t" + ".previous\n\t" + ".section .eh_frame,\"a\",@progbits\n" +"7:\t" ".long 9f-8f # Length of Common Information Entry\n" +"8:\t" ".long 0x0 # CIE Identifier Tag\n\t" + ".byte 0x1 # CIE Version\n\t" + ".ascii \"zR\\0\" # CIE Augmentation\n\t" + ".uleb128 0x1 # CIE Code Alignment Factor\n\t" + ".sleb128 -8 # CIE Data Alignment Factor\n\t" + ".byte 0x10 # CIE RA Column\n\t" + ".uleb128 0x1 # Augmentation size\n\t" + ".byte 0x1b # FDE Encoding (pcrel sdata4)\n\t" + ".byte 0x12 # DW_CFA_def_cfa_sf\n\t" + ".uleb128 0x7\n\t" + ".sleb128 16\n\t" + ".align 8\n" +"9:\t" ".long 23f-10f # FDE Length\n" +"10:\t" ".long 10b-7b # FDE CIE offset\n\t" + ".long 1b-. # FDE initial location\n\t" + ".long 6b-1b # FDE address range\n\t" + ".uleb128 0x0 # Augmentation size\n\t" + ".byte 0x16 # DW_CFA_val_expression\n\t" + ".uleb128 0x10\n\t" + ".uleb128 12f-11f\n" +"11:\t" ".byte 0x80 # DW_OP_breg16\n\t" + ".sleb128 4b-1b\n" +"12:\t" ".byte 0x40 + (2b-1b) # DW_CFA_advance_loc\n\t" + ".byte 0x16 # DW_CFA_val_expression\n\t" + ".uleb128 0x10\n\t" + ".uleb128 14f-13f\n" +"13:\t" ".byte 0x80 # DW_OP_breg16\n\t" + ".sleb128 4b-2b\n" +"14:\t" ".byte 0x40 + (3b-2b) # DW_CFA_advance_loc\n\t" + ".byte 0x0e # DW_CFA_def_cfa_offset\n\t" + ".uleb128 0\n\t" + ".byte 0x16 # DW_CFA_val_expression\n\t" + ".uleb128 0x10\n\t" + ".uleb128 16f-15f\n" +"15:\t" ".byte 0x80 # DW_OP_breg16\n\t" + ".sleb128 4b-3b\n" +"16:\t" ".byte 0x40 + (4b-3b-1) # DW_CFA_advance_loc\n\t" + ".byte 0x0e # DW_CFA_def_cfa_offset\n\t" + ".uleb128 128\n\t" + ".byte 0x16 # DW_CFA_val_expression\n\t" + ".uleb128 0x10\n\t" + ".uleb128 20f-17f\n" +"17:\t" ".byte 0x80 # DW_OP_breg16\n\t" + ".sleb128 19f-18f\n\t" + ".byte 0x0d # DW_OP_const4s\n" +"18:\t" ".4byte 4b-.\n\t" + ".byte 0x1c # DW_OP_minus\n\t" + ".byte 0x0d # DW_OP_const4s\n" +"19:\t" ".4byte 24f-.\n\t" + ".byte 0x22 # DW_OP_plus\n" +"20:\t" ".byte 0x40 + (5b-4b+1) # DW_CFA_advance_loc\n\t" + ".byte 0x13 # DW_CFA_def_cfa_offset_sf\n\t" + ".sleb128 16\n\t" + ".byte 0x16 # DW_CFA_val_expression\n\t" + ".uleb128 0x10\n\t" + ".uleb128 22f-21f\n" +"21:\t" ".byte 0x80 # DW_OP_breg16\n\t" + ".sleb128 4b-5b\n" +"22:\t" ".align 8\n" +"23:\t" ".previous\n" +"24:" + : : "r" (x), "m" (x), "r" (buf) + : "memory", "rax", "rdx", "rcx", "rsi", "rdi", + "r8", "r9", "r10", "r11"); +#else +# error Unsupported test architecture +#endif +} + +static int __attribute__((noinline)) +fn2 (void) +{ + foo (3); + return 0; +} + +static int __attribute__((noinline)) +fn1 (void) +{ + fn2 (); + return 0; +} + +static void * +fn0 (void) +{ + char dummy __attribute__((cleanup (handler))); + fn1 (); + return 0; +} + +int +main (void) +{ + fn0 (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cleanup-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cleanup-2.c new file mode 100644 index 000000000..36dd80da9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cleanup-2.c @@ -0,0 +1,205 @@ +/* { dg-do run { target { *-*-linux* && { ! { ia32 } } } } } */ +/* { dg-options "-fexceptions -fnon-call-exceptions -fasynchronous-unwind-tables -O2" } */ +/* Test complex CFA value expressions. */ + +#include <unwind.h> +#include <stdlib.h> +#include <string.h> +#include <stdio.h> +#include <unistd.h> + +static _Unwind_Reason_Code +force_unwind_stop (int version, _Unwind_Action actions, + _Unwind_Exception_Class exc_class, + struct _Unwind_Exception *exc_obj, + struct _Unwind_Context *context, + void *stop_parameter) +{ + if (actions & _UA_END_OF_STACK) + abort (); + return _URC_NO_REASON; +} + +static void +force_unwind () +{ + struct _Unwind_Exception *exc = malloc (sizeof (*exc)); + memset (&exc->exception_class, 0, sizeof (exc->exception_class)); + exc->exception_cleanup = 0; + + _Unwind_ForcedUnwind (exc, force_unwind_stop, 0); + abort (); +} + +int count; + +static void +counter (void *p __attribute__((unused))) +{ + ++count; +} + +static void +handler (void *p __attribute__((unused))) +{ + if (count != 2) + abort (); + _exit (0); +} + +static int __attribute__((noinline)) +fn5 (void) +{ + char dummy __attribute__((cleanup (counter))); + force_unwind (); + return 0; +} + +void +bar (void) +{ + char dummy __attribute__((cleanup (counter))); + fn5 (); +} + +void __attribute__((noinline)) +foo (int x) +{ + char buf[256]; +#ifdef __x86_64__ + __asm ( + "testl %0, %0\n\t" + "jnz 1f\n\t" + ".subsection 1\n\t" + ".type _L_mutex_lock_%=, @function\n" +"_L_mutex_lock_%=:\n" +"1:\t" "leaq %1, %%rdi\n" +"2:\t" "subq $128, %%rsp\n" +"3:\t" "call bar\n" +"4:\t" "addq $128, %%rsp\n" +"5:\t" "jmp 21f\n" +"6:\t" ".size _L_mutex_lock_%=, .-_L_mutex_lock_%=\n\t" + ".previous\n\t" + ".section .eh_frame,\"a\",@progbits\n" +"7:\t" ".long 9f-8f # Length of Common Information Entry\n" +"8:\t" ".long 0x0 # CIE Identifier Tag\n\t" + ".byte 0x1 # CIE Version\n\t" + ".ascii \"zR\\0\" # CIE Augmentation\n\t" + ".uleb128 0x1 # CIE Code Alignment Factor\n\t" + ".sleb128 -8 # CIE Data Alignment Factor\n\t" + ".byte 0x10 # CIE RA Column\n\t" + ".uleb128 0x1 # Augmentation size\n\t" + ".byte 0x1b # FDE Encoding (pcrel sdata4)\n\t" + ".byte 0xc # DW_CFA_def_cfa\n\t" + ".uleb128 0x7\n\t" + ".uleb128 0x0\n\t" + ".align 8\n" +"9:\t" ".long 20f-10f # FDE Length\n" +"10:\t" ".long 10b-7b # FDE CIE offset\n\t" + ".long 1b-. # FDE initial location\n\t" + ".long 6b-1b # FDE address range\n\t" + ".uleb128 0x0 # Augmentation size\n\t" + /* This CFA expression computes the address right + past the jnz instruction above, from %rip somewhere + within the _L_mutex_lock_%= subsection. */ + ".byte 0x16 # DW_CFA_val_expression\n\t" + ".uleb128 0x10\n\t" + ".uleb128 19f-11f\n" +"11:\t" ".byte 0x80 # DW_OP_breg16\n\t" + ".sleb128 0\n" +"12:\t" ".byte 0x12 # DW_OP_dup\n\t" + ".byte 0x94 # DW_OP_deref_size\n\t" + ".byte 1\n\t" + ".byte 0x12 # DW_OP_dup\n\t" + ".byte 0x08 # DW_OP_const1u\n\t" + ".byte 0x48\n\t" + ".byte 0x2e # DW_OP_ne\n\t" + ".byte 0x28 # DW_OP_bra\n\t" + ".2byte 16f-13f\n" +"13:\t" ".byte 0x13 # DW_OP_drop\n\t" + ".byte 0x23 # DW_OP_plus_uconst\n\t" + ".uleb128 1\n\t" + ".byte 0x12 # DW_OP_dup\n\t" + ".byte 0x94 # DW_OP_deref_size\n\t" + ".byte 1\n\t" + ".byte 0x08 # DW_OP_const1u\n\t" + ".byte 0x81\n\t" + ".byte 0x2e # DW_OP_ne\n\t" + ".byte 0x28 # DW_OP_bra\n\t" + ".2byte 15f-14f\n" +"14:\t" ".byte 0x23 # DW_OP_plus_uconst\n\t" + ".uleb128 3b-2b-1\n\t" + ".byte 0x2f # DW_OP_skip\n\t" + ".2byte 12b-15f\n" +"15:\t" ".byte 0x23 # DW_OP_plus_uconst\n\t" + ".uleb128 2b-1b-1\n\t" + ".byte 0x2f # DW_OP_skip\n\t" + ".2byte 12b-16f\n" +"16:\t" ".byte 0x08 # DW_OP_const1u\n\t" + ".byte 0xe8\n\t" + ".byte 0x2e # DW_OP_ne\n\t" + ".byte 0x28 # DW_OP_bra\n\t" + ".2byte 18f-17f\n" +"17:\t" ".byte 0x23 # DW_OP_plus_uconst\n\t" + ".uleb128 4b-3b\n\t" + ".byte 0x2f # DW_OP_skip\n\t" + ".2byte 12b-18f\n" +"18:\t" ".byte 0x23 # DW_OP_plus_uconst\n\t" + ".uleb128 1\n\t" + ".byte 0x12 # DW_OP_dup\n\t" + ".byte 0x94 # DW_OP_deref_size\n\t" + ".byte 4\n\t" + ".byte 0x08 # DW_OP_const1u\n\t" + ".byte 72 - (6b-5b) * 8 # (6b-5b) == 5 ? 32 : 56\n\t" + ".byte 0x24 # DW_OP_shl\n\t" + ".byte 0x08 # DW_OP_const1u\n\t" + ".byte 72 - (6b-5b) * 8 # (6b-5b) == 5 ? 32 : 56\n\t" + ".byte 0x26 # DW_OP_shra\n\t" + ".byte 0x22 # DW_OP_plus\n\t" + ".byte 0x23 # DW_OP_plus_uconst\n\t" + ".uleb128 6b-5b-1\n" +"19:\t" ".byte 0x40 + (3b-1b) # DW_CFA_advance_loc\n\t" + ".byte 0xe # DW_CFA_def_cfa_offset\n\t" + ".uleb128 128\n\t" + ".byte 0x40 + (5b-3b) # DW_CFA_advance_loc\n\t" + ".byte 0xe # DW_CFA_def_cfa_offset\n\t" + ".uleb128 0\n\t" + ".align 8\n" +"20:\t" ".previous\n" +"21:" + : : "r" (x), "m" (x), "r" (buf) + : "memory", "rax", "rdx", "rcx", "rsi", "rdi", + "r8", "r9", "r10", "r11"); +#else +# error Unsupported test architecture +#endif +} + +static int __attribute__((noinline)) +fn2 (void) +{ + foo (3); + return 0; +} + +static int __attribute__((noinline)) +fn1 (void) +{ + fn2 (); + return 0; +} + +static void * +fn0 (void) +{ + char dummy __attribute__((cleanup (handler))); + fn1 (); + return 0; +} + +int +main (void) +{ + fn0 (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/clearcap.map b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/clearcap.map new file mode 100644 index 000000000..147f922d1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/clearcap.map @@ -0,0 +1,3 @@ +# clear all hardware capabilities emitted by Sun as: the tests here +# guard against execution at runtime +hwcap_1 = V0x0 OVERRIDE; diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/clearcapv2.map b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/clearcapv2.map new file mode 100644 index 000000000..95cb14cc5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/clearcapv2.map @@ -0,0 +1,7 @@ +# clear all hardware capabilities emitted by Sun as: the tests here +# guard against execution at runtime +# uses mapfile v2 syntax which is the only way to clear AT_SUN_CAP_HW2 flags +$mapfile_version 2 +CAPABILITY { + HW = ; +}; diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/clobbers.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/clobbers.c new file mode 100644 index 000000000..1a70688d7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/clobbers.c @@ -0,0 +1,38 @@ +/* Test asm clobbers on x86. */ + +/* { dg-do run } */ + +extern void abort (void); + +int main () +{ + int i; + __asm__ ("movl $1,%0\n\txorl %%eax,%%eax" : "=r" (i) : : "eax"); + if (i != 1) + abort (); + /* On darwin you can't call external functions from non-pic code, + however, clobbering ebx isn't valid in pic code. Instead of + disabling the whole test, just disable the ebx clobbering part. + Ditto for any x86 system that is ilp32 && pic. + */ +#if !(defined (__MACH__)) +#if ! defined (__PIC__) || defined (__x86_64__) + __asm__ ("movl $1,%0\n\txorl %%ebx,%%ebx" : "=r" (i) : : "ebx"); + if (i != 1) + abort (); +#endif /* ! pic || lp64 */ +#endif + __asm__ ("movl $1,%0\n\txorl %%ecx,%%ecx" : "=r" (i) : : "ecx"); + if (i != 1) + abort (); + __asm__ ("movl $1,%0\n\txorl %%edx,%%edx" : "=r" (i) : : "edx"); + if (i != 1) + abort (); + __asm__ ("movl $1,%0\n\txorl %%esi,%%esi" : "=r" (i) : : "esi"); + if (i != 1) + abort (); + __asm__ ("movl $1,%0\n\txorl %%edi,%%edi" : "=r" (i) : : "edi"); + if (i != 1) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov1.c new file mode 100644 index 000000000..edbbda584 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* This test checks for absolute memory operands. */ +/* { dg-require-effective-target nonpic } */ +/* { dg-options "-O2 -march=k8" } */ +/* { dg-final { scan-assembler "sar\[^\\n\]*magic_namea" } } */ +/* { dg-final { scan-assembler "sar\[^\\n\]*magic_nameb" } } */ +/* { dg-final { scan-assembler "sar\[^\\n\]*magic_namec" } } */ +/* { dg-final { scan-assembler "shr\[^\\n\]*magic_named" } } */ +/* { dg-final { scan-assembler "shr\[^\\n\]*magic_namee" } } */ +/* { dg-final { scan-assembler "shr\[^\\n\]*magic_namef" } } */ + +/* Check code generation for several conditional moves doable by single arithmetics. */ + +static int magic_namea; +static char magic_nameb; +static short magic_namec; +static int magic_named; +static char magic_namee; +static short magic_namef; + +unsigned int gen; +void m(void) +{ + magic_namec=magic_namec>=0?0:-1; + magic_namea=magic_namea>=0?0:-1; + magic_nameb=magic_nameb>=0?0:-1; + magic_named=magic_named>=0?0:1; + magic_namee=magic_namee>=0?0:1; + magic_namef=magic_namef>=0?0:1; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov2.c new file mode 100644 index 000000000..2b7c696bb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8" } */ +/* { dg-final { scan-assembler "sbb" } } */ + +/* This conditional move is fastest to be done using sbb. */ +t(unsigned int a, unsigned int b) +{ + return (a<=b?5:-5); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov3.c new file mode 100644 index 000000000..34df0aab7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8" } */ +/* { dg-final { scan-assembler "cmov\[^3\]" } } */ + +/* This conditional move is fastest to be done using cmov. */ +t(int a, int b) +{ + return (a<=b?5:-5); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov4.c new file mode 100644 index 000000000..6a955eaeb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8" } */ +/* { dg-final { scan-assembler "cmov\[^4\]" } } */ + +/* Verify that if conversion happends for memory references. */ +int ARCHnodes; +int *nodekind; +float *nodekindf; +t() +{ +int i; +/* Redefine nodekind to be 1 for all surface nodes */ + + for (i = 0; i < ARCHnodes; i++) { + nodekind[i] = (int) nodekindf[i]; + if (nodekind[i] == 3) + nodekind[i] = 1; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov5.c new file mode 100644 index 000000000..898323b44 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov5.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8" } */ +/* { dg-final { scan-assembler "sbb" } } */ + +int +t(float a, float b) +{ + return a<=b?0:-1; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov6.c new file mode 100644 index 000000000..535326e4c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov6.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8" } */ +/* { dg-final { scan-assembler "cmov\[^6\]" } } */ + +/* Verify that blocks are converted to conditional moves. */ +extern int bar (int, int); +int foo (int c, int d, int e) +{ + int a, b; + + if (c) + { + a = 10; + b = d; + } + else + { + a = e; + b = 20; + } + return bar (a, b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov7.c new file mode 100644 index 000000000..433bf57f8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov7.c @@ -0,0 +1,16 @@ +/* PR middle-end/33187 */ + +/* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=k8" } } */ +/* { dg-options "-O2 -ffast-math -march=k8 -mbranch-cost=5 -mfpmath=387" } */ +/* { dg-final { scan-assembler "fcmov" } } */ + +/* compress_float_constant generates load + float_extend + sequence which combine pass failed to combine into + (set (reg:DF) (float_extend:DF (mem:SF (symbol_ref...)))). */ + +double +sgn (double __x) +{ + return __x >= 0.0 ? 1.0 : -1.0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov8.c new file mode 100644 index 000000000..2d95c25da --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmov8.c @@ -0,0 +1,13 @@ +/* PR target/36936 */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=i686" } */ +/* { dg-final { scan-assembler "cmov\[^8\]" } } */ + +int +foo (int x) +{ + if (x < 0) + x = 1; + return x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c new file mode 100644 index 000000000..e3402014e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mcx16" } */ + +typedef int TItype __attribute__ ((mode (TI))); + +TItype m_128; + +void test(TItype x_128) +{ + m_128 = __sync_val_compare_and_swap (&m_128, x_128, m_128); +} + +/* { dg-final { scan-assembler "cmpxchg16b\[ \\t]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cold-attribute-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cold-attribute-1.c new file mode 100644 index 000000000..db81ee837 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cold-attribute-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +#include <string.h> +static inline +__attribute__ ((cold)) +my_cold_memset (void *a, int b,int c) +{ + memset (a,b,c); +} +t(void *a,int b,int c) +{ + if (a) + my_cold_memset (a,b,40); +} + +/* The IF conditional should be predicted as cold and my_cold_memset inlined + for size expanding memset as rep; stosb. */ +/* { dg-final { scan-assembler "stosb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cold-attribute-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cold-attribute-2.c new file mode 100644 index 000000000..93ea90661 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cold-attribute-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +#include <string.h> +t(int c) +{ + if (__builtin_expect (c, 0)) + { + cold_hint (); + return c * 11; + } + return c; +} + +/* { dg-final { scan-assembler "imul" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cold-attribute-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cold-attribute-3.c new file mode 100644 index 000000000..5225428c5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cold-attribute-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +#include <string.h> + +int +__attribute__ ((cold)) +t(int c) +{ + return c * 11; +} + +/* { dg-final { scan-assembler "imul" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cold-attribute-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cold-attribute-4.c new file mode 100644 index 000000000..37a41e954 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cold-attribute-4.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +#include <string.h> + +int +__attribute__ ((cold)) +t(int c) +{ + return -1; +} + +/* { dg-final { scan-assembler "orl" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/combine-mul.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/combine-mul.c new file mode 100644 index 000000000..8a2e86284 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/combine-mul.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target nonpic } */ +/* { dg-final { scan-assembler-not "12345" } } */ + +static inline unsigned int myrnd (void) +{ + static unsigned int s = 1388815473; + s *= 1103515245; + s += 12345; +} + +struct __attribute__ ((packed)) A { + unsigned short i:1, l:1, j:3, k:11; +}; + +struct A sA; +void testA (void) +{ + char *p = (char *) &sA; + *p++ = myrnd (); + *p++ = myrnd (); + sA.k = -1; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c new file mode 100644 index 000000000..e4d71c21c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=387 -fpic" } */ +double foo (double x) { + return x + 1.75; +} +/* { dg-final { scan-assembler "flds" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/compress-float-387.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/compress-float-387.c new file mode 100644 index 000000000..03a834d2b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/compress-float-387.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=387" } */ +double foo (double x) { + return x + 1.75; +} +/* { dg-final { scan-assembler "flds" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c new file mode 100644 index 000000000..ef024dd0b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=sse -fpic" } */ +double foo (double x) { + return x + 1.75; +} +/* { dg-final { scan-assembler "movsd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/compress-float-sse.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/compress-float-sse.c new file mode 100644 index 000000000..c56be1300 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/compress-float-sse.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=sse" } */ +double foo (double x) { + return x + 1.75; +} +/* { dg-final { scan-assembler "movsd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/conversion.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/conversion.c new file mode 100644 index 000000000..c1718f027 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/conversion.c @@ -0,0 +1,57 @@ +/* Check that conversion functions don't leak into global namespace. */ + +/* { dg-do link } */ +/* { dg-options "-ffast-math" } */ +/* { dg-add-options c99_runtime } */ + +#include "../../gcc.dg/builtins-config.h" + +int ifloor (double a) { return __builtin_ifloor (a); } +#ifdef HAVE_C99_RUNTIME +int ifloorf (float a) { return __builtin_ifloorf (a); } +int ifloorl (long double a) { return __builtin_ifloorl (a); } +#endif + +long lfloor (double a) { return __builtin_lfloor (a); } +#ifdef HAVE_C99_RUNTIME +long lfloorf (float a) { return __builtin_lfloorf (a); } +long lfloorl (long double a) { return __builtin_lfloorl (a); } +#endif + +long long llfloor (double a) { return __builtin_llfloor (a); } +#ifdef HAVE_C99_RUNTIME +long long llfloorf (float a) { return __builtin_llfloorf (a); } +long long llfloorl (long double a) { return __builtin_llfloorl (a); } +#endif + +int iceil (double a) { return __builtin_iceil (a); } +#ifdef HAVE_C99_RUNTIME +int iceilf (float a) { return __builtin_iceilf (a); } +int iceill (long double a) { return __builtin_iceill (a); } +#endif + +long lceil (double a) { return __builtin_lceil (a); } +#ifdef HAVE_C99_RUNTIME +long lceilf (float a) { return __builtin_lceilf (a); } +long lceill (long double a) { return __builtin_lceill (a); } +#endif + +long long llceil (double a) { return __builtin_llceil (a); } +#ifdef HAVE_C99_RUNTIME +long long llceilf (float a) { return __builtin_llceilf (a); } +long long llceill (long double a) { return __builtin_llceill (a); } +#endif + +int iround (double a) { return __builtin_iround (a); } +#ifdef HAVE_C99_RUNTIME +int iroundf (float a) { return __builtin_iroundf (a); } +int iroundl (long double a) { return __builtin_iroundl (a); } +#endif + +int irint (double a) { return __builtin_irint (a); } +#ifdef HAVE_C99_RUNTIME +int irintf (float a) { return __builtin_irintf (a); } +int irintl (long double a) { return __builtin_irintl (a); } +#endif + +int main () { return 0; } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/crc32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/crc32-1.c new file mode 100644 index 000000000..b3ed5b684 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/crc32-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcrc32" } */ +/* { dg-final { scan-assembler "crc32b\[^\\n\]*eax" } } */ +/* { dg-final { scan-assembler "crc32w\[^\\n\]*eax" } } */ +/* { dg-final { scan-assembler "crc32l\[^\\n\]*eax" } } */ + +unsigned int +crc32b (unsigned int x, unsigned char y) +{ + return __builtin_ia32_crc32qi (x, y); +} + +unsigned int +crc32w (unsigned int x, unsigned short y) +{ + return __builtin_ia32_crc32hi (x, y); +} + +unsigned int +crc32d (unsigned int x, unsigned int y) +{ + return __builtin_ia32_crc32si (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/crc32-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/crc32-2.c new file mode 100644 index 000000000..678cfd5a4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/crc32-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcrc32" } */ +/* { dg-final { scan-assembler "crc32q\[^\\n\]*rax" { target { ! { ia32 } } } } } */ + +unsigned long long +crc32d (unsigned long long x, unsigned long long y) +{ + return __builtin_ia32_crc32di (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/crc32-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/crc32-3.c new file mode 100644 index 000000000..7518a4526 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/crc32-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -mcrc32" } */ +/* { dg-final { scan-assembler "__builtin_ia32_crc32di" } } */ + +unsigned long long +crc32d (unsigned long long x, unsigned long long y) +{ + return __builtin_ia32_crc32di (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/crc32-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/crc32-4.c new file mode 100644 index 000000000..65ef4aa1a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/crc32-4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-sse4.2 -mno-crc32" } */ +/* { dg-final { scan-assembler "__builtin_ia32_crc32di" } } */ + +unsigned long long +crc32d (unsigned long long x, unsigned long long y) +{ + return __builtin_ia32_crc32di (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cvt-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cvt-1.c new file mode 100644 index 000000000..9535725e5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/cvt-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8 -mfpmath=sse" } */ +/* { dg-final { scan-assembler "cvttsd2si" } } */ +/* { dg-final { scan-assembler "cvttss2si" } } */ +int a,a1; +double b; +float b1; +t() +{ + a=b; + a1=b1; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/darwin-fpmath.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/darwin-fpmath.c new file mode 100644 index 000000000..7db694670 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/darwin-fpmath.c @@ -0,0 +1,9 @@ +/* { dg-do compile { target i?86-*-darwin* } } */ +/* { dg-final { scan-assembler "addsd" } } */ +/* Do not add -msse or -msse2 or -mfpmath=sse to the options. GCC is + supposed to use SSE math on Darwin by default, and libm won't work + right if it doesn't. */ +double foo(double x, double y) +{ + return x + y; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/defines-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/defines-1.c new file mode 100644 index 000000000..acc39f3f6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/defines-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=nocona -mno-sse" } */ + +#if defined(__SSE__) || defined(__SSE2__) || defined(__SSE3__) +#error +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/defines-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/defines-2.c new file mode 100644 index 000000000..4383a059b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/defines-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=athlon64 -mno-mmx" } */ + +#if defined(__MMX__) || defined(__3dNOW__) || defined(__3dNOW_A__) +#error +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-1.c new file mode 100644 index 000000000..2769a21c4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-1.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +extern void abort (void); + +void +__attribute__((noinline)) +test (int x, int y, int q, int r) +{ + if ((x / y) != q || (x % y) != r) + abort (); +} + +int +main () +{ + test (7, 6, 1, 1); + test (-7, -6, 1, -1); + test (-7, 6, -1, -1); + test (7, -6, -1, 1); + test (255, 254, 1, 1); + test (256, 254, 1, 2); + test (256, 256, 1, 0); + test (254, 256, 0, 254); + test (254, 255, 0, 254); + test (254, 1, 254, 0); + test (255, 2, 127, 1); + test (1, 256, 0, 1); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-2.c new file mode 100644 index 000000000..0e73b2736 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +int +foo (int x, int y) +{ + return x / y; +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-times "idivl" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-3.c new file mode 100644 index 000000000..4b8443699 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +int +foo (int x, int y) +{ + return x % y; +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-times "idivl" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-4.c new file mode 100644 index 000000000..7124d7a06 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +extern void abort (void); + +void +test (int x, int y, int q, int r) +{ + if ((x / y) != q || (x % y) != r) + abort (); +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-times "idivl" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-4a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-4a.c new file mode 100644 index 000000000..572b3df3c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-4a.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -m8bit-idiv" } */ + +extern void abort (void); + +void +test (int x, int y, int q, int r) +{ + if ((x / y) != q || (x % y) != r) + abort (); +} + +/* { dg-final { scan-assembler-not "divb" } } */ +/* { dg-final { scan-assembler-times "idivl" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-5.c new file mode 100644 index 000000000..8d179be9d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-5.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +extern void foo (int, int, int, int, int, int); + +void +bar (int x, int y) +{ + foo (0, 0, 0, 0, x / y, x % y); +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-times "idivl" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-6.c new file mode 100644 index 000000000..c79dba0a5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-6.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +extern void abort (void); + +void +__attribute__((noinline)) +test (long long x, long long y, long long q, long long r) +{ + if ((x / y) != q || (x % y) != r) + abort (); +} + +int +main () +{ + test (7, 6, 1, 1); + test (-7, -6, 1, -1); + test (-7, 6, -1, -1); + test (7, -6, -1, 1); + test (255, 254, 1, 1); + test (256, 254, 1, 2); + test (256, 256, 1, 0); + test (254, 256, 0, 254); + test (254, 255, 0, 254); + test (254, 1, 254, 0); + test (255, 2, 127, 1); + test (1, 256, 0, 1); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-7.c new file mode 100644 index 000000000..de4a1fb93 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-7.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +extern void abort (void); + +void +test (long long x, long long y, long long q, long long r) +{ + if ((x / y) != q || (x % y) != r) + abort (); +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-times "idivq" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-8.c new file mode 100644 index 000000000..eb09a6d7b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/divmod-8.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +extern void foo (long long, long long, long long, long long, + long long, long long); + +void +bar (long long x, long long y) +{ + foo (0, 0, 0, 0, x / y, x % y); +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-times "idivq" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-1.c new file mode 100644 index 000000000..1bd3b8868 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-1.c @@ -0,0 +1,203 @@ +/* Excess precision tests. Test that excess precision is carried + through various operations. */ +/* { dg-do run } */ +/* { dg-options "-O2 -mfpmath=387 -fexcess-precision=standard" } */ + +#include <float.h> + +extern void abort (void); +extern void exit (int); + +volatile float f1 = 1.0f; +volatile float f2 = 0x1.0p-30f; +volatile float f3 = 0x1.0p-60f; +volatile double d1 = 1.0; +volatile double d2 = 0x1.0p-30; +volatile double d3 = 0x1.0p-60; +volatile float fadd1 = 1.0f + 0x1.0p-30f; +volatile double dadd2 = 1.0 + 0x1.0p-30 + 0x1.0p-60; +volatile long double ldadd1 = 1.0l + 0x1.0p-30l; +volatile long double ldadd2 = 1.0l + 0x1.0p-30l + 0x1.0p-60l; + +void +test_add (void) +{ + if (f1 + f2 != ldadd1) + abort (); + if (f1 + f2 + f3 != ldadd2) + abort (); + if (d1 + d2 != ldadd1) + abort (); + if (d1 + d2 + d3 != ldadd2) + abort (); + if (f1 + d2 + f3 != ldadd2) + abort (); + if (f1 + f2 == fadd1) + abort (); + if (f1 + f2 <= fadd1) + abort (); + if (f1 + f2 < fadd1) + abort (); + if (sizeof(long double) > sizeof(double)) { + if ( d1 + d2 + d3 == dadd2) + abort (); + if (!(d1 + d2 + d3 > dadd2)) + abort (); + if (!(d1 + d2 + d3 >= dadd2)) + abort (); + } + else { + if ( d1 + d2 + d3 != dadd2 ) + abort(); + if ( d1 + d2 + d3 < dadd2 ) + abort(); + if ( d1 + d2 + d3 > dadd2 ) + abort(); + } +} + +volatile long double ldsub1 = 1.0l - 0x1.0p-30l; +volatile long double ldsub2 = 1.0l - 0x1.0p-30l - 0x1.0p-60l; + +void +test_sub (void) +{ + if (f1 - f2 != ldsub1) + abort (); + if (f1 - f2 - f3 != ldsub2) + abort (); + if (d1 - d2 != ldsub1) + abort (); + if (d1 - d2 - d3 != ldsub2) + abort (); + if (f1 - d2 - f3 != ldsub2) + abort (); + if (+(f1 - d2 - f3) != ldsub2) + abort (); + if (-(f1 - d2 - f3) != -ldsub2) + abort (); +} + +volatile float flt_min = FLT_MIN; +volatile double dbl_min = DBL_MIN; +volatile long double flt_min2 = (long double)FLT_MIN * (long double)FLT_MIN; +volatile long double dbl_min3 = (long double)DBL_MIN * (long double)DBL_MIN * (long double)DBL_MIN; + +void +test_mul (void) +{ + if (flt_min * flt_min != flt_min2) + abort (); + if (flt_min * flt_min == 0) + abort (); + if (flt_min * flt_min == 0) + abort (); + if (!(flt_min * flt_min)) + abort (); + if (dbl_min * dbl_min * dbl_min != dbl_min3) + abort (); + if ((long double)(dbl_min * dbl_min * dbl_min) != dbl_min3) + abort (); + if ((0, dbl_min * dbl_min * dbl_min) != dbl_min3) + abort (); + if (sizeof(long double) > sizeof(double) ) { + if (dbl_min * dbl_min * dbl_min == 0) + abort (); + if ((flt_min * flt_min ? dbl_min * dbl_min * dbl_min : 0) == 0) + abort (); + } + else { + if (dbl_min * dbl_min * dbl_min != 0) + abort (); + if ((flt_min * flt_min ? dbl_min * dbl_min * dbl_min : 1) != 0) + abort (); + } + if ((flt_min * flt_min ? : 0) == 0) + abort (); +} + +volatile float f4 = 0x1.0p100f; +volatile double d4 = 0x1.0p100; +volatile long double flt_div = 0x1.0p100l / (long double) FLT_MIN; +volatile long double dbl_div = 0x1.0p100l / (long double) DBL_MIN; + +void +test_div (void) +{ + if (f4 / flt_min != flt_div) + abort (); + if (d4 / dbl_min != dbl_div) + abort (); +} + +volatile float f5 = 0x1.0p30; + +void +test_cast (void) +{ + if ((int)(f1 + f5) != 0x40000001) + abort (); +} + +volatile float _Complex f1c = 1.0f + 1.0if; +volatile float _Complex f2c = 0x1.0p-30f + 0x1.0p-31if; +volatile float _Complex f3c = 0x1.0p-60f + 0x1.0p-59if; +volatile double _Complex d1c = 1.0 + 1.0i; +volatile double _Complex d2c = 0x1.0p-30 + 0x1.0p-31i; +volatile double _Complex d3c = 0x1.0p-60 + 0x1.0p-59i; +volatile long double _Complex ldadd1c = 1.0l + 0x1.0p-30l + 1.0il + 0x1.0p-31il; +volatile long double _Complex ldadd2c = 1.0l + 0x1.0p-30l + 0x1.0p-60l + 1.0il + 0x1.0p-31il + 0x1.0p-59il; +volatile long double _Complex ldadd2cc = 1.0l + 0x1.0p-30l + 0x1.0p-60l - 1.0il - 0x1.0p-31il - 0x1.0p-59il; +volatile float _Complex flt_minc = FLT_MIN; +volatile double _Complex dbl_minc = DBL_MIN; +volatile float _Complex f4c = 0x1.0p100f; +volatile double _Complex d4c = 0x1.0p100; + +void +test_complex (void) +{ + if (f1c + f2c != ldadd1c) + abort (); + if (f1c + f2c + f3c != ldadd2c) + abort (); + if (d1c + d2c != ldadd1c) + abort (); + if (d1c + d2c + d3c != ldadd2c) + abort (); + if (__real__ (f1c + f2c + f3c) != ldadd2) + abort (); + if (__imag__ (d1c + d2c + d3c) != __imag__ ldadd2c) + abort (); + if (~(d1c + d2c + d3c) != ldadd2cc) + abort (); + /* The following call libgcc functions and so would fail unless they + call those for long double. */ + if (flt_minc * flt_minc != flt_min2) + abort (); + if (dbl_minc * dbl_minc * dbl_minc != dbl_min3) + abort (); + if (f4c / flt_minc != flt_div) + abort (); + if (d4c / dbl_minc != dbl_div) + abort (); + if (f4 / flt_minc != flt_div) + abort (); + if (d4 / dbl_minc != dbl_div) + abort (); + if (f4c / flt_min != flt_div) + abort (); + if (d4c / dbl_min != dbl_div) + abort (); +} + +int +main (void) +{ + test_add (); + test_sub (); + test_mul (); + test_div (); + test_cast (); + test_complex (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-2.c new file mode 100644 index 000000000..b5035e5a1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-2.c @@ -0,0 +1,33 @@ +/* Excess precision tests. Test excess precision of constants. */ +/* { dg-do run } */ +/* { dg-options "-O2 -mfpmath=387 -fexcess-precision=standard" } */ + +#include <float.h> + +extern void abort (void); +extern void exit (int); + +volatile long double ldadd1 = 1.0l + 0x1.0p-30l; +volatile long double ld11f = 1.1f; +volatile long double ld11d = 1.1; +volatile long double ld11 = 1.1; + +void +test_const (void) +{ + if (1.0f + 0x1.0p-30f != ldadd1) + abort (); + if (ld11f != ld11) + abort (); + if (ld11d != ld11) + abort (); + if (1.1f != ld11) + abort (); +} + +int +main (void) +{ + test_const (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-3.c new file mode 100644 index 000000000..1fd038a87 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-3.c @@ -0,0 +1,237 @@ +/* Excess precision tests. Test excess precision is removed when + necessary. */ +/* { dg-do run } */ +/* { dg-options "-O2 -mfpmath=387 -fexcess-precision=standard" } */ + +#include <float.h> +#include <stdarg.h> + +extern void abort (void); +extern void exit (int); + +volatile float f1 = 1.0f; +volatile float f2 = 0x1.0p-30f; +volatile float f3 = 0x1.0p-60f; +volatile double d1 = 1.0; +volatile double d2 = 0x1.0p-30; +volatile double d3 = 0x1.0p-60; +volatile double d3d = 0x1.0p-52; +volatile float fadd1 = 1.0f + 0x1.0p-30f; +volatile double dadd2 = 1.0 + 0x1.0p-30 + 0x1.0p-60; +volatile double dh = 0x1.0p-24; +volatile float fha = 1.0f + 0x1.0p-23f; + +void +test_assign (void) +{ + float f; + double d; + f = f1 + f2; + if (f != fadd1) + abort (); + d = f1 + f2; + if (d != dadd2) + abort (); + d = d1 + d2 + d3; + if (d != dadd2) + abort (); + /* Verify rounding direct to float without double rounding. */ + if (sizeof(long double) > sizeof(double) ) { + f = d1 + dh + d3; + if (f != fha) + abort (); + } else { + f = d1 + dh + d3d; + if (f != fha) + abort (); + } +} + +void +test_init (void) +{ + float f = f1 + f2; + double d = d1 + d2 + d3; + if (f != fadd1) + abort (); + if (d != dadd2) + abort (); +} + +volatile int i1 = 0x40000001; +volatile unsigned int u1 = 0x80000001u; +volatile long long ll1 = 0x4000000000000001ll; +volatile unsigned long long ull1 = 0x8000000000000001ull; + +void +test_cast (void) +{ + if ((float)(f1 + f2) != fadd1) + abort (); + if ((double)(d1 + d2 + d3) != dadd2) + abort (); + if ((double)(f1 + f2 + f3) != dadd2) + abort (); + if ((float)i1 != 0x1.0p30f) + abort (); + if ((float)u1 != 0x1.0p31f) + abort (); + if ((float)ll1 != 0x1.0p62f) + abort (); + if ((float)ull1 != 0x1.0p63f) + abort (); + if ((double)ll1 != 0x1.0p62) + abort (); + if ((double)ull1 != 0x1.0p63) + abort (); +} + +static inline void +check_float (float f) +{ + if (f != fadd1) + abort (); +} + +static inline void +check_double (double d) +{ + if (d != dadd2) + abort (); +} + +static inline void +check_float_nonproto (f) + float f; +{ + if (f != fadd1) + abort (); +} + +static inline void +check_double_nonproto (d) + double d; +{ + if (d != dadd2) + abort (); +} + +static void +check_double_va (int i, ...) +{ + va_list ap; + va_start (ap, i); + if (va_arg (ap, double) != dadd2) + abort (); + va_end (ap); +} + +void +test_call (void) +{ + check_float (f1 + f2); + check_double (d1 + d2 + d3); + check_double (f1 + f2 + f3); + check_float_nonproto (f1 + f2); + check_double_nonproto (d1 + d2 + d3); + check_double_nonproto (f1 + f2 + f3); + check_double_va (0, d1 + d2 + d3); + check_double_va (0, f1 + f2 + f3); +} + +static inline float +return_float (void) +{ + return f1 + f2; +} + +static inline double +return_double1 (void) +{ + return d1 + d2 + d3; +} + +static inline double +return_double2 (void) +{ + return f1 + f2 + f3; +} + +void +test_return (void) +{ + if (return_float () != fadd1) + abort (); + if (return_double1 () != dadd2) + abort (); + if (return_double2 () != dadd2) + abort (); +} + +volatile float flt_min = FLT_MIN; +volatile double dbl_min = DBL_MIN; +volatile float flt_max = FLT_MAX; +volatile double dbl_max = DBL_MAX; + +void +test_builtin (void) +{ + /* Classification macros convert to the semantic type. signbit and + comparison macros do not. */ + if (!__builtin_isinf (flt_max * flt_max)) + abort (); + if (!__builtin_isinf (dbl_max * dbl_max)) + abort (); + if (__builtin_isnormal (flt_max * flt_max)) + abort (); + if (__builtin_isnormal (dbl_max * dbl_max)) + abort (); + if (__builtin_isfinite (flt_max * flt_max)) + abort (); + if (__builtin_isfinite (dbl_max * dbl_max)) + abort (); + if (!__builtin_isgreater (flt_min * flt_min, 0.0f)) + abort (); + if (!__builtin_isgreaterequal (flt_min * flt_min, 0.0f)) + abort (); + if (!__builtin_isless (0.0f, flt_min * flt_min)) + abort (); + if (__builtin_islessequal (flt_min * flt_min, 0.0f)) + abort (); + if (!__builtin_islessgreater (flt_min * flt_min, 0.0f)) + abort (); + if (!__builtin_isgreaterequal (dbl_min * dbl_min, 0.0)) + abort (); + if (sizeof(long double) > sizeof(double) ) { + if (!__builtin_isgreater (dbl_min * dbl_min, 0.0)) + abort (); + if (!__builtin_isless (0.0, dbl_min * dbl_min)) + abort (); + if (__builtin_islessequal (dbl_min * dbl_min, 0.0)) + abort (); + if (!__builtin_islessgreater (dbl_min * dbl_min, 0.0)) + abort (); + } + else { + if (__builtin_isgreater (dbl_min * dbl_min, 0.0)) + abort (); + if (__builtin_isless (0.0, dbl_min * dbl_min)) + abort (); + if (!__builtin_islessequal (dbl_min * dbl_min, 0.0)) + abort (); + if (__builtin_islessgreater (dbl_min * dbl_min, 0.0)) + abort (); + } +} + +int +main (void) +{ + test_assign (); + test_init (); + test_cast (); + test_call (); + test_return (); + test_builtin (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-4.c new file mode 100644 index 000000000..04e88a375 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-4.c @@ -0,0 +1,7 @@ +/* Excess precision tests. Test diagnostics for excess precision of + constants. */ +/* { dg-do compile } */ +/* { dg-options "-mfpmath=387 -fexcess-precision=standard" } */ + +float f = 0.0f * 1e50f; /* { dg-warning "floating constant exceeds range of 'float'" } */ +double d = 0.0 * 1e400; /* { dg-warning "floating constant exceeds range of 'double'" } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-5.c new file mode 100644 index 000000000..1cc7e589c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-5.c @@ -0,0 +1,22 @@ +/* Excess precision tests. Verify excess precision doesn't affect + actual types. */ +/* { dg-do compile } */ +/* { dg-options "-mfpmath=387 -fexcess-precision=standard" } */ + +float f; +double d; + +void +test_types (void) +{ + float *fp; + double *dp; +#define CHECK_FLOAT(E) fp = &(typeof(E)){0} +#define CHECK_DOUBLE(E) dp = &(typeof(E)){0} + CHECK_FLOAT (f + f); + CHECK_DOUBLE (d + d); + CHECK_FLOAT (f * f / f); + CHECK_DOUBLE (d * d / d); + CHECK_FLOAT (f ? f - f : f); + CHECK_DOUBLE (d ? d - d : d); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-6.c new file mode 100644 index 000000000..fb8d57232 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/excess-precision-6.c @@ -0,0 +1,19 @@ +/* Excess precision tests. Make sure sqrt is not inlined for float or + double. */ +/* { dg-do compile } */ +/* { dg-options "-mfpmath=387 -O2 -fno-math-errno -fexcess-precision=standard" } */ + +float f; +double d; + +float fr; +double dr; + +void +test_builtins (void) +{ + fr = __builtin_sqrtf (f); + dr = __builtin_sqrt (d); +} + +/* { dg-final { scan-assembler-not "fsqrt" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-1.c new file mode 100644 index 000000000..102beb230 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic" } */ + +int +foo (unsigned char x, unsigned char y) +{ + return (x % y) != 0; +} + +/* { dg-final { scan-assembler-not "test\[b\]?\[^\\n\]*%\[a-d\]l" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-2.c new file mode 100644 index 000000000..3bb5f154c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic" } */ + +int +foo (unsigned char x, unsigned char y) +{ + return (x % y) > 4; +} + +/* { dg-final { scan-assembler-times "cmp\[b\]?\[^\\n\]*%\[a-d\]h" 1 } } */ +/* { dg-final { scan-assembler-not "cmp\[b\]?\[^\\n\]*%\[a-d\]l" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-3.c new file mode 100644 index 000000000..520bf3bb5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic" } */ + +typedef struct +{ + unsigned char c1; + unsigned char c2; + unsigned char c3; + unsigned char c4; +} foo_t; + +int +#ifndef __x86_64__ +__attribute__((regparm(3))) +#endif +foo (foo_t x) +{ + return x.c2 != 0; +} + +/* { dg-final { scan-assembler-not "test\[b\]?\[^\\n\]*%\[a-z0-9\]+l" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-4.c new file mode 100644 index 000000000..716ae2299 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-4.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic" } */ + +typedef struct +{ + unsigned char c1; + unsigned char c2; + unsigned char c3; + unsigned char c4; +} foo_t; + +int +#ifndef __x86_64__ +__attribute__((regparm(3))) +#endif +foo (foo_t x) +{ + return x.c2 > 4; +} + +/* { dg-final { scan-assembler-times "cmp\[b\]?\[^\\n\]*%\[a-z0-9\]+h" 1 } } */ +/* { dg-final { scan-assembler-not "cmp\[b\]?\[^\\n\]*%\[a-z0-9\]+l" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-5.c new file mode 100644 index 000000000..a488dafa2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-5.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic" } */ + +typedef struct +{ + unsigned int c1:8; + unsigned int c2:8; + unsigned int c3:8; + unsigned int c4:8; +} foo_t; + +int +#ifndef __x86_64__ +__attribute__((regparm(3))) +#endif +foo (foo_t x) +{ + return x.c2 != 0; +} + +/* { dg-final { scan-assembler-not "test\[b\]?\[^\\n\]*%\[a-z0-9\]+l" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-6.c new file mode 100644 index 000000000..1440ec3be --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/extract-6.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic" } */ + +typedef struct +{ + unsigned int c1:8; + unsigned int c2:8; + unsigned int c3:8; + unsigned int c4:8; + +} foo_t; + +int +#ifndef __x86_64__ +__attribute__((regparm(3))) +#endif +foo (foo_t x) +{ + return x.c2 > 4; +} + +/* { dg-final { scan-assembler-times "cmp\[b\]?\[^\\n\]*%\[a-z0-9\]+h" 1 } } */ +/* { dg-final { scan-assembler-not "cmp\[b\]?\[^\\n\]*%\[a-z0-9\]+l" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/f16c-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/f16c-check.h new file mode 100644 index 000000000..af7f32c5f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/f16c-check.h @@ -0,0 +1,30 @@ +#include <stdlib.h> +#include <stdio.h> +#include "cpuid.h" +#include "m256-check.h" + +static void f16c_test (void); + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run F16C test only if host has F16C support. */ + if (ecx & bit_F16C) + { + f16c_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fastcall-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fastcall-1.c new file mode 100644 index 000000000..9d7012391 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fastcall-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target i?86-*-mingw32* i?86-*-cygwin* } } */ +/* { dg-options "-std=gnu89" } */ + +void +__attribute__ ((fastcall)) +f1() { } + +void +_fastcall +f2() { } + +void +__fastcall +f3() { } + +void +__attribute__ ((fastcall)) +f4(int x, int y, int z) { } + +/* Scan for global label with correct prefix and suffix. */ +/* { dg-final { scan-assembler "\.globl\[ \t\]@f4@12" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c new file mode 100644 index 000000000..3f33f6b21 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-options "-mpreferred-stack-boundary=4 -msse" } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +extern void abort(void); + +void __attribute__((fastcall, sseregparm)) foo(int i, int j, float x) +{ + static int last_align = -1; + int dummy, align = (int)&dummy & 15; + if (last_align < 0) + last_align = align; + else if (align != last_align) + abort (); +} + +static void +sse_test (void) +{ + foo(0,0,0.0); + foo(0,0,0.0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/float128-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/float128-1.c new file mode 100644 index 000000000..76f5dba50 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/float128-1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +extern void abort (void); + +typedef _Complex float __attribute__((mode(TC))) _Complex128; + +_Complex128 __attribute__ ((noinline)) +foo (_Complex128 x, _Complex128 y) +{ + return x * y; +} + +static void +sse2_test (void) +{ + _Complex128 a = 1.3q + 3.4qi, b = 5.6q + 7.8qi, c; + + c = foo (a, b); + if (__real__(c) == 0.0q || __imag__ (c) == 0.0q) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/float128-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/float128-2.c new file mode 100644 index 000000000..ae899ab23 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/float128-2.c @@ -0,0 +1,18 @@ +/* PR target/36710 */ + +/* { dg-do run } */ +/* { dg-options "-Os -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +extern void abort (void); + +static void +sse2_test (void) +{ + static volatile __float128 a = 123.0q; + + if ((int) a != 123) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fmaddXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fmaddXX.c new file mode 100644 index 000000000..7e73402fc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fmaddXX.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm256_fmadd_pd (__m256d __A, __m256d __B, __m256d __C) +{ + union256d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[4]; + int i; + e.x = _mm256_fmadd_pd (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] + c.a[i]; + } + if (check_union256d (e, d)) + abort (); +} + +void +check_mm256_fmadd_ps (__m256 __A, __m256 __B, __m256 __C) +{ + union256 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[8]; + int i; + e.x = _mm256_fmadd_ps (__A, __B, __C); + for (i = 0; i < 8; i++) + { + d[i] = a.a[i] * b.a[i] + c.a[i]; + } + if (check_union256 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union256 c[3]; + union256d d[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 8; j++) + c[i].a[j] = i * j + 3.5; + for (j = 0; j < 4; j++) + d[i].a[j] = i * j + 3.5; + } + check_mm256_fmadd_pd (d[0].x, d[1].x, d[2].x); + check_mm256_fmadd_ps (c[0].x, c[1].x, c[2].x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fmaddsubXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fmaddsubXX.c new file mode 100644 index 000000000..4b61ad5f8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fmaddsubXX.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm256_fmaddsub_ps (__m256 __A, __m256 __B, __m256 __C) +{ + union256 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[8]; + int i; + e.x = _mm256_fmaddsub_ps (__A, __B, __C); + for (i = 0; i < 8; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? c.a[i] : -c.a[i]); + } + if (check_union256 (e, d)) + abort (); +} + +void +check_mm256_fmaddsub_pd (__m256d __A, __m256d __B, __m256d __C) +{ + union256d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[4]; + int i; + e.x = _mm256_fmaddsub_pd (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? c.a[i] : -c.a[i]); + } + if (check_union256d (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union256 c[3]; + union256d d[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 8; j++) + c[i].a[j] = i * j + 3.5; + for (j = 0; j < 4; j++) + d[i].a[j] = i * j + 3.5; + } + check_mm256_fmaddsub_pd (d[0].x, d[1].x, d[2].x); + check_mm256_fmaddsub_ps (c[0].x, c[1].x, c[2].x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fmsubXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fmsubXX.c new file mode 100644 index 000000000..d92aec0ec --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fmsubXX.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + + +void +check_mm256_fmsub_pd (__m256d __A, __m256d __B, __m256d __C) +{ + union256d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[4]; + int i; + e.x = _mm256_fmsub_pd (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] - c.a[i]; + } + if (check_union256d (e, d)) + abort (); +} + +void +check_mm256_fmsub_ps (__m256 __A, __m256 __B, __m256 __C) +{ + union256 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[8]; + int i; + e.x = _mm256_fmsub_ps (__A, __B, __C); + for (i = 0; i < 8; i++) + { + d[i] = a.a[i] * b.a[i] - c.a[i]; + } + if (check_union256 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union256 c[3]; + union256d d[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 8; j++) + c[i].a[j] = i * j + 3.5; + for (j = 0; j < 4; j++) + d[i].a[j] = i * j + 3.5; + } + check_mm256_fmsub_pd (d[0].x, d[1].x, d[2].x); + check_mm256_fmsub_ps (c[0].x, c[1].x, c[2].x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fmsubaddXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fmsubaddXX.c new file mode 100644 index 000000000..84a41c4c0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fmsubaddXX.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm256_fmsubadd_ps (__m256 __A, __m256 __B, __m256 __C) +{ + union256 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[8]; + int i; + e.x = _mm256_fmsubadd_ps (__A, __B, __C); + for (i = 0; i < 8; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? -c.a[i] : c.a[i]); + } + if (check_union256 (e, d)) + abort (); +} + +void +check_mm256_fmsubadd_pd (__m256d __A, __m256d __B, __m256d __C) +{ + union256d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[4]; + int i; + e.x = _mm256_fmsubadd_pd (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? -c.a[i] : c.a[i]); + } + if (check_union256d (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union256 c[3]; + union256d d[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 8; j++) + c[i].a[j] = i * j + 3.5; + for (j = 0; j < 4; j++) + d[i].a[j] = i * j + 3.5; + } + check_mm256_fmsubadd_pd (d[0].x, d[1].x, d[2].x); + check_mm256_fmsubadd_ps (c[0].x, c[1].x, c[2].x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fnmaddXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fnmaddXX.c new file mode 100644 index 000000000..c0dfa6900 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fnmaddXX.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm256_fnmadd_pd (__m256d __A, __m256d __B, __m256d __C) +{ + union256d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[4]; + int i; + e.x = _mm256_fnmadd_pd (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = -a.a[i] * b.a[i] + c.a[i]; + } + if (check_union256d (e, d)) + abort (); +} + +void +check_mm256_fnmadd_ps (__m256 __A, __m256 __B, __m256 __C) +{ + union256 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[8]; + int i; + e.x = _mm256_fnmadd_ps (__A, __B, __C); + for (i = 0; i < 8; i++) + { + d[i] = -a.a[i] * b.a[i] + c.a[i]; + } + if (check_union256 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union256 c[3]; + union256d d[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 8; j++) + c[i].a[j] = i * j + 3.5; + for (j = 0; j < 4; j++) + d[i].a[j] = i * j + 3.5; + } + check_mm256_fnmadd_pd (d[0].x, d[1].x, d[2].x); + check_mm256_fnmadd_ps (c[0].x, c[1].x, c[2].x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fnmsubXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fnmsubXX.c new file mode 100644 index 000000000..ac4705e5c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-256-fnmsubXX.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + + +void +check_mm256_fnmsub_pd (__m256d __A, __m256d __B, __m256d __C) +{ + union256d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[4]; + int i; + e.x = _mm256_fnmsub_pd (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = -a.a[i] * b.a[i] - c.a[i]; + } + if (check_union256d (e, d)) + abort (); +} + +void +check_mm256_fnmsub_ps (__m256 __A, __m256 __B, __m256 __C) +{ + union256 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[8]; + int i; + e.x = _mm256_fnmsub_ps (__A, __B, __C); + for (i = 0; i < 8; i++) + { + d[i] = -a.a[i] * b.a[i] - c.a[i]; + } + if (check_union256 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union256 c[3]; + union256d d[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 8; j++) + c[i].a[j] = i * j + 3.5; + for (j = 0; j < 4; j++) + d[i].a[j] = i * j + 3.5; + } + check_mm256_fnmsub_pd (d[0].x, d[1].x, d[2].x); + check_mm256_fnmsub_ps (c[0].x, c[1].x, c[2].x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-check.h new file mode 100644 index 000000000..8390f5088 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-check.h @@ -0,0 +1,25 @@ +#include <stdlib.h> + +#include "cpuid.h" + +static void fma_test (void); + +static void __attribute__ ((noinline)) do_test (void) +{ + fma_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run FMA test only if host has FMA support. */ + if (ecx & bit_FMA) + do_test (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-compile.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-compile.c new file mode 100644 index 000000000..0445f7bc0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-compile.c @@ -0,0 +1,221 @@ +/* Test that the compiler properly generates floating point multiply + and add instructions FMA systems. */ + +/* { dg-do compile } */ +/* { dg-options "-O2 -mfma" } */ + +#include <x86intrin.h> + +__m128d +check_mm_fmadd_pd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fmadd_pd (a, b, c); +} + +__m256d +check_mm256_fmadd_pd (__m256d a, __m256d b, __m256d c) +{ + return _mm256_fmadd_pd (a, b, c); +} + +__m128 +check_mm_fmadd_ps (__m128 a, __m128 b, __m128 c) +{ + return _mm_fmadd_ps (a, b, c); +} + +__m256 +check_mm256_fmadd_ps (__m256 a, __m256 b, __m256 c) +{ + return _mm256_fmadd_ps (a, b, c); +} + +__m128d +check_mm_fmadd_sd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fmadd_sd (a, b, c); +} + +__m128 +check_mm_fmadd_ss (__m128 a, __m128 b, __m128 c) +{ + return _mm_fmadd_ss (a, b, c); +} + +__m128d +check_mm_fmsub_pd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fmsub_pd (a, b, c); +} + +__m256d +check_mm256_fmsub_pd (__m256d a, __m256d b, __m256d c) +{ + return _mm256_fmsub_pd (a, b, c); +} + +__m128 +check_mm_fmsub_ps (__m128 a, __m128 b, __m128 c) +{ + return _mm_fmsub_ps (a, b, c); +} + +__m256 +check_mm256_fmsub_ps (__m256 a, __m256 b, __m256 c) +{ + return _mm256_fmsub_ps (a, b, c); +} + +__m128d +check_mm_fmsub_sd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fmsub_sd (a, b, c); +} + +__m128 +check_mm_fmsub_ss (__m128 a, __m128 b, __m128 c) +{ + return _mm_fmsub_ss (a, b, c); +} + +__m128d +check_mm_fnmadd_pd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fnmadd_pd (a, b, c); +} + +__m256d +check_mm256_fnmadd_pd (__m256d a, __m256d b, __m256d c) +{ + return _mm256_fnmadd_pd (a, b, c); +} + +__m128 +check_mm_fnmadd_ps (__m128 a, __m128 b, __m128 c) +{ + return _mm_fnmadd_ps (a, b, c); +} + +__m256 +check_mm256_fnmadd_ps (__m256 a, __m256 b, __m256 c) +{ + return _mm256_fnmadd_ps (a, b, c); +} + +__m128d +check_mm_fnmadd_sd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fnmadd_sd (a, b, c); +} + +__m128 +check_mm_fnmadd_ss (__m128 a, __m128 b, __m128 c) +{ + return _mm_fnmadd_ss (a, b, c); +} + +__m128d +check_mm_fnmsub_pd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fnmsub_pd (a, b, c); +} + +__m256d +check_mm256_fnmsub_pd (__m256d a, __m256d b, __m256d c) +{ + return _mm256_fnmsub_pd (a, b, c); +} + +__m128 +check_mm_fnmsub_ps (__m128 a, __m128 b, __m128 c) +{ + return _mm_fnmsub_ps (a, b, c); +} + +__m256 +check_mm256_fnmsub_ps (__m256 a, __m256 b, __m256 c) +{ + return _mm256_fnmsub_ps (a, b, c); +} + +__m128d +check_mm_fnmsub_sd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fnmsub_sd (a, b, c); +} + +__m128 +check_mm_fnmsub_ss (__m128 a, __m128 b, __m128 c) +{ + return _mm_fnmsub_ss (a, b, c); +} + +__m128d +check_mm_fmaddsub_pd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fmaddsub_pd (a, b, c); +} + +__m256d +check_mm256_fmaddsub_pd (__m256d a, __m256d b, __m256d c) +{ + return _mm256_fmaddsub_pd (a, b, c); +} + +__m128 +check_mm_fmaddsub_ps (__m128 a, __m128 b, __m128 c) +{ + return _mm_fmaddsub_ps (a, b, c); +} + +__m256 +check_mm256_fmaddsub_ps (__m256 a, __m256 b, __m256 c) +{ + return _mm256_fmaddsub_ps (a, b, c); +} + +__m128d +check_mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c) +{ + return _mm_fmsubadd_pd (a, b, c); +} + +__m256d +check_mm256_fmsubadd_pd (__m256d a, __m256d b, __m256d c) +{ + return _mm256_fmsubadd_pd (a, b, c); +} + +__m128 +check_mm_fmsubadd_ps (__m128 a, __m128 b, __m128 c) +{ + return _mm_fmsubadd_ps (a, b, c); +} + +__m256 +check_mm256_fmsubadd_ps (__m256 a, __m256 b, __m256 c) +{ + return _mm256_fmsubadd_ps (a, b, c); +} + + +/* { dg-final { scan-assembler-times "vfmadd\[^s\]..ps" 2 } } */ +/* { dg-final { scan-assembler-times "vfmsub\[^s\]..ps" 2 } } */ +/* { dg-final { scan-assembler-times "vfnmadd...ps" 2 } } */ +/* { dg-final { scan-assembler-times "vfnmsub...ps" 2 } } */ +/* { dg-final { scan-assembler-times "vfmaddsub...ps" 2 } } */ +/* { dg-final { scan-assembler-times "vfmsubadd...ps" 2 } } */ +/* { dg-final { scan-assembler-times "vfmadd\[^s\]..pd" 2 } } */ +/* { dg-final { scan-assembler-times "vfmsub\[^s\]..pd" 2 } } */ +/* { dg-final { scan-assembler-times "vfnmadd...pd" 2 } } */ +/* { dg-final { scan-assembler-times "vfnmsub...pd" 2 } } */ +/* { dg-final { scan-assembler-times "vfmaddsub...pd" 2 } } */ +/* { dg-final { scan-assembler-times "vfmsubadd...pd" 2 } } */ +/* { dg-final { scan-assembler-times "vfmadd\[^s\]..ss" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub\[^s\]..ss" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmadd...ss" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsub...ss" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd\[^s\]..sd" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub\[^s\]..sd" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmadd...sd" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsub...sd" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fmaddXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fmaddXX.c new file mode 100644 index 000000000..43ef9e807 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fmaddXX.c @@ -0,0 +1,102 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm_fmadd_pd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fmadd_pd (__A, __B, __C); + for (i = 0; i < 2; i++) + { + d[i] = a.a[i] * b.a[i] + c.a[i]; + } + + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fmadd_ps (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fmadd_ps (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] + c.a[i]; + } + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fmadd_sd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fmadd_sd (__A, __B, __C); + for (i = 1; i < 2; i++) + { + d[i] = a.a[i]; + } + d[0] = a.a[0] * b.a[0] + c.a[0]; + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fmadd_ss (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fmadd_ss (__A, __B, __C); + for (i = 1; i < 4; i++) + { + d[i] = a.a[i]; + } + d[0] = a.a[0] * b.a[0] + c.a[0]; + if (check_union128 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union128 a[3]; + union128d b[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 4; j++) + a[i].a[j] = i * j + 3.5; + for (j = 0; j < 2; j++) + b[i].a[j] = i * j + 3.5; + } + check_mm_fmadd_pd (b[0].x, b[1].x, b[2].x); + check_mm_fmadd_sd (b[0].x, b[1].x, b[2].x); + check_mm_fmadd_ps (a[0].x, a[1].x, a[2].x); + check_mm_fmadd_ss (a[0].x, a[1].x, a[2].x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fmaddsubXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fmaddsubXX.c new file mode 100644 index 000000000..89c816392 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fmaddsubXX.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm_fmaddsub_ps (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fmaddsub_ps (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? c.a[i] : -c.a[i]); + } + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fmaddsub_pd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fmaddsub_pd (__A, __B, __C); + for (i = 0; i < 2; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? c.a[i] : -c.a[i]); + } + if (check_union128d (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union128 a[3]; + union128d b[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 4; j++) + a[i].a[j] = i * j + 3.5; + for (j = 0; j < 2; j++) + b[i].a[j] = i * j + 3.5; + } + check_mm_fmaddsub_pd (b[0].x, b[1].x, b[2].x); + check_mm_fmaddsub_ps (a[0].x, a[1].x, a[2].x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fmsubXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fmsubXX.c new file mode 100644 index 000000000..3d92d4b25 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fmsubXX.c @@ -0,0 +1,101 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm_fmsub_pd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fmsub_pd (__A, __B, __C); + for (i = 0; i < 2; i++) + { + d[i] = a.a[i] * b.a[i] - c.a[i]; + } + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fmsub_ps (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fmsub_ps (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] - c.a[i]; + } + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fmsub_sd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fmsub_sd (__A, __B, __C); + for (i = 1; i < 2; i++) + { + d[i] = a.a[i]; + } + d[0] = a.a[0] * b.a[0] - c.a[0]; + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fmsub_ss (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fmsub_ss (__A, __B, __C); + for (i = 1; i < 4; i++) + { + d[i] = a.a[i]; + } + d[0] = a.a[0] * b.a[0] - c.a[0]; + if (check_union128 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union128 a[3]; + union128d b[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 4; j++) + a[i].a[j] = i * j + 3.5; + for (j = 0; j < 2; j++) + b[i].a[j] = i * j + 3.5; + } + check_mm_fmsub_pd (b[0].x, b[1].x, b[2].x); + check_mm_fmsub_sd (b[0].x, b[1].x, b[2].x); + check_mm_fmsub_ps (a[0].x, a[1].x, a[2].x); + check_mm_fmsub_ss (a[0].x, a[1].x, a[2].x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fmsubaddXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fmsubaddXX.c new file mode 100644 index 000000000..b03f87531 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fmsubaddXX.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm_fmsubadd_ps (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fmsubadd_ps (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? -c.a[i] : c.a[i]); + } + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fmsubadd_pd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fmsubadd_pd (__A, __B, __C); + for (i = 0; i < 2; i++) + { + d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? -c.a[i] : c.a[i]); + } + if (check_union128d (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union128 a[3]; + union128d b[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 4; j++) + a[i].a[j] = i * j + 3.5; + for (j = 0; j < 2; j++) + b[i].a[j] = i * j + 3.5; + } + check_mm_fmsubadd_pd (b[0].x, b[1].x, b[2].x); + check_mm_fmsubadd_ps (a[0].x, a[1].x, a[2].x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fnmaddXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fnmaddXX.c new file mode 100644 index 000000000..f23a6c5e4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fnmaddXX.c @@ -0,0 +1,101 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm_fnmadd_ps (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fnmadd_ps (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = -a.a[i] * b.a[i] + c.a[i]; + } + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fnmadd_pd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fnmadd_pd (__A, __B, __C); + for (i = 0; i < 2; i++) + { + d[i] = -a.a[i] * b.a[i] + c.a[i]; + } + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fnmadd_sd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fnmadd_sd (__A, __B, __C); + for (i = 1; i < 2; i++) + { + d[i] = a.a[i]; + } + d[0] = -a.a[0] * b.a[0] + c.a[0]; + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fnmadd_ss (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fnmadd_ss (__A, __B, __C); + for (i = 1; i < 4; i++) + { + d[i] = a.a[i]; + } + d[0] = -a.a[0] * b.a[0] + c.a[0]; + if (check_union128 (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union128 a[3]; + union128d b[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 4; j++) + a[i].a[j] = i * j + 3.5; + for (j = 0; j < 2; j++) + b[i].a[j] = i * j + 3.5; + } + check_mm_fnmadd_pd (b[0].x, b[1].x, b[2].x); + check_mm_fnmadd_sd (b[0].x, b[1].x, b[2].x); + check_mm_fnmadd_ps (a[0].x, a[1].x, a[2].x); + check_mm_fnmadd_ss (a[0].x, a[1].x, a[2].x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fnmsubXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fnmsubXX.c new file mode 100644 index 000000000..d17c7f2ed --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma-fnmsubXX.c @@ -0,0 +1,101 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O2 -mfma" } */ + +#include "fma-check.h" + +#include <x86intrin.h> +#include "m256-check.h" + +void +check_mm_fnmsub_sd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fnmsub_sd (__A, __B, __C); + for (i = 1; i < 2; i++) + { + d[i] = a.a[i]; + } + d[0] = -a.a[0] * b.a[0] - c.a[0]; + if (check_union128d (e, d)) + abort (); +} + +void +check_mm_fnmsub_ss (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fnmsub_ss (__A, __B, __C); + for (i = 1; i < 4; i++) + { + d[i] = a.a[i]; + } + d[0] = -a.a[0] * b.a[0] - c.a[0]; + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fnmsub_ps (__m128 __A, __m128 __B, __m128 __C) +{ + union128 a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + float d[4]; + int i; + e.x = _mm_fnmsub_ps (__A, __B, __C); + for (i = 0; i < 4; i++) + { + d[i] = -a.a[i] * b.a[i] - c.a[i]; + } + if (check_union128 (e, d)) + abort (); +} + +void +check_mm_fnmsub_pd (__m128d __A, __m128d __B, __m128d __C) +{ + union128d a, b, c, e; + a.x = __A; + b.x = __B; + c.x = __C; + double d[2]; + int i; + e.x = _mm_fnmsub_pd (__A, __B, __C); + for (i = 0; i < 2; i++) + { + d[i] = -a.a[i] * b.a[i] - c.a[i]; + } + if (check_union128d (e, d)) + abort (); +} + +static void +fma_test (void) +{ + union128 a[3]; + union128d b[3]; + int i, j; + for (i = 0; i < 3; i++) + { + for (j = 0; j < 4; j++) + a[i].a[j] = i * j + 3.5; + for (j = 0; j < 2; j++) + b[i].a[j] = i * j + 3.5; + } + check_mm_fnmsub_pd (b[0].x, b[1].x, b[2].x); + check_mm_fnmsub_sd (b[0].x, b[1].x, b[2].x); + check_mm_fnmsub_ps (a[0].x, a[1].x, a[2].x); + check_mm_fnmsub_ss (a[0].x, a[1].x, a[2].x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma3-builtin-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma3-builtin-2.c new file mode 100644 index 000000000..01768b963 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma3-builtin-2.c @@ -0,0 +1,97 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mfma -mno-fma4 -mtune=generic" } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +double vda[SIZE] __attribute__((__aligned__(32))); +double vdb[SIZE] __attribute__((__aligned__(32))); +double vdc[SIZE] __attribute__((__aligned__(32))); +double vdd[SIZE] __attribute__((__aligned__(32))); + +float vfa[SIZE] __attribute__((__aligned__(32))); +float vfb[SIZE] __attribute__((__aligned__(32))); +float vfc[SIZE] __attribute__((__aligned__(32))); +float vfd[SIZE] __attribute__((__aligned__(32))); + +void +vector_fma (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = __builtin_fma (vdb[i], vdc[i], vdd[i]); +} + +void +vector_fms (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = __builtin_fma (vdb[i], vdc[i], -vdd[i]); +} + +void +vector_fnma (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = __builtin_fma (-vdb[i], vdc[i], vdd[i]); +} + +void +vector_fnms (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = __builtin_fma (-vdb[i], vdc[i], -vdd[i]); +} + +void +vector_fmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]); +} + +void +vector_fmsf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (vfb[i], vfc[i], -vfd[i]); +} + +void +vector_fnmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (-vfb[i], vfc[i], vfd[i]); +} + +void +vector_fnmsf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (-vfb[i], vfc[i], -vfd[i]); +} + +/* { dg-final { scan-assembler-times "vfmadd...ps" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd...pd" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub...ps" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub...pd" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmadd...ps" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmadd...pd" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsub...ps" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsub...pd" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma3-builtin.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma3-builtin.c new file mode 100644 index 000000000..2d9c5c73a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma3-builtin.c @@ -0,0 +1,81 @@ +/* Test that the compiler properly generates floating point multiply + and add instructions FMA3 systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfma -mno-fma4" } */ + +#ifndef __FP_FAST_FMAF +# error "__FP_FAST_FMAF should be defined" +#endif +#ifndef __FP_FAST_FMA +# error "__FP_FAST_FMA should be defined" +#endif + +float +flt_mul_add (float a, float b, float c) +{ + return __builtin_fmaf (a, b, c); +} + +double +dbl_mul_add (double a, double b, double c) +{ + return __builtin_fma (a, b, c); +} + +float +flt_mul_sub (float a, float b, float c) +{ + return __builtin_fmaf (a, b, -c); +} + +double +dbl_mul_sub (double a, double b, double c) +{ + return __builtin_fma (a, b, -c); +} + +float +flt_neg_mul_add_1 (float a, float b, float c) +{ + return __builtin_fmaf (-a, b, c); +} + +double +dbl_neg_mul_add_1 (double a, double b, double c) +{ + return __builtin_fma (-a, b, c); +} + +float +flt_neg_mul_add_2 (float a, float b, float c) +{ + return __builtin_fmaf (a, -b, c); +} + +double +dbl_neg_mul_add_2 (double a, double b, double c) +{ + return __builtin_fma (a, -b, c); +} + +float +flt_neg_mul_sub (float a, float b, float c) +{ + return __builtin_fmaf (-a, b, -c); +} + +double +dbl_neg_mul_sub (double a, double b, double c) +{ + return __builtin_fma (-a, b, -c); +} + +/* { dg-final { scan-assembler-times "vfmadd...ss" 1 } } */ +/* { dg-final { scan-assembler-times "vfmadd...sd" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub...ss" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsub...sd" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmadd...ss" 2 } } */ +/* { dg-final { scan-assembler-times "vfnmadd...sd" 2 } } */ +/* { dg-final { scan-assembler-times "vfnmsub...ss" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsub...sd" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma3-fma.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma3-fma.c new file mode 100644 index 000000000..f18f97bf3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma3-fma.c @@ -0,0 +1,81 @@ +/* Test that the compiler properly optimizes floating point multiply + and add instructions FMA3 systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfma -mno-fma4" } */ + +extern void exit (int); + +float +flt_mul_add (float a, float b, float c) +{ + return (a * b) + c; +} + +double +dbl_mul_add (double a, double b, double c) +{ + return (a * b) + c; +} + +float +flt_mul_sub (float a, float b, float c) +{ + return (a * b) - c; +} + +double +dbl_mul_sub (double a, double b, double c) +{ + return (a * b) - c; +} + +float +flt_neg_mul_add (float a, float b, float c) +{ + return (-(a * b)) + c; +} + +double +dbl_neg_mul_add (double a, double b, double c) +{ + return (-(a * b)) + c; +} + +float +flt_neg_mul_sub (float a, float b, float c) +{ + return (-(a * b)) - c; +} + +double +dbl_neg_mul_sub (double a, double b, double c) +{ + return (-(a * b)) - c; +} + +float f[10] = { 2, 3, 4 }; +double d[10] = { 2, 3, 4 }; + +int main () +{ + f[3] = flt_mul_add (f[0], f[1], f[2]); + f[4] = flt_mul_sub (f[0], f[1], f[2]); + f[5] = flt_neg_mul_add (f[0], f[1], f[2]); + f[6] = flt_neg_mul_sub (f[0], f[1], f[2]); + + d[3] = dbl_mul_add (d[0], d[1], d[2]); + d[4] = dbl_mul_sub (d[0], d[1], d[2]); + d[5] = dbl_neg_mul_add (d[0], d[1], d[2]); + d[6] = dbl_neg_mul_sub (d[0], d[1], d[2]); + exit (0); +} + +/* { dg-final { scan-assembler "vfmadd...ss" } } */ +/* { dg-final { scan-assembler "vfmadd...sd" } } */ +/* { dg-final { scan-assembler "vfmsub...ss" } } */ +/* { dg-final { scan-assembler "vfmsub...sd" } } */ +/* { dg-final { scan-assembler "vfnmadd...ss" } } */ +/* { dg-final { scan-assembler "vfnmadd...sd" } } */ +/* { dg-final { scan-assembler "vfnmsub...ss" } } */ +/* { dg-final { scan-assembler "vfnmsub...sd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-maccXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-maccXX.c new file mode 100644 index 000000000..134200af7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-maccXX.c @@ -0,0 +1,96 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma4 } */ +/* { dg-options "-O2 -mfma4" } */ + +#include "fma4-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 20 + +union +{ + __m256 x[NUM]; + float f[NUM * 8]; + __m256d y[NUM]; + double d[NUM * 4]; +} dst, res, src1, src2, src3; + + +/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate + product is not rounded, only the addition is rounded. */ + +static void +init_maccps () +{ + int i; + for (i = 0; i < NUM * 8; i++) + { + src1.f[i] = i; + src2.f[i] = i + 10; + src3.f[i] = i + 20; + } +} + +static void +init_maccpd () +{ + int i; + for (i = 0; i < NUM * 4; i++) + { + src1.d[i] = i; + src2.d[i] = i + 10; + src3.d[i] = i + 20; + } +} + +static int +check_maccps () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 8; i = i + 8) + for (j = 0; j < 8; j++) + { + res.f[i + j] = (src1.f[i + j] * src2.f[i + j]) + src3.f[i + j]; + if (dst.f[i + j] != res.f[i + j]) + check_fails++; + } + return check_fails++; +} + +static int +check_maccpd () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 4; i = i + 4) + for (j = 0; j < 4; j++) + { + res.d[i + j] = (src1.d[i + j] * src2.d[i + j]) + src3.d[i + j]; + if (dst.d[i + j] != res.d[i + j]) + check_fails++; + } + return check_fails++; +} + +static void +fma4_test (void) +{ + int i; + + init_maccps (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm256_macc_ps (src1.x[i], src2.x[i], src3.x[i]); + + if (check_maccps ()) + abort (); + + init_maccpd (); + + for (i = 0; i < NUM; i++) + dst.y[i] = _mm256_macc_pd (src1.y[i], src2.y[i], src3.y[i]); + + if (check_maccpd ()) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-msubXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-msubXX.c new file mode 100644 index 000000000..d6cafb4d5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-msubXX.c @@ -0,0 +1,96 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma4 } */ +/* { dg-options "-O2 -mfma4" } */ + +#include "fma4-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 20 + +union +{ + __m256 x[NUM]; + float f[NUM * 8]; + __m256d y[NUM]; + double d[NUM * 4]; +} dst, res, src1, src2, src3; + +/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate + product is not rounded, only the addition is rounded. */ + +static void +init_msubps () +{ + int i; + for (i = 0; i < NUM * 8; i++) + { + src1.f[i] = i; + src2.f[i] = i + 10; + src3.f[i] = i + 20; + } +} + +static void +init_msubpd () +{ + int i; + for (i = 0; i < NUM * 4; i++) + { + src1.d[i] = i; + src2.d[i] = i + 10; + src3.d[i] = i + 20; + } +} + +static int +check_msubps () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 8; i = i + 8) + for (j = 0; j < 8; j++) + { + res.f[i + j] = (src1.f[i + j] * src2.f[i + j]) - src3.f[i + j]; + if (dst.f[i + j] != res.f[i + j]) + check_fails++; + } + return check_fails++; +} + +static int +check_msubpd () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 4; i = i + 4) + for (j = 0; j < 4; j++) + { + res.d[i + j] = (src1.d[i + j] * src2.d[i + j]) - src3.d[i + j]; + if (dst.d[i + j] != res.d[i + j]) + check_fails++; + } + return check_fails++; +} + +static void +fma4_test (void) +{ + int i; + + init_msubps (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm256_msub_ps (src1.x[i], src2.x[i], src3.x[i]); + + if (check_msubps ()) + abort (); + + init_msubpd (); + + for (i = 0; i < NUM; i++) + dst.y[i] = _mm256_msub_pd (src1.y[i], src2.y[i], src3.y[i]); + + if (check_msubpd ()) + abort (); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-nmaccXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-nmaccXX.c new file mode 100644 index 000000000..261f302f2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-nmaccXX.c @@ -0,0 +1,96 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma4 } */ +/* { dg-options "-O2 -mfma4" } */ + +#include "fma4-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 20 + +union +{ + __m256 x[NUM]; + float f[NUM * 8]; + __m256d y[NUM]; + double d[NUM * 4]; +} dst, res, src1, src2, src3; + +/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate + product is not rounded, only the addition is rounded. */ + +static void +init_nmaccps () +{ + int i; + for (i = 0; i < NUM * 8; i++) + { + src1.f[i] = i; + src2.f[i] = i + 10; + src3.f[i] = i + 20; + } +} + +static void +init_nmaccpd () +{ + int i; + for (i = 0; i < NUM * 4; i++) + { + src1.d[i] = i; + src2.d[i] = i + 10; + src3.d[i] = i + 20; + } +} + +static int +check_nmaccps () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 8; i = i + 8) + for (j = 0; j < 8; j++) + { + res.f[i + j] = - (src1.f[i + j] * src2.f[i + j]) + src3.f[i + j]; + if (dst.f[i + j] != res.f[i + j]) + check_fails++; + } + return check_fails++; +} + +static int +check_nmaccpd () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 4; i = i + 4) + for (j = 0; j < 4; j++) + { + res.d[i + j] = - (src1.d[i + j] * src2.d[i + j]) + src3.d[i + j]; + if (dst.d[i + j] != res.d[i + j]) + check_fails++; + } + return check_fails++; +} + +static void +fma4_test (void) +{ + int i; + + init_nmaccps (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm256_nmacc_ps (src1.x[i], src2.x[i], src3.x[i]); + + if (check_nmaccps ()) + abort (); + + init_nmaccpd (); + + for (i = 0; i < NUM; i++) + dst.y[i] = _mm256_nmacc_pd (src1.y[i], src2.y[i], src3.y[i]); + + if (check_nmaccpd ()) + abort (); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-nmsubXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-nmsubXX.c new file mode 100644 index 000000000..3205715ef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-nmsubXX.c @@ -0,0 +1,95 @@ +/* { dg-require-effective-target fma4 } */ +/* { dg-options "-O2 -mfma4" } */ + +#include "fma4-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 20 + +union +{ + __m256 x[NUM]; + float f[NUM * 8]; + __m256d y[NUM]; + double d[NUM * 4]; +} dst, res, src1, src2, src3; + +/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate + product is not rounded, only the addition is rounded. */ + +static void +init_nmsubps () +{ + int i; + for (i = 0; i < NUM * 8; i++) + { + src1.f[i] = i; + src2.f[i] = i + 10; + src3.f[i] = i + 20; + } +} + +static void +init_nmsubpd () +{ + int i; + for (i = 0; i < NUM * 4; i++) + { + src1.d[i] = i; + src2.d[i] = i + 10; + src3.d[i] = i + 20; + } +} + +static int +check_nmsubps () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 8; i = i + 8) + for (j = 0; j < 8; j++) + { + res.f[i + j] = - (src1.f[i + j] * src2.f[i + j]) - src3.f[i + j]; + if (dst.f[i + j] != res.f[i + j]) + check_fails++; + } + return check_fails++; +} + +static int +check_nmsubpd () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 4; i = i + 4) + for (j = 0; j < 4; j++) + { + res.d[i + j] = - (src1.d[i + j] * src2.d[i + j]) - src3.d[i + j]; + if (dst.d[i + j] != res.d[i + j]) + check_fails++; + } + return check_fails++; +} + +static void +fma4_test (void) +{ + int i; + + init_nmsubps (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm256_nmsub_ps (src1.x[i], src2.x[i], src3.x[i]); + + if (check_nmsubps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], &src3.f[i * 4])) + abort (); + + init_nmsubpd (); + + for (i = 0; i < NUM; i++) + dst.y[i] = _mm256_nmsub_pd (src1.y[i], src2.y[i], src3.y[i]); + + if (check_nmsubpd (&dst.y[i], &src1.d[i * 2], &src2.d[i * 2], &src3.d[i * 2])) + abort (); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-vector.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-vector.c new file mode 100644 index 000000000..edaa21a2d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-256-vector.c @@ -0,0 +1,92 @@ +/* Test that the compiler properly optimizes floating point multiply and add + instructions vector into vfmaddps on FMA4 systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic" } */ + +extern void exit (int); + +typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__)); +typedef double __m256d __attribute__ ((__vector_size__ (32), __may_alias__)); + +#define SIZE 10240 + +union { + __m256 f_align; + __m256d d_align; + float f[SIZE]; + double d[SIZE]; +} a, b, c, d; + +void +flt_mul_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.f[i] = (b.f[i] * c.f[i]) + d.f[i]; +} + +void +dbl_mul_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.d[i] = (b.d[i] * c.d[i]) + d.d[i]; +} + +void +flt_mul_sub (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.f[i] = (b.f[i] * c.f[i]) - d.f[i]; +} + +void +dbl_mul_sub (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.d[i] = (b.d[i] * c.d[i]) - d.d[i]; +} + +void +flt_neg_mul_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.f[i] = (-(b.f[i] * c.f[i])) + d.f[i]; +} + +void +dbl_neg_mul_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.d[i] = (-(b.d[i] * c.d[i])) + d.d[i]; +} + +int main () +{ + flt_mul_add (); + flt_mul_sub (); + flt_neg_mul_add (); + + dbl_mul_add (); + dbl_mul_sub (); + dbl_neg_mul_add (); + exit (0); +} + +/* { dg-final { scan-assembler "vfmaddps" } } */ +/* { dg-final { scan-assembler "vfmaddpd" } } */ +/* { dg-final { scan-assembler "vfmsubps" } } */ +/* { dg-final { scan-assembler "vfmsubpd" } } */ +/* { dg-final { scan-assembler "vfnmaddps" } } */ +/* { dg-final { scan-assembler "vfnmaddpd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-builtin-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-builtin-2.c new file mode 100644 index 000000000..18927bc09 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-builtin-2.c @@ -0,0 +1,97 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mfma4 -mtune=generic" } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +double vda[SIZE] __attribute__((__aligned__(32))); +double vdb[SIZE] __attribute__((__aligned__(32))); +double vdc[SIZE] __attribute__((__aligned__(32))); +double vdd[SIZE] __attribute__((__aligned__(32))); + +float vfa[SIZE] __attribute__((__aligned__(32))); +float vfb[SIZE] __attribute__((__aligned__(32))); +float vfc[SIZE] __attribute__((__aligned__(32))); +float vfd[SIZE] __attribute__((__aligned__(32))); + +void +vector_fma (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = __builtin_fma (vdb[i], vdc[i], vdd[i]); +} + +void +vector_fms (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = __builtin_fma (vdb[i], vdc[i], -vdd[i]); +} + +void +vector_fnma (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = __builtin_fma (-vdb[i], vdc[i], vdd[i]); +} + +void +vector_fnms (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vda[i] = __builtin_fma (-vdb[i], vdc[i], -vdd[i]); +} + +void +vector_fmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]); +} + +void +vector_fmsf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (vfb[i], vfc[i], -vfd[i]); +} + +void +vector_fnmaf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (-vfb[i], vfc[i], vfd[i]); +} + +void +vector_fnmsf (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + vfa[i] = __builtin_fmaf (-vfb[i], vfc[i], -vfd[i]); +} + +/* { dg-final { scan-assembler-times "vfmaddps" 1 } } */ +/* { dg-final { scan-assembler-times "vfmaddpd" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsubps" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsubpd" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmaddps" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmaddpd" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsubps" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsubpd" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-builtin.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-builtin.c new file mode 100644 index 000000000..7135cc933 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-builtin.c @@ -0,0 +1,81 @@ +/* Test that the compiler properly generates floating point multiply + and add instructions FMA4 systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfma4" } */ + +#ifndef __FP_FAST_FMAF +# error "__FP_FAST_FMAF should be defined" +#endif +#ifndef __FP_FAST_FMA +# error "__FP_FAST_FMA should be defined" +#endif + +float +flt_mul_add (float a, float b, float c) +{ + return __builtin_fmaf (a, b, c); +} + +double +dbl_mul_add (double a, double b, double c) +{ + return __builtin_fma (a, b, c); +} + +float +flt_mul_sub (float a, float b, float c) +{ + return __builtin_fmaf (a, b, -c); +} + +double +dbl_mul_sub (double a, double b, double c) +{ + return __builtin_fma (a, b, -c); +} + +float +flt_neg_mul_add_1 (float a, float b, float c) +{ + return __builtin_fmaf (-a, b, c); +} + +double +dbl_neg_mul_add_1 (double a, double b, double c) +{ + return __builtin_fma (-a, b, c); +} + +float +flt_neg_mul_add_2 (float a, float b, float c) +{ + return __builtin_fmaf (a, -b, c); +} + +double +dbl_neg_mul_add_2 (double a, double b, double c) +{ + return __builtin_fma (a, -b, c); +} + +float +flt_neg_mul_sub (float a, float b, float c) +{ + return __builtin_fmaf (-a, b, -c); +} + +double +dbl_neg_mul_sub (double a, double b, double c) +{ + return __builtin_fma (-a, b, -c); +} + +/* { dg-final { scan-assembler-times "vfmaddss" 1 } } */ +/* { dg-final { scan-assembler-times "vfmaddsd" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsubss" 1 } } */ +/* { dg-final { scan-assembler-times "vfmsubsd" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmaddss" 2 } } */ +/* { dg-final { scan-assembler-times "vfnmaddsd" 2 } } */ +/* { dg-final { scan-assembler-times "vfnmsubss" 1 } } */ +/* { dg-final { scan-assembler-times "vfnmsubsd" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-check.h new file mode 100644 index 000000000..33cd9628c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-check.h @@ -0,0 +1,27 @@ +#include <stdlib.h> + +#include "cpuid.h" + +static void fma4_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + fma4_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run FMA4 test only if host has FMA4 support. */ + if (ecx & bit_FMA4) + do_test (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-fma-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-fma-2.c new file mode 100644 index 000000000..c15be1eda --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-fma-2.c @@ -0,0 +1,66 @@ +/* Test that the compiler properly optimizes floating point multiply + and add instructions into vfmaddss, vfmsubss, vfnmaddss, + vfnmsubss on FMA4 systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -funsafe-math-optimizations -mfma4" } */ + +extern void exit (int); + +float +flt_mul_add (float a, float c) +{ + return (a * a) + c; +} + +double +dbl_mul_add (double a, double c) +{ + return (a * a) + c; +} + +float +flt_mul_sub (float a, float c) +{ + return (a * a) - c; +} + +double +dbl_mul_sub (double a, double c) +{ + return (a * a) - c; +} + +float +flt_neg_mul_add (float a, float c) +{ + return (-(a * a)) + c; +} + +double +dbl_neg_mul_add (double a, double c) +{ + return (-(a * a)) + c; +} + +float f[10] = { 2, 3, 4 }; +double d[10] = { 2, 3, 4 }; + +int main () +{ + f[3] = flt_mul_add (f[0], f[2]); + f[4] = flt_mul_sub (f[0], f[2]); + f[5] = flt_neg_mul_add (f[0], f[2]); + + d[3] = dbl_mul_add (d[0], d[2]); + d[4] = dbl_mul_sub (d[0], d[2]); + d[5] = dbl_neg_mul_add (d[0], d[2]); + exit (0); +} + +/* { dg-final { scan-assembler "vfmaddss" } } */ +/* { dg-final { scan-assembler "vfmaddsd" } } */ +/* { dg-final { scan-assembler "vfmsubss" } } */ +/* { dg-final { scan-assembler "vfmsubsd" } } */ +/* { dg-final { scan-assembler "vfnmaddss" } } */ +/* { dg-final { scan-assembler "vfnmaddsd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-fma.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-fma.c new file mode 100644 index 000000000..63b35dc4b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-fma.c @@ -0,0 +1,82 @@ +/* Test that the compiler properly optimizes floating point multiply + and add instructions into vfmaddss, vfmsubss, vfnmaddss, + vfnmsubss on FMA4 systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfma4" } */ + +extern void exit (int); + +float +flt_mul_add (float a, float b, float c) +{ + return (a * b) + c; +} + +double +dbl_mul_add (double a, double b, double c) +{ + return (a * b) + c; +} + +float +flt_mul_sub (float a, float b, float c) +{ + return (a * b) - c; +} + +double +dbl_mul_sub (double a, double b, double c) +{ + return (a * b) - c; +} + +float +flt_neg_mul_add (float a, float b, float c) +{ + return (-(a * b)) + c; +} + +double +dbl_neg_mul_add (double a, double b, double c) +{ + return (-(a * b)) + c; +} + +float +flt_neg_mul_sub (float a, float b, float c) +{ + return (-(a * b)) - c; +} + +double +dbl_neg_mul_sub (double a, double b, double c) +{ + return (-(a * b)) - c; +} + +float f[10] = { 2, 3, 4 }; +double d[10] = { 2, 3, 4 }; + +int main () +{ + f[3] = flt_mul_add (f[0], f[1], f[2]); + f[4] = flt_mul_sub (f[0], f[1], f[2]); + f[5] = flt_neg_mul_add (f[0], f[1], f[2]); + f[6] = flt_neg_mul_sub (f[0], f[1], f[2]); + + d[3] = dbl_mul_add (d[0], d[1], d[2]); + d[4] = dbl_mul_sub (d[0], d[1], d[2]); + d[5] = dbl_neg_mul_add (d[0], d[1], d[2]); + d[6] = dbl_neg_mul_sub (d[0], d[1], d[2]); + exit (0); +} + +/* { dg-final { scan-assembler "vfmaddss" } } */ +/* { dg-final { scan-assembler "vfmaddsd" } } */ +/* { dg-final { scan-assembler "vfmsubss" } } */ +/* { dg-final { scan-assembler "vfmsubsd" } } */ +/* { dg-final { scan-assembler "vfnmaddss" } } */ +/* { dg-final { scan-assembler "vfnmaddsd" } } */ +/* { dg-final { scan-assembler "vfnmsubss" } } */ +/* { dg-final { scan-assembler "vfnmsubsd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-maccXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-maccXX.c new file mode 100644 index 000000000..4b4c00596 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-maccXX.c @@ -0,0 +1,136 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma4 } */ +/* { dg-options "-O0 -mfma4" } */ + +#include "fma4-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 20 + +union +{ + __m128 x[NUM]; + float f[NUM * 4]; + __m128d y[NUM]; + double d[NUM * 2]; +} dst, res, src1, src2, src3; + + +/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate + product is not rounded, only the addition is rounded. */ + +static void +init_maccps () +{ + int i; + for (i = 0; i < NUM * 4; i++) + { + src1.f[i] = i; + src2.f[i] = i + 10; + src3.f[i] = i + 20; + } +} + +static void +init_maccpd () +{ + int i; + for (i = 0; i < NUM * 4; i++) + { + src1.d[i] = i; + src2.d[i] = i + 10; + src3.d[i] = i + 20; + } +} + +static int +check_maccps () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 4; i = i + 4) + for (j = 0; j < 4; j++) + { + res.f[i + j] = (src1.f[i + j] * src2.f[i + j]) + src3.f[i + j]; + if (dst.f[i + j] != res.f[i + j]) + check_fails++; + } + return check_fails++; +} + +static int +check_maccpd () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 2; i = i + 2) + for (j = 0; j < 2; j++) + { + res.d[i + j] = (src1.d[i + j] * src2.d[i + j]) + src3.d[i + j]; + if (dst.d[i + j] != res.d[i + j]) + check_fails++; + } + return check_fails++; +} + + +static int +check_maccss () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 4; i= i + 4) + { + res.f[i] = (src1.f[i] * src2.f[i]) + src3.f[i]; + if (dst.f[i] != res.f[i]) + check_fails++; + } + return check_fails++; +} + +static int +check_maccsd () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 2; i = i + 2) + { + res.d[i] = (src1.d[i] * src2.d[i]) + src3.d[i]; + if (dst.d[i] != res.d[i]) + check_fails++; + } + return check_fails++; +} + +static void +fma4_test (void) +{ + int i; + + init_maccps (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_macc_ps (src1.x[i], src2.x[i], src3.x[i]); + + if (check_maccps ()) + abort (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_macc_ss (src1.x[i], src2.x[i], src3.x[i]); + + if (check_maccss ()) + abort (); + + init_maccpd (); + + for (i = 0; i < NUM; i++) + dst.y[i] = _mm_macc_pd (src1.y[i], src2.y[i], src3.y[i]); + + if (check_maccpd ()) + abort (); + + for (i = 0; i < NUM; i++) + dst.y[i] = _mm_macc_sd (src1.y[i], src2.y[i], src3.y[i]); + + if (check_maccsd ()) + abort (); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-msubXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-msubXX.c new file mode 100644 index 000000000..eed75580e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-msubXX.c @@ -0,0 +1,134 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma4 } */ +/* { dg-options "-O0 -mfma4" } */ + +#include "fma4-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 20 + +union +{ + __m128 x[NUM]; + float f[NUM * 4]; + __m128d y[NUM]; + double d[NUM * 2]; +} dst, res, src1, src2, src3; + +/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate + product is not rounded, only the addition is rounded. */ + +static void +init_msubps () +{ + int i; + for (i = 0; i < NUM * 4; i++) + { + src1.f[i] = i; + src2.f[i] = i + 10; + src3.f[i] = i + 20; + } +} + +static void +init_msubpd () +{ + int i; + for (i = 0; i < NUM * 4; i++) + { + src1.d[i] = i; + src2.d[i] = i + 10; + src3.d[i] = i + 20; + } +} + +static int +check_msubps () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 4; i = i + 4) + for (j = 0; j < 4; j++) + { + res.f[i + j] = (src1.f[i + j] * src2.f[i + j]) - src3.f[i + j]; + if (dst.f[i + j] != res.f[i + j]) + check_fails++; + } + return check_fails++; +} + +static int +check_msubpd () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 2; i = i + 2) + for (j = 0; j < 2; j++) + { + res.d[i + j] = (src1.d[i + j] * src2.d[i + j]) - src3.d[i + j]; + if (dst.d[i + j] != res.d[i + j]) + check_fails++; + } + return check_fails++; +} + + +static int +check_msubss () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 4; i = i + 4) + { + res.f[i] = (src1.f[i] * src2.f[i]) - src3.f[i]; + if (dst.f[i] != res.f[i]) + check_fails++; + } + return check_fails++; +} + +static int +check_msubsd () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 2; i = i + 2) + { + res.d[i] = (src1.d[i] * src2.d[i]) - src3.d[i]; + if (dst.d[i] != res.d[i]) + check_fails++; + } + return check_fails++; +} + +static void +fma4_test (void) +{ + int i; + + init_msubps (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_msub_ps (src1.x[i], src2.x[i], src3.x[i]); + + if (check_msubps ()) + abort (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_msub_ss (src1.x[i], src2.x[i], src3.x[i]); + + if (check_msubss ()) + abort (); + + init_msubpd (); + + for (i = 0; i < NUM; i++) + dst.y[i] = _mm_msub_pd (src1.y[i], src2.y[i], src3.y[i]); + + if (check_msubpd ()) + abort (); + + for (i = 0; i < NUM; i++) + dst.y[i] = _mm_msub_sd (src1.y[i], src2.y[i], src3.y[i]); + + if (check_msubsd ()) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-nmaccXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-nmaccXX.c new file mode 100644 index 000000000..9abf74604 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-nmaccXX.c @@ -0,0 +1,137 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma4 } */ +/* { dg-options "-O0 -mfma4" } */ + +#include "fma4-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 20 + +union +{ + __m128 x[NUM]; + float f[NUM * 4]; + __m128d y[NUM]; + double d[NUM * 2]; +} dst, res, src1, src2, src3; + +/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate + product is not rounded, only the addition is rounded. */ + +static void +init_nmaccps () +{ + int i; + for (i = 0; i < NUM * 4; i++) + { + src1.f[i] = i; + src2.f[i] = i + 10; + src3.f[i] = i + 20; + } +} + +static void +init_nmaccpd () +{ + int i; + for (i = 0; i < NUM * 4; i++) + { + src1.d[i] = i; + src2.d[i] = i + 10; + src3.d[i] = i + 20; + } +} + +static int +check_nmaccps () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 4; i = i + 4) + for (j = 0; j < 4; j++) + { + res.f[i + j] = - (src1.f[i + j] * src2.f[i + j]) + src3.f[i + j]; + if (dst.f[i + j] != res.f[i + j]) + check_fails++; + } + return check_fails++; +} + +static int +check_nmaccpd () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 2; i = i + 2) + for (j = 0; j < 2; j++) + { + res.d[i + j] = - (src1.d[i + j] * src2.d[i + j]) + src3.d[i + j]; + if (dst.d[i + j] != res.d[i + j]) + check_fails++; + } + return check_fails++; +} + + +static int +check_nmaccss () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 4; i = i + 4) + { + res.f[i] = - (src1.f[i] * src2.f[i]) + src3.f[i]; + if (dst.f[i] != res.f[i]) + check_fails++; + } + return check_fails++; +} + +static int +check_nmaccsd () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 2; i = i + 2) + { + res.d[i] = - (src1.d[i] * src2.d[i]) + src3.d[i]; + if (dst.d[i] != res.d[i]) + check_fails++; + } + return check_fails++; +} + +static void +fma4_test (void) +{ + int i; + + init_nmaccps (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_nmacc_ps (src1.x[i], src2.x[i], src3.x[i]); + + if (check_nmaccps ()) + abort (); + + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_nmacc_ss (src1.x[i], src2.x[i], src3.x[i]); + + if (check_nmaccss ()) + abort (); + + init_nmaccpd (); + + for (i = 0; i < NUM; i++) + dst.y[i] = _mm_nmacc_pd (src1.y[i], src2.y[i], src3.y[i]); + + if (check_nmaccpd ()) + abort (); + + + for (i = 0; i < NUM; i++) + dst.y[i] = _mm_nmacc_sd (src1.y[i], src2.y[i], src3.y[i]); + + if (check_nmaccsd ()) + abort (); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-nmsubXX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-nmsubXX.c new file mode 100644 index 000000000..85fbecddb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-nmsubXX.c @@ -0,0 +1,137 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma4 } */ +/* { dg-options "-O0 -mfma4" } */ + +#include "fma4-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 20 + +union +{ + __m128 x[NUM]; + float f[NUM * 4]; + __m128d y[NUM]; + double d[NUM * 2]; +} dst, res, src1, src2, src3; + +/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate + product is not rounded, only the addition is rounded. */ + +static void +init_nmsubps () +{ + int i; + for (i = 0; i < NUM * 4; i++) + { + src1.f[i] = i; + src2.f[i] = i + 10; + src3.f[i] = i + 20; + } +} + +static void +init_nmsubpd () +{ + int i; + for (i = 0; i < NUM * 4; i++) + { + src1.d[i] = i; + src2.d[i] = i + 10; + src3.d[i] = i + 20; + } +} + +static int +check_nmsubps () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 4; i = i + 4) + for (j = 0; j < 4; j++) + { + res.f[i + j] = - (src1.f[i + j] * src2.f[i + j]) - src3.f[i + j]; + if (dst.f[i + j] != res.f[i + j]) + check_fails++; + } + return check_fails++; +} + +static int +check_nmsubpd () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 2; i = i + 2) + for (j = 0; j < 2; j++) + { + res.d[i + j] = - (src1.d[i + j] * src2.d[i + j]) - src3.d[i + j]; + if (dst.d[i + j] != res.d[i + j]) + check_fails++; + } + return check_fails++; +} + + +static int +check_nmsubss () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 4; i = i + 4) + { + res.f[i] = - (src1.f[i] * src2.f[i]) - src3.f[i]; + if (dst.f[i] != res.f[i]) + check_fails++; + } + return check_fails++; +} + +static int +check_nmsubsd () +{ + int i, j, check_fails = 0; + for (i = 0; i < NUM * 2; i = i + 2) + { + res.d[i] = - (src1.d[i] * src2.d[i]) - src3.d[i]; + if (dst.d[i] != res.d[i]) + check_fails++; + } + return check_fails++; +} + +static void +fma4_test (void) +{ + int i; + + init_nmsubps (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_nmsub_ps (src1.x[i], src2.x[i], src3.x[i]); + + if (check_nmsubps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], &src3.f[i * 4])) + abort (); + + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_nmsub_ss (src1.x[i], src2.x[i], src3.x[i]); + + if (check_nmsubss (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], &src3.f[i * 4])) + abort (); + + init_nmsubpd (); + + for (i = 0; i < NUM; i++) + dst.y[i] = _mm_nmsub_pd (src1.y[i], src2.y[i], src3.y[i]); + + if (check_nmsubpd (&dst.y[i], &src1.d[i * 2], &src2.d[i * 2], &src3.d[i * 2])) + abort (); + + + for (i = 0; i < NUM; i++) + dst.y[i] = _mm_nmsub_sd (src1.y[i], src2.y[i], src3.y[i]); + + if (check_nmsubsd (&dst.y[i], &src1.d[i * 2], &src2.d[i * 2], &src3.d[i * 2])) + abort (); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-vector-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-vector-2.c new file mode 100644 index 000000000..d8b0d0813 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-vector-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic" } */ + +float r[256], s[256]; +float x[256]; +float y[256]; +float z[256]; + +void foo (void) +{ + int i; + for (i = 0; i < 256; ++i) + { + r[i] = x[i] * y[i] - z[i]; + s[i] = x[i] * y[i] + z[i]; + } +} + +/* { dg-final { scan-assembler "vfmaddps" } } */ +/* { dg-final { scan-assembler "vfmsubps" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-vector.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-vector.c new file mode 100644 index 000000000..db5ffdd33 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma4-vector.c @@ -0,0 +1,92 @@ +/* Test that the compiler properly optimizes floating point multiply and add + instructions vector into vfmaddps on FMA4 systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic" } */ + +extern void exit (int); + +typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128 f_align; + __m128d d_align; + float f[SIZE]; + double d[SIZE]; +} a, b, c, d; + +void +flt_mul_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.f[i] = (b.f[i] * c.f[i]) + d.f[i]; +} + +void +dbl_mul_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.d[i] = (b.d[i] * c.d[i]) + d.d[i]; +} + +void +flt_mul_sub (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.f[i] = (b.f[i] * c.f[i]) - d.f[i]; +} + +void +dbl_mul_sub (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.d[i] = (b.d[i] * c.d[i]) - d.d[i]; +} + +void +flt_neg_mul_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.f[i] = (-(b.f[i] * c.f[i])) + d.f[i]; +} + +void +dbl_neg_mul_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.d[i] = (-(b.d[i] * c.d[i])) + d.d[i]; +} + +int main () +{ + flt_mul_add (); + flt_mul_sub (); + flt_neg_mul_add (); + + dbl_mul_add (); + dbl_mul_sub (); + dbl_neg_mul_add (); + exit (0); +} + +/* { dg-final { scan-assembler "vfmaddps" } } */ +/* { dg-final { scan-assembler "vfmaddpd" } } */ +/* { dg-final { scan-assembler "vfmsubps" } } */ +/* { dg-final { scan-assembler "vfmsubpd" } } */ +/* { dg-final { scan-assembler "vfnmaddps" } } */ +/* { dg-final { scan-assembler "vfnmaddpd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_1.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_1.h new file mode 100644 index 000000000..72d737394 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_1.h @@ -0,0 +1,101 @@ + +#ifndef fma_1 +#define fma_1 + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * a - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * a + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * a - b; +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_2.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_2.h new file mode 100644 index 000000000..c5d38d19a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_2.h @@ -0,0 +1,101 @@ + +#ifndef fma_2 +#define fma_2 + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * a - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * a + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * a - c; +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_3.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_3.h new file mode 100644 index 000000000..efa88b5d9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_3.h @@ -0,0 +1,101 @@ + +#ifndef fma_3 +#define fma_3 + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * b - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * b + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * b - a; +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_4.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_4.h new file mode 100644 index 000000000..9fbb3efdf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_4.h @@ -0,0 +1,101 @@ + +#ifndef fma_4 +#define fma_4 + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * b - c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * b + c; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * b - c; +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_5.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_5.h new file mode 100644 index 000000000..3409db8f4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_5.h @@ -0,0 +1,101 @@ + +#ifndef fma_5 +#define fma_5 + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * c - a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * c + a; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * c - a; +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_6.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_6.h new file mode 100644 index 000000000..a6bb4b0cd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_6.h @@ -0,0 +1,101 @@ + +#ifndef fma_6 +#define fma_6 + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) + c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) + c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return ((a * b) - c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -((a * b) - c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) + c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) + c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c) +{ + return (-(a * b) - c) * c - b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * c + b; +} + +TYPE __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c) +{ + return -(-(a * b) - c) * c - b; +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_1.c new file mode 100644 index 000000000..c3aa3e83c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_1.h" + +/* { dg-final { scan-assembler-times "vfmadd132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231sd" 4 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_2.c new file mode 100644 index 000000000..843eff0a1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_2.h" + +/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_3.c new file mode 100644 index 000000000..ac69684fe --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_3.h" + +/* { dg-final { scan-assembler-times "vfmadd132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231sd" 4 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_4.c new file mode 100644 index 000000000..51fc111ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_4.h" + +/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_5.c new file mode 100644 index 000000000..3eca38c14 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_5.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_5.h" + +/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_6.c new file mode 100644 index 000000000..7b75a224f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_double_6.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_6.h" + +/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_1.c new file mode 100644 index 000000000..67b1f3fe7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_1.h" + +/* { dg-final { scan-assembler-times "vfmadd132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231ss" 4 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_2.c new file mode 100644 index 000000000..a54644d0c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_2.h" + +/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_3.c new file mode 100644 index 000000000..afb88b607 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_3.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_3.h" + +/* { dg-final { scan-assembler-times "vfmadd132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231ss" 4 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_4.c new file mode 100644 index 000000000..d9689d9a7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_4.h" + +/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_5.c new file mode 100644 index 000000000..cb067ca4a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_5.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_5.h" + +/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_6.c new file mode 100644 index 000000000..c75807368 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_float_6.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_6.h" + +/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_main.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_main.h new file mode 100644 index 000000000..24464ab50 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_main.h @@ -0,0 +1,117 @@ + +#ifndef fma_main +#define fma_main + +#if DEBUG +#include <stdio.h> +#endif + +TYPE m1[32] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 + }; +TYPE m2[32] = { + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, + 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 + }; +TYPE m3[32] = { + 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, + 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 + }; +TYPE m4[32]; +int test_fails = 0; + +void +compare_result(char * title, TYPE *res) +{ + int i; + int good = 1; + for (i =0; i < 32; i++) + if (m4[i] != res[i]) + { + if (good) + { +#if DEBUG + printf ("!!!! %s miscompare\n", title); +#endif + good = 0; + } +#if DEBUG + printf ("res[%d] = %d, must be %d\n", i, (int)res[i], (int) m4[i]); +#endif + } + if (!good) + test_fails = 1; +} + +static void fma_test () +{ + int i; + for (i=0; i <32; i++) + m4[i] = test_noneg_add_noneg_add (m1[i], m2[i], m3[i]); + compare_result ("test0000", res_test0000); + + for (i=0; i <32; i++) + m4[i] = test_noneg_add_noneg_sub (m1[i], m2[i], m3[i]); + compare_result ("test0001", res_test0001); + + for (i=0; i <32; i++) + m4[i] = test_noneg_add_neg_add (m1[i], m2[i], m3[i]); + compare_result ("test0010", res_test0010); + + for (i=0; i <32; i++) + m4[i] = test_noneg_add_neg_sub (m1[i], m2[i], m3[i]); + compare_result ("test0011", res_test0011); + + for (i=0; i <32; i++) + m4[i] = test_noneg_sub_noneg_add (m1[i], m2[i], m3[i]); + compare_result ("test0100", res_test0100); + + for (i=0; i <32; i++) + m4[i] = test_noneg_sub_noneg_sub (m1[i], m2[i], m3[i]); + compare_result ("test0101", res_test0101); + + for (i=0; i <32; i++) + m4[i] = test_noneg_sub_neg_add (m1[i], m2[i], m3[i]); + compare_result ("test0110", res_test0110); + + for (i=0; i <32; i++) + m4[i] = test_noneg_sub_neg_sub (m1[i], m2[i], m3[i]); + compare_result ("test0111", res_test0111); + + for (i=0; i <32; i++) + m4[i] = test_neg_add_noneg_add (m1[i], m2[i], m3[i]); + compare_result ("test1000", res_test1000); + + for (i=0; i <32; i++) + m4[i] = test_neg_add_noneg_sub (m1[i], m2[i], m3[i]); + compare_result ("test1001", res_test1001); + + for (i=0; i <32; i++) + m4[i] = test_neg_add_neg_add (m1[i], m2[i], m3[i]); + compare_result ("test1010", res_test1010); + + for (i=0; i <32; i++) + m4[i] = test_neg_add_neg_sub (m1[i], m2[i], m3[i]); + compare_result ("test1011", res_test1011); + + for (i=0; i <32; i++) + m4[i] = test_neg_sub_noneg_add (m1[i], m2[i], m3[i]); + compare_result ("test1100", res_test1100); + + for (i=0; i <32; i++) + m4[i] = test_neg_sub_noneg_sub (m1[i], m2[i], m3[i]); + compare_result ("test1101", res_test1101); + + for (i=0; i <32; i++) + m4[i] = test_neg_sub_neg_add (m1[i], m2[i], m3[i]); + compare_result ("test1110", res_test1110); + + for (i=0; i <32; i++) + m4[i] = test_neg_sub_neg_sub (m1[i], m2[i], m3[i]); + compare_result ("test1111", res_test1111); + + if (test_fails) abort (); +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_1.c new file mode 100644 index 000000000..a2f2aae9e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_1.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_1.h" + +#include "fma_run_double_results_1.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_2.c new file mode 100644 index 000000000..a389473a8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_2.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_2.h" + +#include "fma_run_double_results_2.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_3.c new file mode 100644 index 000000000..7b9d6273b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_3.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_3.h" + +#include "fma_run_double_results_3.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_4.c new file mode 100644 index 000000000..1c0456dba --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_4.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_4.h" + +#include "fma_run_double_results_4.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_5.c new file mode 100644 index 000000000..6c09f0bb8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_5.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_5.h" + +#include "fma_run_double_results_5.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_6.c new file mode 100644 index 000000000..32e51bf31 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_6.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "fma_6.h" + +#include "fma_run_double_results_6.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_1.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_1.h new file mode 100644 index 000000000..27f325b86 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_1.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_double_results_1 +#define fma_run_double_results_1 + +TYPE res_test0000[32] = { + 7, 23, 55, 109, 191, 307, 463, 665, 919, 1231, 1607, 2053, 2575, 3179, 3871, 4657, 5543, 6535, 7639, 8861, 10207, 11683, 13295, 15049, 16951, 19007, 21223, 23605, 26159, 28891, 31807, 34913 +}; +TYPE res_test0001[32] = { + 3, 17, 47, 99, 179, 293, 447, 647, 899, 1209, 1583, 2027, 2547, 3149, 3839, 4623, 5507, 6497, 7599, 8819, 10163, 11637, 13247, 14999, 16899, 18953, 21167, 23547, 26099, 28829, 31743, 34847 +}; +TYPE res_test0010[32] = { + -3, -17, -47, -99, -179, -293, -447, -647, -899, -1209, -1583, -2027, -2547, -3149, -3839, -4623, -5507, -6497, -7599, -8819, -10163, -11637, -13247, -14999, -16899, -18953, -21167, -23547, -26099, -28829, -31743, -34847 +}; +TYPE res_test0011[32] = { + -7, -23, -55, -109, -191, -307, -463, -665, -919, -1231, -1607, -2053, -2575, -3179, -3871, -4657, -5543, -6535, -7639, -8861, -10207, -11683, -13295, -15049, -16951, -19007, -21223, -23605, -26159, -28891, -31807, -34913 +}; +TYPE res_test0100[32] = { + 1, 7, 25, 61, 121, 211, 337, 505, 721, 991, 1321, 1717, 2185, 2731, 3361, 4081, 4897, 5815, 6841, 7981, 9241, 10627, 12145, 13801, 15601, 17551, 19657, 21925, 24361, 26971, 29761, 32737 +}; +TYPE res_test0101[32] = { + -3, 1, 17, 51, 109, 197, 321, 487, 701, 969, 1297, 1691, 2157, 2701, 3329, 4047, 4861, 5777, 6801, 7939, 9197, 10581, 12097, 13751, 15549, 17497, 19601, 21867, 24301, 26909, 29697, 32671 +}; +TYPE res_test0110[32] = { + 3, -1, -17, -51, -109, -197, -321, -487, -701, -969, -1297, -1691, -2157, -2701, -3329, -4047, -4861, -5777, -6801, -7939, -9197, -10581, -12097, -13751, -15549, -17497, -19601, -21867, -24301, -26909, -29697, -32671 +}; +TYPE res_test0111[32] = { + -1, -7, -25, -61, -121, -211, -337, -505, -721, -991, -1321, -1717, -2185, -2731, -3361, -4081, -4897, -5815, -6841, -7981, -9241, -10627, -12145, -13801, -15601, -17551, -19657, -21925, -24361, -26971, -29761, -32737 +}; +TYPE res_test1000[32] = { + 3, -1, -17, -51, -109, -197, -321, -487, -701, -969, -1297, -1691, -2157, -2701, -3329, -4047, -4861, -5777, -6801, -7939, -9197, -10581, -12097, -13751, -15549, -17497, -19601, -21867, -24301, -26909, -29697, -32671 +}; +TYPE res_test1001[32] = { + -1, -7, -25, -61, -121, -211, -337, -505, -721, -991, -1321, -1717, -2185, -2731, -3361, -4081, -4897, -5815, -6841, -7981, -9241, -10627, -12145, -13801, -15601, -17551, -19657, -21925, -24361, -26971, -29761, -32737 +}; +TYPE res_test1010[32] = { + 1, 7, 25, 61, 121, 211, 337, 505, 721, 991, 1321, 1717, 2185, 2731, 3361, 4081, 4897, 5815, 6841, 7981, 9241, 10627, 12145, 13801, 15601, 17551, 19657, 21925, 24361, 26971, 29761, 32737 +}; +TYPE res_test1011[32] = { + -3, 1, 17, 51, 109, 197, 321, 487, 701, 969, 1297, 1691, 2157, 2701, 3329, 4047, 4861, 5777, 6801, 7939, 9197, 10581, 12097, 13751, 15549, 17497, 19601, 21867, 24301, 26909, 29697, 32671 +}; +TYPE res_test1100[32] = { + -3, -17, -47, -99, -179, -293, -447, -647, -899, -1209, -1583, -2027, -2547, -3149, -3839, -4623, -5507, -6497, -7599, -8819, -10163, -11637, -13247, -14999, -16899, -18953, -21167, -23547, -26099, -28829, -31743, -34847 +}; +TYPE res_test1101[32] = { + -7, -23, -55, -109, -191, -307, -463, -665, -919, -1231, -1607, -2053, -2575, -3179, -3871, -4657, -5543, -6535, -7639, -8861, -10207, -11683, -13295, -15049, -16951, -19007, -21223, -23605, -26159, -28891, -31807, -34913 +}; +TYPE res_test1110[32] = { + 7, 23, 55, 109, 191, 307, 463, 665, 919, 1231, 1607, 2053, 2575, 3179, 3871, 4657, 5543, 6535, 7639, 8861, 10207, 11683, 13295, 15049, 16951, 19007, 21223, 23605, 26159, 28891, 31807, 34913 +}; +TYPE res_test1111[32] = { + 3, 17, 47, 99, 179, 293, 447, 647, 899, 1209, 1583, 2027, 2547, 3149, 3839, 4623, 5507, 6497, 7599, 8819, 10163, 11637, 13247, 14999, 16899, 18953, 21167, 23547, 26099, 28829, 31743, 34847 +}; + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_2.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_2.h new file mode 100644 index 000000000..f9327ce65 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_2.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_double_results_2 +#define fma_run_double_results_2 + +TYPE res_test0000[32] = { + 8, 24, 56, 110, 192, 308, 464, 666, 920, 1232, 1608, 2054, 2576, 3180, 3872, 4658, 5544, 6536, 7640, 8862, 10208, 11684, 13296, 15050, 16952, 19008, 21224, 23606, 26160, 28892, 31808, 34914 +}; +TYPE res_test0001[32] = { + 2, 16, 46, 98, 178, 292, 446, 646, 898, 1208, 1582, 2026, 2546, 3148, 3838, 4622, 5506, 6496, 7598, 8818, 10162, 11636, 13246, 14998, 16898, 18952, 21166, 23546, 26098, 28828, 31742, 34846 +}; +TYPE res_test0010[32] = { + -2, -16, -46, -98, -178, -292, -446, -646, -898, -1208, -1582, -2026, -2546, -3148, -3838, -4622, -5506, -6496, -7598, -8818, -10162, -11636, -13246, -14998, -16898, -18952, -21166, -23546, -26098, -28828, -31742, -34846 +}; +TYPE res_test0011[32] = { + -8, -24, -56, -110, -192, -308, -464, -666, -920, -1232, -1608, -2054, -2576, -3180, -3872, -4658, -5544, -6536, -7640, -8862, -10208, -11684, -13296, -15050, -16952, -19008, -21224, -23606, -26160, -28892, -31808, -34914 +}; +TYPE res_test0100[32] = { + 2, 8, 26, 62, 122, 212, 338, 506, 722, 992, 1322, 1718, 2186, 2732, 3362, 4082, 4898, 5816, 6842, 7982, 9242, 10628, 12146, 13802, 15602, 17552, 19658, 21926, 24362, 26972, 29762, 32738 +}; +TYPE res_test0101[32] = { + -4, 0, 16, 50, 108, 196, 320, 486, 700, 968, 1296, 1690, 2156, 2700, 3328, 4046, 4860, 5776, 6800, 7938, 9196, 10580, 12096, 13750, 15548, 17496, 19600, 21866, 24300, 26908, 29696, 32670 +}; +TYPE res_test0110[32] = { + 4, 0, -16, -50, -108, -196, -320, -486, -700, -968, -1296, -1690, -2156, -2700, -3328, -4046, -4860, -5776, -6800, -7938, -9196, -10580, -12096, -13750, -15548, -17496, -19600, -21866, -24300, -26908, -29696, -32670 +}; +TYPE res_test0111[32] = { + -2, -8, -26, -62, -122, -212, -338, -506, -722, -992, -1322, -1718, -2186, -2732, -3362, -4082, -4898, -5816, -6842, -7982, -9242, -10628, -12146, -13802, -15602, -17552, -19658, -21926, -24362, -26972, -29762, -32738 +}; +TYPE res_test1000[32] = { + 4, 0, -16, -50, -108, -196, -320, -486, -700, -968, -1296, -1690, -2156, -2700, -3328, -4046, -4860, -5776, -6800, -7938, -9196, -10580, -12096, -13750, -15548, -17496, -19600, -21866, -24300, -26908, -29696, -32670 +}; +TYPE res_test1001[32] = { + -2, -8, -26, -62, -122, -212, -338, -506, -722, -992, -1322, -1718, -2186, -2732, -3362, -4082, -4898, -5816, -6842, -7982, -9242, -10628, -12146, -13802, -15602, -17552, -19658, -21926, -24362, -26972, -29762, -32738 +}; +TYPE res_test1010[32] = { + 2, 8, 26, 62, 122, 212, 338, 506, 722, 992, 1322, 1718, 2186, 2732, 3362, 4082, 4898, 5816, 6842, 7982, 9242, 10628, 12146, 13802, 15602, 17552, 19658, 21926, 24362, 26972, 29762, 32738 +}; +TYPE res_test1011[32] = { + -4, 0, 16, 50, 108, 196, 320, 486, 700, 968, 1296, 1690, 2156, 2700, 3328, 4046, 4860, 5776, 6800, 7938, 9196, 10580, 12096, 13750, 15548, 17496, 19600, 21866, 24300, 26908, 29696, 32670 +}; +TYPE res_test1100[32] = { + -2, -16, -46, -98, -178, -292, -446, -646, -898, -1208, -1582, -2026, -2546, -3148, -3838, -4622, -5506, -6496, -7598, -8818, -10162, -11636, -13246, -14998, -16898, -18952, -21166, -23546, -26098, -28828, -31742, -34846 +}; +TYPE res_test1101[32] = { + -8, -24, -56, -110, -192, -308, -464, -666, -920, -1232, -1608, -2054, -2576, -3180, -3872, -4658, -5544, -6536, -7640, -8862, -10208, -11684, -13296, -15050, -16952, -19008, -21224, -23606, -26160, -28892, -31808, -34914 +}; +TYPE res_test1110[32] = { + 8, 24, 56, 110, 192, 308, 464, 666, 920, 1232, 1608, 2054, 2576, 3180, 3872, 4658, 5544, 6536, 7640, 8862, 10208, 11684, 13296, 15050, 16952, 19008, 21224, 23606, 26160, 28892, 31808, 34914 +}; +TYPE res_test1111[32] = { + 2, 16, 46, 98, 178, 292, 446, 646, 898, 1208, 1582, 2026, 2546, 3148, 3838, 4622, 5506, 6496, 7598, 8818, 10162, 11636, 13246, 14998, 16898, 18952, 21166, 23546, 26098, 28828, 31742, 34846 +}; + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_3.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_3.h new file mode 100644 index 000000000..44cf82735 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_3.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_double_results_3 +#define fma_run_double_results_3 + +TYPE res_test0000[32] = { + 11, 32, 71, 134, 227, 356, 527, 746, 1019, 1352, 1751, 2222, 2771, 3404, 4127, 4946, 5867, 6896, 8039, 9302, 10691, 12212, 13871, 15674, 17627, 19736, 22007, 24446, 27059, 29852, 32831, 36002 +}; +TYPE res_test0001[32] = { + 9, 28, 65, 126, 217, 344, 513, 730, 1001, 1332, 1729, 2198, 2745, 3376, 4097, 4914, 5833, 6860, 8001, 9262, 10649, 12168, 13825, 15626, 17577, 19684, 21953, 24390, 27001, 29792, 32769, 35938 +}; +TYPE res_test0010[32] = { + -9, -28, -65, -126, -217, -344, -513, -730, -1001, -1332, -1729, -2198, -2745, -3376, -4097, -4914, -5833, -6860, -8001, -9262, -10649, -12168, -13825, -15626, -17577, -19684, -21953, -24390, -27001, -29792, -32769, -35938 +}; +TYPE res_test0011[32] = { + -11, -32, -71, -134, -227, -356, -527, -746, -1019, -1352, -1751, -2222, -2771, -3404, -4127, -4946, -5867, -6896, -8039, -9302, -10691, -12212, -13871, -15674, -17627, -19736, -22007, -24446, -27059, -29852, -32831, -36002 +}; +TYPE res_test0100[32] = { + -1, 8, 31, 74, 143, 244, 383, 566, 799, 1088, 1439, 1858, 2351, 2924, 3583, 4334, 5183, 6136, 7199, 8378, 9679, 11108, 12671, 14374, 16223, 18224, 20383, 22706, 25199, 27868, 30719, 33758 +}; +TYPE res_test0101[32] = { + -3, 4, 25, 66, 133, 232, 369, 550, 781, 1068, 1417, 1834, 2325, 2896, 3553, 4302, 5149, 6100, 7161, 8338, 9637, 11064, 12625, 14326, 16173, 18172, 20329, 22650, 25141, 27808, 30657, 33694 +}; +TYPE res_test0110[32] = { + 3, -4, -25, -66, -133, -232, -369, -550, -781, -1068, -1417, -1834, -2325, -2896, -3553, -4302, -5149, -6100, -7161, -8338, -9637, -11064, -12625, -14326, -16173, -18172, -20329, -22650, -25141, -27808, -30657, -33694 +}; +TYPE res_test0111[32] = { + 1, -8, -31, -74, -143, -244, -383, -566, -799, -1088, -1439, -1858, -2351, -2924, -3583, -4334, -5183, -6136, -7199, -8378, -9679, -11108, -12671, -14374, -16223, -18224, -20383, -22706, -25199, -27868, -30719, -33758 +}; +TYPE res_test1000[32] = { + 3, -4, -25, -66, -133, -232, -369, -550, -781, -1068, -1417, -1834, -2325, -2896, -3553, -4302, -5149, -6100, -7161, -8338, -9637, -11064, -12625, -14326, -16173, -18172, -20329, -22650, -25141, -27808, -30657, -33694 +}; +TYPE res_test1001[32] = { + 1, -8, -31, -74, -143, -244, -383, -566, -799, -1088, -1439, -1858, -2351, -2924, -3583, -4334, -5183, -6136, -7199, -8378, -9679, -11108, -12671, -14374, -16223, -18224, -20383, -22706, -25199, -27868, -30719, -33758 +}; +TYPE res_test1010[32] = { + -1, 8, 31, 74, 143, 244, 383, 566, 799, 1088, 1439, 1858, 2351, 2924, 3583, 4334, 5183, 6136, 7199, 8378, 9679, 11108, 12671, 14374, 16223, 18224, 20383, 22706, 25199, 27868, 30719, 33758 +}; +TYPE res_test1011[32] = { + -3, 4, 25, 66, 133, 232, 369, 550, 781, 1068, 1417, 1834, 2325, 2896, 3553, 4302, 5149, 6100, 7161, 8338, 9637, 11064, 12625, 14326, 16173, 18172, 20329, 22650, 25141, 27808, 30657, 33694 +}; +TYPE res_test1100[32] = { + -9, -28, -65, -126, -217, -344, -513, -730, -1001, -1332, -1729, -2198, -2745, -3376, -4097, -4914, -5833, -6860, -8001, -9262, -10649, -12168, -13825, -15626, -17577, -19684, -21953, -24390, -27001, -29792, -32769, -35938 +}; +TYPE res_test1101[32] = { + -11, -32, -71, -134, -227, -356, -527, -746, -1019, -1352, -1751, -2222, -2771, -3404, -4127, -4946, -5867, -6896, -8039, -9302, -10691, -12212, -13871, -15674, -17627, -19736, -22007, -24446, -27059, -29852, -32831, -36002 +}; +TYPE res_test1110[32] = { + 11, 32, 71, 134, 227, 356, 527, 746, 1019, 1352, 1751, 2222, 2771, 3404, 4127, 4946, 5867, 6896, 8039, 9302, 10691, 12212, 13871, 15674, 17627, 19736, 22007, 24446, 27059, 29852, 32831, 36002 +}; +TYPE res_test1111[32] = { + 9, 28, 65, 126, 217, 344, 513, 730, 1001, 1332, 1729, 2198, 2745, 3376, 4097, 4914, 5833, 6860, 8001, 9262, 10649, 12168, 13825, 15626, 17577, 19684, 21953, 24390, 27001, 29792, 32769, 35938 +}; + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_4.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_4.h new file mode 100644 index 000000000..0b7f85775 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_4.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_double_results_4 +#define fma_run_double_results_4 + +TYPE res_test0000[32] = { + 13, 34, 73, 136, 229, 358, 529, 748, 1021, 1354, 1753, 2224, 2773, 3406, 4129, 4948, 5869, 6898, 8041, 9304, 10693, 12214, 13873, 15676, 17629, 19738, 22009, 24448, 27061, 29854, 32833, 36004 +}; +TYPE res_test0001[32] = { + 7, 26, 63, 124, 215, 342, 511, 728, 999, 1330, 1727, 2196, 2743, 3374, 4095, 4912, 5831, 6858, 7999, 9260, 10647, 12166, 13823, 15624, 17575, 19682, 21951, 24388, 26999, 29790, 32767, 35936 +}; +TYPE res_test0010[32] = { + -7, -26, -63, -124, -215, -342, -511, -728, -999, -1330, -1727, -2196, -2743, -3374, -4095, -4912, -5831, -6858, -7999, -9260, -10647, -12166, -13823, -15624, -17575, -19682, -21951, -24388, -26999, -29790, -32767, -35936 +}; +TYPE res_test0011[32] = { + -13, -34, -73, -136, -229, -358, -529, -748, -1021, -1354, -1753, -2224, -2773, -3406, -4129, -4948, -5869, -6898, -8041, -9304, -10693, -12214, -13873, -15676, -17629, -19738, -22009, -24448, -27061, -29854, -32833, -36004 +}; +TYPE res_test0100[32] = { + 1, 10, 33, 76, 145, 246, 385, 568, 801, 1090, 1441, 1860, 2353, 2926, 3585, 4336, 5185, 6138, 7201, 8380, 9681, 11110, 12673, 14376, 16225, 18226, 20385, 22708, 25201, 27870, 30721, 33760 +}; +TYPE res_test0101[32] = { + -5, 2, 23, 64, 131, 230, 367, 548, 779, 1066, 1415, 1832, 2323, 2894, 3551, 4300, 5147, 6098, 7159, 8336, 9635, 11062, 12623, 14324, 16171, 18170, 20327, 22648, 25139, 27806, 30655, 33692 +}; +TYPE res_test0110[32] = { + 5, -2, -23, -64, -131, -230, -367, -548, -779, -1066, -1415, -1832, -2323, -2894, -3551, -4300, -5147, -6098, -7159, -8336, -9635, -11062, -12623, -14324, -16171, -18170, -20327, -22648, -25139, -27806, -30655, -33692 +}; +TYPE res_test0111[32] = { + -1, -10, -33, -76, -145, -246, -385, -568, -801, -1090, -1441, -1860, -2353, -2926, -3585, -4336, -5185, -6138, -7201, -8380, -9681, -11110, -12673, -14376, -16225, -18226, -20385, -22708, -25201, -27870, -30721, -33760 +}; +TYPE res_test1000[32] = { + 5, -2, -23, -64, -131, -230, -367, -548, -779, -1066, -1415, -1832, -2323, -2894, -3551, -4300, -5147, -6098, -7159, -8336, -9635, -11062, -12623, -14324, -16171, -18170, -20327, -22648, -25139, -27806, -30655, -33692 +}; +TYPE res_test1001[32] = { + -1, -10, -33, -76, -145, -246, -385, -568, -801, -1090, -1441, -1860, -2353, -2926, -3585, -4336, -5185, -6138, -7201, -8380, -9681, -11110, -12673, -14376, -16225, -18226, -20385, -22708, -25201, -27870, -30721, -33760 +}; +TYPE res_test1010[32] = { + 1, 10, 33, 76, 145, 246, 385, 568, 801, 1090, 1441, 1860, 2353, 2926, 3585, 4336, 5185, 6138, 7201, 8380, 9681, 11110, 12673, 14376, 16225, 18226, 20385, 22708, 25201, 27870, 30721, 33760 +}; +TYPE res_test1011[32] = { + -5, 2, 23, 64, 131, 230, 367, 548, 779, 1066, 1415, 1832, 2323, 2894, 3551, 4300, 5147, 6098, 7159, 8336, 9635, 11062, 12623, 14324, 16171, 18170, 20327, 22648, 25139, 27806, 30655, 33692 +}; +TYPE res_test1100[32] = { + -7, -26, -63, -124, -215, -342, -511, -728, -999, -1330, -1727, -2196, -2743, -3374, -4095, -4912, -5831, -6858, -7999, -9260, -10647, -12166, -13823, -15624, -17575, -19682, -21951, -24388, -26999, -29790, -32767, -35936 +}; +TYPE res_test1101[32] = { + -13, -34, -73, -136, -229, -358, -529, -748, -1021, -1354, -1753, -2224, -2773, -3406, -4129, -4948, -5869, -6898, -8041, -9304, -10693, -12214, -13873, -15676, -17629, -19738, -22009, -24448, -27061, -29854, -32833, -36004 +}; +TYPE res_test1110[32] = { + 13, 34, 73, 136, 229, 358, 529, 748, 1021, 1354, 1753, 2224, 2773, 3406, 4129, 4948, 5869, 6898, 8041, 9304, 10693, 12214, 13873, 15676, 17629, 19738, 22009, 24448, 27061, 29854, 32833, 36004 +}; +TYPE res_test1111[32] = { + 7, 26, 63, 124, 215, 342, 511, 728, 999, 1330, 1727, 2196, 2743, 3374, 4095, 4912, 5831, 6858, 7999, 9260, 10647, 12166, 13823, 15624, 17575, 19682, 21951, 24388, 26999, 29790, 32767, 35936 +}; + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_5.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_5.h new file mode 100644 index 000000000..0f96cad01 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_5.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_double_results_5 +#define fma_run_double_results_5 + +TYPE res_test0000[32] = { + 16, 42, 88, 160, 264, 406, 592, 828, 1120, 1474, 1896, 2392, 2968, 3630, 4384, 5236, 6192, 7258, 8440, 9744, 11176, 12742, 14448, 16300, 18304, 20466, 22792, 25288, 27960, 30814, 33856, 37092 +}; +TYPE res_test0001[32] = { + 14, 38, 82, 152, 254, 394, 578, 812, 1102, 1454, 1874, 2368, 2942, 3602, 4354, 5204, 6158, 7222, 8402, 9704, 11134, 12698, 14402, 16252, 18254, 20414, 22738, 25232, 27902, 30754, 33794, 37028 +}; +TYPE res_test0010[32] = { + -14, -38, -82, -152, -254, -394, -578, -812, -1102, -1454, -1874, -2368, -2942, -3602, -4354, -5204, -6158, -7222, -8402, -9704, -11134, -12698, -14402, -16252, -18254, -20414, -22738, -25232, -27902, -30754, -33794, -37028 +}; +TYPE res_test0011[32] = { + -16, -42, -88, -160, -264, -406, -592, -828, -1120, -1474, -1896, -2392, -2968, -3630, -4384, -5236, -6192, -7258, -8440, -9744, -11176, -12742, -14448, -16300, -18304, -20466, -22792, -25288, -27960, -30814, -33856, -37092 +}; +TYPE res_test0100[32] = { + -2, 10, 38, 88, 166, 278, 430, 628, 878, 1186, 1558, 2000, 2518, 3118, 3806, 4588, 5470, 6458, 7558, 8776, 10118, 11590, 13198, 14948, 16846, 18898, 21110, 23488, 26038, 28766, 31678, 34780 +}; +TYPE res_test0101[32] = { + -4, 6, 32, 80, 156, 266, 416, 612, 860, 1166, 1536, 1976, 2492, 3090, 3776, 4556, 5436, 6422, 7520, 8736, 10076, 11546, 13152, 14900, 16796, 18846, 21056, 23432, 25980, 28706, 31616, 34716 +}; +TYPE res_test0110[32] = { + 4, -6, -32, -80, -156, -266, -416, -612, -860, -1166, -1536, -1976, -2492, -3090, -3776, -4556, -5436, -6422, -7520, -8736, -10076, -11546, -13152, -14900, -16796, -18846, -21056, -23432, -25980, -28706, -31616, -34716 +}; +TYPE res_test0111[32] = { + 2, -10, -38, -88, -166, -278, -430, -628, -878, -1186, -1558, -2000, -2518, -3118, -3806, -4588, -5470, -6458, -7558, -8776, -10118, -11590, -13198, -14948, -16846, -18898, -21110, -23488, -26038, -28766, -31678, -34780 +}; +TYPE res_test1000[32] = { + 4, -6, -32, -80, -156, -266, -416, -612, -860, -1166, -1536, -1976, -2492, -3090, -3776, -4556, -5436, -6422, -7520, -8736, -10076, -11546, -13152, -14900, -16796, -18846, -21056, -23432, -25980, -28706, -31616, -34716 +}; +TYPE res_test1001[32] = { + 2, -10, -38, -88, -166, -278, -430, -628, -878, -1186, -1558, -2000, -2518, -3118, -3806, -4588, -5470, -6458, -7558, -8776, -10118, -11590, -13198, -14948, -16846, -18898, -21110, -23488, -26038, -28766, -31678, -34780 +}; +TYPE res_test1010[32] = { + -2, 10, 38, 88, 166, 278, 430, 628, 878, 1186, 1558, 2000, 2518, 3118, 3806, 4588, 5470, 6458, 7558, 8776, 10118, 11590, 13198, 14948, 16846, 18898, 21110, 23488, 26038, 28766, 31678, 34780 +}; +TYPE res_test1011[32] = { + -4, 6, 32, 80, 156, 266, 416, 612, 860, 1166, 1536, 1976, 2492, 3090, 3776, 4556, 5436, 6422, 7520, 8736, 10076, 11546, 13152, 14900, 16796, 18846, 21056, 23432, 25980, 28706, 31616, 34716 +}; +TYPE res_test1100[32] = { + -14, -38, -82, -152, -254, -394, -578, -812, -1102, -1454, -1874, -2368, -2942, -3602, -4354, -5204, -6158, -7222, -8402, -9704, -11134, -12698, -14402, -16252, -18254, -20414, -22738, -25232, -27902, -30754, -33794, -37028 +}; +TYPE res_test1101[32] = { + -16, -42, -88, -160, -264, -406, -592, -828, -1120, -1474, -1896, -2392, -2968, -3630, -4384, -5236, -6192, -7258, -8440, -9744, -11176, -12742, -14448, -16300, -18304, -20466, -22792, -25288, -27960, -30814, -33856, -37092 +}; +TYPE res_test1110[32] = { + 16, 42, 88, 160, 264, 406, 592, 828, 1120, 1474, 1896, 2392, 2968, 3630, 4384, 5236, 6192, 7258, 8440, 9744, 11176, 12742, 14448, 16300, 18304, 20466, 22792, 25288, 27960, 30814, 33856, 37092 +}; +TYPE res_test1111[32] = { + 14, 38, 82, 152, 254, 394, 578, 812, 1102, 1454, 1874, 2368, 2942, 3602, 4354, 5204, 6158, 7222, 8402, 9704, 11134, 12698, 14402, 16252, 18254, 20414, 22738, 25232, 27902, 30754, 33794, 37028 +}; + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_6.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_6.h new file mode 100644 index 000000000..29ae9256c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_double_results_6.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_double_results_6 +#define fma_run_double_results_6 + +TYPE res_test0000[32] = { + 17, 43, 89, 161, 265, 407, 593, 829, 1121, 1475, 1897, 2393, 2969, 3631, 4385, 5237, 6193, 7259, 8441, 9745, 11177, 12743, 14449, 16301, 18305, 20467, 22793, 25289, 27961, 30815, 33857, 37093 +}; +TYPE res_test0001[32] = { + 13, 37, 81, 151, 253, 393, 577, 811, 1101, 1453, 1873, 2367, 2941, 3601, 4353, 5203, 6157, 7221, 8401, 9703, 11133, 12697, 14401, 16251, 18253, 20413, 22737, 25231, 27901, 30753, 33793, 37027 +}; +TYPE res_test0010[32] = { + -13, -37, -81, -151, -253, -393, -577, -811, -1101, -1453, -1873, -2367, -2941, -3601, -4353, -5203, -6157, -7221, -8401, -9703, -11133, -12697, -14401, -16251, -18253, -20413, -22737, -25231, -27901, -30753, -33793, -37027 +}; +TYPE res_test0011[32] = { + -17, -43, -89, -161, -265, -407, -593, -829, -1121, -1475, -1897, -2393, -2969, -3631, -4385, -5237, -6193, -7259, -8441, -9745, -11177, -12743, -14449, -16301, -18305, -20467, -22793, -25289, -27961, -30815, -33857, -37093 +}; +TYPE res_test0100[32] = { + -1, 11, 39, 89, 167, 279, 431, 629, 879, 1187, 1559, 2001, 2519, 3119, 3807, 4589, 5471, 6459, 7559, 8777, 10119, 11591, 13199, 14949, 16847, 18899, 21111, 23489, 26039, 28767, 31679, 34781 +}; +TYPE res_test0101[32] = { + -5, 5, 31, 79, 155, 265, 415, 611, 859, 1165, 1535, 1975, 2491, 3089, 3775, 4555, 5435, 6421, 7519, 8735, 10075, 11545, 13151, 14899, 16795, 18845, 21055, 23431, 25979, 28705, 31615, 34715 +}; +TYPE res_test0110[32] = { + 5, -5, -31, -79, -155, -265, -415, -611, -859, -1165, -1535, -1975, -2491, -3089, -3775, -4555, -5435, -6421, -7519, -8735, -10075, -11545, -13151, -14899, -16795, -18845, -21055, -23431, -25979, -28705, -31615, -34715 +}; +TYPE res_test0111[32] = { + 1, -11, -39, -89, -167, -279, -431, -629, -879, -1187, -1559, -2001, -2519, -3119, -3807, -4589, -5471, -6459, -7559, -8777, -10119, -11591, -13199, -14949, -16847, -18899, -21111, -23489, -26039, -28767, -31679, -34781 +}; +TYPE res_test1000[32] = { + 5, -5, -31, -79, -155, -265, -415, -611, -859, -1165, -1535, -1975, -2491, -3089, -3775, -4555, -5435, -6421, -7519, -8735, -10075, -11545, -13151, -14899, -16795, -18845, -21055, -23431, -25979, -28705, -31615, -34715 +}; +TYPE res_test1001[32] = { + 1, -11, -39, -89, -167, -279, -431, -629, -879, -1187, -1559, -2001, -2519, -3119, -3807, -4589, -5471, -6459, -7559, -8777, -10119, -11591, -13199, -14949, -16847, -18899, -21111, -23489, -26039, -28767, -31679, -34781 +}; +TYPE res_test1010[32] = { + -1, 11, 39, 89, 167, 279, 431, 629, 879, 1187, 1559, 2001, 2519, 3119, 3807, 4589, 5471, 6459, 7559, 8777, 10119, 11591, 13199, 14949, 16847, 18899, 21111, 23489, 26039, 28767, 31679, 34781 +}; +TYPE res_test1011[32] = { + -5, 5, 31, 79, 155, 265, 415, 611, 859, 1165, 1535, 1975, 2491, 3089, 3775, 4555, 5435, 6421, 7519, 8735, 10075, 11545, 13151, 14899, 16795, 18845, 21055, 23431, 25979, 28705, 31615, 34715 +}; +TYPE res_test1100[32] = { + -13, -37, -81, -151, -253, -393, -577, -811, -1101, -1453, -1873, -2367, -2941, -3601, -4353, -5203, -6157, -7221, -8401, -9703, -11133, -12697, -14401, -16251, -18253, -20413, -22737, -25231, -27901, -30753, -33793, -37027 +}; +TYPE res_test1101[32] = { + -17, -43, -89, -161, -265, -407, -593, -829, -1121, -1475, -1897, -2393, -2969, -3631, -4385, -5237, -6193, -7259, -8441, -9745, -11177, -12743, -14449, -16301, -18305, -20467, -22793, -25289, -27961, -30815, -33857, -37093 +}; +TYPE res_test1110[32] = { + 17, 43, 89, 161, 265, 407, 593, 829, 1121, 1475, 1897, 2393, 2969, 3631, 4385, 5237, 6193, 7259, 8441, 9745, 11177, 12743, 14449, 16301, 18305, 20467, 22793, 25289, 27961, 30815, 33857, 37093 +}; +TYPE res_test1111[32] = { + 13, 37, 81, 151, 253, 393, 577, 811, 1101, 1453, 1873, 2367, 2941, 3601, 4353, 5203, 6157, 7221, 8401, 9703, 11133, 12697, 14401, 16251, 18253, 20413, 22737, 25231, 27901, 30753, 33793, 37027 +}; + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_1.c new file mode 100644 index 000000000..eccf60a88 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_1.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_1.h" + +#include "fma_run_float_results_1.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_2.c new file mode 100644 index 000000000..18177520a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_2.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_2.h" + +#include "fma_run_float_results_2.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_3.c new file mode 100644 index 000000000..b206a0775 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_3.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_3.h" + +#include "fma_run_float_results_3.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_4.c new file mode 100644 index 000000000..31c5a4dbb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_4.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_4.h" + +#include "fma_run_float_results_4.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_5.c new file mode 100644 index 000000000..615886ced --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_5.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_5.h" + +#include "fma_run_float_results_5.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_6.c new file mode 100644 index 000000000..ca6cf5b1c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_6.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "fma_6.h" + +#include "fma_run_float_results_6.h" + +#include "fma-check.h" +#include "fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_1.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_1.h new file mode 100644 index 000000000..65f52f2c7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_1.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_float_results_1 +#define fma_run_float_results_1 + +TYPE res_test0000[32] = { + 7, 23, 55, 109, 191, 307, 463, 665, 919, 1231, 1607, 2053, 2575, 3179, 3871, 4657, 5543, 6535, 7639, 8861, 10207, 11683, 13295, 15049, 16951, 19007, 21223, 23605, 26159, 28891, 31807, 34913 +}; +TYPE res_test0001[32] = { + 3, 17, 47, 99, 179, 293, 447, 647, 899, 1209, 1583, 2027, 2547, 3149, 3839, 4623, 5507, 6497, 7599, 8819, 10163, 11637, 13247, 14999, 16899, 18953, 21167, 23547, 26099, 28829, 31743, 34847 +}; +TYPE res_test0010[32] = { + -3, -17, -47, -99, -179, -293, -447, -647, -899, -1209, -1583, -2027, -2547, -3149, -3839, -4623, -5507, -6497, -7599, -8819, -10163, -11637, -13247, -14999, -16899, -18953, -21167, -23547, -26099, -28829, -31743, -34847 +}; +TYPE res_test0011[32] = { + -7, -23, -55, -109, -191, -307, -463, -665, -919, -1231, -1607, -2053, -2575, -3179, -3871, -4657, -5543, -6535, -7639, -8861, -10207, -11683, -13295, -15049, -16951, -19007, -21223, -23605, -26159, -28891, -31807, -34913 +}; +TYPE res_test0100[32] = { + 1, 7, 25, 61, 121, 211, 337, 505, 721, 991, 1321, 1717, 2185, 2731, 3361, 4081, 4897, 5815, 6841, 7981, 9241, 10627, 12145, 13801, 15601, 17551, 19657, 21925, 24361, 26971, 29761, 32737 +}; +TYPE res_test0101[32] = { + -3, 1, 17, 51, 109, 197, 321, 487, 701, 969, 1297, 1691, 2157, 2701, 3329, 4047, 4861, 5777, 6801, 7939, 9197, 10581, 12097, 13751, 15549, 17497, 19601, 21867, 24301, 26909, 29697, 32671 +}; +TYPE res_test0110[32] = { + 3, -1, -17, -51, -109, -197, -321, -487, -701, -969, -1297, -1691, -2157, -2701, -3329, -4047, -4861, -5777, -6801, -7939, -9197, -10581, -12097, -13751, -15549, -17497, -19601, -21867, -24301, -26909, -29697, -32671 +}; +TYPE res_test0111[32] = { + -1, -7, -25, -61, -121, -211, -337, -505, -721, -991, -1321, -1717, -2185, -2731, -3361, -4081, -4897, -5815, -6841, -7981, -9241, -10627, -12145, -13801, -15601, -17551, -19657, -21925, -24361, -26971, -29761, -32737 +}; +TYPE res_test1000[32] = { + 3, -1, -17, -51, -109, -197, -321, -487, -701, -969, -1297, -1691, -2157, -2701, -3329, -4047, -4861, -5777, -6801, -7939, -9197, -10581, -12097, -13751, -15549, -17497, -19601, -21867, -24301, -26909, -29697, -32671 +}; +TYPE res_test1001[32] = { + -1, -7, -25, -61, -121, -211, -337, -505, -721, -991, -1321, -1717, -2185, -2731, -3361, -4081, -4897, -5815, -6841, -7981, -9241, -10627, -12145, -13801, -15601, -17551, -19657, -21925, -24361, -26971, -29761, -32737 +}; +TYPE res_test1010[32] = { + 1, 7, 25, 61, 121, 211, 337, 505, 721, 991, 1321, 1717, 2185, 2731, 3361, 4081, 4897, 5815, 6841, 7981, 9241, 10627, 12145, 13801, 15601, 17551, 19657, 21925, 24361, 26971, 29761, 32737 +}; +TYPE res_test1011[32] = { + -3, 1, 17, 51, 109, 197, 321, 487, 701, 969, 1297, 1691, 2157, 2701, 3329, 4047, 4861, 5777, 6801, 7939, 9197, 10581, 12097, 13751, 15549, 17497, 19601, 21867, 24301, 26909, 29697, 32671 +}; +TYPE res_test1100[32] = { + -3, -17, -47, -99, -179, -293, -447, -647, -899, -1209, -1583, -2027, -2547, -3149, -3839, -4623, -5507, -6497, -7599, -8819, -10163, -11637, -13247, -14999, -16899, -18953, -21167, -23547, -26099, -28829, -31743, -34847 +}; +TYPE res_test1101[32] = { + -7, -23, -55, -109, -191, -307, -463, -665, -919, -1231, -1607, -2053, -2575, -3179, -3871, -4657, -5543, -6535, -7639, -8861, -10207, -11683, -13295, -15049, -16951, -19007, -21223, -23605, -26159, -28891, -31807, -34913 +}; +TYPE res_test1110[32] = { + 7, 23, 55, 109, 191, 307, 463, 665, 919, 1231, 1607, 2053, 2575, 3179, 3871, 4657, 5543, 6535, 7639, 8861, 10207, 11683, 13295, 15049, 16951, 19007, 21223, 23605, 26159, 28891, 31807, 34913 +}; +TYPE res_test1111[32] = { + 3, 17, 47, 99, 179, 293, 447, 647, 899, 1209, 1583, 2027, 2547, 3149, 3839, 4623, 5507, 6497, 7599, 8819, 10163, 11637, 13247, 14999, 16899, 18953, 21167, 23547, 26099, 28829, 31743, 34847 +}; + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_2.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_2.h new file mode 100644 index 000000000..d215efd58 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_2.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_float_results_2 +#define fma_run_float_results_2 + +TYPE res_test0000[32] = { + 8, 24, 56, 110, 192, 308, 464, 666, 920, 1232, 1608, 2054, 2576, 3180, 3872, 4658, 5544, 6536, 7640, 8862, 10208, 11684, 13296, 15050, 16952, 19008, 21224, 23606, 26160, 28892, 31808, 34914 +}; +TYPE res_test0001[32] = { + 2, 16, 46, 98, 178, 292, 446, 646, 898, 1208, 1582, 2026, 2546, 3148, 3838, 4622, 5506, 6496, 7598, 8818, 10162, 11636, 13246, 14998, 16898, 18952, 21166, 23546, 26098, 28828, 31742, 34846 +}; +TYPE res_test0010[32] = { + -2, -16, -46, -98, -178, -292, -446, -646, -898, -1208, -1582, -2026, -2546, -3148, -3838, -4622, -5506, -6496, -7598, -8818, -10162, -11636, -13246, -14998, -16898, -18952, -21166, -23546, -26098, -28828, -31742, -34846 +}; +TYPE res_test0011[32] = { + -8, -24, -56, -110, -192, -308, -464, -666, -920, -1232, -1608, -2054, -2576, -3180, -3872, -4658, -5544, -6536, -7640, -8862, -10208, -11684, -13296, -15050, -16952, -19008, -21224, -23606, -26160, -28892, -31808, -34914 +}; +TYPE res_test0100[32] = { + 2, 8, 26, 62, 122, 212, 338, 506, 722, 992, 1322, 1718, 2186, 2732, 3362, 4082, 4898, 5816, 6842, 7982, 9242, 10628, 12146, 13802, 15602, 17552, 19658, 21926, 24362, 26972, 29762, 32738 +}; +TYPE res_test0101[32] = { + -4, 0, 16, 50, 108, 196, 320, 486, 700, 968, 1296, 1690, 2156, 2700, 3328, 4046, 4860, 5776, 6800, 7938, 9196, 10580, 12096, 13750, 15548, 17496, 19600, 21866, 24300, 26908, 29696, 32670 +}; +TYPE res_test0110[32] = { + 4, 0, -16, -50, -108, -196, -320, -486, -700, -968, -1296, -1690, -2156, -2700, -3328, -4046, -4860, -5776, -6800, -7938, -9196, -10580, -12096, -13750, -15548, -17496, -19600, -21866, -24300, -26908, -29696, -32670 +}; +TYPE res_test0111[32] = { + -2, -8, -26, -62, -122, -212, -338, -506, -722, -992, -1322, -1718, -2186, -2732, -3362, -4082, -4898, -5816, -6842, -7982, -9242, -10628, -12146, -13802, -15602, -17552, -19658, -21926, -24362, -26972, -29762, -32738 +}; +TYPE res_test1000[32] = { + 4, 0, -16, -50, -108, -196, -320, -486, -700, -968, -1296, -1690, -2156, -2700, -3328, -4046, -4860, -5776, -6800, -7938, -9196, -10580, -12096, -13750, -15548, -17496, -19600, -21866, -24300, -26908, -29696, -32670 +}; +TYPE res_test1001[32] = { + -2, -8, -26, -62, -122, -212, -338, -506, -722, -992, -1322, -1718, -2186, -2732, -3362, -4082, -4898, -5816, -6842, -7982, -9242, -10628, -12146, -13802, -15602, -17552, -19658, -21926, -24362, -26972, -29762, -32738 +}; +TYPE res_test1010[32] = { + 2, 8, 26, 62, 122, 212, 338, 506, 722, 992, 1322, 1718, 2186, 2732, 3362, 4082, 4898, 5816, 6842, 7982, 9242, 10628, 12146, 13802, 15602, 17552, 19658, 21926, 24362, 26972, 29762, 32738 +}; +TYPE res_test1011[32] = { + -4, 0, 16, 50, 108, 196, 320, 486, 700, 968, 1296, 1690, 2156, 2700, 3328, 4046, 4860, 5776, 6800, 7938, 9196, 10580, 12096, 13750, 15548, 17496, 19600, 21866, 24300, 26908, 29696, 32670 +}; +TYPE res_test1100[32] = { + -2, -16, -46, -98, -178, -292, -446, -646, -898, -1208, -1582, -2026, -2546, -3148, -3838, -4622, -5506, -6496, -7598, -8818, -10162, -11636, -13246, -14998, -16898, -18952, -21166, -23546, -26098, -28828, -31742, -34846 +}; +TYPE res_test1101[32] = { + -8, -24, -56, -110, -192, -308, -464, -666, -920, -1232, -1608, -2054, -2576, -3180, -3872, -4658, -5544, -6536, -7640, -8862, -10208, -11684, -13296, -15050, -16952, -19008, -21224, -23606, -26160, -28892, -31808, -34914 +}; +TYPE res_test1110[32] = { + 8, 24, 56, 110, 192, 308, 464, 666, 920, 1232, 1608, 2054, 2576, 3180, 3872, 4658, 5544, 6536, 7640, 8862, 10208, 11684, 13296, 15050, 16952, 19008, 21224, 23606, 26160, 28892, 31808, 34914 +}; +TYPE res_test1111[32] = { + 2, 16, 46, 98, 178, 292, 446, 646, 898, 1208, 1582, 2026, 2546, 3148, 3838, 4622, 5506, 6496, 7598, 8818, 10162, 11636, 13246, 14998, 16898, 18952, 21166, 23546, 26098, 28828, 31742, 34846 +}; + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_3.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_3.h new file mode 100644 index 000000000..11751f131 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_3.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_float_results_3 +#define fma_run_float_results_3 + +TYPE res_test0000[32] = { + 11, 32, 71, 134, 227, 356, 527, 746, 1019, 1352, 1751, 2222, 2771, 3404, 4127, 4946, 5867, 6896, 8039, 9302, 10691, 12212, 13871, 15674, 17627, 19736, 22007, 24446, 27059, 29852, 32831, 36002 +}; +TYPE res_test0001[32] = { + 9, 28, 65, 126, 217, 344, 513, 730, 1001, 1332, 1729, 2198, 2745, 3376, 4097, 4914, 5833, 6860, 8001, 9262, 10649, 12168, 13825, 15626, 17577, 19684, 21953, 24390, 27001, 29792, 32769, 35938 +}; +TYPE res_test0010[32] = { + -9, -28, -65, -126, -217, -344, -513, -730, -1001, -1332, -1729, -2198, -2745, -3376, -4097, -4914, -5833, -6860, -8001, -9262, -10649, -12168, -13825, -15626, -17577, -19684, -21953, -24390, -27001, -29792, -32769, -35938 +}; +TYPE res_test0011[32] = { + -11, -32, -71, -134, -227, -356, -527, -746, -1019, -1352, -1751, -2222, -2771, -3404, -4127, -4946, -5867, -6896, -8039, -9302, -10691, -12212, -13871, -15674, -17627, -19736, -22007, -24446, -27059, -29852, -32831, -36002 +}; +TYPE res_test0100[32] = { + -1, 8, 31, 74, 143, 244, 383, 566, 799, 1088, 1439, 1858, 2351, 2924, 3583, 4334, 5183, 6136, 7199, 8378, 9679, 11108, 12671, 14374, 16223, 18224, 20383, 22706, 25199, 27868, 30719, 33758 +}; +TYPE res_test0101[32] = { + -3, 4, 25, 66, 133, 232, 369, 550, 781, 1068, 1417, 1834, 2325, 2896, 3553, 4302, 5149, 6100, 7161, 8338, 9637, 11064, 12625, 14326, 16173, 18172, 20329, 22650, 25141, 27808, 30657, 33694 +}; +TYPE res_test0110[32] = { + 3, -4, -25, -66, -133, -232, -369, -550, -781, -1068, -1417, -1834, -2325, -2896, -3553, -4302, -5149, -6100, -7161, -8338, -9637, -11064, -12625, -14326, -16173, -18172, -20329, -22650, -25141, -27808, -30657, -33694 +}; +TYPE res_test0111[32] = { + 1, -8, -31, -74, -143, -244, -383, -566, -799, -1088, -1439, -1858, -2351, -2924, -3583, -4334, -5183, -6136, -7199, -8378, -9679, -11108, -12671, -14374, -16223, -18224, -20383, -22706, -25199, -27868, -30719, -33758 +}; +TYPE res_test1000[32] = { + 3, -4, -25, -66, -133, -232, -369, -550, -781, -1068, -1417, -1834, -2325, -2896, -3553, -4302, -5149, -6100, -7161, -8338, -9637, -11064, -12625, -14326, -16173, -18172, -20329, -22650, -25141, -27808, -30657, -33694 +}; +TYPE res_test1001[32] = { + 1, -8, -31, -74, -143, -244, -383, -566, -799, -1088, -1439, -1858, -2351, -2924, -3583, -4334, -5183, -6136, -7199, -8378, -9679, -11108, -12671, -14374, -16223, -18224, -20383, -22706, -25199, -27868, -30719, -33758 +}; +TYPE res_test1010[32] = { + -1, 8, 31, 74, 143, 244, 383, 566, 799, 1088, 1439, 1858, 2351, 2924, 3583, 4334, 5183, 6136, 7199, 8378, 9679, 11108, 12671, 14374, 16223, 18224, 20383, 22706, 25199, 27868, 30719, 33758 +}; +TYPE res_test1011[32] = { + -3, 4, 25, 66, 133, 232, 369, 550, 781, 1068, 1417, 1834, 2325, 2896, 3553, 4302, 5149, 6100, 7161, 8338, 9637, 11064, 12625, 14326, 16173, 18172, 20329, 22650, 25141, 27808, 30657, 33694 +}; +TYPE res_test1100[32] = { + -9, -28, -65, -126, -217, -344, -513, -730, -1001, -1332, -1729, -2198, -2745, -3376, -4097, -4914, -5833, -6860, -8001, -9262, -10649, -12168, -13825, -15626, -17577, -19684, -21953, -24390, -27001, -29792, -32769, -35938 +}; +TYPE res_test1101[32] = { + -11, -32, -71, -134, -227, -356, -527, -746, -1019, -1352, -1751, -2222, -2771, -3404, -4127, -4946, -5867, -6896, -8039, -9302, -10691, -12212, -13871, -15674, -17627, -19736, -22007, -24446, -27059, -29852, -32831, -36002 +}; +TYPE res_test1110[32] = { + 11, 32, 71, 134, 227, 356, 527, 746, 1019, 1352, 1751, 2222, 2771, 3404, 4127, 4946, 5867, 6896, 8039, 9302, 10691, 12212, 13871, 15674, 17627, 19736, 22007, 24446, 27059, 29852, 32831, 36002 +}; +TYPE res_test1111[32] = { + 9, 28, 65, 126, 217, 344, 513, 730, 1001, 1332, 1729, 2198, 2745, 3376, 4097, 4914, 5833, 6860, 8001, 9262, 10649, 12168, 13825, 15626, 17577, 19684, 21953, 24390, 27001, 29792, 32769, 35938 +}; + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_4.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_4.h new file mode 100644 index 000000000..13906dbdd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_4.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_float_results_4 +#define fma_run_float_results_4 + +TYPE res_test0000[32] = { + 13, 34, 73, 136, 229, 358, 529, 748, 1021, 1354, 1753, 2224, 2773, 3406, 4129, 4948, 5869, 6898, 8041, 9304, 10693, 12214, 13873, 15676, 17629, 19738, 22009, 24448, 27061, 29854, 32833, 36004 +}; +TYPE res_test0001[32] = { + 7, 26, 63, 124, 215, 342, 511, 728, 999, 1330, 1727, 2196, 2743, 3374, 4095, 4912, 5831, 6858, 7999, 9260, 10647, 12166, 13823, 15624, 17575, 19682, 21951, 24388, 26999, 29790, 32767, 35936 +}; +TYPE res_test0010[32] = { + -7, -26, -63, -124, -215, -342, -511, -728, -999, -1330, -1727, -2196, -2743, -3374, -4095, -4912, -5831, -6858, -7999, -9260, -10647, -12166, -13823, -15624, -17575, -19682, -21951, -24388, -26999, -29790, -32767, -35936 +}; +TYPE res_test0011[32] = { + -13, -34, -73, -136, -229, -358, -529, -748, -1021, -1354, -1753, -2224, -2773, -3406, -4129, -4948, -5869, -6898, -8041, -9304, -10693, -12214, -13873, -15676, -17629, -19738, -22009, -24448, -27061, -29854, -32833, -36004 +}; +TYPE res_test0100[32] = { + 1, 10, 33, 76, 145, 246, 385, 568, 801, 1090, 1441, 1860, 2353, 2926, 3585, 4336, 5185, 6138, 7201, 8380, 9681, 11110, 12673, 14376, 16225, 18226, 20385, 22708, 25201, 27870, 30721, 33760 +}; +TYPE res_test0101[32] = { + -5, 2, 23, 64, 131, 230, 367, 548, 779, 1066, 1415, 1832, 2323, 2894, 3551, 4300, 5147, 6098, 7159, 8336, 9635, 11062, 12623, 14324, 16171, 18170, 20327, 22648, 25139, 27806, 30655, 33692 +}; +TYPE res_test0110[32] = { + 5, -2, -23, -64, -131, -230, -367, -548, -779, -1066, -1415, -1832, -2323, -2894, -3551, -4300, -5147, -6098, -7159, -8336, -9635, -11062, -12623, -14324, -16171, -18170, -20327, -22648, -25139, -27806, -30655, -33692 +}; +TYPE res_test0111[32] = { + -1, -10, -33, -76, -145, -246, -385, -568, -801, -1090, -1441, -1860, -2353, -2926, -3585, -4336, -5185, -6138, -7201, -8380, -9681, -11110, -12673, -14376, -16225, -18226, -20385, -22708, -25201, -27870, -30721, -33760 +}; +TYPE res_test1000[32] = { + 5, -2, -23, -64, -131, -230, -367, -548, -779, -1066, -1415, -1832, -2323, -2894, -3551, -4300, -5147, -6098, -7159, -8336, -9635, -11062, -12623, -14324, -16171, -18170, -20327, -22648, -25139, -27806, -30655, -33692 +}; +TYPE res_test1001[32] = { + -1, -10, -33, -76, -145, -246, -385, -568, -801, -1090, -1441, -1860, -2353, -2926, -3585, -4336, -5185, -6138, -7201, -8380, -9681, -11110, -12673, -14376, -16225, -18226, -20385, -22708, -25201, -27870, -30721, -33760 +}; +TYPE res_test1010[32] = { + 1, 10, 33, 76, 145, 246, 385, 568, 801, 1090, 1441, 1860, 2353, 2926, 3585, 4336, 5185, 6138, 7201, 8380, 9681, 11110, 12673, 14376, 16225, 18226, 20385, 22708, 25201, 27870, 30721, 33760 +}; +TYPE res_test1011[32] = { + -5, 2, 23, 64, 131, 230, 367, 548, 779, 1066, 1415, 1832, 2323, 2894, 3551, 4300, 5147, 6098, 7159, 8336, 9635, 11062, 12623, 14324, 16171, 18170, 20327, 22648, 25139, 27806, 30655, 33692 +}; +TYPE res_test1100[32] = { + -7, -26, -63, -124, -215, -342, -511, -728, -999, -1330, -1727, -2196, -2743, -3374, -4095, -4912, -5831, -6858, -7999, -9260, -10647, -12166, -13823, -15624, -17575, -19682, -21951, -24388, -26999, -29790, -32767, -35936 +}; +TYPE res_test1101[32] = { + -13, -34, -73, -136, -229, -358, -529, -748, -1021, -1354, -1753, -2224, -2773, -3406, -4129, -4948, -5869, -6898, -8041, -9304, -10693, -12214, -13873, -15676, -17629, -19738, -22009, -24448, -27061, -29854, -32833, -36004 +}; +TYPE res_test1110[32] = { + 13, 34, 73, 136, 229, 358, 529, 748, 1021, 1354, 1753, 2224, 2773, 3406, 4129, 4948, 5869, 6898, 8041, 9304, 10693, 12214, 13873, 15676, 17629, 19738, 22009, 24448, 27061, 29854, 32833, 36004 +}; +TYPE res_test1111[32] = { + 7, 26, 63, 124, 215, 342, 511, 728, 999, 1330, 1727, 2196, 2743, 3374, 4095, 4912, 5831, 6858, 7999, 9260, 10647, 12166, 13823, 15624, 17575, 19682, 21951, 24388, 26999, 29790, 32767, 35936 +}; + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_5.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_5.h new file mode 100644 index 000000000..f156bef6f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_5.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_float_results_5 +#define fma_run_float_results_5 + +TYPE res_test0000[32] = { + 16, 42, 88, 160, 264, 406, 592, 828, 1120, 1474, 1896, 2392, 2968, 3630, 4384, 5236, 6192, 7258, 8440, 9744, 11176, 12742, 14448, 16300, 18304, 20466, 22792, 25288, 27960, 30814, 33856, 37092 +}; +TYPE res_test0001[32] = { + 14, 38, 82, 152, 254, 394, 578, 812, 1102, 1454, 1874, 2368, 2942, 3602, 4354, 5204, 6158, 7222, 8402, 9704, 11134, 12698, 14402, 16252, 18254, 20414, 22738, 25232, 27902, 30754, 33794, 37028 +}; +TYPE res_test0010[32] = { + -14, -38, -82, -152, -254, -394, -578, -812, -1102, -1454, -1874, -2368, -2942, -3602, -4354, -5204, -6158, -7222, -8402, -9704, -11134, -12698, -14402, -16252, -18254, -20414, -22738, -25232, -27902, -30754, -33794, -37028 +}; +TYPE res_test0011[32] = { + -16, -42, -88, -160, -264, -406, -592, -828, -1120, -1474, -1896, -2392, -2968, -3630, -4384, -5236, -6192, -7258, -8440, -9744, -11176, -12742, -14448, -16300, -18304, -20466, -22792, -25288, -27960, -30814, -33856, -37092 +}; +TYPE res_test0100[32] = { + -2, 10, 38, 88, 166, 278, 430, 628, 878, 1186, 1558, 2000, 2518, 3118, 3806, 4588, 5470, 6458, 7558, 8776, 10118, 11590, 13198, 14948, 16846, 18898, 21110, 23488, 26038, 28766, 31678, 34780 +}; +TYPE res_test0101[32] = { + -4, 6, 32, 80, 156, 266, 416, 612, 860, 1166, 1536, 1976, 2492, 3090, 3776, 4556, 5436, 6422, 7520, 8736, 10076, 11546, 13152, 14900, 16796, 18846, 21056, 23432, 25980, 28706, 31616, 34716 +}; +TYPE res_test0110[32] = { + 4, -6, -32, -80, -156, -266, -416, -612, -860, -1166, -1536, -1976, -2492, -3090, -3776, -4556, -5436, -6422, -7520, -8736, -10076, -11546, -13152, -14900, -16796, -18846, -21056, -23432, -25980, -28706, -31616, -34716 +}; +TYPE res_test0111[32] = { + 2, -10, -38, -88, -166, -278, -430, -628, -878, -1186, -1558, -2000, -2518, -3118, -3806, -4588, -5470, -6458, -7558, -8776, -10118, -11590, -13198, -14948, -16846, -18898, -21110, -23488, -26038, -28766, -31678, -34780 +}; +TYPE res_test1000[32] = { + 4, -6, -32, -80, -156, -266, -416, -612, -860, -1166, -1536, -1976, -2492, -3090, -3776, -4556, -5436, -6422, -7520, -8736, -10076, -11546, -13152, -14900, -16796, -18846, -21056, -23432, -25980, -28706, -31616, -34716 +}; +TYPE res_test1001[32] = { + 2, -10, -38, -88, -166, -278, -430, -628, -878, -1186, -1558, -2000, -2518, -3118, -3806, -4588, -5470, -6458, -7558, -8776, -10118, -11590, -13198, -14948, -16846, -18898, -21110, -23488, -26038, -28766, -31678, -34780 +}; +TYPE res_test1010[32] = { + -2, 10, 38, 88, 166, 278, 430, 628, 878, 1186, 1558, 2000, 2518, 3118, 3806, 4588, 5470, 6458, 7558, 8776, 10118, 11590, 13198, 14948, 16846, 18898, 21110, 23488, 26038, 28766, 31678, 34780 +}; +TYPE res_test1011[32] = { + -4, 6, 32, 80, 156, 266, 416, 612, 860, 1166, 1536, 1976, 2492, 3090, 3776, 4556, 5436, 6422, 7520, 8736, 10076, 11546, 13152, 14900, 16796, 18846, 21056, 23432, 25980, 28706, 31616, 34716 +}; +TYPE res_test1100[32] = { + -14, -38, -82, -152, -254, -394, -578, -812, -1102, -1454, -1874, -2368, -2942, -3602, -4354, -5204, -6158, -7222, -8402, -9704, -11134, -12698, -14402, -16252, -18254, -20414, -22738, -25232, -27902, -30754, -33794, -37028 +}; +TYPE res_test1101[32] = { + -16, -42, -88, -160, -264, -406, -592, -828, -1120, -1474, -1896, -2392, -2968, -3630, -4384, -5236, -6192, -7258, -8440, -9744, -11176, -12742, -14448, -16300, -18304, -20466, -22792, -25288, -27960, -30814, -33856, -37092 +}; +TYPE res_test1110[32] = { + 16, 42, 88, 160, 264, 406, 592, 828, 1120, 1474, 1896, 2392, 2968, 3630, 4384, 5236, 6192, 7258, 8440, 9744, 11176, 12742, 14448, 16300, 18304, 20466, 22792, 25288, 27960, 30814, 33856, 37092 +}; +TYPE res_test1111[32] = { + 14, 38, 82, 152, 254, 394, 578, 812, 1102, 1454, 1874, 2368, 2942, 3602, 4354, 5204, 6158, 7222, 8402, 9704, 11134, 12698, 14402, 16252, 18254, 20414, 22738, 25232, 27902, 30754, 33794, 37028 +}; + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_6.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_6.h new file mode 100644 index 000000000..d2c2e1f97 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fma_run_float_results_6.h @@ -0,0 +1,54 @@ + +#ifndef fma_run_float_results_6 +#define fma_run_float_results_6 + +TYPE res_test0000[32] = { + 17, 43, 89, 161, 265, 407, 593, 829, 1121, 1475, 1897, 2393, 2969, 3631, 4385, 5237, 6193, 7259, 8441, 9745, 11177, 12743, 14449, 16301, 18305, 20467, 22793, 25289, 27961, 30815, 33857, 37093 +}; +TYPE res_test0001[32] = { + 13, 37, 81, 151, 253, 393, 577, 811, 1101, 1453, 1873, 2367, 2941, 3601, 4353, 5203, 6157, 7221, 8401, 9703, 11133, 12697, 14401, 16251, 18253, 20413, 22737, 25231, 27901, 30753, 33793, 37027 +}; +TYPE res_test0010[32] = { + -13, -37, -81, -151, -253, -393, -577, -811, -1101, -1453, -1873, -2367, -2941, -3601, -4353, -5203, -6157, -7221, -8401, -9703, -11133, -12697, -14401, -16251, -18253, -20413, -22737, -25231, -27901, -30753, -33793, -37027 +}; +TYPE res_test0011[32] = { + -17, -43, -89, -161, -265, -407, -593, -829, -1121, -1475, -1897, -2393, -2969, -3631, -4385, -5237, -6193, -7259, -8441, -9745, -11177, -12743, -14449, -16301, -18305, -20467, -22793, -25289, -27961, -30815, -33857, -37093 +}; +TYPE res_test0100[32] = { + -1, 11, 39, 89, 167, 279, 431, 629, 879, 1187, 1559, 2001, 2519, 3119, 3807, 4589, 5471, 6459, 7559, 8777, 10119, 11591, 13199, 14949, 16847, 18899, 21111, 23489, 26039, 28767, 31679, 34781 +}; +TYPE res_test0101[32] = { + -5, 5, 31, 79, 155, 265, 415, 611, 859, 1165, 1535, 1975, 2491, 3089, 3775, 4555, 5435, 6421, 7519, 8735, 10075, 11545, 13151, 14899, 16795, 18845, 21055, 23431, 25979, 28705, 31615, 34715 +}; +TYPE res_test0110[32] = { + 5, -5, -31, -79, -155, -265, -415, -611, -859, -1165, -1535, -1975, -2491, -3089, -3775, -4555, -5435, -6421, -7519, -8735, -10075, -11545, -13151, -14899, -16795, -18845, -21055, -23431, -25979, -28705, -31615, -34715 +}; +TYPE res_test0111[32] = { + 1, -11, -39, -89, -167, -279, -431, -629, -879, -1187, -1559, -2001, -2519, -3119, -3807, -4589, -5471, -6459, -7559, -8777, -10119, -11591, -13199, -14949, -16847, -18899, -21111, -23489, -26039, -28767, -31679, -34781 +}; +TYPE res_test1000[32] = { + 5, -5, -31, -79, -155, -265, -415, -611, -859, -1165, -1535, -1975, -2491, -3089, -3775, -4555, -5435, -6421, -7519, -8735, -10075, -11545, -13151, -14899, -16795, -18845, -21055, -23431, -25979, -28705, -31615, -34715 +}; +TYPE res_test1001[32] = { + 1, -11, -39, -89, -167, -279, -431, -629, -879, -1187, -1559, -2001, -2519, -3119, -3807, -4589, -5471, -6459, -7559, -8777, -10119, -11591, -13199, -14949, -16847, -18899, -21111, -23489, -26039, -28767, -31679, -34781 +}; +TYPE res_test1010[32] = { + -1, 11, 39, 89, 167, 279, 431, 629, 879, 1187, 1559, 2001, 2519, 3119, 3807, 4589, 5471, 6459, 7559, 8777, 10119, 11591, 13199, 14949, 16847, 18899, 21111, 23489, 26039, 28767, 31679, 34781 +}; +TYPE res_test1011[32] = { + -5, 5, 31, 79, 155, 265, 415, 611, 859, 1165, 1535, 1975, 2491, 3089, 3775, 4555, 5435, 6421, 7519, 8735, 10075, 11545, 13151, 14899, 16795, 18845, 21055, 23431, 25979, 28705, 31615, 34715 +}; +TYPE res_test1100[32] = { + -13, -37, -81, -151, -253, -393, -577, -811, -1101, -1453, -1873, -2367, -2941, -3601, -4353, -5203, -6157, -7221, -8401, -9703, -11133, -12697, -14401, -16251, -18253, -20413, -22737, -25231, -27901, -30753, -33793, -37027 +}; +TYPE res_test1101[32] = { + -17, -43, -89, -161, -265, -407, -593, -829, -1121, -1475, -1897, -2393, -2969, -3631, -4385, -5237, -6193, -7259, -8441, -9745, -11177, -12743, -14449, -16301, -18305, -20467, -22793, -25289, -27961, -30815, -33857, -37093 +}; +TYPE res_test1110[32] = { + 17, 43, 89, 161, 265, 407, 593, 829, 1121, 1475, 1897, 2393, 2969, 3631, 4385, 5237, 6193, 7259, 8441, 9745, 11177, 12743, 14449, 16301, 18305, 20467, 22793, 25289, 27961, 30815, 33857, 37093 +}; +TYPE res_test1111[32] = { + 13, 37, 81, 151, 253, 393, 577, 811, 1101, 1453, 1873, 2367, 2941, 3601, 4353, 5203, 6157, 7221, 8401, 9703, 11133, 12697, 14401, 16251, 18253, 20413, 22737, 25231, 27901, 30753, 33793, 37027 +}; + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpcvt-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpcvt-1.c new file mode 100644 index 000000000..1c3b9b834 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpcvt-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -march=k8" } */ +/* { dg-final { scan-assembler-not "cvtss2sd" } } */ +float a,b; +main() +{ + a=b*3.0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpcvt-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpcvt-2.c new file mode 100644 index 000000000..066d84365 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpcvt-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -march=k8" } */ +/* { dg-final { scan-assembler-not "cvtss2sd" } } */ +float a,b; +main() +{ + return a<0.0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpcvt-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpcvt-3.c new file mode 100644 index 000000000..569d21a5a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpcvt-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -march=k8" } */ +/* { dg-final { scan-assembler-not "cvtss2sd" } } */ +extern double fabs (double); +float a,b; +main() +{ + a=fabs(b)+1.0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpcvt-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpcvt-4.c new file mode 100644 index 000000000..8257f6520 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpcvt-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8 -mfpmath=sse" } */ +/* { dg-final { scan-assembler "cvtsi2sd" } } */ +/* Check that conversions will get folded. */ +double +t(short a) +{ + float b=a; + return b; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpprec-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpprec-1.c new file mode 100644 index 000000000..1c17c1d10 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fpprec-1.c @@ -0,0 +1,80 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-math-errno -fno-trapping-math -msse2 -mfpmath=sse" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +double x[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(), + -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023, /* +-DBL_MAX */ + -0x1p-52, 0x1p-52, /* +-DBL_EPSILON */ + /* nextafter/before 0.5, 1.0 and 1.5 */ + 0x1.0000000000001p-1, 0x1.fffffffffffffp-2, + 0x1.0000000000001p+0, 0x1.fffffffffffffp-1, + 0x1.8000000000001p+0, 0x1.7ffffffffffffp+0, + -0.0, 0.0, -0.5, 0.5, -1.0, 1.0, -1.5, 1.5, -2.0, 2.0, + -2.5, 2.5 }; +#define NUM (sizeof(x)/sizeof(double)) + +double expect_round[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(), + -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023, + -0.0, 0.0, + 1.0, 0.0, 1.0, 1.0, 2.0, 1.0, + -0.0, 0.0, -1.0, 1.0, -1.0, 1.0, -2.0, 2.0, -2.0, 2.0, + -3.0, 3.0 }; + +double expect_rint[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(), + -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023, + -0.0, 0.0, + 1.0, 0.0, 1.0, 1.0, 2.0, 1.0, + -0.0, 0.0, -0.0, 0.0, -1.0, 1.0, -2.0, 2.0, -2.0, 2.0, + -2.0, 2.0 }; + +double expect_floor[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(), + -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023, + -1.0, 0.0, + 0.0, 0.0, 1.0, 0.0, 1.0, 1.0, + -0.0, 0.0, -1.0, 0.0, -1.0, 1.0, -2.0, 1.0, -2.0, 2.0, + -3.0, 2.0 }; + +double expect_ceil[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(), + -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023, + -0.0, 1.0, + 1.0, 1.0, 2.0, 1.0, 2.0, 2.0, + -0.0, 0.0, -0.0, 1.0, -1.0, 1.0, -1.0, 2.0, -2.0, 2.0, + -2.0, 3.0 }; + +double expect_trunc[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(), + -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023, + -0.0, 0.0, + 0.0, 0.0, 1.0, 0.0, 1.0, 1.0, + -0.0, 0.0, -0.0, 0.0, -1.0, 1.0, -1.0, 1.0, -2.0, 2.0, + -2.0, 2.0 }; + + +#define CHECK(fn) \ +void check_ ## fn (void) \ +{ \ + int i; \ + for (i = 0; i < NUM; ++i) \ + { \ + double res = __builtin_ ## fn (x[i]); \ + if (__builtin_memcmp (&res, &expect_ ## fn [i], sizeof(double)) != 0) \ + printf( # fn " [%i]: %.18e %.18e\n", i, expect_ ## fn [i], res), abort (); \ + } \ +} + +CHECK(round) +CHECK(rint) +CHECK(floor) +CHECK(ceil) +CHECK(trunc) + +static void +sse2_test (void) +{ + check_round (); + check_rint (); + check_floor (); + check_ceil (); + check_trunc (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-1.c new file mode 100644 index 000000000..742e3a19e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-1.c @@ -0,0 +1,35 @@ +/* Test whether using target specific options, we can generate SSE2 code on + 32-bit, which does not generate SSE2 by default, but still generate 387 code + for a function that doesn't use attribute((option)). */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O3 -ftree-vectorize -mno-sse" } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +float a[SIZE] __attribute__((__aligned__(16))); +float b[SIZE] __attribute__((__aligned__(16))); +float c[SIZE] __attribute__((__aligned__(16))); + +void sse_addnums (void) __attribute__ ((__target__ ("sse2"))); + +void +sse_addnums (void) +{ + int i = 0; + for (; i < SIZE; ++i) + a[i] = b[i] + c[i]; +} + +void +i387_subnums (void) +{ + int i = 0; + for (; i < SIZE; ++i) + a[i] = b[i] - c[i]; +} + +/* { dg-final { scan-assembler "addps\[ \t\]" } } */ +/* { dg-final { scan-assembler "fsubs\[ \t\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-10.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-10.c new file mode 100644 index 000000000..de39ff00e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-10.c @@ -0,0 +1,15 @@ +/* PR target/36936 */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=i686" } */ +/* { dg-final { scan-assembler-not "cmov" } } */ + +extern int foo (int) __attribute__((__target__("arch=i386"))); + +int +foo (int x) +{ + if (x < 0) + x = 1; + return x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-11.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-11.c new file mode 100644 index 000000000..7c39f4cd2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-11.c @@ -0,0 +1,15 @@ +/* PR target/36936 */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=i386" } */ +/* { dg-final { scan-assembler "cmov" } } */ + +extern int foo (int) __attribute__((__target__("arch=i686"))); + +int +foo (int x) +{ + if (x < 0) + x = 1; + return x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-2.c new file mode 100644 index 000000000..88c14b29b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-2.c @@ -0,0 +1,98 @@ +/* Test whether using target specific options, we can generate FMA4 code. */ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -march=k8" } */ + +extern void exit (int); + +#define FMA4_ATTR __attribute__((__target__("fma4"))) +extern float flt_mul_add (float a, float b, float c) FMA4_ATTR; +extern float flt_mul_sub (float a, float b, float c) FMA4_ATTR; +extern float flt_neg_mul_add (float a, float b, float c) FMA4_ATTR; +extern float flt_neg_mul_sub (float a, float b, float c) FMA4_ATTR; + +extern double dbl_mul_add (double a, double b, double c) FMA4_ATTR; +extern double dbl_mul_sub (double a, double b, double c) FMA4_ATTR; +extern double dbl_neg_mul_add (double a, double b, double c) FMA4_ATTR; +extern double dbl_neg_mul_sub (double a, double b, double c) FMA4_ATTR; + +float +flt_mul_add (float a, float b, float c) +{ + return (a * b) + c; +} + +double +dbl_mul_add (double a, double b, double c) +{ + return (a * b) + c; +} + +float +flt_mul_sub (float a, float b, float c) +{ + return (a * b) - c; +} + +double +dbl_mul_sub (double a, double b, double c) +{ + return (a * b) - c; +} + +float +flt_neg_mul_add (float a, float b, float c) +{ + return (-(a * b)) + c; +} + +double +dbl_neg_mul_add (double a, double b, double c) +{ + return (-(a * b)) + c; +} + +float +flt_neg_mul_sub (float a, float b, float c) +{ + return (-(a * b)) - c; +} + +double +dbl_neg_mul_sub (double a, double b, double c) +{ + return (-(a * b)) - c; +} + +float f[10] = { 2, 3, 4 }; +double d[10] = { 2, 3, 4 }; + +int main () +{ + f[3] = flt_mul_add (f[0], f[1], f[2]); + f[4] = flt_mul_sub (f[0], f[1], f[2]); + f[5] = flt_neg_mul_add (f[0], f[1], f[2]); + f[6] = flt_neg_mul_sub (f[0], f[1], f[2]); + + d[3] = dbl_mul_add (d[0], d[1], d[2]); + d[4] = dbl_mul_sub (d[0], d[1], d[2]); + d[5] = dbl_neg_mul_add (d[0], d[1], d[2]); + d[6] = dbl_neg_mul_sub (d[0], d[1], d[2]); + exit (0); +} + +/* { dg-final { scan-assembler "vfmaddss" } } */ +/* { dg-final { scan-assembler "vfmaddsd" } } */ +/* { dg-final { scan-assembler "vfmsubss" } } */ +/* { dg-final { scan-assembler "vfmsubsd" } } */ +/* { dg-final { scan-assembler "vfnmaddss" } } */ +/* { dg-final { scan-assembler "vfnmaddsd" } } */ +/* { dg-final { scan-assembler "vfnmsubss" } } */ +/* { dg-final { scan-assembler "vfnmsubsd" } } */ +/* { dg-final { scan-assembler "call\t(.*)flt_mul_add" } } */ +/* { dg-final { scan-assembler "call\t(.*)flt_mul_sub" } } */ +/* { dg-final { scan-assembler "call\t(.*)flt_neg_mul_add" } } */ +/* { dg-final { scan-assembler "call\t(.*)flt_neg_mul_sub" } } */ +/* { dg-final { scan-assembler "call\t(.*)dbl_mul_add" } } */ +/* { dg-final { scan-assembler "call\t(.*)dbl_mul_sub" } } */ +/* { dg-final { scan-assembler "call\t(.*)dbl_neg_mul_add" } } */ +/* { dg-final { scan-assembler "call\t(.*)dbl_neg_mul_sub" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-3.c new file mode 100644 index 000000000..f3f4db76a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-3.c @@ -0,0 +1,67 @@ +/* Test whether using target specific options, we can generate popcnt by + setting the architecture. */ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -march=k8 -mno-sse3" } */ + +extern void exit (int); +extern void abort (void); + +#define SSE4A_ATTR __attribute__((__target__("arch=amdfam10"))) +#define SSE42_ATTR __attribute__((__target__("sse4.2"))) + +static int sse4a_pop_i (int a) SSE4A_ATTR; +static long sse42_pop_l (long a) SSE42_ATTR; +static int generic_pop_i (int a); +static long generic_pop_l (long a); + +static +int sse4a_pop_i (int a) +{ + return __builtin_popcount (a); +} + +static +long sse42_pop_l (long a) +{ + return __builtin_popcountl (a); +} + +static +int generic_pop_i (int a) +{ + return __builtin_popcount (a); +} + +static +long generic_pop_l (long a) +{ + return __builtin_popcountl (a); +} + +int five = 5; +long seven = 7; + +int main () +{ + if (sse4a_pop_i (five) != 2) + abort (); + + if (sse42_pop_l (seven) != 3L) + abort (); + + if (generic_pop_i (five) != 2) + abort (); + + if (generic_pop_l (seven) != 3L) + abort (); + + exit (0); +} + +/* { dg-final { scan-assembler "popcntl" { target { ! *-*-darwin* } } } } */ +/* { dg-final { scan-assembler "popcntq" { target { ! *-*-darwin* } } } } */ +/* { dg-final { scan-assembler-times "popcnt" 2 { target *-*-darwin* } } } */ +/* { dg-final { scan-assembler "call\t(.*)sse4a_pop_i" } } */ +/* { dg-final { scan-assembler "call\t(.*)sse42_pop_l" } } */ +/* { dg-final { scan-assembler "call\t(.*)popcountdi2" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-4.c new file mode 100644 index 000000000..025b97dff --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-4.c @@ -0,0 +1,14 @@ +/* Test some error conditions with function specific options. */ +/* { dg-do compile } */ + +/* no fma400 switch */ +extern void error1 (void) __attribute__((__target__("fma400"))); /* { dg-error "unknown" } */ + +/* Multiple arch switches */ +extern void error2 (void) __attribute__((__target__("arch=core2,arch=k8"))); /* { dg-error "already specified" } */ + +/* Unknown tune target */ +extern void error3 (void) __attribute__((__target__("tune=foobar"))); /* { dg-error "bad value" } */ + +/* option on a variable */ +extern int error4 __attribute__((__target__("sse2"))); /* { dg-warning "ignored" } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-5.c new file mode 100644 index 000000000..df97a2d7b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-5.c @@ -0,0 +1,131 @@ +/* Test whether all of the 32-bit function specific options are accepted + without error. */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ + +extern void test_abm (void) __attribute__((__target__("abm"))); +extern void test_aes (void) __attribute__((__target__("aes"))); +extern void test_bmi (void) __attribute__((__target__("bmi"))); +extern void test_mmx (void) __attribute__((__target__("mmx"))); +extern void test_pclmul (void) __attribute__((__target__("pclmul"))); +extern void test_popcnt (void) __attribute__((__target__("popcnt"))); +extern void test_recip (void) __attribute__((__target__("recip"))); +extern void test_sse (void) __attribute__((__target__("sse"))); +extern void test_sse2 (void) __attribute__((__target__("sse2"))); +extern void test_sse3 (void) __attribute__((__target__("sse3"))); +extern void test_sse4 (void) __attribute__((__target__("sse4"))); +extern void test_sse4_1 (void) __attribute__((__target__("sse4.1"))); +extern void test_sse4_2 (void) __attribute__((__target__("sse4.2"))); +extern void test_sse4a (void) __attribute__((__target__("sse4a"))); +extern void test_fma4 (void) __attribute__((__target__("fma4"))); +extern void test_ssse3 (void) __attribute__((__target__("ssse3"))); +extern void test_tbm (void) __attribute__((__target__("tbm"))); +extern void test_avx (void) __attribute__((__target__("avx"))); +extern void test_avx2 (void) __attribute__((__target__("avx2"))); + +extern void test_no_abm (void) __attribute__((__target__("no-abm"))); +extern void test_no_aes (void) __attribute__((__target__("no-aes"))); +extern void test_no_bmi (void) __attribute__((__target__("no-bmi"))); +extern void test_no_mmx (void) __attribute__((__target__("no-mmx"))); +extern void test_no_pclmul (void) __attribute__((__target__("no-pclmul"))); +extern void test_no_popcnt (void) __attribute__((__target__("no-popcnt"))); +extern void test_no_recip (void) __attribute__((__target__("no-recip"))); +extern void test_no_sse (void) __attribute__((__target__("no-sse"))); +extern void test_no_sse2 (void) __attribute__((__target__("no-sse2"))); +extern void test_no_sse3 (void) __attribute__((__target__("no-sse3"))); +extern void test_no_sse4 (void) __attribute__((__target__("no-sse4"))); +extern void test_no_sse4_1 (void) __attribute__((__target__("no-sse4.1"))); +extern void test_no_sse4_2 (void) __attribute__((__target__("no-sse4.2"))); +extern void test_no_sse4a (void) __attribute__((__target__("no-sse4a"))); +extern void test_no_fma4 (void) __attribute__((__target__("no-fma4"))); +extern void test_no_ssse3 (void) __attribute__((__target__("no-ssse3"))); +extern void test_no_tbm (void) __attribute__((__target__("no-tbm"))); +extern void test_no_avx (void) __attribute__((__target__("no-avx"))); +extern void test_no_avx2 (void) __attribute__((__target__("no-avx2"))); + +extern void test_arch_i386 (void) __attribute__((__target__("arch=i386"))); +extern void test_arch_i486 (void) __attribute__((__target__("arch=i486"))); +extern void test_arch_i586 (void) __attribute__((__target__("arch=i586"))); +extern void test_arch_pentium (void) __attribute__((__target__("arch=pentium"))); +extern void test_arch_pentium_mmx (void) __attribute__((__target__("arch=pentium-mmx"))); +extern void test_arch_winchip_c6 (void) __attribute__((__target__("arch=winchip-c6"))); +extern void test_arch_winchip2 (void) __attribute__((__target__("arch=winchip2"))); +extern void test_arch_c3 (void) __attribute__((__target__("arch=c3"))); +extern void test_arch_c3_2 (void) __attribute__((__target__("arch=c3-2"))); +extern void test_arch_i686 (void) __attribute__((__target__("arch=i686"))); +extern void test_arch_pentiumpro (void) __attribute__((__target__("arch=pentiumpro"))); +extern void test_arch_pentium2 (void) __attribute__((__target__("arch=pentium2"))); +extern void test_arch_pentium3 (void) __attribute__((__target__("arch=pentium3"))); +extern void test_arch_pentium3m (void) __attribute__((__target__("arch=pentium3m"))); +extern void test_arch_pentium_m (void) __attribute__((__target__("arch=pentium-m"))); +extern void test_arch_pentium4 (void) __attribute__((__target__("arch=pentium4"))); +extern void test_arch_pentium4m (void) __attribute__((__target__("arch=pentium4m"))); +extern void test_arch_prescott (void) __attribute__((__target__("arch=prescott"))); +extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona"))); +extern void test_arch_core2 (void) __attribute__((__target__("arch=core2"))); +extern void test_arch_geode (void) __attribute__((__target__("arch=geode"))); +extern void test_arch_k6 (void) __attribute__((__target__("arch=k6"))); +extern void test_arch_k6_2 (void) __attribute__((__target__("arch=k6-2"))); +extern void test_arch_k6_3 (void) __attribute__((__target__("arch=k6-3"))); +extern void test_arch_athlon (void) __attribute__((__target__("arch=athlon"))); +extern void test_arch_athlon_tbird (void) __attribute__((__target__("arch=athlon-tbird"))); +extern void test_arch_athlon_4 (void) __attribute__((__target__("arch=athlon-4"))); +extern void test_arch_athlon_xp (void) __attribute__((__target__("arch=athlon-xp"))); +extern void test_arch_athlon_mp (void) __attribute__((__target__("arch=athlon-mp"))); +extern void test_arch_k8 (void) __attribute__((__target__("arch=k8"))); +extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3"))); +extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron"))); +extern void test_arch_opteron_sse3 (void) __attribute__((__target__("arch=opteron-sse3"))); +extern void test_arch_athlon64 (void) __attribute__((__target__("arch=athlon64"))); +extern void test_arch_athlon64_sse3 (void) __attribute__((__target__("arch=athlon64-sse3"))); +extern void test_arch_athlon_fx (void) __attribute__((__target__("arch=athlon-fx"))); +extern void test_arch_amdfam10 (void) __attribute__((__target__("arch=amdfam10"))); +extern void test_arch_barcelona (void) __attribute__((__target__("arch=barcelona"))); +extern void test_arch_foo (void) __attribute__((__target__("arch=foo"))); /* { dg-error "bad value" } */ + +extern void test_tune_i386 (void) __attribute__((__target__("tune=i386"))); +extern void test_tune_i486 (void) __attribute__((__target__("tune=i486"))); +extern void test_tune_i586 (void) __attribute__((__target__("tune=i586"))); +extern void test_tune_pentium (void) __attribute__((__target__("tune=pentium"))); +extern void test_tune_pentium_mmx (void) __attribute__((__target__("tune=pentium-mmx"))); +extern void test_tune_winchip_c6 (void) __attribute__((__target__("tune=winchip-c6"))); +extern void test_tune_winchip2 (void) __attribute__((__target__("tune=winchip2"))); +extern void test_tune_c3 (void) __attribute__((__target__("tune=c3"))); +extern void test_tune_c3_2 (void) __attribute__((__target__("tune=c3-2"))); +extern void test_tune_i686 (void) __attribute__((__target__("tune=i686"))); +extern void test_tune_pentiumpro (void) __attribute__((__target__("tune=pentiumpro"))); +extern void test_tune_pentium2 (void) __attribute__((__target__("tune=pentium2"))); +extern void test_tune_pentium3 (void) __attribute__((__target__("tune=pentium3"))); +extern void test_tune_pentium3m (void) __attribute__((__target__("tune=pentium3m"))); +extern void test_tune_pentium_m (void) __attribute__((__target__("tune=pentium-m"))); +extern void test_tune_pentium4 (void) __attribute__((__target__("tune=pentium4"))); +extern void test_tune_pentium4m (void) __attribute__((__target__("tune=pentium4m"))); +extern void test_tune_prescott (void) __attribute__((__target__("tune=prescott"))); +extern void test_tune_nocona (void) __attribute__((__target__("tune=nocona"))); +extern void test_tune_core2 (void) __attribute__((__target__("tune=core2"))); +extern void test_tune_geode (void) __attribute__((__target__("tune=geode"))); +extern void test_tune_k6 (void) __attribute__((__target__("tune=k6"))); +extern void test_tune_k6_2 (void) __attribute__((__target__("tune=k6-2"))); +extern void test_tune_k6_3 (void) __attribute__((__target__("tune=k6-3"))); +extern void test_tune_athlon (void) __attribute__((__target__("tune=athlon"))); +extern void test_tune_athlon_tbird (void) __attribute__((__target__("tune=athlon-tbird"))); +extern void test_tune_athlon_4 (void) __attribute__((__target__("tune=athlon-4"))); +extern void test_tune_athlon_xp (void) __attribute__((__target__("tune=athlon-xp"))); +extern void test_tune_athlon_mp (void) __attribute__((__target__("tune=athlon-mp"))); +extern void test_tune_k8 (void) __attribute__((__target__("tune=k8"))); +extern void test_tune_k8_sse3 (void) __attribute__((__target__("tune=k8-sse3"))); +extern void test_tune_opteron (void) __attribute__((__target__("tune=opteron"))); +extern void test_tune_opteron_sse3 (void) __attribute__((__target__("tune=opteron-sse3"))); +extern void test_tune_athlon64 (void) __attribute__((__target__("tune=athlon64"))); +extern void test_tune_athlon64_sse3 (void) __attribute__((__target__("tune=athlon64-sse3"))); +extern void test_tune_athlon_fx (void) __attribute__((__target__("tune=athlon-fx"))); +extern void test_tune_amdfam10 (void) __attribute__((__target__("tune=amdfam10"))); +extern void test_tune_barcelona (void) __attribute__((__target__("tune=barcelona"))); +extern void test_tune_generic (void) __attribute__((__target__("tune=generic"))); +extern void test_tune_foo (void) __attribute__((__target__("tune=foo"))); /* { dg-error "bad value" } */ + +extern void test_fpmath_sse (void) __attribute__((__target__("sse2,fpmath=sse"))); +extern void test_fpmath_387 (void) __attribute__((__target__("sse2,fpmath=387"))); +extern void test_fpmath_sse_387 (void) __attribute__((__target__("sse2,fpmath=sse+387"))); +extern void test_fpmath_387_sse (void) __attribute__((__target__("sse2,fpmath=387+sse"))); +extern void test_fpmath_both (void) __attribute__((__target__("sse2,fpmath=both"))); diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-6.c new file mode 100644 index 000000000..e28b38c44 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-6.c @@ -0,0 +1,76 @@ +/* Test whether all of the 64-bit function specific options are accepted + without error. */ +/* { dg-do compile { target { ! { ia32 } } } } */ + +extern void test_abm (void) __attribute__((__target__("abm"))); +extern void test_aes (void) __attribute__((__target__("aes"))); +extern void test_bmi (void) __attribute__((__target__("bmi"))); +extern void test_mmx (void) __attribute__((__target__("mmx"))); +extern void test_pclmul (void) __attribute__((__target__("pclmul"))); +extern void test_popcnt (void) __attribute__((__target__("popcnt"))); +extern void test_recip (void) __attribute__((__target__("recip"))); +extern void test_sse (void) __attribute__((__target__("sse"))); +extern void test_sse2 (void) __attribute__((__target__("sse2"))); +extern void test_sse3 (void) __attribute__((__target__("sse3"))); +extern void test_sse4 (void) __attribute__((__target__("sse4"))); +extern void test_sse4_1 (void) __attribute__((__target__("sse4.1"))); +extern void test_sse4_2 (void) __attribute__((__target__("sse4.2"))); +extern void test_sse4a (void) __attribute__((__target__("sse4a"))); +extern void test_fma4 (void) __attribute__((__target__("fma4"))); +extern void test_ssse3 (void) __attribute__((__target__("ssse3"))); +extern void test_tbm (void) __attribute__((__target__("tbm"))); +extern void test_avx (void) __attribute__((__target__("avx"))); +extern void test_avx2 (void) __attribute__((__target__("avx2"))); + +extern void test_no_abm (void) __attribute__((__target__("no-abm"))); +extern void test_no_aes (void) __attribute__((__target__("no-aes"))); +extern void test_no_bmi (void) __attribute__((__target__("no-bmi"))); +extern void test_no_mmx (void) __attribute__((__target__("no-mmx"))); +extern void test_no_pclmul (void) __attribute__((__target__("no-pclmul"))); +extern void test_no_popcnt (void) __attribute__((__target__("no-popcnt"))); +extern void test_no_recip (void) __attribute__((__target__("no-recip"))); +extern void test_no_sse (void) __attribute__((__target__("no-sse"))); +extern void test_no_sse2 (void) __attribute__((__target__("no-sse2"))); +extern void test_no_sse3 (void) __attribute__((__target__("no-sse3"))); +extern void test_no_sse4 (void) __attribute__((__target__("no-sse4"))); +extern void test_no_sse4_1 (void) __attribute__((__target__("no-sse4.1"))); +extern void test_no_sse4_2 (void) __attribute__((__target__("no-sse4.2"))); +extern void test_no_sse4a (void) __attribute__((__target__("no-sse4a"))); +extern void test_no_fma4 (void) __attribute__((__target__("no-fma4"))); +extern void test_no_ssse3 (void) __attribute__((__target__("no-ssse3"))); +extern void test_no_tbm (void) __attribute__((__target__("no-tbm"))); +extern void test_no_avx (void) __attribute__((__target__("no-avx"))); +extern void test_no_avx2 (void) __attribute__((__target__("no-avx2"))); + +extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona"))); +extern void test_arch_core2 (void) __attribute__((__target__("arch=core2"))); +extern void test_arch_k8 (void) __attribute__((__target__("arch=k8"))); +extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3"))); +extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron"))); +extern void test_arch_opteron_sse3 (void) __attribute__((__target__("arch=opteron-sse3"))); +extern void test_arch_athlon64 (void) __attribute__((__target__("arch=athlon64"))); +extern void test_arch_athlon64_sse3 (void) __attribute__((__target__("arch=athlon64-sse3"))); +extern void test_arch_athlon_fx (void) __attribute__((__target__("arch=athlon-fx"))); +extern void test_arch_amdfam10 (void) __attribute__((__target__("arch=amdfam10"))); +extern void test_arch_barcelona (void) __attribute__((__target__("arch=barcelona"))); +extern void test_arch_foo (void) __attribute__((__target__("arch=foo"))); /* { dg-error "bad value" } */ + +extern void test_tune_nocona (void) __attribute__((__target__("tune=nocona"))); +extern void test_tune_core2 (void) __attribute__((__target__("tune=core2"))); +extern void test_tune_k8 (void) __attribute__((__target__("tune=k8"))); +extern void test_tune_k8_sse3 (void) __attribute__((__target__("tune=k8-sse3"))); +extern void test_tune_opteron (void) __attribute__((__target__("tune=opteron"))); +extern void test_tune_opteron_sse3 (void) __attribute__((__target__("tune=opteron-sse3"))); +extern void test_tune_athlon64 (void) __attribute__((__target__("tune=athlon64"))); +extern void test_tune_athlon64_sse3 (void) __attribute__((__target__("tune=athlon64-sse3"))); +extern void test_tune_athlon_fx (void) __attribute__((__target__("tune=athlon-fx"))); +extern void test_tune_amdfam10 (void) __attribute__((__target__("tune=amdfam10"))); +extern void test_tune_barcelona (void) __attribute__((__target__("tune=barcelona"))); +extern void test_tune_generic (void) __attribute__((__target__("tune=generic"))); +extern void test_tune_foo (void) __attribute__((__target__("tune=foo"))); /* { dg-error "bad value" } */ + +extern void test_fpmath_sse (void) __attribute__((__target__("sse2,fpmath=sse"))); +extern void test_fpmath_387 (void) __attribute__((__target__("sse2,fpmath=387"))); +extern void test_fpmath_sse_387 (void) __attribute__((__target__("sse2,fpmath=sse+387"))); +extern void test_fpmath_387_sse (void) __attribute__((__target__("sse2,fpmath=387+sse"))); +extern void test_fpmath_both (void) __attribute__((__target__("sse2,fpmath=both"))); diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-7.c new file mode 100644 index 000000000..56b549050 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-7.c @@ -0,0 +1,13 @@ +/* Test whether using target specific options, we can generate the reciprocal + square root instruction. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8 -mno-recip -mfpmath=sse -ffast-math" } */ + +float do_recip (float a) __attribute__((__target__("recip"))); +float do_normal (float a); + +float do_recip (float a) { return 1.0f / __builtin_sqrtf (a); } +float do_normal (float a) { return 1.0f / __builtin_sqrtf (a); } + +/* { dg-final { scan-assembler "sqrtss" } } */ +/* { dg-final { scan-assembler "rsqrtss" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-8.c new file mode 100644 index 000000000..225843493 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-8.c @@ -0,0 +1,162 @@ +/* Test whether using target specific options, we can use the x86 builtin + functions in functions with the appropriate function specific options. */ +/* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=k8" } } */ +/* { dg-options "-O2 -march=k8 -mno-sse3 -mfpmath=sse" } */ + +typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef int __m128w __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#ifdef __SSE3__ +#error "-msse3 should not be set for this test" +#endif + +__m128d sse3_hsubpd (__m128d a, __m128d b) __attribute__((__target__("sse3"))); +__m128d generic_hsubpd (__m128d a, __m128d b); + +__m128d +sse3_hsubpd (__m128d a, __m128d b) +{ + return __builtin_ia32_hsubpd (a, b); +} + +__m128d +generic_hsubpd (__m128d a, __m128d b) +{ + return __builtin_ia32_hsubpd (a, b); /* { dg-error "needs isa option" } */ +} + +#ifdef __SSSE3__ +#error "-mssse3 should not be set for this test" +#endif + +__m128w ssse3_psignd128 (__m128w a, __m128w b) __attribute__((__target__("ssse3"))); +__m128w generic_psignd (__m128w ab, __m128w b); + +__m128w +ssse3_psignd128 (__m128w a, __m128w b) +{ + return __builtin_ia32_psignd128 (a, b); +} + +__m128w +generic_psignd128 (__m128w a, __m128w b) +{ + return __builtin_ia32_psignd128 (a, b); /* { dg-error "needs isa option" } */ +} + +#ifdef __SSE4_1__ +#error "-msse4.1 should not be set for this test" +#endif + +__m128d sse4_1_blendvpd (__m128d a, __m128d b, __m128d c) __attribute__((__target__("sse4.1"))); +__m128d generic_blendvpd (__m128d a, __m128d b, __m128d c); + +__m128d +sse4_1_blendvpd (__m128d a, __m128d b, __m128d c) +{ + return __builtin_ia32_blendvpd (a, b, c); +} + +__m128d +generic_blendvpd (__m128d a, __m128d b, __m128d c) +{ + return __builtin_ia32_blendvpd (a, b, c); /* { dg-error "needs isa option" } */ +} + +#ifdef __SSE4_2__ +#error "-msse4.2 should not be set for this test" +#endif + +__m128i sse4_2_pcmpgtq (__m128i a, __m128i b) __attribute__((__target__("sse4.2"))); +__m128i generic_pcmpgtq (__m128i ab, __m128i b); + +__m128i +sse4_2_pcmpgtq (__m128i a, __m128i b) +{ + return __builtin_ia32_pcmpgtq (a, b); +} + +__m128i +generic_pcmpgtq (__m128i a, __m128i b) +{ + return __builtin_ia32_pcmpgtq (a, b); /* { dg-error "needs isa option" } */ +} + +#ifdef __SSE4A__ +#error "-msse4a should not be set for this test" +#endif + +__m128i sse4_2_insertq (__m128i a, __m128i b) __attribute__((__target__("sse4a"))); +__m128i generic_insertq (__m128i ab, __m128i b); + +__m128i +sse4_2_insertq (__m128i a, __m128i b) +{ + return __builtin_ia32_insertq (a, b); +} + +__m128i +generic_insertq (__m128i a, __m128i b) +{ + return __builtin_ia32_insertq (a, b); /* { dg-error "needs isa option" } */ +} + +#ifdef __FMA4__ +#error "-mfma4 should not be set for this test" +#endif + +__m128d fma4_fmaddpd (__m128d a, __m128d b, __m128d c) __attribute__((__target__("fma4"))); +__m128d generic_fmaddpd (__m128d a, __m128d b, __m128d c); + +__m128d +fma4_fmaddpd (__m128d a, __m128d b, __m128d c) +{ + return __builtin_ia32_vfmaddpd (a, b, c); +} + +__m128d +generic_fmaddpd (__m128d a, __m128d b, __m128d c) +{ + return __builtin_ia32_vfmaddpd (a, b, c); /* { dg-error "needs isa option" } */ +} + +#ifdef __AES__ +#error "-maes should not be set for this test" +#endif + +__m128i aes_aesimc128 (__m128i a) __attribute__((__target__("aes"))); +__m128i generic_aesimc128 (__m128i a); + +__m128i +aes_aesimc128 (__m128i a) +{ + return __builtin_ia32_aesimc128 (a); +} + +__m128i +generic_aesimc128 (__m128i a) +{ + return __builtin_ia32_aesimc128 (a); /* { dg-error "needs isa option" } */ +} + +#ifdef __PCLMUL__ +#error "-mpclmul should not be set for this test" +#endif + +__m128i pclmul_pclmulqdq128 (__m128i a, __m128i b) __attribute__((__target__("pclmul"))); +__m128i generic_pclmulqdq128 (__m128i a, __m128i b); + +__m128i +pclmul_pclmulqdq128 (__m128i a, __m128i b) +{ + return __builtin_ia32_pclmulqdq128 (a, b, 5); +} + +__m128i +generic_pclmulqdq128 (__m128i a, __m128i b) +{ + return __builtin_ia32_pclmulqdq128 (a, b, 5); /* { dg-error "needs isa option" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-9.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-9.c new file mode 100644 index 000000000..78714e124 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/funcspec-9.c @@ -0,0 +1,36 @@ +/* Test whether using target specific options, we can generate FMA4 code. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8 -mfpmath=sse -msse2" } */ + +extern void exit (int); + +#ifdef __FMA4__ +#warning "__FMA4__ should not be defined before #pragma GCC target." +#endif + +#pragma GCC push_options +#pragma GCC target ("fma4") + +#ifndef __FMA4__ +#warning "__FMA4__ should have be defined after #pragma GCC target." +#endif + +float +flt_mul_add (float a, float b, float c) +{ + return (a * b) + c; +} + +#pragma GCC pop_options +#ifdef __FMA4__ +#warning "__FMA4__ should not be defined after #pragma GCC pop target." +#endif + +double +dbl_mul_add (double a, double b, double c) +{ + return (a * b) + c; +} + +/* { dg-final { scan-assembler "vfmaddss" } } */ +/* { dg-final { scan-assembler "addsd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fxrstor-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fxrstor-1.c new file mode 100644 index 000000000..0e1ca191f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fxrstor-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mfxsr -O2" } */ +/* { dg-final { scan-assembler "fxrstor\[ \\t\]" } } */ + +#include <x86intrin.h> + +void extern +fxsave_test (void) +{ + char fxsave_region [512] __attribute__((aligned(16))); + _fxrstor (fxsave_region); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fxrstor64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fxrstor64-1.c new file mode 100644 index 000000000..fbdb1f6fe --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fxrstor64-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mfxsr -O2" } */ +/* { dg-final { scan-assembler "fxrstor64\[ \\t\]" } } */ + +#include <x86intrin.h> + +void extern +fxsave_test (void) +{ + char fxsave_region [512] __attribute__((aligned(16))); + _fxrstor64 (fxsave_region); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fxsave-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fxsave-1.c new file mode 100644 index 000000000..567af8d0e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fxsave-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mfxsr -O2" } */ +/* { dg-final { scan-assembler "fxsave\[ \\t\]" } } */ + +#include <x86intrin.h> + +void extern +fxsave_test (void) +{ + char fxsave_region [512] __attribute__((aligned(16))); + _fxsave (fxsave_region); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fxsave64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fxsave64-1.c new file mode 100644 index 000000000..317548ad6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/fxsave64-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mfxsr -O2" } */ +/* { dg-final { scan-assembler "fxsave64\[ \\t\]" } } */ + +#include <x86intrin.h> + +void extern +fxsave_test (void) +{ + char fxsave_region [512] __attribute__((aligned(16))); + _fxsave64 (fxsave_region); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c new file mode 100644 index 000000000..6d6ce992b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c @@ -0,0 +1,24 @@ +/* { dg-do preprocess } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */ +/* { dg-options "-march=i386" } */ + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 +#error nonono +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c new file mode 100644 index 000000000..08c4e0b85 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c @@ -0,0 +1,25 @@ +/* { dg-do preprocess } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i486" } } */ +/* { dg-options "-march=i486" } */ + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 +#error nonono +#endif + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c new file mode 100644 index 000000000..40dd9357f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c @@ -0,0 +1,23 @@ +/* { dg-do preprocess } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-march=i586" } */ + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +#error nonono +#endif + +#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 +#error nonono +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c new file mode 100644 index 000000000..ab250ddfa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c @@ -0,0 +1,22 @@ +/* { dg-do preprocess { target { ! { ia32 } } } } */ +/* { dg-options "-mcx16" } */ + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 +#error nonono +#endif + +#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 +#error nonono +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/headmerge-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/headmerge-1.c new file mode 100644 index 000000000..0c1914340 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/headmerge-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "\\\$120|, 120" 1 } } */ + +extern void foo1 (int); +extern void foo2 (int); + +void t (int x, int y) +{ + if (y < 5) + foo1 (120); + else + foo2 (120); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/headmerge-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/headmerge-2.c new file mode 100644 index 000000000..aa2e56255 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/headmerge-2.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "\\\$120|, 120" 1 } } */ + +extern void foo1 (int); +extern void foo2 (int); +extern void foo3 (int); +extern void foo4 (int); +extern void foo5 (int); +extern void foo6 (int); + +void t (int x, int y) +{ + switch (y) + { + case 1: + foo1 (120); + break; + case 5: + foo2 (120); + break; + case 7: + foo3 (120); + break; + case 10: + foo4 (120); + break; + case 13: + foo5 (120); + break; + default: + foo6 (120); + break; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-add-acq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-add-acq-1.c new file mode 100644 index 000000000..71230d52c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-add-acq-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+add" } } */ + +void +hle_add (int *p, int v) +{ + __atomic_fetch_add (p, v, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-add-rel-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-add-rel-1.c new file mode 100644 index 000000000..6b7cfc403 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-add-rel-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+add" } } */ + +void +hle_add (int *p, int v) +{ + __atomic_fetch_add (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-and-acq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-and-acq-1.c new file mode 100644 index 000000000..078f89610 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-and-acq-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+and" } } */ + +void +hle_and (int *p, int v) +{ + __atomic_fetch_and (p, v, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-and-rel-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-and-rel-1.c new file mode 100644 index 000000000..c1025f36b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-and-rel-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+and" } } */ + +void +hle_and (int *p, int v) +{ + __atomic_fetch_and (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-clear-rel.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-clear-rel.c new file mode 100644 index 000000000..137a820c8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-clear-rel.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+mov" } } */ + +void +hle_clear (char *p, int v) +{ + __atomic_clear (p, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-cmpxchg-acq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-cmpxchg-acq-1.c new file mode 100644 index 000000000..cea7c09ae --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-cmpxchg-acq-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+cmpxchg" } } */ + +int +hle_cmpxchg (int *p, int oldv, int newv) +{ + return __atomic_compare_exchange_n (p, &oldv, newv, 0, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE, __ATOMIC_ACQUIRE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-cmpxchg-rel-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-cmpxchg-rel-1.c new file mode 100644 index 000000000..a2749e82f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-cmpxchg-rel-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+cmpxchg" } } */ + +int +hle_cmpxchg (int *p, int oldv, int newv) +{ + return __atomic_compare_exchange_n (p, &oldv, newv, 0, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE, __ATOMIC_ACQUIRE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-or-acq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-or-acq-1.c new file mode 100644 index 000000000..8b28036bf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-or-acq-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+or" } } */ + +void +hle_or (int *p, int v) +{ + __atomic_or_fetch (p, 1, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-or-rel-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-or-rel-1.c new file mode 100644 index 000000000..939697a85 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-or-rel-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+or" } } */ + +void +hle_xor (int *p, int v) +{ + __atomic_fetch_or (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-store-rel.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-store-rel.c new file mode 100644 index 000000000..7295d3321 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-store-rel.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+mov" } } */ + +void +hle_store (int *p, int v) +{ + __atomic_store_n (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-sub-acq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-sub-acq-1.c new file mode 100644 index 000000000..02e94b361 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-sub-acq-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+sub" } } */ + +void +hle_sub (int *p, int v) +{ + __atomic_fetch_sub (p, v, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-sub-rel-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-sub-rel-1.c new file mode 100644 index 000000000..3a8c04e5d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-sub-rel-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+sub" } } */ + +void +hle_sub (int *p, int v) +{ + __atomic_fetch_sub (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xadd-acq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xadd-acq-1.c new file mode 100644 index 000000000..4527fa957 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xadd-acq-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+xadd" } } */ + +int +hle_xadd (int *p, int v) +{ + return __atomic_fetch_add (p, v, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xadd-rel-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xadd-rel-1.c new file mode 100644 index 000000000..dd514143f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xadd-rel-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+xadd" } } */ + +int +hle_xadd (int *p, int v) +{ + return __atomic_fetch_add (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xchg-acq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xchg-acq-1.c new file mode 100644 index 000000000..441c45470 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xchg-acq-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+xchg" } } */ + +int +hle_xchg (int *p, int v) +{ + return __atomic_exchange_n (p, v, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xchg-rel-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xchg-rel-1.c new file mode 100644 index 000000000..a6bad3335 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xchg-rel-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+xchg" } } */ + +int +hle_xchg (int *p, int v) +{ + return __atomic_exchange_n (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xor-acq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xor-acq-1.c new file mode 100644 index 000000000..d381be92c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xor-acq-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+xor" } } */ + +void +hle_xor (int *p, int v) +{ + __atomic_fetch_xor (p, v, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xor-rel-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xor-rel-1.c new file mode 100644 index 000000000..777bc0ac0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/hle-xor-rel-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mhle" } */ +/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+xor" } } */ + +void +hle_xor (int *p, int v) +{ + __atomic_fetch_xor (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/i386.exp b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/i386.exp new file mode 100644 index 000000000..15f744cf2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/i386.exp @@ -0,0 +1,328 @@ +# Copyright (C) 1997-2013 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't a x86 target. +if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Return 1 if attribute ms_hook_prologue is supported. +proc check_effective_target_ms_hook_prologue { } { + if { [check_no_compiler_messages ms_hook_prologue object { + void __attribute__ ((__ms_hook_prologue__)) foo (); + } ""] } { + return 1 + } else { + return 0 + } +} + +# Return 1 if 3dnow instructions can be compiled. +proc check_effective_target_3dnow { } { + return [check_no_compiler_messages 3dnow object { + typedef int __m64 __attribute__ ((__vector_size__ (8))); + typedef float __v2sf __attribute__ ((__vector_size__ (8))); + + __m64 _m_pfadd (__m64 __A, __m64 __B) + { + return (__m64) __builtin_ia32_pfadd ((__v2sf)__A, (__v2sf)__B); + } + } "-O2 -m3dnow" ] +} + +# Return 1 if sse3 instructions can be compiled. +proc check_effective_target_sse3 { } { + return [check_no_compiler_messages sse3 object { + typedef double __m128d __attribute__ ((__vector_size__ (16))); + typedef double __v2df __attribute__ ((__vector_size__ (16))); + + __m128d _mm_addsub_pd (__m128d __X, __m128d __Y) + { + return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y); + } + } "-O2 -msse3" ] +} + +# Return 1 if ssse3 instructions can be compiled. +proc check_effective_target_ssse3 { } { + return [check_no_compiler_messages ssse3 object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef int __v4si __attribute__ ((__vector_size__ (16))); + + __m128i _mm_abs_epi32 (__m128i __X) + { + return (__m128i) __builtin_ia32_pabsd128 ((__v4si)__X); + } + } "-O2 -mssse3" ] +} + +# Return 1 if sse4 instructions can be compiled. +proc check_effective_target_sse4 { } { + return [check_no_compiler_messages sse4.1 object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef int __v4si __attribute__ ((__vector_size__ (16))); + + __m128i _mm_mullo_epi32 (__m128i __X, __m128i __Y) + { + return (__m128i) __builtin_ia32_pmulld128 ((__v4si)__X, + (__v4si)__Y); + } + } "-O2 -msse4.1" ] +} + +# Return 1 if aes instructions can be compiled. +proc check_effective_target_aes { } { + return [check_no_compiler_messages aes object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef long long __v2di __attribute__ ((__vector_size__ (16))); + + __m128i _mm_aesimc_si128 (__m128i __X) + { + return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X); + } + } "-O2 -maes" ] +} + +# Return 1 if vaes instructions can be compiled. +proc check_effective_target_vaes { } { + return [check_no_compiler_messages vaes object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef long long __v2di __attribute__ ((__vector_size__ (16))); + + __m128i _mm_aesimc_si128 (__m128i __X) + { + return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X); + } + } "-O2 -maes -mavx" ] +} + +# Return 1 if pclmul instructions can be compiled. +proc check_effective_target_pclmul { } { + return [check_no_compiler_messages pclmul object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef long long __v2di __attribute__ ((__vector_size__ (16))); + + __m128i pclmulqdq_test (__m128i __X, __m128i __Y) + { + return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X, + (__v2di)__Y, + 1); + } + } "-O2 -mpclmul" ] +} + +# Return 1 if vpclmul instructions can be compiled. +proc check_effective_target_vpclmul { } { + return [check_no_compiler_messages vpclmul object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef long long __v2di __attribute__ ((__vector_size__ (16))); + + __m128i pclmulqdq_test (__m128i __X, __m128i __Y) + { + return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X, + (__v2di)__Y, + 1); + } + } "-O2 -mpclmul -mavx" ] +} + +# Return 1 if sse4a instructions can be compiled. +proc check_effective_target_sse4a { } { + return [check_no_compiler_messages sse4a object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef long long __v2di __attribute__ ((__vector_size__ (16))); + + __m128i _mm_insert_si64 (__m128i __X,__m128i __Y) + { + return (__m128i) __builtin_ia32_insertq ((__v2di)__X, (__v2di)__Y); + } + } "-O2 -msse4a" ] +} + +# Return 1 if fma4 instructions can be compiled. +proc check_effective_target_fma4 { } { + return [check_no_compiler_messages fma4 object { + typedef float __m128 __attribute__ ((__vector_size__ (16))); + typedef float __v4sf __attribute__ ((__vector_size__ (16))); + __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C) + { + return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A, + (__v4sf)__B, + (__v4sf)__C); + } + } "-O2 -mfma4" ] +} + +# Return 1 if fma instructions can be compiled. +proc check_effective_target_fma { } { + return [check_no_compiler_messages fma object { + typedef float __m128 __attribute__ ((__vector_size__ (16))); + typedef float __v4sf __attribute__ ((__vector_size__ (16))); + __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C) + { + return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A, + (__v4sf)__B, + (__v4sf)__C); + } + } "-O2 -mfma" ] +} + +# Return 1 if xop instructions can be compiled. +proc check_effective_target_xop { } { + return [check_no_compiler_messages xop object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef short __v8hi __attribute__ ((__vector_size__ (16))); + __m128i _mm_maccs_epi16(__m128i __A, __m128i __B, __m128i __C) + { + return (__m128i) __builtin_ia32_vpmacssww ((__v8hi)__A, + (__v8hi)__B, + (__v8hi)__C); + } + } "-O2 -mxop" ] +} + +# Return 1 if lzcnt instruction can be compiled. +proc check_effective_target_lzcnt { } { + return [check_no_compiler_messages lzcnt object { + unsigned short _lzcnt (unsigned short __X) + { + return __builtin_clzs (__X); + } + } "-mlzcnt" ] +} + +# Return 1 if avx2 instructions can be compiled. +proc check_effective_target_avx2 { } { + return [check_no_compiler_messages avx2 object { + typedef long long __v4di __attribute__ ((__vector_size__ (32))); + __v4di + mm256_is32_andnotsi256 (__v4di __X, __v4di __Y) + { + return __builtin_ia32_andnotsi256 (__X, __Y); + } + } "-O0 -mavx2" ] +} + +# Return 1 if bmi instructions can be compiled. +proc check_effective_target_bmi { } { + return [check_no_compiler_messages bmi object { + unsigned int __bextr_u32 (unsigned int __X, unsigned int __Y) + { + return __builtin_ia32_bextr_u32 (__X, __Y); + } + } "-mbmi" ] +} + +# Return 1 if bmi2 instructions can be compiled. +proc check_effective_target_bmi2 { } { + return [check_no_compiler_messages bmi2 object { + unsigned int + _bzhi_u32 (unsigned int __X, unsigned int __Y) + { + return __builtin_ia32_bzhi_si (__X, __Y); + } + } "-mbmi2" ] +} + +# Return 1 if ADX instructions can be compiled. +proc check_effective_target_adx { } { + return [check_no_compiler_messages adx object { + unsigned char + _adxcarry_u32 (unsigned char __CF, unsigned int __X, + unsigned int __Y, unsigned int *__P) + { + return __builtin_ia32_addcarryx_u32 (__CF, __X, __Y, __P); + } + } "-madx" ] +} + +# Return 1 if rtm instructions can be compiled. +proc check_effective_target_rtm { } { + return [check_no_compiler_messages rtm object { + void + _rtm_xend (void) + { + return __builtin_ia32_xend (); + } + } "-mrtm" ] +} + +# If the linker used understands -M <mapfile>, pass it to clear hardware +# capabilities set by the Sun assembler. +# Try mapfile syntax v2 first which is the only way to clear hwcap_2 flags. +set clearcap_ldflags "-Wl,-M,$srcdir/$subdir/clearcapv2.map" + +if ![check_no_compiler_messages mapfilev2 executable { + int main (void) { return 0; } +} $clearcap_ldflags ] { + # If this doesn't work, fall back to the less capable v1 syntax. + set clearcap_ldflags "-Wl,-M,$srcdir/$subdir/clearcap.map" + + if ![check_no_compiler_messages mapfile executable { + int main (void) { return 0; } + } $clearcap_ldflags ] { + unset clearcap_ldflags + } +} + +if [info exists clearcap_ldflags] { + if { [info procs gcc_target_compile] != [list] \ + && [info procs saved_gcc_target_compile] == [list] } { + rename gcc_target_compile saved_gcc_target_compile + + proc gcc_target_compile { source dest type options } { + global clearcap_ldflags + # Always pass -Wl,-M,<mapfile>, but don't let it show up in gcc.sum. + lappend options "additional_flags=$clearcap_ldflags" + + return [saved_gcc_target_compile $source $dest $type $options] + } + } +} + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize `dg'. +dg-init + +# Special case compilation of vect-args.c so we don't have to +# replicate it 10 times. +foreach type { "" -mmmx -m3dnow -msse -msse2 } { + foreach level { "" -O } { + set flags "$type $level" + verbose -log "Testing vect-args, $flags" 1 + dg-test $srcdir/$subdir/vect-args.c $flags "" + } +} + +# Everything else. +set tests [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] +set tests [prune $tests $srcdir/$subdir/vect-args.c] + +# Main loop. +dg-runtest $tests "" $DEFAULT_CFLAGS + +# All done. +dg-finish diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ifcvt-onecmpl-abs-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ifcvt-onecmpl-abs-1.c new file mode 100644 index 000000000..7d26f31c7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ifcvt-onecmpl-abs-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* This test checks for if-conversion of one's complement + * abs function. */ +/* { dg-options "-O -mtune=generic" } */ +/* { dg-final { scan-assembler "cltd" } } */ +/* { dg-final { scan-assembler "xor" } } */ + +/* Check code generation for one's complement version of abs */ + +int onecmplabs(int x) +{ + if (x < 0) + x = ~x; + return x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-1.c new file mode 100644 index 000000000..c59b208a6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-1.c @@ -0,0 +1,19 @@ +/* PR middle-end/37009 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */ + +#include <emmintrin.h> + +extern void bar (int *); + +int +foo(__m128 x, __m128 y, __m128 z, int size) +{ + int __attribute((aligned(16))) xxx; + + xxx = 2; + bar (&xxx); + return size; +} + +/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-10.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-10.c new file mode 100644 index 000000000..612fa7208 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-10.c @@ -0,0 +1,19 @@ +/* PR target/40838 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -mstackrealign -fomit-frame-pointer -O3 -march=barcelona -mpreferred-stack-boundary=4" } */ + +struct s { + int x[8]; +}; + +void g(struct s *); + +void f() +{ + int i; + struct s s; + for (i = 0; i < sizeof(s.x) / sizeof(*s.x); i++) s.x[i] = 1; + g(&s); +} + +/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-11.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-11.c new file mode 100644 index 000000000..a830c96f7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-11.c @@ -0,0 +1,18 @@ +/* PR target/40838 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -mstackrealign -fomit-frame-pointer -O3 -march=barcelona -mpreferred-stack-boundary=4" } */ + +void g(); + +int p[100]; +int q[100]; + +void f() +{ + int i; + for (i = 0; i < 100; i++) p[i] = 1; + g(); + for (i = 0; i < 100; i++) q[i] = 1; +} + +/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-12.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-12.c new file mode 100644 index 000000000..21f3f01f7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-12.c @@ -0,0 +1,20 @@ +/* PR target/40838 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */ + +typedef int v4si __attribute__ ((vector_size (16))); + +struct x { + v4si v; + v4si w; +}; + +void y(void *); + +v4si x(void) +{ + struct x x; + y(&x); +} + +/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-13.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-13.c new file mode 100644 index 000000000..cad47a9c6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-13.c @@ -0,0 +1,15 @@ +/* PR target/40838 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -mstackrealign -O2 -mpreferred-stack-boundary=4" } */ + +extern double y(double *s3); + +extern double s1, s2; + +double x(void) +{ + double s3 = s1 + s2; + return y(&s3); +} + +/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-14.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-14.c new file mode 100644 index 000000000..03ef50b69 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-14.c @@ -0,0 +1,15 @@ +/* PR target/40838 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -mstackrealign -O2 -mpreferred-stack-boundary=4" } */ + +extern int y(int *s3); + +extern int s1, s2; + +int x(void) +{ + int s3 = s1 + s2; + return y(&s3); +} + +/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-15.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-15.c new file mode 100644 index 000000000..897f3bc3c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-15.c @@ -0,0 +1,15 @@ +/* PR target/40838 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -mstackrealign -O2 -mpreferred-stack-boundary=4" } */ + +extern long long y(long long *s3); + +extern long long s1, s2; + +long long x(void) +{ + long long s3 = s1 + s2; + return y(&s3); +} + +/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-2.c new file mode 100644 index 000000000..4fc5629f0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-2.c @@ -0,0 +1,19 @@ +/* PR middle-end/37009 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */ + +#include <emmintrin.h> + +extern void bar (int *); + +int +foo(__m128 x, __m128 y, __m128 z, __m128 a, int size) +{ + int __attribute((aligned(16))) xxx; + + xxx = 2; + bar (&xxx); + return size; +} + +/* { dg-final { scan-assembler-not "and\[l\]\[ \t\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-3.c new file mode 100644 index 000000000..1d39b03f8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-3.c @@ -0,0 +1,19 @@ +/* PR middle-end/37009 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */ + +#include <emmintrin.h> + +extern void bar (int *); + +int +foo(__m128 y, int size, ...) +{ + int __attribute((aligned(16))) xxx; + + xxx = 2; + bar (&xxx); + return size; +} + +/* { dg-final { scan-assembler-not "and\[l\]\[ \t\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-4.c new file mode 100644 index 000000000..c3be961bc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-4.c @@ -0,0 +1,20 @@ +/* PR middle-end/37009 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */ + +#include <stdarg.h> +#include <emmintrin.h> + +extern void bar (int *); + +__m128 +foo(va_list arg) +{ + int __attribute((aligned(16))) xxx; + + xxx = 2; + bar (&xxx); + return va_arg (arg, __m128); +} + +/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-5.c new file mode 100644 index 000000000..9bbecdb95 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-5.c @@ -0,0 +1,16 @@ +/* PR middle-end/37009 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-m32 -mincoming-stack-boundary=2 -mpreferred-stack-boundary=2" } */ + +extern void bar (double *); + +double +foo(double x) +{ + double xxx = x + 13.0; + + bar (&xxx); + return xxx; +} + +/* { dg-final { scan-assembler "andl\[\\t \]*\\$-8,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-6.c new file mode 100644 index 000000000..a2448ec3a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-6.c @@ -0,0 +1,17 @@ +/* PR target/40838 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */ + +typedef int v4si __attribute__ ((vector_size (16))); + +extern v4si y(v4si *s3); + +extern v4si s1, s2; + +v4si x(void) +{ + v4si s3 = s1 + s2; + return y(&s3); +} + +/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-7.c new file mode 100644 index 000000000..0b8bbd570 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-7.c @@ -0,0 +1,16 @@ +/* PR target/40838 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */ + +typedef int v4si __attribute__ ((vector_size (16))); + +extern v4si y(v4si, v4si, v4si, v4si, v4si); + +extern v4si s1, s2; + +v4si x(void) +{ + return y(s1, s2, s1, s2, s2); +} + +/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-8.c new file mode 100644 index 000000000..61d9cb37d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-8.c @@ -0,0 +1,18 @@ +/* PR target/40838 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -mstackrealign -O3 -msse2 -mno-avx -mpreferred-stack-boundary=4" } */ + +float +foo (float f) +{ + float array[128]; + float x; + int i; + for (i = 0; i < sizeof(array) / sizeof(*array); i++) + array[i] = f; + for (i = 0; i < sizeof(array) / sizeof(*array); i++) + x += array[i]; + return x; +} + +/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-9.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-9.c new file mode 100644 index 000000000..178693791 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/incoming-9.c @@ -0,0 +1,18 @@ +/* PR target/40838 */ +/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */ +/* { dg-options "-w -mstackrealign -O3 -mno-sse -mpreferred-stack-boundary=4" } */ + +float +foo (float f) +{ + float array[128]; + float x; + int i; + for (i = 0; i < sizeof(array) / sizeof(*array); i++) + array[i] = f; + for (i = 0; i < sizeof(array) / sizeof(*array); i++) + x += array[i]; + return x; +} + +/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/inline-mcpy.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/inline-mcpy.c new file mode 100644 index 000000000..7eacb5f98 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/inline-mcpy.c @@ -0,0 +1,11 @@ +/* Test if we inline memcpy even with -Os, when the user requested it. */ +/* Don't name this test with memcpy in its name, otherwise the scan-assembler + would be confused. */ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-Os -minline-all-stringops" } */ +/* { dg-final { scan-assembler-not "memcpy" } } */ +char f(int i) +{ + char *ram_split[] = { "5:3", "3:1", "1:1", "3:5" }; + return ram_split[i][0]; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-1.c new file mode 100644 index 000000000..d98c14ffb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-1.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-options "-march=x86-64 -msse4" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if !defined __SSE2__ + abort (); +#endif +#if !defined __SSE3__ + abort (); +#endif +#if !defined __SSSE3__ + abort (); +#endif +#if !defined __SSE4_1__ + abort (); +#endif +#if !defined __SSE4_2__ + abort (); +#endif +#if defined __SSE4A__ + abort (); +#endif +#if defined __AVX__ + abort (); +#endif +#if defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-10.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-10.c new file mode 100644 index 000000000..5f57be913 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-10.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-march=x86-64 -mfma4 -mno-sse4" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if !defined __SSE2__ + abort (); +#endif +#if !defined __SSE3__ + abort (); +#endif +#if !defined __SSSE3__ + abort (); +#endif +#if defined __SSE4_1__ + abort (); +#endif +#if defined __SSE4_2__ + abort (); +#endif +#if !defined __SSE4A__ + abort (); +#endif +#if defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-11.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-11.c new file mode 100644 index 000000000..64755b099 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-11.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-march=x86-64 -mfma4 -mno-ssse3" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if !defined __SSE2__ + abort (); +#endif +#if !defined __SSE3__ + abort (); +#endif +#if defined __SSSE3__ + abort (); +#endif +#if defined __SSE4_1__ + abort (); +#endif +#if defined __SSE4_2__ + abort (); +#endif +#if !defined __SSE4A__ + abort (); +#endif +#if defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-12.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-12.c new file mode 100644 index 000000000..fde84a21a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-12.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-march=x86-64 -mfma4 -mno-sse3" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if !defined __SSE2__ + abort (); +#endif +#if defined __SSE3__ + abort (); +#endif +#if defined __SSSE3__ + abort (); +#endif +#if defined __SSE4_1__ + abort (); +#endif +#if defined __SSE4_2__ + abort (); +#endif +#if defined __SSE4A__ + abort (); +#endif +#if defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-13.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-13.c new file mode 100644 index 000000000..74e37d92d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-13.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-march=x86-64 -mfma4 -mno-sse2" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if defined __SSE2__ + abort (); +#endif +#if defined __SSE3__ + abort (); +#endif +#if defined __SSSE3__ + abort (); +#endif +#if defined __SSE4_1__ + abort (); +#endif +#if defined __SSE4_2__ + abort (); +#endif +#if defined __SSE4A__ + abort (); +#endif +#if defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-14.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-14.c new file mode 100644 index 000000000..5d49e6e77 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-14.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-march=x86-64 -msse4a -mfma4 -mno-sse" } */ + +extern void abort (void); + +int +main () +{ +#if defined __SSE__ + abort (); +#endif +#if defined __SSE2__ + abort (); +#endif +#if defined __SSE3__ + abort (); +#endif +#if defined __SSSE3__ + abort (); +#endif +#if defined __SSE4_1__ + abort (); +#endif +#if defined __SSE4_2__ + abort (); +#endif +#if defined __SSE4A__ + abort (); +#endif +#if defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-2.c new file mode 100644 index 000000000..aa8958c93 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-2.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-options "-march=x86-64 -msse4 -mfma4" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if !defined __SSE2__ + abort (); +#endif +#if !defined __SSE3__ + abort (); +#endif +#if !defined __SSSE3__ + abort (); +#endif +#if !defined __SSE4_1__ + abort (); +#endif +#if !defined __SSE4_2__ + abort (); +#endif +#if !defined __SSE4A__ + abort (); +#endif +#if !defined __AVX__ + abort (); +#endif +#if !defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-3.c new file mode 100644 index 000000000..a4d93f4bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-3.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-options "-march=x86-64 -msse4 -mfma4 -msse4a" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if !defined __SSE2__ + abort (); +#endif +#if !defined __SSE3__ + abort (); +#endif +#if !defined __SSSE3__ + abort (); +#endif +#if !defined __SSE4_1__ + abort (); +#endif +#if !defined __SSE4_2__ + abort (); +#endif +#if !defined __SSE4A__ + abort (); +#endif +#if !defined __AVX__ + abort (); +#endif +#if !defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-4.c new file mode 100644 index 000000000..0137257c8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-4.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-options "-march=core2 -mfma4 -mno-sse4" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if !defined __SSE2__ + abort (); +#endif +#if !defined __SSE3__ + abort (); +#endif +#if !defined __SSSE3__ + abort (); +#endif +#if defined __SSE4_1__ + abort (); +#endif +#if defined __SSE4_2__ + abort (); +#endif +#if !defined __SSE4A__ + abort (); +#endif +#if defined __AVX__ + abort (); +#endif +#if defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-5.c new file mode 100644 index 000000000..39d065e68 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-5.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-options "-march=core2 -msse4a -mno-sse4" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if !defined __SSE2__ + abort (); +#endif +#if !defined __SSE3__ + abort (); +#endif +#if !defined __SSSE3__ + abort (); +#endif +#if defined __SSE4_1__ + abort (); +#endif +#if defined __SSE4_2__ + abort (); +#endif +#if !defined __SSE4A__ + abort (); +#endif +#if defined __AVX__ + abort (); +#endif +#if defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-6.c new file mode 100644 index 000000000..a9a0ddb14 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-6.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=amdfam10" } } */ +/* { dg-options "-march=amdfam10 -mno-sse4" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if !defined __SSE2__ + abort (); +#endif +#if !defined __SSE3__ + abort (); +#endif +#if defined __SSSE3__ + abort (); +#endif +#if defined __SSE4_1__ + abort (); +#endif +#if defined __SSE4_2__ + abort (); +#endif +#if !defined __SSE4A__ + abort (); +#endif +#if defined __AVX__ + abort (); +#endif +#if defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-7.c new file mode 100644 index 000000000..8dd628e92 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-7.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-options "-march=amdfam10 -mfma4 -mno-sse4" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if !defined __SSE2__ + abort (); +#endif +#if !defined __SSE3__ + abort (); +#endif +#if !defined __SSSE3__ + abort (); +#endif +#if defined __SSE4_1__ + abort (); +#endif +#if defined __SSE4_2__ + abort (); +#endif +#if !defined __SSE4A__ + abort (); +#endif +#if defined __AVX__ + abort (); +#endif +#if defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-8.c new file mode 100644 index 000000000..2ffd80fba --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-8.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-march=amdfam10 -mfma4 -mno-sse4a" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if !defined __SSE2__ + abort (); +#endif +#if !defined __SSE3__ + abort (); +#endif +#if !defined __SSSE3__ + abort (); +#endif +#if !defined __SSE4_1__ + abort (); +#endif +#if !defined __SSE4_2__ + abort (); +#endif +#if defined __SSE4A__ + abort (); +#endif +#if defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-9.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-9.c new file mode 100644 index 000000000..b312be11e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-9.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=amdfam10" } } */ +/* { dg-options "-march=amdfam10 -mno-fma4" } */ + +extern void abort (void); + +int +main () +{ +#if !defined __SSE__ + abort (); +#endif +#if !defined __SSE2__ + abort (); +#endif +#if !defined __SSE3__ + abort (); +#endif +#if defined __SSSE3__ + abort (); +#endif +#if defined __SSE4_1__ + abort (); +#endif +#if defined __SSE4_2__ + abort (); +#endif +#if !defined __SSE4A__ + abort (); +#endif +#if defined __FMA4__ + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-check.h new file mode 100644 index 000000000..8ddbf4dfc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/isa-check.h @@ -0,0 +1,85 @@ +#include "cpuid.h" + +extern void exit (int) __attribute__((noreturn)); + +/* Determine what instruction set we've been compiled for, + and detect that we're running with it. */ +static void __attribute__((constructor)) +check_isa (void) +{ + int a, b, c, d; + int c1, d1, c1e, d1e; + + c1 = d1 = c1e = d1e = 0; + +#ifdef __MMX__ + d1 |= bit_MMX; +#endif +#ifdef __3dNOW__ + d1e |= bit_3DNOW; +#endif +#ifdef __3dNOW_A__ + d1e |= bit_3DNOWP; +#endif +#ifdef __SSE__ + d1 |= bit_SSE; +#endif +#ifdef __SSE2__ + d1 |= bit_SSE2; +#endif +#ifdef __SSE3__ + c1 |= bit_SSE3; +#endif +#ifdef __SSSE3__ + c1 |= bit_SSSE3; +#endif +#ifdef __SSE4_1__ + c1 |= bit_SSE4_1; +#endif +#ifdef __SSE4_2__ + c1 |= bit_SSE4_2; +#endif +#ifdef __AES__ + c1 |= bit_AES; +#endif +#ifdef __PCLMUL__ + c1 |= bit_PCLMUL; +#endif +#ifdef __AVX__ + c1 |= bit_AVX; +#endif +#ifdef __FMA__ + c1 |= bit_FMA; +#endif +#ifdef __SSE4A__ + c1e |= bit_SSE4a; +#endif +#ifdef __FMA4__ + c1e |= bit_FMA4; +#endif +#ifdef __XOP__ + c1e |= bit_XOP; +#endif +#ifdef __LWP__ + c1e |= bit_LWP; +#endif + + if (c1 | d1) + { + if (!__get_cpuid (1, &a, &b, &c, &d)) + goto fail; + if ((c & c1) != c1 || (d & d1) != d1) + goto fail; + } + if (c1e | d1e) + { + if (!__get_cpuid (0x80000001, &a, &b, &c, &d)) + goto fail; + if ((c & c1e) != c1e || (d & d1e) != d1e) + goto fail; + } + return; + + fail: + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_1.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_1.h new file mode 100644 index 000000000..4a0fd6e00 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_1.h @@ -0,0 +1,133 @@ + +#ifndef l_fma_1 +#define l_fma_1 + +void __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * a[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * a[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * a[i] - b[i]; +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_2.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_2.h new file mode 100644 index 000000000..fd64b61fd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_2.h @@ -0,0 +1,133 @@ + +#ifndef l_fma_2 +#define l_fma_2 + +void __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * a[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * a[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * a[i] - c[i]; +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_3.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_3.h new file mode 100644 index 000000000..226af24a0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_3.h @@ -0,0 +1,133 @@ + +#ifndef l_fma_3 +#define l_fma_3 + +void __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * b[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * b[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * b[i] - a[i]; +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_4.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_4.h new file mode 100644 index 000000000..e33fe25ff --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_4.h @@ -0,0 +1,133 @@ + +#ifndef l_fma_4 +#define l_fma_4 + +void __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * b[i] - c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * b[i] + c[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * b[i] - c[i]; +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_5.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_5.h new file mode 100644 index 000000000..a754812e3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_5.h @@ -0,0 +1,133 @@ + +#ifndef l_fma_5 +#define l_fma_5 + +void __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * c[i] - a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * c[i] + a[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * c[i] - a[i]; +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_6.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_6.h new file mode 100644 index 000000000..39be29ad3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_6.h @@ -0,0 +1,133 @@ + +#ifndef l_fma_6 +#define l_fma_6 + +void __attribute__((sseregparm)) +test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) + c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) + c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = ((a[i] * b[i]) - c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -((a[i] * b[i]) - c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) + c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) + c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = (-(a[i] * b[i]) - c[i]) * c[i] - b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * c[i] + b[i]; +} + +void __attribute__((sseregparm)) +test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n) +{ + int i; + for (i = 0; i < n; i++) + d[i] = -(-(a[i] * b[i]) - c[i]) * c[i] - b[i]; +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_1.c new file mode 100644 index 000000000..270659359 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_1.h" + +/* { dg-final { scan-assembler-times "vfmadd132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd132sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfmadd213sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfmsub213sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfnmadd213sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfnmsub213sd" 16 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_2.c new file mode 100644 index 000000000..e8933e25d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_2.h" + +/* { dg-final { scan-assembler-times "vfmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132sd" 32 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 32 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_3.c new file mode 100644 index 000000000..00c756775 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_3.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_3.h" + +/* { dg-final { scan-assembler-times "vfmadd132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231pd" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd132sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfmadd213sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfmsub213sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfnmadd213sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 16 } } */ +/* { dg-final { scan-assembler-times "vfnmsub213sd" 16 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_4.c new file mode 100644 index 000000000..09970bdb5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_4.h" + +/* { dg-final { scan-assembler-times "vfmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132sd" 32 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 32 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_5.c new file mode 100644 index 000000000..2a1428e4d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_5.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_5.h" + +/* { dg-final { scan-assembler-times "vfmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132sd" 32 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 32 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_6.c new file mode 100644 index 000000000..092032aa0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_double_6.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_6.h" + +/* { dg-final { scan-assembler-times "vfmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132sd" 32 } } */ +/* { dg-final { scan-assembler-times "vfmsub132sd" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132sd" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132sd" 32 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_1.c new file mode 100644 index 000000000..4bcd81de9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_1.h" + +/* { dg-final { scan-assembler-times "vfmadd132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfmadd213ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfmsub213ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmadd213ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmsub213ss" 32 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_2.c new file mode 100644 index 000000000..34b7fcb6d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_2.h" + +/* { dg-final { scan-assembler-times "vfmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ss" 64 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 64 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 64 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 64 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_3.c new file mode 100644 index 000000000..6ff2c6eac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_3.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_3.h" + +/* { dg-final { scan-assembler-times "vfmadd132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmsub231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmadd231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfnmsub231ps" 4 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfmadd213ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfmsub213ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmadd213ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 32 } } */ +/* { dg-final { scan-assembler-times "vfnmsub213ss" 32 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_4.c new file mode 100644 index 000000000..39548bfa7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_4.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_4.h" + +/* { dg-final { scan-assembler-times "vfmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ss" 64 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 64 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 64 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 64 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_5.c new file mode 100644 index 000000000..83d795125 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_5.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_5.h" + +/* { dg-final { scan-assembler-times "vfmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ss" 64 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 64 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 64 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 64 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_6.c new file mode 100644 index 000000000..1eefc817c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_float_6.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_6.h" + +/* { dg-final { scan-assembler-times "vfmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */ +/* { dg-final { scan-assembler-times "vfmadd132ss" 64 } } */ +/* { dg-final { scan-assembler-times "vfmsub132ss" 64 } } */ +/* { dg-final { scan-assembler-times "vfnmadd132ss" 64 } } */ +/* { dg-final { scan-assembler-times "vfnmsub132ss" 64 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_main.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_main.h new file mode 100644 index 000000000..a9dc5cd20 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_main.h @@ -0,0 +1,100 @@ + +#ifndef l_fma_main +#define l_fma_main + +#if DEBUG +#include <stdio.h> +#endif + +TYPE m1[32] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 + }; +TYPE m2[32] = { + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, + 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 + }; +TYPE m3[32] = { + 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, + 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 + }; +TYPE m4[32]; +int test_fails = 0; + +void +compare_result(char *title, TYPE *res) +{ + int i; + int good = 1; + for (i =0; i < 32; i++) + if (m4[i] != res[i]) + { + if (good) + { +#if DEBUG + printf ("!!!! %s miscompare\n", title); +#endif + good = 0; + } +#if DEBUG + printf ("res[%d] = %d, must be %d\n", i, (int)res[i], (int) m4[i]); +#endif + } + if (!good) + test_fails = 1; +} + +static void fma_test () +{ + test_noneg_add_noneg_add (m1, m2, m3, m4, 32); + compare_result ("test0000", res_test0000); + + test_noneg_add_noneg_sub (m1, m2, m3, m4, 32); + compare_result ("test0001", res_test0001); + + test_noneg_add_neg_add (m1, m2, m3, m4, 32); + compare_result ("test0010", res_test0010); + + test_noneg_add_neg_sub (m1, m2, m3, m4, 32); + compare_result ("test0011", res_test0011); + + test_noneg_sub_noneg_add (m1, m2, m3, m4, 32); + compare_result ("test0100", res_test0100); + + test_noneg_sub_noneg_sub (m1, m2, m3, m4, 32); + compare_result ("test0101", res_test0101); + + test_noneg_sub_neg_add (m1, m2, m3, m4, 32); + compare_result ("test0110", res_test0110); + + test_noneg_sub_neg_sub (m1, m2, m3, m4, 32); + compare_result ("test0111", res_test0111); + + test_neg_add_noneg_add (m1, m2, m3, m4, 32); + compare_result ("test1000", res_test1000); + + test_neg_add_noneg_sub (m1, m2, m3, m4, 32); + compare_result ("test1001", res_test1001); + + test_neg_add_neg_add (m1, m2, m3, m4, 32); + compare_result ("test1010", res_test1010); + + test_neg_add_neg_sub (m1, m2, m3, m4, 32); + compare_result ("test1011", res_test1011); + + test_neg_sub_noneg_add (m1, m2, m3, m4, 32); + compare_result ("test1100", res_test1100); + + test_neg_sub_noneg_sub (m1, m2, m3, m4, 32); + compare_result ("test1101", res_test1101); + + test_neg_sub_neg_add (m1, m2, m3, m4, 32); + compare_result ("test1110", res_test1110); + + test_neg_sub_neg_sub (m1, m2, m3, m4, 32); + compare_result ("test1111", res_test1111); + + if (test_fails) abort (); +} + +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_1.c new file mode 100644 index 000000000..f1d3c3a6b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_1.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_1.h" + +#include "fma_run_double_results_1.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_2.c new file mode 100644 index 000000000..db85598c1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_2.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_2.h" + +#include "fma_run_double_results_2.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_3.c new file mode 100644 index 000000000..8043f6fbf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_3.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_3.h" + +#include "fma_run_double_results_3.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_4.c new file mode 100644 index 000000000..eef05f58c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_4.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_4.h" + +#include "fma_run_double_results_4.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_5.c new file mode 100644 index 000000000..95b4b66d0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_5.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_5.h" + +#include "fma_run_double_results_5.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_6.c new file mode 100644 index 000000000..24c1a78cd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_double_6.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE double + +#include "l_fma_6.h" + +#include "fma_run_double_results_6.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_1.c new file mode 100644 index 000000000..8a046131d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_1.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_1.h" + +#include "fma_run_float_results_1.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_2.c new file mode 100644 index 000000000..ea6df76f1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_2.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_2.h" + +#include "fma_run_float_results_2.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_3.c new file mode 100644 index 000000000..5789867d3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_3.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_3.h" + +#include "fma_run_float_results_3.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_4.c new file mode 100644 index 000000000..377370b89 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_4.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_4.h" + +#include "fma_run_float_results_4.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_5.c new file mode 100644 index 000000000..8b0cf3f0f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_5.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_5.h" + +#include "fma_run_float_results_5.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_6.c new file mode 100644 index 000000000..1300618da --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/l_fma_run_float_6.c @@ -0,0 +1,15 @@ +/* { dg-do run } */ +/* { dg-require-effective-target fma } */ +/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */ + +/* Test that the compiler properly optimizes floating point multiply + and add instructions into FMA3 instructions. */ + +#define TYPE float + +#include "l_fma_6.h" + +#include "fma_run_float_results_6.h" + +#include "fma-check.h" +#include "l_fma_main.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/large-frame.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/large-frame.c new file mode 100644 index 000000000..2b6df1f6d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/large-frame.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-final { scan-assembler "-429496" } } */ +extern void dump (int *buf, int a); + +void func (int a) +{ + int bigbuf[1 << 30]; + dump (bigbuf, a); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/large-size-array-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/large-size-array-3.c new file mode 100644 index 000000000..07c877a93 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/large-size-array-3.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-mcmodel=medium" } */ +/* { dg-final { scan-assembler "8589934588" } } */ +int bigarray[2147483647]; diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lea.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lea.c new file mode 100644 index 000000000..bba345ef0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lea.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=pentiumpro" } } */ +/* { dg-options "-O2 -march=pentiumpro" } */ +/* { dg-final { scan-assembler "leal" } } */ +typedef struct { + char **visbuf; + char **allbuf; +} TScreen; + +void +VTallocbuf(TScreen *screen, unsigned long savelines) +{ + screen->visbuf = &screen->allbuf[savelines]; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/local.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/local.c new file mode 100644 index 000000000..4423001f6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/local.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -funit-at-a-time" } */ +/* { dg-final { scan-assembler "magic\[^\\n\]*eax" { target ia32 } } } */ +/* { dg-final { scan-assembler "magic\[^\\n\]*(edi|ecx)" { target { ! { ia32 } } } } } */ + +/* Verify that local calling convention is used. */ +static t(int) __attribute__ ((noinline)); +extern volatile int i; + +void m(void) +{ + t(i); +} + +static t(int a) +{ + asm("magic %0"::"g"(a)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-64-1.c new file mode 100644 index 000000000..cf933796f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-64-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlong-double-64" } */ + +long double +foo (long double x) +{ + return x * x; +} + +/* { dg-final { scan-assembler-not "fldt" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-64-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-64-2.c new file mode 100644 index 000000000..ddf4fe656 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-64-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -mbionic" } */ + +long double +foo (long double x) +{ + return x * x; +} + +/* { dg-final { scan-assembler-not "fldt" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-64-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-64-3.c new file mode 100644 index 000000000..e748fab2e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-64-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -mandroid" } */ + +long double +foo (long double x) +{ + return x * x; +} + +/* { dg-final { scan-assembler-not "fldt" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-64-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-64-4.c new file mode 100644 index 000000000..d9c25aaec --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-64-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlong-double-80 -mlong-double-64" } */ + +long double +foo (long double x) +{ + return x * x; +} + +/* { dg-final { scan-assembler-not "fldt" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-1.c new file mode 100644 index 000000000..d3b75a0be --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlong-double-80" } */ + +long double +foo (long double x) +{ + return x * x; +} + +/* { dg-final { scan-assembler "fldt" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-2.c new file mode 100644 index 000000000..954dfd15d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -mlong-double-80 -mbionic" } */ + +long double +foo (long double x) +{ + return x * x; +} + +/* { dg-final { scan-assembler "fldt" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-3.c new file mode 100644 index 000000000..e0e8365e3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -mlong-double-80 -mandroid" } */ + +long double +foo (long double x) +{ + return x * x; +} + +/* { dg-final { scan-assembler "fldt" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-4.c new file mode 100644 index 000000000..cac2d55bc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlong-double-64 -mlong-double-80" } */ + +long double +foo (long double x) +{ + return x * x; +} + +/* { dg-final { scan-assembler "fldt" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-5.c new file mode 100644 index 000000000..4aa606fd1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-5.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlong-double-64" } */ + +__float80 +foo (__float80 x) +{ + return x * x; +} + +/* { dg-final { scan-assembler "fldt" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-6.c new file mode 100644 index 000000000..a395a2659 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-6.c @@ -0,0 +1,11 @@ +/* { dg-do run } */ +/* { dg-options "-O0 -mlong-double-64 -mfpmath=387" } */ + +int +main () +{ + __float80 a = -0.23456789; + if ((double) a >= 0) + __builtin_abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-7.c new file mode 100644 index 000000000..e6f9cbebe --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/long-double-80-7.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-options "-O0 -mlong-double-64 -mfpmath=sse -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +static void +sse2_test (void) +{ + __float80 a = -0.23456789; + if ((double) a >= 0) + __builtin_abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/loop-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/loop-1.c new file mode 100644 index 000000000..1af62f284 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/loop-1.c @@ -0,0 +1,106 @@ +/* PR optimization/9888 */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-mtune=k6 -O3" } */ + +/* Verify that GCC doesn't emit out of range 'loop' instructions. */ + +extern void abort (void); +extern void exit (int); + + +f1 (a) + long a; +{ + int i; + for (i = 0; i < 10; i++) + { + if (--a == -1) + return i; + } + return -1; +} + +f2 (a) + long a; +{ + int i; + for (i = 0; i < 10; i++) + { + if (--a != -1) + return i; + } + return -1; +} + +f3 (a) + long a; +{ + int i; + for (i = 0; i < 10; i++) + { + if (--a == 0) + return i; + } + return -1; +} + +f4 (a) + long a; +{ + int i; + for (i = 0; i < 10; i++) + { + if (--a != 0) + return i; + } + return -1; +} + +f5 (a) + long a; +{ + int i; + for (i = 0; i < 10; i++) + { + if (++a == 0) + return i; + } + return -1; +} + +f6 (a) + long a; +{ + int i; + for (i = 0; i < 10; i++) + { + if (++a != 0) + return i; + } + return -1; +} + + +int main() +{ + if (f1 (5L) != 5) + abort (); + if (f2 (1L) != 0) + abort (); + if (f2 (0L) != 1) + abort (); + if (f3 (5L) != 4) + abort (); + if (f4 (1L) != 1) + abort (); + if (f4 (0L) != 0) + abort (); + if (f5 (-5L) != 4) + abort (); + if (f6 (-1L) != 1) + abort (); + if (f6 (0L) != 0) + abort (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/loop-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/loop-2.c new file mode 100644 index 000000000..eec71636e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/loop-2.c @@ -0,0 +1,81 @@ +/* PR optimization/9888 */ +/* Originator: Jim Bray <jb@as220.org> */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-mtune=k6 -Os" } */ + +enum reload_type +{ + RELOAD_FOR_INPUT, RELOAD_FOR_OUTPUT, RELOAD_FOR_INSN, + RELOAD_FOR_INPUT_ADDRESS, RELOAD_FOR_INPADDR_ADDRESS, + RELOAD_FOR_OUTPUT_ADDRESS, RELOAD_FOR_OUTADDR_ADDRESS, + RELOAD_FOR_OPERAND_ADDRESS, RELOAD_FOR_OPADDR_ADDR, + RELOAD_OTHER, RELOAD_FOR_OTHER_ADDRESS +}; + +#define FOO_SIZE 3 + +/* My results, varying with FOO_SIZE: + 30: asm error "value of ..fff77 too large: + 3 to 29: ....ff7d... + 1 to 2: no error. */ + +struct reload +{ + int foo[FOO_SIZE]; + int opnum; + enum reload_type when_needed; + unsigned int optional:1; + unsigned int secondary_p:1; +}; + +#define N_RELOADS 2 + +struct reload rld[N_RELOADS]; +int n_reloads = N_RELOADS; + +int main(void) +{ + int i; + + enum reload_type operand_type[1]; + + enum reload_type address_type[1]; + + int operand_reloadnum[1]; + int goal_alternative_matches[1]; + + for (i = 0; i < n_reloads; i++) + { + if (rld[i].secondary_p + && rld[i].when_needed == operand_type[rld[i].opnum]) + rld[i].when_needed = address_type[rld[i].opnum]; + + if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS + || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS + || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS + || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) + && (operand_reloadnum[rld[i].opnum] < 0 + || rld[operand_reloadnum[rld[i].opnum]].optional)) + { + + if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS + || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS) + rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR; + else + rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS; + } + + if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS + || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS) + && operand_reloadnum[rld[i].opnum] >= 0 + && (rld[operand_reloadnum[rld[i].opnum]].when_needed + == RELOAD_OTHER)) + rld[i].when_needed = RELOAD_FOR_OTHER_ADDRESS; + + if (goal_alternative_matches[rld[i].opnum] >= 0) + rld[i].opnum = goal_alternative_matches[rld[i].opnum]; + } + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/loop-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/loop-3.c new file mode 100644 index 000000000..4fcd39072 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/loop-3.c @@ -0,0 +1,80 @@ +/* PR target/11044 */ +/* Originator: Tim McGrath <misty-@charter.net> */ +/* Testcase contributed by Eric Botcazou <ebotcazou@libertysurf.fr> */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-mtune=k6 -O3 -ffast-math -funroll-loops" } */ + +extern void *memset (void *, int, __SIZE_TYPE__); +extern void abort (void); + +typedef struct +{ + unsigned char colormod; +} entity_state_t; + +typedef struct +{ + int num_entities; + entity_state_t *entities; +} packet_entities_t; + +typedef struct +{ + double senttime; + float ping_time; + packet_entities_t entities; +} client_frame_t; + +typedef enum +{ + cs_free, + cs_server, + cs_zombie, + cs_connected, + cs_spawned +} sv_client_state_t; + +typedef struct client_s +{ + sv_client_state_t state; + int ping; + client_frame_t frames[64]; +} client_t; + +int CalcPing (client_t *cl) +{ + float ping; + int count, i; + register client_frame_t *frame; + + if (cl->state == cs_server) + return cl->ping; + ping = 0; + count = 0; + for (frame = cl->frames, i = 0; i < 64; i++, frame++) { + if (frame->ping_time > 0) { + ping += frame->ping_time; + count++; + } + } + if (!count) + return 9999; + ping /= count; + + return ping * 1000; +} + +int main(void) +{ + client_t cl; + + memset(&cl, 0, sizeof(cl)); + + cl.frames[0].ping_time = 1.0f; + + if (CalcPing(&cl) != 1000) + abort(); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-1.c new file mode 100644 index 000000000..f6240d1ba --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlzcnt " } */ +/* { dg-final { scan-assembler "lzcntw\[^\\n]*(%|)ax" } } */ + +#include <x86intrin.h> + +unsigned int +func_lzcnt16 (unsigned int X) +{ + return __lzcnt16(X); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-2.c new file mode 100644 index 000000000..329a11f97 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-2.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { lzcnt } } } */ +/* { dg-options "-O2 -mlzcnt -fno-inline" } */ + +#include <x86intrin.h> + +#include "lzcnt-check.h" + +short calc_lzcnt_u16 (short src) +{ + int i; + short res = 0; + + while ((res < 16) && (((src >> (15 - res)) & 1) == 0)) + ++res; + + return res; +} + +static void +lzcnt_test () +{ + unsigned i; + short src = 0x7ace; + short res, res_ref; + + for (i=0; i<5; ++i) { + src = src >> i; + + res_ref = calc_lzcnt_u16 (src); + res = __lzcnt16 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-2a.c new file mode 100644 index 000000000..fe1069fee --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-2a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlzcnt" } */ + +#include "lzcnt-2.c" + +/* { dg-final { scan-assembler "lzcntw" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-3.c new file mode 100644 index 000000000..147795117 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mlzcnt " } */ +/* { dg-final { scan-assembler "lzcntl\[^\\n]*(%|)eax" } } */ + +#include <x86intrin.h> + +unsigned int +func_lzcnt32 (unsigned int X) +{ + return __lzcnt32(X); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-4.c new file mode 100644 index 000000000..20653265b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-4.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { lzcnt } } } */ +/* { dg-options "-O2 -mlzcnt -fno-inline" } */ + +#include <x86intrin.h> + +#include "lzcnt-check.h" + +int calc_lzcnt_u32 (int src) +{ + int i; + int res = 0; + + while ((res < 32) && (((src >> (31 - res)) & 1) == 0)) + ++res; + + return res; +} + +static void +lzcnt_test () +{ + unsigned i; + int src = 0xce7ace0; + int res, res_ref; + + for (i=0; i<5; ++i) { + src = src >> i; + + res_ref = calc_lzcnt_u32 (src); + res = __lzcnt32 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-4a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-4a.c new file mode 100644 index 000000000..6bba6a97d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-4a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlzcnt" } */ + +#include "lzcnt-4.c" + +/* { dg-final { scan-assembler "lzcntl" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-5.c new file mode 100644 index 000000000..a4b9aafcd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-5.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mlzcnt" } */ +/* { dg-final { scan-assembler "lzcntq\[^\\n]*(%|)rax" } } */ + +#include <x86intrin.h> + +unsigned int +func_lzcnt64 (unsigned long long X) +{ + return __lzcnt64(X); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-6.c new file mode 100644 index 000000000..f0bf5dab0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-6.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { lzcnt && { ! ia32 } } } } */ +/* { dg-options "-O2 -mlzcnt -fno-inline" } */ + +#include <x86intrin.h> + +#include "lzcnt-check.h" + +long long calc_lzcnt_u64 (long long src) +{ + int i; + int res = 0; + + while ((res < 64) && (((src >> (63 - res)) & 1) == 0)) + ++res; + + return res; +} + +static void +lzcnt_test () +{ + unsigned i; + long long src = 0xce7ace0ce7ace0; + long long res, res_ref; + + for (i=0; i<5; ++i) { + src = src >> i; + + res_ref = calc_lzcnt_u64 (src); + res = __lzcnt64 (src); + + if (res != res_ref) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-6a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-6a.c new file mode 100644 index 000000000..209009344 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-6a.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mlzcnt" } */ + +#include "lzcnt-6.c" + +/* { dg-final { scan-assembler "lzcntq" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-check.h new file mode 100644 index 000000000..8aad834d6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/lzcnt-check.h @@ -0,0 +1,37 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void lzcnt_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + lzcnt_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run LZCNT test only if host has LZCNT support. */ + if (ecx & bit_LZCNT) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/m128-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/m128-check.h new file mode 100644 index 000000000..4e2deecb1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/m128-check.h @@ -0,0 +1,166 @@ +#include <stdio.h> +#include <xmmintrin.h> + +#ifdef __SSE2__ +#include <emmintrin.h> + +typedef union +{ + __m128i x; + char a[16]; +} union128i_b; + +typedef union +{ + __m128i x; + unsigned char a[16]; +} union128i_ub; + +typedef union +{ + __m128i x; + short a[8]; +} union128i_w; + +typedef union +{ + __m128i x; + unsigned short a[8]; +} union128i_uw; + +typedef union +{ + __m128i x; + int a[4]; +} union128i_d; + +typedef union +{ + __m128i x; + long long a[2]; +} union128i_q; + +typedef union +{ + __m128d x; + double a[2]; +} union128d; +#endif + +typedef union +{ + __m128 x; + float a[4]; +} union128; + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(A) (sizeof (A) / sizeof ((A)[0])) +#endif + +#ifdef DEBUG +#define PRINTF printf +#else +#define PRINTF(...) +#endif + +#define CHECK_EXP(UINON_TYPE, VALUE_TYPE, FMT) \ +static int \ +__attribute__((noinline, unused)) \ +check_##UINON_TYPE (UINON_TYPE u, const VALUE_TYPE *v) \ +{ \ + int i; \ + int err = 0; \ + \ + for (i = 0; i < ARRAY_SIZE (u.a); i++) \ + if (u.a[i] != v[i]) \ + { \ + err++; \ + PRINTF ("%i: " FMT " != " FMT "\n", \ + i, v[i], u.a[i]); \ + } \ + return err; \ +} + +#ifdef __SSE2__ +CHECK_EXP (union128i_b, char, "%d") +CHECK_EXP (union128i_ub, unsigned char, "%d") +CHECK_EXP (union128i_w, short, "%d") +CHECK_EXP (union128i_uw, unsigned short, "%d") +CHECK_EXP (union128i_d, int, "0x%x") +CHECK_EXP (union128i_q, long long, "0x%llx") +CHECK_EXP (union128d, double, "%f") +#endif + +CHECK_EXP (union128, float, "%f") + +#define ESP_FLOAT 0.000001 +#define ESP_DOUBLE 0.000001 +#define CHECK_ARRAY(ARRAY, TYPE, FMT) \ +static int \ +__attribute__((noinline, unused)) \ +checkV##ARRAY (const TYPE *v, const TYPE *e, int n) \ +{ \ + int i; \ + int err = 0; \ + \ + for (i = 0; i < n; i++) \ + if (v[i] != e[i]) \ + { \ + err++; \ + PRINTF ("%i: " FMT " != " FMT "\n", \ + i, v[i], e[i]); \ + } \ + return err; \ +} + +CHECK_ARRAY(i, int, "0x%x") +CHECK_ARRAY(l, long long, "0x%llx") + +#define CHECK_FP_ARRAY(ARRAY, TYPE, ESP, FMT) \ +static int \ +__attribute__((noinline, unused)) \ +checkV##ARRAY (const TYPE *v, const TYPE *e, int n) \ +{ \ + int i; \ + int err = 0; \ + \ + for (i = 0; i < n; i++) \ + if (v[i] > (e[i] + (ESP)) || v[i] < (e[i] - (ESP))) \ + if (e[i] != v[i]) \ + { \ + err++; \ + PRINTF ("%i: " FMT " != " FMT "\n", \ + i, v[i], e[i]); \ + } \ + return err; \ +} + +CHECK_FP_ARRAY (d, double, ESP_DOUBLE, "%f") +CHECK_FP_ARRAY (f, float, ESP_FLOAT, "%f") + +#ifdef NEED_IEEE754_FLOAT +union ieee754_float +{ + float d; + struct + { + unsigned long frac : 23; + unsigned exp : 8; + unsigned sign : 1; + } bits __attribute__((packed)); +}; +#endif + +#ifdef NEED_IEEE754_DOUBLE +union ieee754_double +{ + double d; + struct + { + unsigned long frac1 : 32; + unsigned long frac0 : 20; + unsigned exp : 11; + unsigned sign : 1; + } bits __attribute__((packed)); +}; +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/m256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/m256-1.c new file mode 100644 index 000000000..a40b9e88f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/m256-1.c @@ -0,0 +1,63 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-mavx" } */ + +#include <assert.h> +#include "avx-check.h" + +__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 }; +__m256d n2 = { -93.83, 893.318, 3884.34, -3134.3 }; +__m256i n3 = { 893, -3180, 3334, -3984 }; +int n4 = -30; +double n5 = 40.3; +__m128i n6 = { 8931, -13984 }; +__m128d n7 = { 1893.318, -31134.3 }; +__m256 n8 = +{ + -913.87, 8193.518, 312884.34, -9134.9, + -19093.83, 89312.318, 7884.84, -4134.3 +}; +__m128 n9 = { -1283.3, -213.3, 3213.4, 81119.03 }; +__m128i n10 = { 28131, -313684 }; +int n11 = 103; +double n12 = -3004.3; +__m256d n13 = { 913.73, -93.38, 84.34, -734.3 }; +__m128d n14 = { -73.378, 934.31 }; +__m256 n15 = +{ + 13.73, -8193.318, 384.74, 734.9, + 193.83, 312.78, 7884.34, -8134.3 +}; +__m128i n16 = { 831, -3849 }; + +void +__attribute__((noinline)) +m256_test (__m128 a1, __m256d a2, __m256i a3, int a4, double a5, + __m128i a6, __m128d a7, __m256 a8, __m128 a9, __m128i a10, + int a11, double a12, __m256d a13, __m128d a14, __m256 a15, + __m128i a16) +{ + assert (__builtin_memcmp (&a1, &n1, sizeof (a1)) == 0); + assert (__builtin_memcmp (&a2, &n2, sizeof (a2)) == 0); + assert (__builtin_memcmp (&a3, &n3, sizeof (a3)) == 0); + assert (a4 == n4); + assert (a5 == n5); + assert (__builtin_memcmp (&a6, &n6, sizeof (a6)) == 0); + assert (__builtin_memcmp (&a7, &n7, sizeof (a7)) == 0); + assert (__builtin_memcmp (&a8, &n8, sizeof (a8)) == 0); + assert (__builtin_memcmp (&a9, &n9, sizeof (a9)) == 0); + assert (__builtin_memcmp (&a10, &n10, sizeof (a10)) == 0); + assert (a11 == n11); + assert (a12 == n12); + assert (__builtin_memcmp (&a13, &n13, sizeof (a13)) == 0); + assert (__builtin_memcmp (&a14, &n14, sizeof (a14)) == 0); + assert (__builtin_memcmp (&a15, &n15, sizeof (a15)) == 0); + assert (__builtin_memcmp (&a16, &n16, sizeof (a16)) == 0); +} + +static void +avx_test (void) +{ + m256_test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, + n13, n14, n15, n16); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/m256-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/m256-2.c new file mode 100644 index 000000000..64e38527d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/m256-2.c @@ -0,0 +1,73 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-mavx" } */ + +#include <assert.h> +#include "avx-check.h" + +struct m128 +{ + __m128 v; +}; + +struct m256d +{ + __m256d v; +}; + +struct m128 n1 = { { -283.3, -23.3, 213.4, 1119.03 } }; +struct m256d n2 = { { -93.83, 893.318, 3884.34, -3134.3 } }; +__m256i n3 = { 893, -3180, 3334, -3984 }; +int n4 = -30; +double n5 = 40.3; +__m128i n6 = { 8931, -13984 }; +__m128d n7 = { 1893.318, -31134.3 }; +__m256 n8 = +{ + -913.87, 8193.518, 312884.34, -9134.9, + -19093.83, 89312.318, 7884.84, -4134.3 +}; +__m128 n9 = { -1283.3, -213.3, 3213.4, 81119.03 }; +__m128i n10 = { 28131, -313684 }; +int n11 = 103; +double n12 = -3004.3; +struct m256d n13 = { { 913.73, -93.38, 84.34, -734.3 } }; +__m128d n14 = { -73.378, 934.31 }; +__m256 n15 = +{ + 13.73, -8193.318, 384.74, 734.9, + 193.83, 312.78, 7884.34, -8134.3 +}; +__m128i n16 = { 831, -3849 }; + +void +__attribute__((noinline)) +m256_test (struct m128 a1, struct m256d a2, __m256i a3, int a4, double a5, + __m128i a6, __m128d a7, __m256 a8, __m128 a9, __m128i a10, + int a11, double a12, struct m256d a13, __m128d a14, __m256 a15, + __m128i a16) +{ + assert (__builtin_memcmp (&a1, &n1, sizeof (a1)) == 0); + assert (__builtin_memcmp (&a2, &n2, sizeof (a2)) == 0); + assert (__builtin_memcmp (&a3, &n3, sizeof (a3)) == 0); + assert (a4 == n4); + assert (a5 == n5); + assert (__builtin_memcmp (&a6, &n6, sizeof (a6)) == 0); + assert (__builtin_memcmp (&a7, &n7, sizeof (a7)) == 0); + assert (__builtin_memcmp (&a8, &n8, sizeof (a8)) == 0); + assert (__builtin_memcmp (&a9, &n9, sizeof (a9)) == 0); + assert (__builtin_memcmp (&a10, &n10, sizeof (a10)) == 0); + assert (a11 == n11); + assert (a12 == n12); + assert (__builtin_memcmp (&a13, &n13, sizeof (a13)) == 0); + assert (__builtin_memcmp (&a14, &n14, sizeof (a14)) == 0); + assert (__builtin_memcmp (&a15, &n15, sizeof (a15)) == 0); + assert (__builtin_memcmp (&a16, &n16, sizeof (a16)) == 0); +} + +static void +avx_test (void) +{ + m256_test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, + n13, n14, n15, n16); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/m256-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/m256-check.h new file mode 100644 index 000000000..e1843550e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/m256-check.h @@ -0,0 +1,73 @@ +#include <immintrin.h> +#include "m128-check.h" + +#ifndef max +#define max(a, b) (((a) > (b)) ? (a):(b)) +#endif +#ifndef min +#define min(a, b) (((a) < (b)) ? (a):(b)) +#endif + +typedef union +{ + __m256i x; + char a[32]; +} union256i_b; + +typedef union +{ + __m256i x; + short a[16]; +} union256i_w; + +typedef union +{ + __m256i x; + int a[8]; +} union256i_d; + +typedef union +{ + __m256i x; + long long a[4]; +} union256i_q; + +typedef union +{ + __m256 x; + float a[8]; +} union256; + +typedef union +{ + __m256d x; + double a[4]; +} union256d; + +CHECK_EXP (union256i_b, char, "%d") +CHECK_EXP (union256i_w, short, "%d") +CHECK_EXP (union256i_d, int, "0x%x") +CHECK_EXP (union256i_q, long long, "0x%llx") +CHECK_EXP (union256, float, "%f") +CHECK_EXP (union256d, double, "%f") + +#define CHECK_FP_EXP(UINON_TYPE, VALUE_TYPE, ESP, FMT) \ +static int \ +__attribute__((noinline, unused)) \ +check_fp_##UINON_TYPE (UINON_TYPE u, const VALUE_TYPE *v) \ +{ \ + int i; \ + int err = 0; \ + \ + for (i = 0; i < ARRAY_SIZE (u.a); i++) \ + if (u.a[i] > (v[i] + (ESP)) || u.a[i] < (v[i] - (ESP))) \ + { \ + err++; \ + PRINTF ("%i: " FMT " != " FMT "\n", \ + i, v[i], u.a[i]); \ + } \ + return err; \ +} + +CHECK_FP_EXP (union256, float, ESP_FLOAT, "%f") +CHECK_FP_EXP (union256d, double, ESP_DOUBLE, "%f") diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/ceil.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/ceil.c new file mode 100644 index 000000000..dfccd7af4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/ceil.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ + +float testlf (float x) +{ + return __builtin_ceilf (x); +} +double testl (double x) +{ + return __builtin_ceil (x); +} +long double testll (long double x) +{ + return __builtin_ceill (x); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/floor.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/floor.c new file mode 100644 index 000000000..0c3aa9156 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/floor.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ + +float testlf (float x) +{ + return __builtin_floorf (x); +} +double testl (double x) +{ + return __builtin_floor (x); +} +long double testll (long double x) +{ + return __builtin_floorl (x); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/lceil.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/lceil.c new file mode 100644 index 000000000..d09847904 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/lceil.c @@ -0,0 +1,26 @@ +/* { dg-do assemble } */ + +long testlf (float x) +{ + return __builtin_lceilf (x); +} +long testl (double x) +{ + return __builtin_lceil (x); +} +long testll (long double x) +{ + return __builtin_lceill (x); +} +long long testllf (float x) +{ + return __builtin_llceilf (x); +} +long long testll_ (double x) +{ + return __builtin_llceil (x); +} +long long testlll (long double x) +{ + return __builtin_llceill (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/lfloor.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/lfloor.c new file mode 100644 index 000000000..2c2e96f2e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/lfloor.c @@ -0,0 +1,26 @@ +/* { dg-do assemble } */ + +long testlf (float x) +{ + return __builtin_lfloorf (x); +} +long testl (double x) +{ + return __builtin_lfloor (x); +} +long testll (long double x) +{ + return __builtin_lfloorl (x); +} +long long testllf (float x) +{ + return __builtin_llfloorf (x); +} +long long testll_ (double x) +{ + return __builtin_llfloor (x); +} +long long testlll (long double x) +{ + return __builtin_llfloorl (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/lrint.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/lrint.c new file mode 100644 index 000000000..73b75b7ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/lrint.c @@ -0,0 +1,26 @@ +/* { dg-do assemble } */ + +long testlf (float x) +{ + return __builtin_lrintf (x); +} +long testl (double x) +{ + return __builtin_lrint (x); +} +long testll (long double x) +{ + return __builtin_lrintl (x); +} +long long testllf (float x) +{ + return __builtin_llrintf (x); +} +long long testll_ (double x) +{ + return __builtin_llrint (x); +} +long long testlll (long double x) +{ + return __builtin_llrintl (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/lround.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/lround.c new file mode 100644 index 000000000..756356d62 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/lround.c @@ -0,0 +1,26 @@ +/* { dg-do assemble } */ + +long testlf (float x) +{ + return __builtin_lroundf (x); +} +long testl (double x) +{ + return __builtin_lround (x); +} +long testll (long double x) +{ + return __builtin_lroundl (x); +} +long long testllf (float x) +{ + return __builtin_llroundf (x); +} +long long testll_ (double x) +{ + return __builtin_llround (x); +} +long long testlll (long double x) +{ + return __builtin_llroundl (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp new file mode 100644 index 000000000..bea35516c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp @@ -0,0 +1,70 @@ +# Copyright (C) 2006-2013 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# This harness is for tests that should be run at all optimisation levels. + +load_lib target-supports.exp + +# Exit immediately if this isn't a x86 target. +if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then { + return +} + +set MATH_TORTURE_OPTIONS [list \ + { -O0 } \ + { -O0 -mfpmath=387 } \ + { -O0 -mfpmath=387 -ffast-math } \ + { -O2 } \ + { -O2 -mfpmath=387 } \ + { -O2 -mfpmath=387 -ffast-math } \ +] + +if { [check_effective_target_sse] } { + lappend MATH_TORTURE_OPTIONS \ + { -O0 -msse -mno-sse2 -mfpmath=sse } \ + { -O0 -msse -mno-sse2 -mfpmath=sse,387 } \ + { -O0 -msse -mno-sse2 -mfpmath=sse -ffast-math } \ + { -O0 -msse -mno-sse2 -mfpmath=sse,387 -ffast-math } \ + { -O2 -msse -mno-sse2 -mfpmath=sse } \ + { -O2 -msse -mno-sse2 -mfpmath=sse,387 } \ + { -O2 -msse -mno-sse2 -mfpmath=sse -ffast-math } \ + { -O2 -msse -mno-sse2 -mfpmath=sse,387 -ffast-math } \ +} + +if { [check_effective_target_sse2] } { + lappend MATH_TORTURE_OPTIONS \ + { -O0 -msse -msse2 -mfpmath=sse } \ + { -O0 -msse -msse2 -mfpmath=sse,387 } \ + { -O0 -msse -msse2 -mfpmath=sse -ffast-math } \ + { -O0 -msse -msse2 -mfpmath=sse,387 -ffast-math } \ + { -O2 -msse -msse2 -mfpmath=sse } \ + { -O2 -msse -msse2 -mfpmath=sse,387 } \ + { -O2 -msse -msse2 -mfpmath=sse -ffast-math } \ + { -O2 -msse -msse2 -mfpmath=sse,387 -ffast-math } \ +} + +load_lib gcc-dg.exp +load_lib torture-options.exp + +torture-init +set-torture-options $MATH_TORTURE_OPTIONS {{}} $LTO_TORTURE_OPTIONS + +dg-init +gcc-dg-runtest [lsort [glob $srcdir/$subdir/*.c]] "" +torture-finish +dg-finish diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/nearbyint.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/nearbyint.c new file mode 100644 index 000000000..dd646f012 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/nearbyint.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ + +float testlf (float x) +{ + return __builtin_nearbyintf (x); +} +double testl (double x) +{ + return __builtin_nearbyint (x); +} +long double testll (long double x) +{ + return __builtin_nearbyintl (x); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/rint.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/rint.c new file mode 100644 index 000000000..f9dfff7ca --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/rint.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ + +float testlf (float x) +{ + return __builtin_rintf (x); +} +double testl (double x) +{ + return __builtin_rint (x); +} +long double testll (long double x) +{ + return __builtin_rintl (x); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/round.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/round.c new file mode 100644 index 000000000..fddac7abb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/round.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ + +float testlf (float x) +{ + return __builtin_roundf (x); +} +double testl (double x) +{ + return __builtin_round (x); +} +long double testll (long double x) +{ + return __builtin_roundl (x); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/trunc.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/trunc.c new file mode 100644 index 000000000..a71e026c5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/math-torture/trunc.c @@ -0,0 +1,14 @@ +/* { dg-do assemble } */ + +float testlf (float x) +{ + return __builtin_truncf (x); +} +double testl (double x) +{ + return __builtin_trunc (x); +} +long double testll (long double x) +{ + return __builtin_truncl (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/max-stack-align.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/max-stack-align.c new file mode 100644 index 000000000..9f37a63e0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/max-stack-align.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-fomit-frame-pointer" } */ + +void foo() +{ + int a=0, b=0, c=0, e=0, f=0, g=0, h=0, i=0; + __asm__ __volatile__ ("" + : + : + : "bp" + ); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/memcpy-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/memcpy-1.c new file mode 100644 index 000000000..bc6f95ab6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/memcpy-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=pentiumpro -minline-all-stringops" } */ +/* { dg-final { scan-assembler "rep" } } */ +/* { dg-final { scan-assembler "movs" } } */ +/* { dg-final { scan-assembler-not "test" } } */ +/* { dg-final { scan-assembler "\.L?:" } } */ + +/* A and B are aligned, but we used to lose track of it. + Ensure that memcpy is inlined and alignment prologue is missing. */ + +char a[2048]; +char b[2048]; +t() +{ + __builtin_memcpy (a,b,2048); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/memset-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/memset-1.c new file mode 100644 index 000000000..eaf3230ec --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/memset-1.c @@ -0,0 +1,104 @@ +/* Copyright (C) 2002, 2005 Free Software Foundation. + + Test -minline-all-stringops memset with various combinations of pointer + alignments and lengths to make sure builtin optimizations are correct. + PR target/6456. + + Written by Michael Meissner, March 9, 2002. + Target by Roger Sayle, April 25, 2002. */ + +/* { dg-do run } */ +/* { dg-options "-O2 -minline-all-stringops" } */ + +extern void *memset (void *, int, __SIZE_TYPE__); +extern void abort (void); +extern void exit (int); + +#ifndef MAX_OFFSET +#define MAX_OFFSET (sizeof (long long)) +#endif + +#ifndef MAX_COPY +#define MAX_COPY (8 * sizeof (long long)) +#endif + +#ifndef MAX_EXTRA +#define MAX_EXTRA (sizeof (long long)) +#endif + +#define MAX_LENGTH (MAX_OFFSET + MAX_COPY + MAX_EXTRA) + +static union { + char buf[MAX_LENGTH]; + long long align_int; + long double align_fp; +} u; + +char A = 'A'; + +main () +{ + int off, len, i; + char *p, *q; + + for (off = 0; off < MAX_OFFSET; off++) + for (len = 1; len < MAX_COPY; len++) + { + for (i = 0; i < MAX_LENGTH; i++) + u.buf[i] = 'a'; + + p = memset (u.buf + off, '\0', len); + if (p != u.buf + off) + abort (); + + q = u.buf; + for (i = 0; i < off; i++, q++) + if (*q != 'a') + abort (); + + for (i = 0; i < len; i++, q++) + if (*q != '\0') + abort (); + + for (i = 0; i < MAX_EXTRA; i++, q++) + if (*q != 'a') + abort (); + + p = memset (u.buf + off, A, len); + if (p != u.buf + off) + abort (); + + q = u.buf; + for (i = 0; i < off; i++, q++) + if (*q != 'a') + abort (); + + for (i = 0; i < len; i++, q++) + if (*q != 'A') + abort (); + + for (i = 0; i < MAX_EXTRA; i++, q++) + if (*q != 'a') + abort (); + + p = memset (u.buf + off, 'B', len); + if (p != u.buf + off) + abort (); + + q = u.buf; + for (i = 0; i < off; i++, q++) + if (*q != 'a') + abort (); + + for (i = 0; i < len; i++, q++) + if (*q != 'B') + abort (); + + for (i = 0; i < MAX_EXTRA; i++, q++) + if (*q != 'a') + abort (); + } + + exit(0); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/minmax-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/minmax-1.c new file mode 100644 index 000000000..ca7fb6a91 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/minmax-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=opteron" } */ +/* { dg-final { scan-assembler "test" } } */ +/* { dg-final { scan-assembler-not "cmp" } } */ +#define max(a,b) (((a) > (b))? (a) : (b)) +t(int a) +{ + return (max(a,1)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/minmax-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/minmax-2.c new file mode 100644 index 000000000..2021aaa07 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/minmax-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "test" } } */ +/* { dg-final { scan-assembler-not "cmp" } } */ +#define max(a,b) (((a) > (b))? (a) : (b)) +t(unsigned int a) +{ + return (max(a,1)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-1.c new file mode 100644 index 000000000..e304acaa3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-do compile { target { nonpic } } } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -mmmx" } */ + +/* Test that the intrinsics compile with optimization. All of them are + defined as inline functions in mmintrin.h that reference the proper + builtin functions. Defining away "extern" and "__inline" results in + all of them being compiled as proper functions. */ + +#define extern +#define __inline + +#include <mmintrin.h> diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-2.c new file mode 100644 index 000000000..d15ceb185 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -mmmx" } */ + +/* Test that the intrinsics compile without optimization. All of them are + defined as inline functions in mmintrin.h that reference the proper + builtin functions. Defining away "extern" and "__inline" results in + all of them being compiled as proper functions. */ + +#define extern +#define __inline + +#include <mmintrin.h> diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-3.c new file mode 100644 index 000000000..6022d5294 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-3.c @@ -0,0 +1,17 @@ +/* PR target/8870 */ +/* Originator: otaylor@redhat.com */ +/* { dg-do compile } */ +/* { dg-options "-O1 -mmmx -march=k8" } */ + +typedef short v4hi __attribute__ ((vector_size (8))); + +static inline v4hi cvtsi_v4hi (int i) +{ + long long tmp = i; + return (v4hi) tmp; +} + +v4hi bar (unsigned short a) +{ + return cvtsi_v4hi (a); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-3dnow-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-3dnow-check.h new file mode 100644 index 000000000..4f2f7f3ac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-3dnow-check.h @@ -0,0 +1,28 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void mmx_3dnow_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + mmx_3dnow_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run 3DNow! test only if host has 3DNow! support. */ + if (edx & bit_3DNOW) + do_test (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-4.c new file mode 100644 index 000000000..05d2b553b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-4.c @@ -0,0 +1,236 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mmmx" } */ + +#include "mmx-check.h" + +#include <mmintrin.h> +#include <string.h> + +#define SHIFT (4) + +typedef union { + __m64 v; + unsigned char c[8]; + unsigned short int s[4]; + unsigned long long t; + unsigned int u[2]; +}vecInWord; + +void mmx_tests (void) __attribute__((noinline)); +void dump64_16 (char *, char *, vecInWord); +void dump64_32 (char *, char *, vecInWord); +void dump64_64 (char *, char *, vecInWord); +int check (const char *, const char *[]); + +char buf[8000]; +char comparison[8000]; +static int errors = 0; + +vecInWord a64, b64, c64, d64, e64; +__m64 m64_16, s64, m64_32, m64_64; + +const char *reference_mmx[] = { + "_mm_srai_pi16 0012 0012 0012 0012 \n", + "_mm_sra_pi16 0012 0012 0012 0012 \n", + "_mm_srai_pi32 00123456 00123456 \n", + "_mm_sra_pi32 00123456 00123456 \n", + "_mm_srli_pi16 0012 0012 0012 0012 \n", + "_mm_srl_pi16 0012 0012 0012 0012 \n", + "_mm_srli_pi32 00123456 00123456 \n", + "_mm_srl_pi32 00123456 00123456 \n", + "_mm_srli_si64 00123456789abcde\n", + "_mm_srl_si64 00123456789abcde\n", + "_mm_slli_pi16 1230 1230 1230 1230 \n", + "_mm_sll_pi16 1230 1230 1230 1230 \n", + "_mm_slli_pi32 12345670 12345670 \n", + "_mm_sll_pi32 12345670 12345670 \n", + "_mm_slli_si64 123456789abcdef0\n", + "_mm_sll_si64 123456789abcdef0\n", + "" +}; + + +static void +mmx_test (void) +{ + d64.u[0] = 0x01234567; + d64.u[1] = 0x01234567; + + m64_32 = d64.v; + + e64.t = 0x0123456789abcdefULL; + + m64_64 = e64.v; + + a64.s[0] = 0x0123; + a64.s[1] = 0x0123; + a64.s[2] = 0x0123; + a64.s[3] = 0x0123; + + m64_16 = a64.v; + + b64.s[0] = SHIFT; + b64.s[1] = 0; + b64.s[2] = 0; + b64.s[3] = 0; + + s64 = b64.v; + + mmx_tests(); + check (buf, reference_mmx); +#ifdef DEBUG + printf ("mmx testing:\n"); + printf (buf); + printf ("\ncomparison:\n"); + printf (comparison); +#endif + buf[0] = '\0'; + + if (errors != 0) + abort (); +} + +void __attribute__((noinline)) +mmx_tests (void) +{ + /* psraw */ + c64.v = _mm_srai_pi16 (m64_16, SHIFT); + dump64_16 (buf, "_mm_srai_pi16", c64); + c64.v = _mm_sra_pi16 (m64_16, s64); + dump64_16 (buf, "_mm_sra_pi16", c64); + + /* psrad */ + c64.v = _mm_srai_pi32 (m64_32, SHIFT); + dump64_32 (buf, "_mm_srai_pi32", c64); + c64.v = _mm_sra_pi32 (m64_32, s64); + dump64_32 (buf, "_mm_sra_pi32", c64); + + /* psrlw */ + c64.v = _mm_srli_pi16 (m64_16, SHIFT); + dump64_16 (buf, "_mm_srli_pi16", c64); + c64.v = _mm_srl_pi16 (m64_16, s64); + dump64_16 (buf, "_mm_srl_pi16", c64); + + /* psrld */ + c64.v = _mm_srli_pi32 (m64_32, SHIFT); + dump64_32 (buf, "_mm_srli_pi32", c64); + c64.v = _mm_srl_pi32 (m64_32, s64); + dump64_32 (buf, "_mm_srl_pi32", c64); + + /* psrlq */ + c64.v = _mm_srli_si64 (m64_64, SHIFT); + dump64_64 (buf, "_mm_srli_si64", c64); + c64.v = _mm_srl_si64 (m64_64, s64); + dump64_64 (buf, "_mm_srl_si64", c64); + + /* psllw */ + c64.v = _mm_slli_pi16 (m64_16, SHIFT); + dump64_16 (buf, "_mm_slli_pi16", c64); + c64.v = _mm_sll_pi16 (m64_16, s64); + dump64_16 (buf, "_mm_sll_pi16", c64); + + /* pslld */ + c64.v = _mm_slli_pi32 (m64_32, SHIFT); + dump64_32 (buf, "_mm_slli_pi32", c64); + c64.v = _mm_sll_pi32 (m64_32, s64); + dump64_32 (buf, "_mm_sll_pi32", c64); + + /* psllq */ + c64.v = _mm_slli_si64 (m64_64, SHIFT); + dump64_64 (buf, "_mm_slli_si64", c64); + c64.v = _mm_sll_si64 (m64_64, s64); + dump64_64 (buf, "_mm_sll_si64", c64); +} + +void +dump64_16 (char *buf, char *name, vecInWord x) +{ + int i; + char *p = buf + strlen (buf); + + sprintf (p, "%s ", name); + p += strlen (p); + + for (i=0; i<4; i++) + { + sprintf (p, "%4.4x ", x.s[i]); + p += strlen (p); + } + strcat (p, "\n"); +} + +void +dump64_32 (char *buf, char *name, vecInWord x) +{ + int i; + char *p = buf + strlen (buf); + + sprintf (p, "%s ", name); + p += strlen (p); + + for (i=0; i<2; i++) + { + sprintf (p, "%8.8x ", x.u[i]); + p += strlen (p); + } + strcat (p, "\n"); +} + +void +dump64_64 (char *buf, char *name, vecInWord x) +{ + char *p = buf + strlen (buf); + + sprintf (p, "%s ", name); + p += strlen (p); + +#if defined(_WIN32) && !defined(__CYGWIN__) + sprintf (p, "%16.16I64x\n", x.t); +#else + sprintf (p, "%16.16llx\n", x.t); +#endif +} + +int +check (const char *input, const char *reference[]) +{ + int broken, i, j, len; + const char *p_input; + char *p_comparison; + int new_errors = 0; + + p_comparison = &comparison[0]; + p_input = input; + + for (i = 0; *reference[i] != '\0'; i++) + { + broken = 0; + len = strlen (reference[i]); + for (j = 0; j < len; j++) + { + /* Ignore the terminating NUL characters at the end of every string in 'reference[]'. */ + if (!broken && *p_input != reference[i][j]) + { + *p_comparison = '\0'; + strcat (p_comparison, " >>> "); + p_comparison += strlen (p_comparison); + new_errors++; + broken = 1; + } + *p_comparison = *p_input; + p_comparison++; + p_input++; + } + if (broken) + { + *p_comparison = '\0'; + strcat (p_comparison, "expected:\n"); + strcat (p_comparison, reference[i]); + p_comparison += strlen (p_comparison); + } + } + *p_comparison = '\0'; + strcat (p_comparison, new_errors ? "failure\n\n" : "O.K.\n\n") ; + errors += new_errors; + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-5.c new file mode 100644 index 000000000..a58fbb7b1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-5.c @@ -0,0 +1,18 @@ +/* PR rtl-optimization/17853 */ +/* Contributed by Stuart Hastings <stuart@apple.com> */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mmmx" } */ +#include <mmintrin.h> +#include <stdlib.h> + +__m64 global_mask; + +int main() +{ + __m64 zero = _mm_setzero_si64(); + __m64 mask = _mm_cmpeq_pi8( zero, zero ); + mask = _mm_unpacklo_pi8( mask, zero ); + global_mask = mask; + return 0; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-6.c new file mode 100644 index 000000000..e0bc6bdd3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-6.c @@ -0,0 +1,17 @@ +/* PR middle-end/17767 */ +/* Contributed by Volker Reichelt <reichelt@igpm.rwth-aachen.de> */ +/* { dg-do compile } */ +/* { dg-options "-O -mmmx" } */ +typedef int __m64 __attribute__ ((vector_size (8))); +typedef short __v4hi __attribute__ ((vector_size (8))); + +__m64 foo () +{ + int i; + __m64 m; + + for (i = 0; i < 2; i++) + m = (__m64) __builtin_ia32_pcmpeqw ((__v4hi) m, (__v4hi) m); + + return m; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-7.c new file mode 100644 index 000000000..683ca102d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-7.c @@ -0,0 +1,18 @@ +/* PR middle-end/26379 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mmmx" } */ + +#include <mmintrin.h> + +void +foo (__m64 *p) +{ + __m64 m; + + m = p[0]; + m = _mm_srli_pi16(m, 2); + m = _mm_slli_pi16(m, 8); + + p[0] = m; + _mm_empty(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-8.c new file mode 100644 index 000000000..c90083bab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-8.c @@ -0,0 +1,137 @@ +/* PR middle-end/37809 */ + +/* { dg-do run } */ +/* { dg-options "-O2 -mmmx" } */ + +#include <mmintrin.h> + +#include "mmx-check.h" + +// Various tests of cases where it is incorrect to optimise vectors as if they +// were integers of the same width. + +extern void abort (void); + +void __attribute__ ((noinline)) +Sshift() +{ + volatile __m64 y = (__m64) 0xffffffffll; + __m64 x = y & (__m64) 0xffffffffll; + x = _m_psradi (x, 1); + x &= (__m64) 0x80000000ll; + if (0 == (long long) x) + abort(); +} + +#define SHIFTU(F,B,S,T) \ + void F() \ + { \ + volatile __m64 y = (__m64) 0ll; \ + __m64 x = y | (__m64) (1llu << B); \ + if (S > 0) \ + x = _m_pslldi (x, S); \ + else \ + x = _m_psrldi (x, -S); \ + if (T > 0) \ + x = _m_pslldi (x, T); \ + else \ + x = _m_psrldi (x, -T); \ + x &= (__m64) (1llu << (B + S + T)); \ + if ((long long) x) \ + abort(); \ + } + +SHIFTU (shiftU1, 31, 1, -1) +SHIFTU (shiftU2, 32, -1, 1) +SHIFTU (shiftU3, 31, 1, 0) +SHIFTU (shiftU4, 32, -1, 0) + +void __attribute__ ((noinline)) +add_1() +{ + volatile long long ONE = 1; + long long one = ONE; + + __m64 a = (__m64) one; + __m64 b = (__m64) -one; + __m64 c = a + b; + if (0 == (long long) c) + abort(); +} + +void __attribute__ ((noinline)) +add_2() +{ + volatile long long ONE = 1; + long long one = ONE; + + __m64 a = (__m64) one; + __m64 b = (__m64) -one; + __m64 c = _m_paddd (a, b); + if (0 == (long long) c) + abort(); +} + +void __attribute__ ((noinline)) +mult_1() +{ + volatile __m64 y = (__m64) 0ll; + __m64 x = y | (__m64) (1ll << 32); + x = x * (__m64) 1ll; + x &= (__m64) (1ll << 32); + if (0 != (long long) x) + abort(); +} + +void __attribute__ ((noinline)) +mult_2() +{ + volatile int foo = 1; + unsigned long long one = foo & 1; + + __m64 x = (__m64) (one << 16); + x *= x; + x &= (__m64) (1ll << 32); + if (0 != (long long) x) + abort(); +} + +void __attribute__ ((noinline)) +mult_3() +{ + volatile __m64 y = (__m64) (1ll << 32); + __m64 a = y; + __m64 b = y * (__m64) 1ll; + if (((long long) a) == (long long) b) + abort(); +} + +void __attribute__ ((noinline)) +div_1() +{ + volatile __m64 y = (__m64) 0ll; + __m64 x = y | (__m64) (1ull << 32); + x |= (__m64) 1ull; + x = x / x; + if (1ll == (long long) x) + abort(); +} + + +void mmx_test (void) +{ + Sshift(); + shiftU1(); + shiftU2(); + shiftU3(); + shiftU4(); + + add_1(); + add_2(); + + mult_1(); + mult_2(); + mult_3(); + + div_1(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-check.h new file mode 100644 index 000000000..faf9b876f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mmx-check.h @@ -0,0 +1,28 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void mmx_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + mmx_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run MMX test only if host has MMX support. */ + if (edx & bit_MMX) + do_test (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mod-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mod-1.c new file mode 100644 index 000000000..a7b1a9225 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mod-1.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mtune=generic" } */ + +typedef struct { + int a; +} VCR; + +typedef struct { + VCR vcr[8]; +} VCRC; + +typedef struct { + char vcr; +} OWN; + +OWN Own[16]; + +void +f (VCRC *x, OWN *own) +{ + x[own->vcr / 8].vcr[own->vcr % 8].a--; + x[own->vcr / 8].vcr[own->vcr % 8].a = x[own->vcr / 8].vcr[own->vcr % 8].a; +} + +/* { dg-final { scan-assembler-times "idivb" 1 } } */ +/* { dg-final { scan-assembler-not "incl" } } */ +/* { dg-final { scan-assembler-not "orl" } } */ +/* { dg-final { scan-assembler-not "andb" } } */ +/* { dg-final { scan-assembler-not "jns" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/monitor.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/monitor.c new file mode 100644 index 000000000..939969f79 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/monitor.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse3" } */ + +/* Verify that they work in both 32bit and 64bit. */ + +#include <pmmintrin.h> + +void +foo (char *p, int x, int y, int z) +{ + _mm_monitor (p, y, x); + _mm_mwait (z, y); +} + +void +bar (char *p, long x, long y, long z) +{ + _mm_monitor (p, y, x); + _mm_mwait (z, y); +} + +void +foo1 (char *p) +{ + _mm_monitor (p, 0, 0); + _mm_mwait (0, 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movbe-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movbe-1.c new file mode 100644 index 000000000..391d4ad98 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movbe-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mmovbe" } */ + +extern int x; + +void +foo (int i) +{ + x = __builtin_bswap32 (i); +} + +int +bar () +{ + return __builtin_bswap32 (x); +} + +/* { dg-final { scan-assembler-times "movbe\[ \t\]" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movbe-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movbe-2.c new file mode 100644 index 000000000..b322f774a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movbe-2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mmovbe" } */ + +extern long long x; + +void +foo (long long i) +{ + x = __builtin_bswap64 (i); +} + +long long +bar () +{ + return __builtin_bswap64 (x); +} + +/* { dg-final { scan-assembler-times "movbe\[ \t\]" 4 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movbe\[ \t\]" 2 { target { ! { ia32 } } } } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movdi-rex64.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movdi-rex64.c new file mode 100644 index 000000000..f8b838810 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movdi-rex64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-fPIE" } */ +/* { dg-require-effective-target pie } */ + +char *strcpy (char *dest, const char *src); + +static __thread char buffer[25]; +const char * error_message (void) +{ + strcpy (buffer, "Unknown code "); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movq-2.c new file mode 100644 index 000000000..37194b88d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movq-2.c @@ -0,0 +1,26 @@ +/* PR target/25199 */ +/* { dg-do compile } */ +/* { dg-options "-Os -mtune=pentium4" } */ +/* { dg-require-effective-target ia32 } */ + +struct S +{ + void *p[30]; + unsigned char c[4]; +}; + +unsigned char d; + +void +foo (struct S *x) +{ + register unsigned char e __asm ("esi"); + e = x->c[3]; + __asm __volatile ("" : : "r" (e)); + e = x->c[0]; + __asm __volatile ("" : : "r" (e)); +} + +/* { dg-final { scan-assembler-not "movl\[ \t\]*123" } } */ +/* { dg-final { scan-assembler "movzbl\[ \t\]*123" } } */ +/* { dg-final { scan-assembler "mov(zb)?l\[ \t\]*120" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movq.c new file mode 100644 index 000000000..53cb42143 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movq.c @@ -0,0 +1,10 @@ +/* { dg-do compile } +/* { dg-options "-Os -march=pentium4 -mtune=prescott" } */ +/* { dg-require-effective-target ia32 } */ + +register char foo asm("edi"); +char x; +int bar() { + foo = x; +} +/* { dg-final { scan-assembler "movz" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movsd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movsd.c new file mode 100644 index 000000000..32a19e79a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movsd.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse2 -mfpmath=sse" } */ + +volatile double y; + +void +test () +{ + int z; + + for (z = 0; z < 1000; z++) + y = 1.23; +} + +/* { dg-final { scan-assembler-not "(fld|fst)" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movsi-sm-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movsi-sm-1.c new file mode 100644 index 000000000..35941405d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movsi-sm-1.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fgcse-sm -minline-all-stringops" } */ + +/* Store motion used to fail to recognize killed expressions within + parallels such as those generated for memory copying. */ + +static const char s[1024] __attribute__ ((__aligned__ (32))) + = "This is what we should get!"; + +int bug (int arg) { + char str[sizeof(s) > 4 ? sizeof(s) : 4] __attribute__ ((__aligned__ (32))); + + __builtin_memcpy (str, "Bug", 4); + + if (arg <= 2) + __builtin_memcpy (str, s, sizeof (s)); + + if (arg <= 1) + __builtin_memcpy (str, "Err", 4); + + __builtin_puts (str); + + return str[0] != s[0]; +} + +int main () { + if (bug (2)) + __builtin_abort (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movti.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movti.c new file mode 100644 index 000000000..86a0279fa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/movti.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target dfp } */ +/* { dg-options "-O -std=gnu99" } */ + +_Decimal128 test (void) +{ + return 1234123412341234.123412341234dl; +} + +/* { dg-final { scan-assembler-not "movabs" { target { ! x86_64-*-mingw* } } } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ms_hook_prologue.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ms_hook_prologue.c new file mode 100644 index 000000000..e11bcc049 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ms_hook_prologue.c @@ -0,0 +1,38 @@ +/* Test that the ms_hook_prologue attribute generates the correct code. */ + +/* { dg-do run } */ +/* { dg-require-effective-target ms_hook_prologue } */ +/* { dg-options "-O2 -fomit-frame-pointer" } */ + +int __attribute__ ((__ms_hook_prologue__)) foo () +{ + unsigned char *ptr = (unsigned char *) foo; + + /* The NOP mov must not be optimized away by optimizations. + The push %ebp, mov %esp, %ebp must not be removed by + -fomit-frame-pointer */ +#ifndef __x86_64__ + /* movl.s %edi, %edi */ + if(*ptr++ != 0x8b) return 1; + if(*ptr++ != 0xff) return 1; + /* push %ebp */ + if(*ptr++ != 0x55) return 1; + /* movl.s %esp, %ebp */ + if(*ptr++ != 0x8b) return 1; + if(*ptr++ != 0xec) return 1; +#else + /* leaq 0(%rsp), %rsp */ + if (*ptr++ != 0x48) return 1; + if (*ptr++ != 0x8d) return 1; + if (*ptr++ != 0xa4) return 1; + if (*ptr++ != 0x24) return 1; + if (ptr[0] != 0 || ptr[1] != 0 || ptr[2] != 0 || ptr[3] != 0) + return 1; +#endif + return 0; +} + +int main () +{ + return foo(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mul.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mul.c new file mode 100644 index 000000000..94f0b8dc8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/mul.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* This test checks for absolute memory operands. */ +/* { dg-require-effective-target nonpic } */ +/* { dg-options "-O2 -march=k8" } */ +/* { dg-final { scan-assembler "and\[^\\n\]*magic" } } */ + +/* Should be done as "andw $32767, magic". */ +static unsigned short magic; +void t(void) +{ + magic%=(unsigned short)0x8000U; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/nrv1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/nrv1.c new file mode 100644 index 000000000..a02823697 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/nrv1.c @@ -0,0 +1,12 @@ +/* Verify that gimple-level NRV is occurring even for SSA_NAMEs. *./ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-tree-optimized" } */ +/* { dg-require-effective-target ia32 } */ + +_Complex double foo (_Complex double x) +{ + return __builtin_cexp (x); +} + +/* { dg-final { scan-tree-dump-times "return slot optimization" 1 "optimized" } } */ +/* { dg-final { cleanup-tree-dump "optimized" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/opt-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/opt-1.c new file mode 100644 index 000000000..2585236a6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/opt-1.c @@ -0,0 +1,35 @@ +/* Test the attribute((optimize)) really works. Do this test by checking + whether we vectorize a simple loop. */ +/* { dg-do compile } */ +/* { dg-options "-O1 -msse2 -mfpmath=sse -march=k8 --param min-insn-to-prefetch-ratio=0" } */ +/* { dg-final { scan-assembler "prefetcht0" } } */ +/* { dg-final { scan-assembler "addps" } } */ +/* { dg-final { scan-assembler "subss" } } */ + +#define SIZE 10240 +float a[SIZE] __attribute__((__aligned__(32))); +float b[SIZE] __attribute__((__aligned__(32))); +float c[SIZE] __attribute__((__aligned__(32))); + +/* This should vectorize. */ +void opt3 (void) __attribute__((__optimize__(3,"unroll-all-loops,-fprefetch-loop-arrays"))); + +void +opt3 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] + c[i]; +} + +/* This should not vectorize. */ +void +not_opt3 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] - c[i]; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/opt-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/opt-2.c new file mode 100644 index 000000000..1fa18c1f9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/opt-2.c @@ -0,0 +1,38 @@ +/* Test the attribute((optimize)) really works. Do this test by checking + whether we vectorize a simple loop. */ +/* { dg-do compile } */ +/* { dg-options "-O1 -msse2 -mfpmath=sse -march=k8 --param min-insn-to-prefetch-ratio=0" } */ +/* { dg-final { scan-assembler "prefetcht0" } } */ +/* { dg-final { scan-assembler "addps" } } */ +/* { dg-final { scan-assembler "subss" } } */ + +#define SIZE 10240 +float a[SIZE] __attribute__((__aligned__(32))); +float b[SIZE] __attribute__((__aligned__(32))); +float c[SIZE] __attribute__((__aligned__(32))); + +/* This should vectorize. */ +#pragma GCC push_options +#pragma GCC optimize (3, "unroll-all-loops", "-fprefetch-loop-arrays") + +void +opt3 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] + c[i]; +} + +#pragma GCC pop_options + +/* This should not vectorize. */ +void +not_opt3 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] - c[i]; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ordcmp-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ordcmp-1.c new file mode 100644 index 000000000..a136182ac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ordcmp-1.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-final { scan-assembler "cmpordss" } } */ +/* { dg-final { scan-assembler "cmpordps" } } */ +/* { dg-final { scan-assembler "cmpordsd" } } */ +/* { dg-final { scan-assembler "cmpordpd" } } */ +/* { dg-final { scan-assembler-not "cmpunordss" } } */ +/* { dg-final { scan-assembler-not "cmpunordps" } } */ +/* { dg-final { scan-assembler-not "cmpunordsd" } } */ +/* { dg-final { scan-assembler-not "cmpunordpd" } } */ + +#include <emmintrin.h> + +__m128 +f1 (__m128 x, __m128 y) +{ + return _mm_cmpord_ss (x, y); +} + +__m128 +f2 (__m128 x, __m128 y) +{ + return _mm_cmpord_ps (x, y); +} + +__m128d +f3 (__m128d x, __m128d y) +{ + return _mm_cmpord_sd (x, y); +} + +__m128d +f4 (__m128d x, __m128d y) +{ + return _mm_cmpord_pd (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-1.c new file mode 100644 index 000000000..c2e27c9e6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fomit-frame-pointer -mtune=generic" } */ +/* { dg-final { scan-assembler "rep" { target { ! x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-not "nop" } } */ + +void +foo () +{ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-10.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-10.c new file mode 100644 index 000000000..cd65041fd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-10.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ +/* { dg-final { scan-assembler-not "nop" } } */ +/* { dg-final { scan-assembler-not "rep" } } */ + +extern void bar (); + +int +foo2 (int z, int x) +{ + if (x == 1) + { + bar (); + return z; + } + else + return x - z; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-2.c new file mode 100644 index 000000000..fe45c19d1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ +/* { dg-final { scan-assembler-times "nop" 8 { target { ! x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-times "nop" 6 { target { x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-not "rep" } } */ + +void +foo () +{ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-3.c new file mode 100644 index 000000000..43d654f3f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-3.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -fomit-frame-pointer -march=atom -fno-pic" } */ +/* { dg-final { scan-assembler-not "nop" } } */ +/* { dg-final { scan-assembler-not "rep" } } */ + +int s[8] = {1, 2, 3, 4, 5, 6, 7, 8}; +int d[8] = {11, 22, 33, 44, 55, 66, 77, 88}; + +void +foo () +{ + int i; + for (i = 0; i < 8; i++) + d[i] = s[i] + 0x1000; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-4.c new file mode 100644 index 000000000..7b198a63d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target fpic } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } { "*" } { "" } } */ +/* { dg-options "-O2 -fomit-frame-pointer -march=atom -fPIC" } */ +/* { dg-final { scan-assembler-times "nop" 8 } } */ +/* { dg-final { scan-assembler-not "rep" } } */ + +extern int bar; + +int +foo () +{ + asm volatile (""); + return bar; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-5a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-5a.c new file mode 100644 index 000000000..3a02262a0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-5a.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ +/* { dg-final { scan-assembler-times "nop" 2 } } */ +/* { dg-final { scan-assembler-not "rep" } } */ + +int +foo (int x, int y, int z) +{ + return x + y + z; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-5b.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-5b.c new file mode 100644 index 000000000..4cd034092 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-5b.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ +/* { dg-final { scan-assembler-times "nop" 4 { target { ! x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-times "nop" 2 { target { x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-not "rep" } } */ + +int +foo (int x, int y, int z) +{ + return x + y + z; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-6a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-6a.c new file mode 100644 index 000000000..97af9f9ca --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-6a.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ +/* { dg-final { scan-assembler-times "nop" 4 } } */ +/* { dg-final { scan-assembler-not "rep" } } */ + +int +foo (int x, int y) +{ + return x + y; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-6b.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-6b.c new file mode 100644 index 000000000..82a3d331c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-6b.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ +/* { dg-final { scan-assembler-times "nop" 6 { target { ! x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-times "nop" 4 { target { x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-not "rep" } } */ + +int +foo (int x, int y) +{ + return x + y; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-7.c new file mode 100644 index 000000000..a4dbd260b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-7.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ +/* { dg-final { scan-assembler-not "nop" } } */ +/* { dg-final { scan-assembler-not "rep" } } */ + +int +foo (int x, int y, int z) +{ + return x + y + z + y; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-8.c new file mode 100644 index 000000000..634cd7417 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-8.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ +/* { dg-final { scan-assembler-times "nop" 6 { target { ! x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-times "nop" 4 { target { x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-not "rep" } } */ + +int +foo (int x, int y) +{ + return y; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-9.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-9.c new file mode 100644 index 000000000..226a0932b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pad-9.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */ +/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */ +/* { dg-final { scan-assembler-times "nop" 4 { target { ! x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-times "nop" 2 { target { x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler-not "rep" } } */ + +extern void bar (void); + +void +foo (int x) +{ + if (x) + bar (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/parity-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/parity-1.c new file mode 100644 index 000000000..1b0001ef2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/parity-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8 -mno-popcnt" } */ +/* { dg-final { scan-assembler "setnp" } } */ + +int foo(unsigned int x) +{ + return __builtin_parity(x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/parity-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/parity-2.c new file mode 100644 index 000000000..9adca35a6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/parity-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8 -mno-popcnt" } */ +/* { dg-final { scan-assembler "setnp" } } */ + +int foo(unsigned long long int x) +{ + return __builtin_parityll(x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pause-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pause-1.c new file mode 100644 index 000000000..50eb8e7e2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pause-1.c @@ -0,0 +1,11 @@ +/* Test that we generate pause instruction. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -dp" } */ +/* { dg-final { scan-assembler-times "\\*pause" 1 } } */ + +#include <x86intrin.h> + +void foo(void) +{ + __pause(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h new file mode 100644 index 000000000..5eed2e220 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h @@ -0,0 +1,41 @@ +#ifdef DEBUG +#include <stdio.h> +#endif +#include <stdlib.h> +#include "cpuid.h" +#include "avx-os-support.h" + +static void pclmul_avx_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + pclmul_avx_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run PCLMUL + AVX test only if host has PCLMUL + AVX support. */ + if (((ecx & (bit_AVX | bit_OSXSAVE | bit_PCLMUL)) + == (bit_AVX | bit_OSXSAVE | bit_PCLMUL)) + && avx_os_support ()) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pclmul-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pclmul-check.h new file mode 100644 index 000000000..7526cbe2d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pclmul-check.h @@ -0,0 +1,37 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void pclmul_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + pclmul_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run PCLMULQDQ test only if host has PCLMULQDQ support. */ + if (ecx & bit_PCLMUL) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pclmulqdq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pclmulqdq.c new file mode 100644 index 000000000..1c1d2aabe --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pclmulqdq.c @@ -0,0 +1,95 @@ +/* { dg-do run } */ +/* { dg-require-effective-target pclmul } */ +/* { dg-options "-O2 -mpclmul" } */ + +#ifndef CHECK_H +#define CHECK_H "pclmul-check.h" +#endif + +#ifndef TEST +#define TEST pclmul_test +#endif + +#include CHECK_H + +#include <wmmintrin.h> +#include <string.h> + +extern void abort (void); + +#define NUM 1024 + +static __m128i s1[NUM]; +static __m128i s2[NUM]; +/* We need this array to generate mem form of inst */ +static __m128i s2m[NUM]; + +static __m128i e_00[NUM]; +static __m128i e_01[NUM]; +static __m128i e_10[NUM]; +static __m128i e_11[NUM]; + +static __m128i d_00[NUM]; +static __m128i d_01[NUM]; +static __m128i d_10[NUM]; +static __m128i d_11[NUM]; + +/* Initialize input/output vectors. (Currently, there is only one set + of input/output vectors). */ +static void +init_data (__m128i *ls1, __m128i *ls2, __m128i *le_00, __m128i *le_01, + __m128i *le_10, __m128i *le_11) +{ + int i; + + for (i = 0; i < NUM; i++) + { + ls1[i] = _mm_set_epi32 (0x7B5B5465, 0x73745665, + 0x63746F72, 0x5D53475D); + ls2[i] = _mm_set_epi32 (0x48692853, 0x68617929, + 0x5B477565, 0x726F6E5D); + s2m[i] = _mm_set_epi32 (0x48692853, 0x68617929, + 0x5B477565, 0x726F6E5D); + le_00[i] = _mm_set_epi32 (0x1D4D84C8, 0x5C3440C0, + 0x929633D5, 0xD36F0451); + le_01[i] = _mm_set_epi32 (0x1A2BF6DB, 0x3A30862F, + 0xBABF262D, 0xF4B7D5C9); + le_10[i] = _mm_set_epi32 (0x1BD17C8D, 0x556AB5A1, + 0x7FA540AC, 0x2A281315); + le_11[i] = _mm_set_epi32 (0x1D1E1F2C, 0x592E7C45, + 0xD66EE03E, 0x410FD4ED); + } +} + +static void +TEST (void) +{ + int i; + + init_data (s1, s2, e_00, e_01, e_10, e_11); + + for (i = 0; i < NUM; i += 2) + { + d_00[i] = _mm_clmulepi64_si128 (s1[i], s2m[i], 0x00); + d_01[i] = _mm_clmulepi64_si128 (s1[i], s2[i], 0x01); + d_10[i] = _mm_clmulepi64_si128 (s1[i], s2[i], 0x10); + d_11[i] = _mm_clmulepi64_si128 (s1[i], s2[i], 0x11); + + d_11[i + 1] = _mm_clmulepi64_si128 (s1[i + 1], s2[i + 1], 0x11); + d_00[i + 1] = _mm_clmulepi64_si128 (s1[i + 1], s2[i + 1], 0x00); + d_10[i + 1] = _mm_clmulepi64_si128 (s1[i + 1], s2m[i + 1], 0x10); + d_01[i + 1] = _mm_clmulepi64_si128 (s1[i + 1], s2[i + 1], 0x01); + } + + for (i = 0; i < NUM; i++) + { + if (memcmp (d_00 + i, e_00 + i, sizeof (__m128i))) + abort (); + if (memcmp (d_01 + i, e_01 + i, sizeof (__m128i))) + abort (); + if (memcmp (d_10 + i, e_10 + i, sizeof (__m128i))) + abort (); + if (memcmp(d_11 + i, e_11 + i, sizeof (__m128i))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c new file mode 100644 index 000000000..c840c47e3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=pentium4" } } */ +/* { dg-options "-O2 -march=pentium4" } */ +/* { dg-final { scan-assembler-not "imull" } } */ + +/* Should be done not using imull. */ +int t(int x) +{ + return x*29; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/perm-concat.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/perm-concat.c new file mode 100644 index 000000000..10955c207 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/perm-concat.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mavx -mfpmath=sse" } */ + +typedef double v2df __attribute__ ((__vector_size__ (16))); + +v2df +f (double d) +{ + v2df x = {-d, d}; + return __builtin_ia32_vpermilpd (x, 1); +} + +/* { dg-final { scan-assembler-not "\tvpermilpd\[ \t\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pic-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pic-1.c new file mode 100644 index 000000000..af2424b07 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pic-1.c @@ -0,0 +1,21 @@ +/* PR target/8340 */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target fpic } */ +/* { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } { "*" } { "" } } */ +/* { dg-options "-fPIC" } */ + +int foo () +{ + static int a; + + __asm__ __volatile__ ( /* { dg-error "PIC register" } */ + "xorl %%ebx, %%ebx\n" + "movl %%ebx, %0\n" + : "=m" (a) + : + : "%ebx" + ); + + return a; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pow-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pow-1.c new file mode 100644 index 000000000..2e1ac61bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pow-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O -ffast-math" } */ + +double test1 (double x) +{ + return __builtin_pow (x, 1./2.); +} + +double test2 (double x) +{ + return __builtin_pow (x, 3./2.); +} + +double test3 (double x) +{ + return __builtin_pow (x, 5./2.); +} + +double test4 (double x) +{ + return __builtin_pow (x, -5./2.); +} + +/* { dg-final { scan-assembler-not "call\[ \t\]*pow" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memcpy-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memcpy-1.c new file mode 100644 index 000000000..c63f84869 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memcpy-1.c @@ -0,0 +1,23 @@ +/* Ensure that we don't use 'rep movX' in the presence of register globals. */ +/* { dg-do compile } */ +/* { dg-options "-Os -w" } */ + +extern void *memcpy (void *, const void *, __SIZE_TYPE__); + +register int regvar asm("%esi"); + +int foo[10]; +int bar[10]; + +char baz[15]; +char quux[15]; + +void +do_copy () +{ + memcpy (foo, bar, sizeof foo); + memcpy (baz, quux, sizeof baz); +} + +/* { dg-final { scan-assembler-not "rep movsl" } } */ +/* { dg-final { scan-assembler-not "rep movsb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memcpy-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memcpy-2.c new file mode 100644 index 000000000..ae1c3a886 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memcpy-2.c @@ -0,0 +1,23 @@ +/* Ensure that we don't use 'rep movX' in the presence of register globals. */ +/* { dg-do compile } */ +/* { dg-options "-Os -w" } */ + +extern void *memcpy (void *, const void *, __SIZE_TYPE__); + +register int regvar asm("%edi"); + +int foo[10]; +int bar[10]; + +char baz[15]; +char quux[15]; + +void +do_copy () +{ + memcpy (foo, bar, sizeof foo); + memcpy (baz, quux, sizeof baz); +} + +/* { dg-final { scan-assembler-not "rep movsl" } } */ +/* { dg-final { scan-assembler-not "rep movsb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memcpy-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memcpy-3.c new file mode 100644 index 000000000..0f5bd561d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memcpy-3.c @@ -0,0 +1,23 @@ +/* Ensure that we don't use 'rep movX' in the presence of register globals. */ +/* { dg-do compile } */ +/* { dg-options "-Os -w" } */ + +extern void *memcpy (void *, const void *, __SIZE_TYPE__); + +register int regvar asm("%ecx"); + +int foo[10]; +int bar[10]; + +char baz[15]; +char quux[15]; + +void +do_copy () +{ + memcpy (foo, bar, sizeof foo); + memcpy (baz, quux, sizeof baz); +} + +/* { dg-final { scan-assembler-not "rep movsl" } } */ +/* { dg-final { scan-assembler-not "rep movsb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memset-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memset-1.c new file mode 100644 index 000000000..e44d32fb4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memset-1.c @@ -0,0 +1,23 @@ +/* Ensure that we don't use 'rep stoX' in the presence of register globals. */ +/* { dg-do compile } */ +/* { dg-options "-Os -w" } */ + +extern void *memset (void *, int, __SIZE_TYPE__); + +register int regvar asm("%eax"); + +int foo[10]; +int bar[10]; + +char baz[15]; +char quux[15]; + +void +do_copy () +{ + memset (foo, 0, sizeof foo); + memset (baz, 0, sizeof baz); +} + +/* { dg-final { scan-assembler-not "rep stosl" } } */ +/* { dg-final { scan-assembler-not "rep stosb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memset-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memset-2.c new file mode 100644 index 000000000..02fc8d319 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memset-2.c @@ -0,0 +1,23 @@ +/* Ensure that we don't use 'rep stoX' in the presence of register globals. */ +/* { dg-do compile } */ +/* { dg-options "-Os -w" } */ + +extern void *memset (void *, int, __SIZE_TYPE__); + +register int regvar asm("%ecx"); + +int foo[10]; +int bar[10]; + +char baz[15]; +char quux[15]; + +void +do_copy () +{ + memset (foo, 0, sizeof foo); + memset (baz, 0, sizeof baz); +} + +/* { dg-final { scan-assembler-not "rep stosl" } } */ +/* { dg-final { scan-assembler-not "rep stosb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memset-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memset-3.c new file mode 100644 index 000000000..1bdfb8656 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-memset-3.c @@ -0,0 +1,23 @@ +/* Ensure that we don't use 'rep stoX' in the presence of register globals. */ +/* { dg-do compile } */ +/* { dg-options "-Os -w" } */ + +extern void *memset (void *, int, __SIZE_TYPE__); + +register int regvar asm("%edi"); + +int foo[10]; +int bar[10]; + +char baz[15]; +char quux[15]; + +void +do_copy () +{ + memset (foo, 0, sizeof foo); + memset (baz, 0, sizeof baz); +} + +/* { dg-final { scan-assembler-not "rep stosl" } } */ +/* { dg-final { scan-assembler-not "rep stosb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-strlen-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-strlen-1.c new file mode 100644 index 000000000..6e159e445 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-strlen-1.c @@ -0,0 +1,16 @@ +/* Ensure that we don't use 'repnz scasb' in the presence of register globals. */ +/* { dg-do compile } */ +/* { dg-options "-O1 -w" } */ + +extern __SIZE_TYPE__ strlen (const char *); +extern void *malloc (__SIZE_TYPE__); + +register int regvar asm("%edi"); + +char * +do_copy (char *str) +{ + return malloc (strlen (str) + 1); +} + +/* { dg-final { scan-assembler-not "repnz scasb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-strlen-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-strlen-2.c new file mode 100644 index 000000000..e03adb25f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-strlen-2.c @@ -0,0 +1,16 @@ +/* Ensure that we don't use 'repnz scasb' in the presence of register globals. */ +/* { dg-do compile } */ +/* { dg-options "-O1 -w" } */ + +extern __SIZE_TYPE__ strlen (const char *); +extern void *malloc (__SIZE_TYPE__); + +register int regvar asm("%eax"); + +char * +do_copy (char *str) +{ + return malloc (strlen (str) + 1); +} + +/* { dg-final { scan-assembler-not "repnz scasb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-strlen-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-strlen-3.c new file mode 100644 index 000000000..c7a379ae0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr11001-strlen-3.c @@ -0,0 +1,16 @@ +/* Ensure that we don't use 'repnz scasb' in the presence of register globals. */ +/* { dg-do compile } */ +/* { dg-options "-O1 -w" } */ + +extern __SIZE_TYPE__ strlen (const char *); +extern void *malloc (__SIZE_TYPE__); + +register int regvar asm("%ecx"); + +char * +do_copy (char *str) +{ + return malloc (strlen (str) + 1); +} + +/* { dg-final { scan-assembler-not "repnz scasb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr12092-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr12092-1.c new file mode 100644 index 000000000..c230c84b7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr12092-1.c @@ -0,0 +1,13 @@ +/* PR rtl-optimization/12092 */ +/* Test case reduced by Andrew Pinski <pinskia@physics.uc.edu> */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -mtune=i486 -march=pentium4 -fprefetch-loop-arrays" } */ + +void DecodeAC(int index,int *matrix) +{ + int *mptr; + + for(mptr=matrix+index;mptr<matrix+64;mptr++) {*mptr = 0;} +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr12329.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr12329.c new file mode 100644 index 000000000..e7b43a78e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr12329.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2" } */ + +extern void abort (void); + +int test_nested1 (int i) +{ + int __attribute__ ((__noinline__, __regparm__(3))) foo(int j, int k, int l) + { + return i + j + k + l; + } + + return foo (i, i+1, i+2); +} + +int test_nested2 (int i) +{ + int x; + + int __attribute__ ((__noinline__, __regparm__(3))) foo(int j, int k, int l) + { + return i + j + k + l; + } + + x = foo (i+3, i+1, i+2); + if (x != (4*i + 6)) + abort (); + + return x; +} + +int +main () +{ + int i = test_nested1 (3); + + if (i != 15) + abort (); + + i = test_nested2 (4); + + if (i != 22) + abort (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr13366.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr13366.c new file mode 100644 index 000000000..f0dce0b24 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr13366.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O -msse" } */ + +#include <xmmintrin.h> + +typedef unsigned short v4hi __attribute__ ((vector_size (8))); + +int f(unsigned short n) +{ + __m64 vec = (__m64)(v4hi){ 0, 0, 1, n }; + __m64 hw = _mm_mulhi_pi16 (vec, vec); + return _mm_extract_pi16 (hw, 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr13685.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr13685.c new file mode 100644 index 000000000..a50681bea --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr13685.c @@ -0,0 +1,32 @@ +/* PR target/13685 */ +/* { dg-do run } */ +/* { dg-options "-Os -msse" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +#include <xmmintrin.h> + +void foo (__m128 *, __m64 *, int); + +__m128 xmm0 = { 0 }; +__m64 mm0 = { 0 }; + +static void +sse_test (void) +{ + foo (&xmm0, &mm0, 4); +} + +void +foo (__m128 *dst, __m64 *src, int n) +{ + __m128 xmm0 = { 0 }; + while (n > 64) + { + puts (""); + xmm0 = _mm_cvtpi32_ps (xmm0, *src); + *dst = xmm0; + n--; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr14289-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr14289-1.c new file mode 100644 index 000000000..e427b2d0c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr14289-1.c @@ -0,0 +1,12 @@ +/* PR middle-end/14289 */ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ + +register int a[2] asm("ebx"); + +void Nase(void) +{ + int i=6; + a[i]=5; /* { dg-error "address of global" } */ +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr14552.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr14552.c new file mode 100644 index 000000000..659257c32 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr14552.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mmmx" } */ + +typedef short mmxw __attribute__ ((vector_size (8))); +typedef int mmxdw __attribute__ ((vector_size (8))); + +mmxdw dw; +mmxw w; + +void test() +{ + w+=w; + dw= (mmxdw)w; +} + +/* { dg-final { scan-assembler-not "%mm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr17390.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr17390.c new file mode 100644 index 000000000..9a3d61fcd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr17390.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -mfpmath=387" } */ + +double sgn (double __x) +{ + return __x == 0.0 ? 0.0 : (__x > 0.0 ? 1.0 : -1.0); +} + +/* { dg-final { scan-assembler-times "fcom|ftst" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr17692.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr17692.c new file mode 100644 index 000000000..476d8e3de --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr17692.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mfpmath=sse -msse2" } */ + +/* The fact that t1 and t2 are uninitialized is critical. With them + uninitialized, the register allocator is free to put them in the same + hard register, which results in + + xmm0 = xmm0 >= xmm0 ? xmm0 : xmm0 + + Which is of course a nop, but one for which we would ICE splitting the + pattern. */ + +double out; + +static void foo(void) +{ + double t1, t2, t3, t4; + + t4 = t1 >= t2 ? t1 : t2; + t4 = t4 >= t3 ? t4 : t3; + out = t4; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr18614-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr18614-1.c new file mode 100644 index 000000000..1a4997537 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr18614-1.c @@ -0,0 +1,15 @@ +/* PR rtl-optimization/18614 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef double v2df __attribute__ ((vector_size (16))); + +v2df foo (void) +{ + v2df yd = { 1.0, 4.0 }; + v2df xd; + + xd = __builtin_ia32_cvtps2pd (__builtin_ia32_rsqrtps + (__builtin_ia32_cvtpd2ps (yd))); + return xd; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr19236-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr19236-1.c new file mode 100644 index 000000000..38db79812 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr19236-1.c @@ -0,0 +1,14 @@ +/* PR target/19236 */ +/* { dg-do compile } */ +/* { dg-options "-ffast-math" } */ + +extern float log1pf (float); +extern double log1p (double); + +float testf (float __x) { + return log1pf(1.0); +} + +double test (double __x) { + return log1p(1.0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr19398.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr19398.c new file mode 100644 index 000000000..60931c0a0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr19398.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -msse -mno-sse3 -mfpmath=387" } */ + +int test (float a) +{ + return (a * a); +} + +/* { dg-final { scan-assembler-not "cvttss2si\[^\\n\]*%xmm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr20020-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr20020-1.c new file mode 100644 index 000000000..f36a8a095 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr20020-1.c @@ -0,0 +1,27 @@ +/* Check that 128-bit struct's are represented as TImode values. */ +/* { dg-do compile { target int128 } } */ +/* { dg-skip-if "different ABI" { x86_64-*-mingw* } } */ +/* { dg-options "-O2 -fdump-rtl-expand" } */ + +struct shared_ptr_struct +{ + unsigned long long phase:48; + unsigned short thread:16; + union + { + void *addr; + unsigned long long pad; + }; +}; +typedef struct shared_ptr_struct sptr_t; + +sptr_t S; + +sptr_t +sptr_result (void) +{ + return S; +} +/* { dg-final { scan-rtl-dump "\\\(set \\\(reg:TI \[0-9\]* \\\[ <retval> \\\]\\\)" "expand" } } */ +/* { dg-final { scan-rtl-dump "\\\(set \\\(reg/i:TI 0 ax\\\)" "expand" } } */ +/* { dg-final { cleanup-rtl-dump "expand" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr20020-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr20020-2.c new file mode 100644 index 000000000..fa5b6edaf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr20020-2.c @@ -0,0 +1,25 @@ +/* Check that 128-bit struct's are represented as TImode values. */ +/* { dg-do compile { target int128 } } */ +/* { dg-skip-if "different ABI" { x86_64-*-mingw* } } */ +/* { dg-options "-O2 -fdump-rtl-expand" } */ + +struct shared_ptr_struct +{ + unsigned long long phase:48; + unsigned short thread:16; + union + { + void *addr; + unsigned long long pad; + }; +}; +typedef struct shared_ptr_struct sptr_t; + +void +copy_sptr (sptr_t *dest, sptr_t src) +{ + *dest = src; +} + +/* { dg-final { scan-rtl-dump "\\\(set \\\(reg:TI \[0-9\]*" "expand" } } */ +/* { dg-final { cleanup-rtl-dump "expand" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr20020-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr20020-3.c new file mode 100644 index 000000000..a30fbc4b1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr20020-3.c @@ -0,0 +1,28 @@ +/* Check that 128-bit struct's are represented as TImode values. */ +/* { dg-do compile { target int128 } } */ +/* { dg-skip-if "different ABI" { x86_64-*-mingw* } } */ +/* { dg-options "-O2 -fdump-rtl-expand" } */ + +struct shared_ptr_struct +{ + unsigned long long phase:48; + unsigned short thread:16; + union + { + void *addr; + unsigned long long pad; + }; +}; +typedef struct shared_ptr_struct sptr_t; + +sptr_t sptr_1, sptr_2; + +void +copy_sptr (void) +{ + sptr_1 = sptr_2; +} + +/* { dg-final { scan-rtl-dump "\\\(set \\\(reg:TI \[0-9\]*" "expand" } } */ +/* { dg-final { scan-rtl-dump "\\\(set \\\(mem/c:TI" "expand" } } */ +/* { dg-final { cleanup-rtl-dump "expand" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr20204.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr20204.c new file mode 100644 index 000000000..ca97a3ae9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr20204.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +void *x (void *pdst, const void *psrc, unsigned int pn) +{ + register void *return_dst = pdst; + register unsigned char *dst = pdst; + register unsigned const char *src = psrc; + register int n __asm__ ("ebx") = pn; + + if (src < dst && dst < src + n) + { + src += n; + dst += n; + while (n--) + *--dst = *--src; + return return_dst; + } + + while (n >= 16) n--; + + return return_dst; +} +extern void abort (); +extern void exit (int); +char xx[30] = "abc"; +int main (void) +{ + char yy[30] = "aab"; + + if (x (xx + 1, xx, 2) != xx + 1 || memcmp (xx, yy, sizeof (yy)) != 0) + abort (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr21101.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr21101.c new file mode 100644 index 000000000..104b08cd2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr21101.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -funroll-loops -march=nocona" } */ + +#include <mmintrin.h> + +int W; +void f() +{ + int j; + int B, C; + unsigned char* S; + __m64 *T = (__m64 *) &W; + + for (j = 0; j < 16; j++, T++) + { + T[0] = T[1] = _mm_set1_pi8(*S); + S += W; + } + + C = 3 * B; + + __m64 E = _mm_set_pi16(3 * B, 3 * B, 3 * B, 5 * B); + __m64 G = _mm_set1_pi16(3 * B); + + for (j = 0; j < 16; j++) + { + __m64 R = _mm_set1_pi16(B + j * C); + R = _m_paddw(R, E); + R = _m_paddw(R, G); + T[0] = _mm_srai_pi16(R, 3); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr21291.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr21291.c new file mode 100644 index 000000000..b59750985 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr21291.c @@ -0,0 +1,36 @@ +/* The asm has 2 "r" in/out operands, 1 earlyclobber "r" output, 1 "r" + input and 2 fixed "r" clobbers (eax and edx), so there are a total of + 6 registers that must not conflict. Add to that the PIC register, + the frame pointer, and the stack pointer, and we've run out of + registers on 32-bit targets. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +typedef unsigned long bngdigit; +typedef bngdigit *bng; +typedef unsigned int bngcarry; +typedef unsigned long bngsize; + +bngdigit +bng_ia32_mult_sub_digit (bng a, bngsize alen, bng b, bngsize blen, bngdigit d) +{ + bngdigit out, tmp; + bngcarry carry; + bngdigit a11; + + alen -= blen; + out = 0; + asm ("" + : "+r" (a), "+r" (b), "+mr" (blen), "+mr" (out), "=&r" (tmp) + : "mr" (d) + : "eax", "edx"); + if (alen == 0) + { + a11 = out; + goto t; + } + + a11 = 1; + t: + return a11; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr21518.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr21518.c new file mode 100644 index 000000000..52cbed6f4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr21518.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fPIC -fno-tree-pre" } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target fpic } */ + +extern void __attribute__ ((regparm (3))) +drawPointsLines (char type, int first, int *dd); + +int +do_locator (int *call) +{ + char prephitmp5; + int type; + int i; + + if (call == 0) + prephitmp5 = 1; + else + { + type = *call; + i = 0; + do + { + if (i != type) + drawPointsLines ((int) (char) type, 0, call); + i = i + 1; + } + while (i != 2); + prephitmp5 = (char) type; + } + drawPointsLines ((int) prephitmp5, 0, call); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22076.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22076.c new file mode 100644 index 000000000..38b40a26b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22076.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fomit-frame-pointer -flax-vector-conversions -mmmx" } */ +/* { dg-options "-O2 -fomit-frame-pointer -flax-vector-conversions -mmmx -mno-vect8-ret-in-mem" { target i?86-*-solaris2.9 *-*-vxworks* } } */ + +#include <mmintrin.h> + +__v8qi test () +{ + __v8qi mm0 = {1,2,3,4,5,6,7,8}; + __v8qi mm1 = {11,22,33,44,55,66,77,88}; + volatile __m64 x; + + x = _mm_add_pi8 (mm0, mm1); + + return x; +} + +/* { dg-final { scan-assembler-times "movq" 3 } } */ +/* { dg-final { scan-assembler-not "movl" { target nonpic } } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22152.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22152.c new file mode 100644 index 000000000..0b00169d0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22152.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-options "-O2 -msse2 -mno-vect8-ret-in-mem" { target i?86-*-solaris2.9 *-*-vxworks* } } */ +/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ + +#include <mmintrin.h> + +__m64 +unsigned_add3 (const __m64 * a, const __m64 * b, unsigned int count) +{ + __m64 sum; + unsigned int i; + + for (i = 1; i < count; i++) + sum = _mm_add_si64 (a[i], b[i]); + + return sum; +} + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+\[^\n\]*%mm" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22362.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22362.c new file mode 100644 index 000000000..04d6b2706 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22362.c @@ -0,0 +1,25 @@ +/* PR target/22362 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target ia32 } */ + +register unsigned int reg0 __asm__ ("esi"); +register unsigned int reg1 __asm__ ("edi"); +register unsigned int reg2 __asm__ ("ebx"); + +static unsigned int +__attribute__((noinline)) +foo (unsigned long *x, void *y, void *z) +{ + int i; + + for (i = 5; i > 0; i--) + x[i] = (unsigned long) foo ((unsigned long *) x[i], y, z); + return 0; +} + +unsigned int +bar (void) +{ + return foo (0, 0, 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22432.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22432.c new file mode 100644 index 000000000..86ae4b28f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22432.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mmmx" } */ +/* { dg-final { scan-assembler-not "paddb" } } */ + +typedef int v2si __attribute__ ((__vector_size__ (8))); +typedef short v4hi __attribute__ ((__vector_size__ (8))); +typedef char v8qi __attribute__ ((__vector_size__ (8))); + +int +foo (unsigned int *a, unsigned int *b) +{ + long long i, j, k; + + i = (long long) __builtin_ia32_vec_init_v2si (*a, 0); + j = (long long) __builtin_ia32_vec_init_v2si (*b, 0); + i = (long long) __builtin_ia32_punpcklbw ((v8qi) i, (v8qi) 0ll); + j = (long long) __builtin_ia32_punpcklbw ((v8qi) j, (v8qi) 0ll); + k = (long long) __builtin_ia32_paddw ((v4hi) i, (v4hi) j); + return __builtin_ia32_vec_ext_v2si ((v2si) k, 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22576.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22576.c new file mode 100644 index 000000000..083fbf648 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22576.c @@ -0,0 +1,10 @@ +/* PR target/22576 */ +/* Testcase reduced by Volker Reichelt */ +/* { dg-do compile } */ +/* { dg-options "-ffast-math" } */ + +int +foo (long double d) +{ + return d == 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22585.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22585.c new file mode 100644 index 000000000..e5f027ce8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr22585.c @@ -0,0 +1,12 @@ +/* PR target/22585 */ +/* Testcase reduced by Volker Reichelt */ +/* { dg-do compile } */ +/* { dg-options "-march=i386 -O -ffast-math" } */ +/* { dg-require-effective-target ia32 } */ + +int +foo (long double d, int i) +{ + if (d == (long double) i) + return 1; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23098.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23098.c new file mode 100644 index 000000000..66ab0e122 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23098.c @@ -0,0 +1,26 @@ +/* PR rtl-optimization/23098 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fPIC" } */ +/* { dg-final { scan-assembler-not "\.LC\[0-9\]" { xfail *-*-vxworks* } } } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target fpic } */ + +double foo (float); + +double +f1 (void) +{ + return foo (1.0); +} + +double +f2 (void) +{ + return foo (0.0); +} + +void +f3 (float *x, float t) +{ + *x = 0.0 + t; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23268.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23268.c new file mode 100644 index 000000000..b5645b297 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23268.c @@ -0,0 +1,13 @@ +/* PR target/23268 */ +/* Testcase reduced by Andrew Pinski */ +/* { dg-do compile } */ +/* { dg-options "-O1 -ffast-math" } */ + +int +f (float x) +{ + int a, b; + a = __builtin_log (2.f); + b = __builtin_lrint (x); + return (a + b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23376.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23376.c new file mode 100644 index 000000000..0dee77f6b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23376.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -mmmx -funroll-loops -fvariable-expansion-in-unroller" } */ + +typedef int __m64 __attribute__ ((__vector_size__ (8))); +typedef int __v2si __attribute__ ((__vector_size__ (8))); + +static __inline __m64 __attribute__((__always_inline__)) +_mm_add_pi32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_ia32_paddd ((__v2si)__m1, (__v2si)__m2); +} + +__m64 +simple_block_diff_up_mmx_4 (const int width, __m64 ref1) +{ + __m64 sum; + int count = width >>1; + while (count--) + sum = _mm_add_pi32 (sum, ref1); + return sum; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23570.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23570.c new file mode 100644 index 000000000..1542663fa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23570.c @@ -0,0 +1,92 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef float __v4sf __attribute__ ((__vector_size__ (16))); +typedef float __m128 __attribute__ ((__vector_size__ (16))); +typedef long long __v2di __attribute__ ((__vector_size__ (16))); + +static __inline __m128 +_mm_cmpeq_ps (__m128 __A, __m128 __B) +{ + return (__m128) __builtin_ia32_cmpeqps ((__v4sf)__A, (__v4sf)__B); +} + +static __inline __m128 +_mm_setr_ps (float __Z, float __Y, float __X, float __W) +{ + return __extension__ (__m128)(__v4sf){__Z, __Y, __X, __W }; +} + +static __inline __m128 +_mm_and_si128 (__m128 __A, __m128 __B) +{ + return (__m128)__builtin_ia32_pand128 ((__v2di)__A, (__v2di)__B); +} + +static __inline __m128 +_mm_or_si128 (__m128 __A, __m128 __B) +{ + return (__m128)__builtin_ia32_por128 ((__v2di)__A, (__v2di)__B); +} + +typedef union +{ + __m128 xmmi; + int si[4]; +} +__attribute__ ((aligned (16))) um128; + +um128 u; + +static inline int +sse_max_abs_indexf (float *v, int step, int n) +{ + __m128 m1, mm; + __m128 mim, mi, msk; + um128 u, ui; + int n4, step2, step3; + mm = __builtin_ia32_andps ((__m128) (__v4sf) + { 0.0, v[step], v[step2], v[step3] } + , u.xmmi); + if (n4) + { + int i; + for (i = 0; i < n4; ++i); + msk = (__m128) _mm_cmpeq_ps (m1, mm); + mim = _mm_or_si128 (_mm_and_si128 (msk, mi), mim); + } + ui.xmmi = (__m128) mim; + return ui.si[n]; +} + +static void +sse_swap_rowf (float *r1, float *r2, int n) +{ + int n4 = (n / 4) * 4; + float *r14end = r1 + n4; + while (r1 < r14end) + { + *r1 = *r2; + r1++; + } +} + +void +ludcompf (float *m, int nw, int *prow, int n) +{ + int i, s = 0; + float *pm; + for (i = 0, pm = m; i < n - 1; ++i, pm += nw) + { + int vi = sse_max_abs_indexf (pm + i, nw, n - i); + float *pt; + int j; + if (vi != 0) + { + sse_swap_rowf (pm, pm + vi * nw, nw); + swap_index (prow, i, i + vi); + } + for (j = i + 1, pt = pm + nw; j < n; ++j, pt += nw) + sse_add_rowf (pt + i + 1, pm + i + 1, -1.0, n - i - 1); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23575.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23575.c new file mode 100644 index 000000000..522226ef7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23575.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -O2" } */ + +/* We used to ICE because of a bogous pattern. */ + +typedef double __v2df __attribute__ ((__vector_size__ (16))); +typedef __v2df __m128d; +static __inline __m128d __attribute__((__always_inline__)) _mm_set1_pd (double __F) { + return __extension__ (__m128d){__F, __F}; +} +static __inline __m128d __attribute__((__always_inline__)) _mm_move_sd (__m128d __A, __m128d __B) { + return (__m128d) __builtin_ia32_movsd ((__v2df)__A, (__v2df)__B); +} +void g(__m128d b); +__m128d cross(__m128d tmp9) +{ + __m128d t1 = _mm_set1_pd(1.0); + __m128d tmp10 = _mm_move_sd(t1, tmp9); + return tmp10; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23943.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23943.c new file mode 100644 index 000000000..d70e5a6b2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr23943.c @@ -0,0 +1,21 @@ +/* This used to ICE in side_effects_p, due to a problem in cse.c. + Origin: marcus at jet dot franken dot de. */ +/* { dg-do compile } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -fPIC" } */ + +__extension__ typedef __SIZE_TYPE__ size_t; + +extern size_t strlen (__const char *__s) + __attribute__ ((__nothrow__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1))); + +static char savecallsin[256] = ""; + +int read_agent_config(void) +{ + savecallsin[0] = '\0'; + + if (savecallsin[strlen(savecallsin) - 1] != '/') + __builtin___strncat_chk (savecallsin, "/", sizeof(savecallsin) - strlen(savecallsin) - 1, __builtin_object_size (savecallsin, 2 > 1)) ; + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr24055.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr24055.c new file mode 100644 index 000000000..5190ec4b9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr24055.c @@ -0,0 +1,26 @@ +/* PR target/24055 */ +/* Testcase reduced by Serge Belyshev */ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math" } */ + +extern double rint(double); + +void foo_1 (int *p, double x) +{ + *p = rint (x); +} + +void foo_2 (long long *p, double x) +{ + *p = rint (x); +} + +int foo_3 (double x) +{ + return rint (x); +} + +long long foo_4 (double x) +{ + return rint (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr24178.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr24178.c new file mode 100644 index 000000000..b1a920813 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr24178.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-rtl-expand" } */ + +struct S { + int l; + unsigned char c; +}; +unsigned long f(unsigned char *p10) { + struct S *p = (struct S *) (p10 + 10); + return p->c; +} + +/* The p->c memory access should have alignment of 4 bytes. */ + +/* { dg-final { scan-rtl-dump "MEM\[^\\n\]*A32" "expand" } } */ +/* { dg-final { cleanup-rtl-dump "expand" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr24306.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr24306.c new file mode 100644 index 000000000..1319918c3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr24306.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-options "-msse" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +extern void abort(void); +typedef int __attribute__ ((vector_size (16))) foo_t; + +struct s +{ + foo_t f[0]; +} s1; + +void +check (int x, ...) __attribute__((noinline)); +void +check (int x, ...) +{ + int y; + __builtin_va_list ap; + + __builtin_va_start (ap, x); + __builtin_va_arg (ap, struct s); + y = __builtin_va_arg (ap, int); + + if (y != 7) + abort (); +} + +static void +sse_test (void) +{ + check (3, s1, 7); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr24315.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr24315.c new file mode 100644 index 000000000..dc6133eb9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr24315.c @@ -0,0 +1,9 @@ +/* PR target/24315 */ +/* { dg-do compile } */ +/* { dg-options "-O0 -fpeephole2" } */ + +void s48_double_to_bignum (int exponent) +{ + long length = ((((exponent) + ((((sizeof (long)) * 8) - 2) - 1)) / + (((sizeof (long)) * 8) - 2))); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25196.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25196.c new file mode 100644 index 000000000..6ebdee174 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25196.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-march=i386 -O3 -fomit-frame-pointer" } */ + +/* For this test case, we used to do an invalid load motion after + reload, because we missed autoincrements of the stack pointer. */ + +extern void abort (void); + +static int j; + +static void __attribute__((noinline)) +f1 (int a, int b, int c, int d, int e) +{ + j = a; +} + +int __attribute__((noinline)) +f2 (int a, int b, int c, int d, int e) +{ + if ((b & 0x1111) != 1) + f1 (a, b, c, d, e); + return 0; +} + +int +main (void) +{ + f2 (123, 0, 0, 0, 0); + if (j != 123) + abort (); + return 0; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25254.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25254.c new file mode 100644 index 000000000..ad602024c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25254.c @@ -0,0 +1,12 @@ +/* PR target/25254 */ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-mcmodel=medium -mlarge-data-threshold=1" } */ + +const struct { int i; int j; } c = { 2, 6 }; + +const char * +foo (void) +{ + return "OK"; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25293.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25293.c new file mode 100644 index 000000000..94923aba1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25293.c @@ -0,0 +1,51 @@ +/* PR target/25293 */ +/* { dg-do compile } */ +/* { dg-options "-mpreferred-stack-boundary=2 -mtune=i586 -O2 -fomit-frame-pointer -g" } */ +/* { dg-require-effective-target ia32 } */ + +struct T { unsigned short t1, t2, t3, t4, t5, t6, t7; }; +struct S { struct T s1; unsigned short s2, s3; }; +unsigned short v1; +int f1 (void); +int f2 (struct T); +int f3 (const char *); + +int +foo (struct S *x, struct T y) +{ + unsigned short a, b, c; + unsigned long d, e; + int f = 0; + y.t6 = 6; + a = y.t7; + b = y.t6; + c = y.t7; + switch (a) + { + case 8: + case 7: + c = 9; + break; + case 1: + case 6: + case 3: + b = 16; + c = 9; + break; + } + if ((f = f1 ())) + goto error; + if ((f = f2 (y))) + goto error; + d = (long) &y; + e = (long) &x->s1; + __asm __volatile ("" : "+D" (e), "+S" (d) :: "memory"); + x->s2 = b; + x->s3 = c; + f3 ("foo"); + return 0; +error: + if (v1 >= 1) + f3 ("bar"); + return f; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25654.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25654.c new file mode 100644 index 000000000..d53a29794 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25654.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -mpreferred-stack-boundary=2 -march=i686 -frename-registers" } */ + +extern void abort (void) __attribute__((noreturn)); + +struct wrapper { +union setconflict +{ + short a[20]; + int b[10]; +} a; +}; + +int +main () +{ + int sum = 0; + { + struct wrapper a; + short *c; + c = a.a.a; + asm ("": "=r" (c):"0" (c)); + *c = 0; + asm ("": "=r" (c):"0" (c)); + sum += *c; + } + { + struct wrapper a; + int *c; + c = a.a.b; + asm ("": "=r" (c):"0" (c)); + *c = 1; + asm ("": "=r" (c):"0" (c)); + sum += *c; + } + + if (sum != 1) + abort(); + return 0; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25993.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25993.c new file mode 100644 index 000000000..b079e257f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr25993.c @@ -0,0 +1,18 @@ +/* { dg-do assemble } */ +/* { dg-skip-if "" { "*-*-darwin*" "*-*-mingw*" } { "*" } { "" } } */ +/* { dg-options "-std=c99 -x assembler-with-cpp" } */ + +#ifndef __ASSEMBLER__ +extern int func(void); +#else +#ifdef __sun__ +.globl func +#else +.global func +#endif +.type func,@function +.align 4 +func: + ret +.size func,.-func +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26449-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26449-1.c new file mode 100644 index 000000000..b4ef78048 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26449-1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -mtune=k8" } */ + +typedef short __v8hi __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); + +void sse2_test (void) +{ + union + { + __m128i x; + } val1, res[8], tmp; + short ins[8] = { 8, 5, 9, 4, 2, 6, 1, 20 }; + int i; + + for (i = 0; i < 8; i++) + { + tmp.x = val1.x; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi) val1.x, ins[i], 0); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26449.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26449.c new file mode 100644 index 000000000..4a976ff7f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26449.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O1 -ftree-vectorize -march=pentium4 -std=c99" } */ + +void matmul_i4 (int bbase_yn, int xcount) +{ + int x; + int * restrict dest_y; + const int * abase_n; + + for (x = 0; x < xcount; x++) + { + dest_y[x] += abase_n[x] * bbase_yn; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26600.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26600.c new file mode 100644 index 000000000..bbe0663da --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26600.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O -ftree-vectorize -msse2" } */ + +void foo(int *p, int N) +{ + int i; + for (i=0; i<8; ++i, ++p) + { + int j = N+2*(N+p[0]), k = 2*N+p[0]; + p[0] = j+N; + p[5] = j+k; + } +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26778.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26778.c new file mode 100644 index 000000000..f871b5d61 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26778.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=pentium3" } */ + +typedef union { + long long l; + double d; +} db_number; + +double test(double x[3]) { + double th = x[1] + x[2]; + if (x[2] != th - x[1]) { + db_number thdb; + thdb.d = th; + thdb.l++; + th = thdb.d; + } + return x[0] + th; +} + +/* { dg-final { scan-assembler-not "mov.ps" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26826.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26826.c new file mode 100644 index 000000000..062e1737f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr26826.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O -fomit-frame-pointer -march=i586" } */ + +void foo(char* p, char c, int i) +{ + char a[2], *q=a+1; + if (p && i) + *p = q-a+bar(i); + if (c) + bar(i); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27266.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27266.c new file mode 100644 index 000000000..8735780c7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27266.c @@ -0,0 +1,14 @@ +/* PR target/27266. + The testcase below used to trigger an ICE. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-march=pentium" } */ + +signed long long sll; + +void +foo (void) +{ + __sync_fetch_and_add (&sll, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27696.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27696.c new file mode 100644 index 000000000..2f281e3f7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27696.c @@ -0,0 +1,11 @@ +/* PR target/27696 + The testcase below uses to trigger an ICE. */ + +/* { dg-do compile } */ +/* { dg-options "-msse3" } */ + +void +foo (void const * P, unsigned int E, unsigned int H) +{ + __builtin_ia32_monitor (P, E, H); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27790.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27790.c new file mode 100644 index 000000000..e8986c415 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27790.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O -ftree-vectorize -msse2" } */ + +void binarize (int npixels, unsigned char *b) +{ + int i; + for (i = 0; i < npixels; i++) + b[i] = (b[i] > 225 ? 0xff : 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27827.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27827.c new file mode 100644 index 000000000..3b337444a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27827.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mfpmath=387" } */ + +double a, b; +double f(double c) +{ + double x = a * b; + return x + c * a; +} + +/* { dg-final { scan-assembler-not "fld\[ \t\]*%st" } } */ +/* { dg-final { scan-assembler "fmul\[ \t\]*%st" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27971.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27971.c new file mode 100644 index 000000000..27888de6d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr27971.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned array[4]; + +#ifdef _WIN64 +__extension__ typedef unsigned long long TYPE; +#else +#define TYPE unsigned long +#endif + +unsigned foo(TYPE x) +{ + return array[(x>>2)&3ul]; +} + +/* { dg-final { scan-assembler-not "shr\[^\\n\]*2" } } */ +/* { dg-final { scan-assembler "and\[^\\n\]*12" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr28839.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr28839.c new file mode 100644 index 000000000..6a215164c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr28839.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -ftree-vectorize -funswitch-loops" } */ + +static int ready[10]; +void abort (void); +void test_once (int t,int t1) +{ + int i, repeat; + for (i = 0; i < 10; i++) + { + ready[i] = 0; + if (t1) + if (b()) + abort (); + } + if (t) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr28946.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr28946.c new file mode 100644 index 000000000..327207977 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr28946.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -fno-ident" } */ +/* { dg-final { scan-assembler-not "test" } } */ + +int fct1 (void); +int fct2 (void); + +int +fct (unsigned nb) +{ + if ((nb >> 5) != 0) + return fct1 (); + else + return fct2 (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr29978.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr29978.c new file mode 100644 index 000000000..e27bbdcd8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr29978.c @@ -0,0 +1,16 @@ +/* PR target/29978 */ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + +void g (); + +void +f (long long v) +{ + if (v > 0xfffffffffLL) + g (); + g (); +} + +/* Verify there are no redundant jumps jl .L2; jle .L2 */ +/* { dg-final { scan-assembler-not "jl\[^e\]*\\.L" { target ia32 } } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30120.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30120.c new file mode 100644 index 000000000..22fd843a7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30120.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math" } */ + +extern void abort (void); + +static void +foo (double a, double weight, const double *ring, double *phase) +{ + *phase = *ring * weight; +} + +void +foo2 (void) +{ + foo (0, 1, (double *) 0, (double *) 0); +} + +int +main (void) +{ + double t1 = 1, c1; + foo (0, 1, &t1, &c1); + if (c1 < 0.5) + abort(); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30315.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30315.c new file mode 100644 index 000000000..998d5071e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30315.c @@ -0,0 +1,97 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "cmp" 4 } } */ + +extern void abort (void); +int c; + +#define PLUSCC1(T, t, C) \ +T pluscc##t##C (T a, T b) \ +{ \ + T sum = a + b; \ + if (sum < C) \ + abort (); \ + return sum; \ +} +#define PLUSCC(T, t) PLUSCC1(T, t, a) PLUSCC1(T, t, b) + +#define INCCC1(T, t, C) \ +T inccc##t##C (T a, T b) \ +{ \ + T sum = a + b; \ + if (sum < C) \ + c ++; \ + return sum; \ +} +#define INCCC(T, t) INCCC1(T, t, a) INCCC1(T, t, b) + +#define PLUSCCONLY1(T, t, C) \ +void pluscconly##t##C (T a, T b) \ +{ \ + T sum = a + b; \ + if (sum < C) \ + abort (); \ +} +#define PLUSCCONLY(T, t) PLUSCCONLY1(T, t, a) PLUSCCONLY1(T, t, b) + +#define MINUSCC(T, t) \ +T minuscc##t (T a, T b) \ +{ \ + T difference = a - b; \ + if (difference > a) \ + abort (); \ + return difference; \ +} + +#define DECCC(T, t) \ +T deccc##t (T a, T b) \ +{ \ + T difference = a - b; \ + if (difference > a) \ + c --; \ + return difference; \ +} + +#define MINUSCCONLY(T, t) \ +void minuscconly##t (T a, T b) \ +{ \ + T difference = a - b; \ + if (difference > a) \ + abort (); \ +} + +#define TEST(T, t) \ + PLUSCC(T, t) \ + PLUSCCONLY(T, t) \ + INCCC(T, t) \ + MINUSCC(T, t) \ + MINUSCCONLY(T, t) \ + DECCC(T, t) + +TEST (unsigned long, l) +TEST (unsigned int, i) +TEST (unsigned short, s) +TEST (unsigned char, c) + +#define PLUSCCZEXT(C) \ +unsigned long pluscczext##C (unsigned int a, unsigned int b) \ +{ \ + unsigned int sum = a + b; \ + if (sum < C) \ + abort (); \ + return sum; \ +} + +PLUSCCZEXT(a) +PLUSCCZEXT(b) + +#define MINUSCCZEXT \ +unsigned long minuscczext (unsigned int a, unsigned int b) \ +{ \ + unsigned int difference = a - b; \ + if (difference > a) \ + abort (); \ + return difference; \ +} + +MINUSCCZEXT diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30413.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30413.c new file mode 100644 index 000000000..1d3a94f97 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30413.c @@ -0,0 +1,18 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +extern void abort (void); + +int test() { + char a, b = -1; + asm volatile ("mov%z0 %1, %0" : "=q"(a) : "m"(b)); + return a; +} + +int main() +{ + if (test() != -1) + abort(); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30505.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30505.c new file mode 100644 index 000000000..3cebbe695 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30505.c @@ -0,0 +1,20 @@ +/* PR inline-asm/30505 */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2" } */ + +unsigned long long a, c; +unsigned int b, d; + +void +test () +{ + unsigned int e, f; + + __asm__ ("divl %5;movl %1, %0;movl %4, %1;divl %5" + : "=&rm" (e), "=a" (f), "=d" (d) + : "1" ((unsigned int) (a >> 32)), "g" ((unsigned int) a), + "rm" (b), "2" (0) + : "cc"); + c = (unsigned long long) e << 32 | f; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30848.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30848.c new file mode 100644 index 000000000..2a9285151 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30848.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ + +void foo(double d) +{ + __asm__ ("" : "=u" (d)); /* { dg-error "output regs" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30961-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30961-1.c new file mode 100644 index 000000000..c7c5e5383 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30961-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2" } */ + +double +convert (long long in) +{ + double f; + __builtin_memcpy( &f, &in, sizeof( in ) ); + return f; +} + +/* { dg-final { scan-assembler-not "movapd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30970.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30970.c new file mode 100644 index 000000000..96d64e5a9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr30970.c @@ -0,0 +1,15 @@ +/* { dg-do compile } +/* { dg-options "-msse2 -O2 -ftree-vectorize" } */ + +#define N 256 +int b[N]; + +void test() +{ + int i; + + for (i = 0; i < N; i++) + b[i] = 0; +} + +/* { dg-final { scan-assembler-times "pxor" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr31167.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr31167.c new file mode 100644 index 000000000..43d9f848b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr31167.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target int128 } */ +/* { dg-options "-O" } */ + +typedef int int32_t; + +int32_t round32hi (const __int128_t arg) +{ + const int SHIFT = 96; + const int mshift = 96; + const __int128_t M = (~(__int128_t) 0) << mshift; + const __int128_t L = (~M) + 1; + const __int128_t L1 = ((__int128_t) L) >> 1; + const __int128_t Mlo = ((__int128_t) (~M)) >> 1; + __int128_t vv = arg & M; + + if ((arg & (L1)) && ((arg & Mlo) || (arg & L))) + vv += L; + + return (int32_t) (vv >> SHIFT); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr31486.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr31486.c new file mode 100644 index 000000000..7082d3de9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr31486.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-msse -mno-sse2" } */ + +typedef double __v2df __attribute__ ((vector_size (16))); + +__v2df b = { 1.1, 1.2 }; + +extern __v2df a2 (__v2df a, __v2df b); + +void test2 () +{ + b = a2 (b, b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr31628.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr31628.c new file mode 100644 index 000000000..eece2a0db --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr31628.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fPIC" } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target fpic } */ + +typedef int tt, *lptt; + +int __attribute__((__stdcall__)) bar(lptt); + +int __attribute__((__stdcall__)) bar(tt *x) +{ + return 0; +} + +int +foo (void) +{ + return bar (0); +} + +int +main() +{ + return foo (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr31854.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr31854.c new file mode 100644 index 000000000..6fcd20ef0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr31854.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target dfp } */ +/* { dg-options "-O -std=gnu99" } */ + +_Decimal128 d128; +long double tf; + +void foo (void) +{ + d128 = tf; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32000-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32000-1.c new file mode 100644 index 000000000..9c7bfa24b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32000-1.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target dfp } */ +/* { dg-options "-O -msse2 -std=gnu99" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +typedef struct { _Decimal128 f __attribute__((packed)); } packed; + +_Decimal128 __attribute__((noinline)) +foo (_Decimal128 a1, _Decimal128 a2, _Decimal128 a3, _Decimal128 a4, + _Decimal128 a5, _Decimal128 a6, _Decimal128 a7, _Decimal128 a8, + int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y) +{ + return y.f; +} + +void +sse2_test (void) +{ + packed x; + _Decimal128 y = -1; + x.f = y; + y = foo (0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, -1, x); + if (__builtin_memcmp (&y, &x.f, sizeof (y))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32000-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32000-2.c new file mode 100644 index 000000000..374b23f83 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32000-2.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-skip-if "" { ! { ia32 && dfp } } { "*" } { "" } } */ +/* { dg-options "-O -msse2 -std=gnu99 -mpreferred-stack-boundary=2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +typedef struct { _Decimal128 f __attribute__((packed)); } packed; + +_Decimal128 __attribute__((noinline)) +foo (_Decimal128 a1, _Decimal128 a2, _Decimal128 a3, _Decimal128 a4, + _Decimal128 a5, _Decimal128 a6, _Decimal128 a7, _Decimal128 a8, + int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y) +{ + return y.f; +} + +void +sse2_test (void) +{ + packed x; + _Decimal128 y = -1; + x.f = y; + y = foo (0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, -1, x); + if (__builtin_memcmp (&y, &x.f, sizeof (y))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32065-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32065-1.c new file mode 100644 index 000000000..eefea27f1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32065-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target dfp } */ +/* { dg-options "-msse -std=gnu99" } */ + +_Decimal128 test (void) +{ + return 1234123412341234.123412341234dl; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32065-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32065-2.c new file mode 100644 index 000000000..5f055b59c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32065-2.c @@ -0,0 +1,16 @@ +/* { dg-do run } */ +/* { dg-require-effective-target dfp } */ +/* { dg-require-effective-target sse } */ +/* { dg-options "-Os -msse -std=gnu99" } */ + +#include "sse-check.h" + +extern void abort (void); + +static void +sse_test (void) +{ + if (7.999999999999999999999999999999999E6144dl + 3.0E6144dl + != __builtin_infd32 ()) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32191.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32191.c new file mode 100644 index 000000000..f5238b01d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32191.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c99" } */ + +typedef _Complex float __attribute__((mode(TC))) _Complex128; + +_Complex128 foo (_Complex128 x, _Complex128 y) +{ + return x * y; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32268.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32268.c new file mode 100644 index 000000000..a5d673ad9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32268.c @@ -0,0 +1,34 @@ +/* { dg-do run { target *-*-linux* } } */ +/* { dg-options "-O2" } */ + +extern void abort(void); + +int __attribute__ ((__noinline__)) +test_lt(__float128 x, __float128 y) +{ + return x < y; +} + +int __attribute__ ((__noinline__)) +test_gt (__float128 x, __float128 y) +{ + return x > y; +} + +int main() +{ + __float128 a = 0.0; + __float128 b = 1.0; + + int r; + + r = test_lt (a, b); + if (r != ((double) a < (double) b)) + abort(); + + r = test_gt (a, b); + if (r != ((double) a > (double) b)) + abort(); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32280-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32280-1.c new file mode 100644 index 000000000..e8619fa7e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32280-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target int128 } */ +/* { dg-options "-O2" } */ + +__uint128_t +t1 (__uint128_t a) +{ + return a << 8; +} + +__uint128_t +t2 (__uint128_t a) +{ + return a >> 8; +} + +/* { dg-final { scan-assembler-not "pslldq" } } */ +/* { dg-final { scan-assembler-not "psrldq" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32280.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32280.c new file mode 100644 index 000000000..d48a635a4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32280.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef long long __m128i __attribute__ ((__vector_size__ (16))); + +__m128i foo1(__m128i __a) +{ + return (__m128i)__builtin_ia32_pslldqi128 (__a, 8); +} + +__m128i foo2(__m128i __a) +{ + return (__m128i)__builtin_ia32_psrldqi128 (__a, 8); +} + +/* { dg-final { scan-assembler "psrldq" } } */ +/* { dg-final { scan-assembler "pslldq" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32389.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32389.c new file mode 100644 index 000000000..24c27674c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32389.c @@ -0,0 +1,11 @@ +/* Testcase by Mike Frysinger <vapier@gentoo.org> */ + +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-msse" } */ + +double f1(); +int f2() { + __builtin_ia32_stmxcsr(); + return f1(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32661-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32661-1.c new file mode 100644 index 000000000..39cd8f90c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32661-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -fomit-frame-pointer" } */ + +typedef long long __m128i __attribute__ ((__vector_size__ (16))); + +long long foo_0(__m128i* val) +{ + return __builtin_ia32_vec_ext_v2di(*val, 0); +} + +long long foo_1(__m128i* val) +{ + return __builtin_ia32_vec_ext_v2di(*val, 1); +} + +/* { dg-final { scan-assembler-times "mov" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32661.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32661.c new file mode 100644 index 000000000..247ae1319 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32661.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef int __v4si __attribute__ ((__vector_size__ (16))); +typedef float __v4sf __attribute__ ((__vector_size__ (16))); + +int fooSI_1(__v4si *val) +{ + return __builtin_ia32_vec_ext_v4si(*val, 1); +} +/* { dg-final { scan-assembler-not "pshufd" } } */ + +int fooSI_2(__v4si *val) +{ + return __builtin_ia32_vec_ext_v4si(*val, 2); +} +/* { dg-final { scan-assembler-not "punpckhdq" } } */ + +float fooSF_2(__v4sf *val) +{ + return __builtin_ia32_vec_ext_v4sf(*val, 2); +} +/* { dg-final { scan-assembler-not "unpckhps" } } */ + +float fooSF_3(__v4sf *val) +{ + return __builtin_ia32_vec_ext_v4sf(*val, 3); +} +/* { dg-final { scan-assembler-not "shufps" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32708-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32708-1.c new file mode 100644 index 000000000..c5308937b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32708-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef long long __v2di __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); + +static __inline __m128i __attribute__((__always_inline__)) +_mm_set_epi64x (long long __q1, long long __q0) +{ + return __extension__ (__m128i)(__v2di){ __q0, __q1 }; +} + +__m128i long2vector(long long __i) +{ + return _mm_set_epi64x (0, __i); +} + +/* { dg-final { scan-assembler-not "movq2dq" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32708-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32708-2.c new file mode 100644 index 000000000..f28caf91a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32708-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mtune=k8" } */ + +typedef long long __v2di __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); + +static __inline __m128i __attribute__((__always_inline__)) +_mm_set_epi64x (long long __q1, long long __q0) +{ + return __extension__ (__m128i)(__v2di){ __q0, __q1 }; +} + +__m128i long2vector(long long __i) +{ + return _mm_set_epi64x (0, __i); +} + +/* { dg-final { scan-assembler-not "movq2dq" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32708-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32708-3.c new file mode 100644 index 000000000..77e50b241 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32708-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mtune=core2" } */ + +typedef long long __v2di __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); + +static __inline __m128i __attribute__((__always_inline__)) +_mm_set_epi64x (long long __q1, long long __q0) +{ + return __extension__ (__m128i)(__v2di){ __q0, __q1 }; +} + +__m128i long2vector(long long __i) +{ + return _mm_set_epi64x (0, __i); +} + +/* { dg-final { scan-assembler-not "movq2dq" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32961.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32961.c new file mode 100644 index 000000000..a2326289a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr32961.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -msse2" } */ + +#include <xmmintrin.h> + +void x (int n) +{ + __m128i a; + a = _mm_slli_epi32 (a, n); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33329.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33329.c new file mode 100644 index 000000000..5aae9aa7d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33329.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -msse2" } */ + +extern void g (int *); + +void f (void) +{ + int tabs[1024], tabcount; + + for (tabcount = 1; tabcount <= 8; tabcount += 7) + { + int i; + for (i = 0; i < 1024; i++) + tabs[i] = i * 12345; + g (tabs); + } +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33483.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33483.c new file mode 100644 index 000000000..8fe2a946b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33483.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +long double f1 (long double x) +{ + return __builtin_fmodl (x, x); +} + +long double f2 (long double x) +{ + return __builtin_remainderl (x, x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33552.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33552.c new file mode 100644 index 000000000..68a81222e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33552.c @@ -0,0 +1,41 @@ +/* PR rtl-optimization/33552 */ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +extern void abort (void); + +void +__attribute__((noinline)) +foo (unsigned long *wp, unsigned long *up, long un, unsigned long *vp) +{ + long j; + unsigned long prod_low, prod_high; + unsigned long cy_dig; + unsigned long v_limb; + v_limb = vp[0]; + cy_dig = 64; + for (j = un; j > 0; j--) + { + unsigned long u_limb, w_limb; + u_limb = *up++; + __asm__ ("" + : "=r" (prod_low), "=r" (prod_high) + : "0" (u_limb), "1" (v_limb)); + __asm__ ("mov %5, %1; add %5, %0" + : "=r" (cy_dig), "=&r" (w_limb) + : "0" (prod_high), "rm" (0), "1" (prod_low), "rm" (cy_dig)); + *wp++ = w_limb; + } +} + +int +main (void) +{ + unsigned long wp[4]; + unsigned long up[4] = { 0x1248, 0x248a, 0x1745, 0x1853 }; + unsigned long vp = 0xdead; + foo (wp, up, 4, &vp); + if (wp[0] != 0x40 || wp[1] != 0xdeed || wp[2] != 0x1bd9a || wp[3] != 0x29c47) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33555.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33555.c new file mode 100644 index 000000000..21c56b7bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33555.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "sbbl" } } */ + +int test(unsigned long a, unsigned long b) +{ + return -(a < b); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33600.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33600.c new file mode 100644 index 000000000..a2ab91e57 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr33600.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +int f(int n) +{ + int x; + + asm("" : "=&c"(n), "=r"(x) : "1"(n), "0"(n)); + + return n; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34012.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34012.c new file mode 100644 index 000000000..00b1240d1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34012.c @@ -0,0 +1,25 @@ +/* PR rtl-optimization/34012 */ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2" } */ + +void bar (long int *); +void +foo (void) +{ + long int buf[10]; + buf[0] = 0x0808080808080808; + buf[1] = 0x0808080808080808; + buf[2] = 0x0808080808080808; + buf[3] = 0x0808080808080808; + buf[4] = 0x0808080808080808; + buf[5] = 0x0808080808080808; + buf[6] = 0x0808080808080808; + buf[7] = 0x0808080808080808; + buf[8] = 0x0808080808080808; + buf[9] = 0x0808080808080808; + bar (buf); +} + +/* Check that CSE did its job and fwprop hasn't undone it. */ +/* { dg-final { scan-assembler-times "578721382704613384|0808080808080808" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34077.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34077.c new file mode 100644 index 000000000..a2ec5d12b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34077.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -minline-all-stringops -minline-stringops-dynamically" } */ + +#include <string.h> + +extern double ran(void); + +struct spec_fd_t { + int limit; + int len; + int pos; + unsigned char *buf; +} spec_fd[3]; + +int spec_random_load (int fd) { + int i, j; + char random_text[(32)][(128*1024)]; + + for (j = 0; j < (128*1024); j++) { + random_text[i][j] = (int)(ran()*256); + } + + for (i = 0 ; i < spec_fd[fd].limit; i+= (128*1024)) { + memcpy(spec_fd[fd].buf + i, random_text[(int)(ran()*(32))], + (128*1024)); + } + + spec_fd[fd].len = 1024*1024; + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34215.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34215.c new file mode 100644 index 000000000..9e194ff44 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34215.c @@ -0,0 +1,19 @@ +/* Testcase by Martin Michlmayr <tbm@cyrius.com> */ + +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2" } */ + +double pow (double, double); + +void calc_score_dist (int mxdlen, long double d, long double **dist) +{ + unsigned long i, scr2; + for (i = 1; i <= mxdlen; i++) + { + for (scr2 = mxdlen; scr2 <= mxdlen + 10; scr2++) + { + } + dist[i][scr2] *= pow (1.0 / d, i); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34256.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34256.c new file mode 100644 index 000000000..4ce7e30c5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34256.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -fomit-frame-pointer -march=core2" } */ + +#include <mmintrin.h> + +__m64 x; +__m64 y; + +unsigned long long foo(__m64 m) { + return _mm_cvtm64_si64(_mm_add_pi32(x, y)); +} + +/* { dg-final { scan-assembler-times "mov" 2 { target nonpic } } } */ +/* { dg-final { scan-assembler-times "mov" 4 { target { ! nonpic } } } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34283.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34283.c new file mode 100644 index 000000000..60e11a509 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34283.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse4" } */ + +typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef long long __v2di __attribute__ ((__vector_size__ (16))); + +__m128i _mm_set_epi64x (long long __q1, long long __q0) +{ + return __extension__ (__m128i)(__v2di){ __q0, __q1 }; +} + +/* { dg-final { scan-assembler-not "movdqa" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34312.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34312.c new file mode 100644 index 000000000..876ac4040 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34312.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -march=pentium-m -fpic" } */ + +typedef struct +{ + unsigned char seq[3]; +} JamoNormMap; + +static const JamoNormMap * +JamoClusterSearch (JamoNormMap aKey, const JamoNormMap * aClusters, + short aClustersSize) +{ + unsigned short l = 0, u = aClustersSize - 1; + unsigned short h = (l + u) / 2; + + if ((aKey.seq[1] - aClusters[h].seq[1]) < 0) + return JamoClusterSearch (aKey, &(aClusters[l]), h - l); +} + +short +JamoSrchReplace (const JamoNormMap * aClusters, unsigned short aClustersSize, + unsigned short * aIn, unsigned int * aLength, + unsigned short aOffset) +{ + JamoNormMap key; + + key.seq[0] = 0; + key.seq[1] = 1; + key.seq[2] = 2; + + JamoClusterSearch (key, aClusters, aClustersSize); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34522.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34522.c new file mode 100644 index 000000000..eb1e03a77 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr34522.c @@ -0,0 +1,13 @@ +/* { dg-options "-O2" } */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ + +int test(long long a, long long b) +{ + return a * b; +} + +/* Check that we did not spill anything. This is all that is needed + to qualify the generated code as "decent"... */ + +/* { dg-final { scan-assembler-not "%e\[sd\]i" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35083.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35083.c new file mode 100644 index 000000000..c765d3254 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35083.c @@ -0,0 +1,8 @@ +/* { dg-options "-O2 -mno-80387" } */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ + +float test (unsigned int x) +{ + return (float) x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35160.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35160.c new file mode 100644 index 000000000..259c2a3ea --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35160.c @@ -0,0 +1,32 @@ +/* PR inline-asm/35160 */ +/* { dg-do run } */ +/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */ +/* { dg-options "-O2" } */ + +extern void abort (void); + +void +__attribute__((noinline)) +foo (unsigned int *y) +{ + unsigned int c0, c1, c2, d0, d1, d2; + d0 = 0; d1 = 0; d2 = 0; c0 = c1 = c2 = 0; + + __asm__ ("movl $7, %k0; movl $8, %k1; movl $9, %k2" + : "+r" (d0), "+r" (d1), "+r" (d2)); + __asm__ ("movl %3, %0; movl %4, %1; movl %5, %2" + : "+r" (c0), "+r" (c1), "+r" (c2), "+r" (d0), "+r" (d1), "+r" (d2)); + y[0] = c0; + y[1] = c1; + y[2] = c2; +} + +int +main (void) +{ + unsigned int y[3]; + foo (y); + if (y[0] != 7 || y[1] != 8 || y[2] != 9) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35281.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35281.c new file mode 100644 index 000000000..efd5c3d63 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35281.c @@ -0,0 +1,19 @@ +/* { dg-options "-O2" } */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ + +unsigned long long a; +unsigned int b; +unsigned short c; + +unsigned long long mul32() +{ + return a * b; +} + +unsigned long long mul16() +{ + return a * c; +} + +/* { dg-final { scan-assembler-not "xor" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35540.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35540.c new file mode 100644 index 000000000..00af637d0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35540.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +extern void abort (void); + +int __attribute__ ((noinline)) +test (unsigned int *a, int b) +{ + return b ? 1 : __builtin_parity (*a); +} + +int __attribute__ ((noinline)) +testl (unsigned long *a, int b) +{ + return b ? 1 : __builtin_parityl (*a); +} + +int __attribute__ ((noinline)) +testll (unsigned long long *a, int b) +{ + return b ? 1 : __builtin_parityll (*a); +} + +int +main () +{ + unsigned int a = 0; + unsigned long al; + unsigned long long all; + + a = 0x12345670; + if (test (&a, 0)) + abort (); + + al = 0x12345670ul; + if (testl (&al, 0)) + abort(); + +#if 1 + all = 0x12345678abcdef0ull; + if (testll (&all, 0)) + abort (); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35714.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35714.c new file mode 100644 index 000000000..13ca47c23 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35714.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +#include <emmintrin.h> + +extern __m128i a; + +__m128i madd (__m128i b) +{ + return _mm_madd_epi16(a, b); +} + +__m128i madd_swapped (__m128i b) +{ + return _mm_madd_epi16(b, a); +} + +/* { dg-final { scan-assembler-not "movaps" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-1.c new file mode 100644 index 000000000..0945e19ba --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-1.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +typedef struct { __m128 f __attribute__((packed)); } packed; + +__m128 __attribute__((noinline)) +foo (__m128 a1, __m128 a2, __m128 a3, __m128 a4, + __m128 a5, __m128 a6, __m128 a7, __m128 a8, + int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y) +{ + return y.f; +} + +void +sse2_test (void) +{ + packed x; + __m128 y = { 0 }; + x.f = y; + y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x); + if (__builtin_memcmp (&y, &x.f, sizeof (y)) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-1d.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-1d.c new file mode 100644 index 000000000..fa7d73f6e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-1d.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +typedef struct { __m128d f __attribute__((packed)); } packed; + +__m128d __attribute__((noinline)) +foo (__m128d a1, __m128d a2, __m128d a3, __m128d a4, + __m128d a5, __m128d a6, __m128d a7, __m128d a8, + int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y) +{ + return y.f; +} + +void +sse2_test (void) +{ + packed x; + __m128d y = { 0 }; + x.f = y; + y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x); + if (__builtin_memcmp (&y, &x.f, sizeof (y)) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-1i.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-1i.c new file mode 100644 index 000000000..b76204802 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-1i.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +typedef struct { __m128i f __attribute__((packed)); } packed; + +__m128i __attribute__((noinline)) +foo (__m128i a1, __m128i a2, __m128i a3, __m128i a4, + __m128i a5, __m128i a6, __m128i a7, __m128i a8, + int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y) +{ + return y.f; +} + +void +sse2_test (void) +{ + packed x; + __m128i y = { 0 }; + x.f = y; + y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x); + if (__builtin_memcmp (&y, &x.f, sizeof (y)) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-2.c new file mode 100644 index 000000000..5457c4811 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +typedef __m128 __attribute__((aligned(1))) unaligned; + +__m128 __attribute__((noinline)) +foo (__m128 a1, __m128 a2, __m128 a3, __m128 a4, + __m128 a5, __m128 a6, __m128 a7, __m128 a8, + int b1, int b2, int b3, int b4, int b5, int b6, int b7, unaligned y) +{ + return y; +} + +void +sse2_test (void) +{ + unaligned x; + __m128 y = { 0 }; + x = y; + y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x); + if (__builtin_memcmp (&y, &x, sizeof (y)) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-2d.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-2d.c new file mode 100644 index 000000000..cb9d74190 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-2d.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +typedef __m128d __attribute__((aligned(1))) unaligned; + +__m128d __attribute__((noinline)) +foo (__m128d a1, __m128d a2, __m128d a3, __m128d a4, + __m128d a5, __m128d a6, __m128d a7, __m128d a8, + int b1, int b2, int b3, int b4, int b5, int b6, int b7, unaligned y) +{ + return y; +} + +void +sse2_test (void) +{ + unaligned x; + __m128d y = { 0 }; + x = y; + y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x); + if (__builtin_memcmp (&y, &x, sizeof (y)) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-2i.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-2i.c new file mode 100644 index 000000000..f2dede9e7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-2i.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +typedef __m128i __attribute__((aligned(1))) unaligned; + +__m128i __attribute__((noinline)) +foo (__m128i a1, __m128i a2, __m128i a3, __m128i a4, + __m128i a5, __m128i a6, __m128i a7, __m128i a8, + int b1, int b2, int b3, int b4, int b5, int b6, int b7, unaligned y) +{ + return y; +} + +void +sse2_test (void) +{ + unaligned x; + __m128i y = { 0 }; + x = y; + y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x); + if (__builtin_memcmp (&y, &x, sizeof (y)) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-3.c new file mode 100644 index 000000000..19162cfe2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-3.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target dfp } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O -msse2 -std=gnu99" } */ + +#include "sse2-check.h" + +typedef _Decimal128 unaligned __attribute__((aligned(1))); + +_Decimal128 __attribute__((noinline)) +foo (_Decimal128 a1, _Decimal128 a2, _Decimal128 a3, _Decimal128 a4, + _Decimal128 a5, _Decimal128 a6, _Decimal128 a7, _Decimal128 a8, + int b1, int b2, int b3, int b4, int b5, int b6, int b7, unaligned y) +{ + return y; +} + +void +sse2_test (void) +{ + unaligned x; + _Decimal128 y = -1; + x = y; + y = foo (0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, -1, x); + if (__builtin_memcmp (&y, &x, sizeof (y))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-4.c new file mode 100644 index 000000000..1b58cfd4a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-4.c @@ -0,0 +1,14 @@ +/* Test that we generate aligned load when memory is aligned. */ +/* { dg-do compile } */ +/* { dg-require-effective-target dfp } */ +/* { dg-options "-O -march=x86-64 -mtune=generic -std=gnu99" } */ +/* { dg-final { scan-assembler-not "movdqu" } } */ +/* { dg-final { scan-assembler "movdqa" { target { ! x86_64-*-mingw* } } } } */ + +extern _Decimal128 foo (_Decimal128, _Decimal128, _Decimal128); + +void +bar (void) +{ + foo (0, 0, 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-5.c new file mode 100644 index 000000000..4372d2e57 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr35767-5.c @@ -0,0 +1,17 @@ +/* Test that we generate aligned load when memory is aligned. */ +/* { dg-do compile } */ +/* { dg-options "-O -msse2 -mtune=generic" } */ +/* { dg-final { scan-assembler-not "movups" } } */ +/* { dg-final { scan-assembler "movaps" } } */ + +typedef float v4sf __attribute__ ((__vector_size__ (16))); + +extern void foo(v4sf, v4sf, v4sf, v4sf, v4sf, v4sf, v4sf, v4sf, v4sf); + +int test(void) +{ + v4sf x = { 0.0, 1.0, 2.0, 3.0 }; + + foo (x, x, x, x, x, x, x, x, x); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36064.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36064.c new file mode 100644 index 000000000..7964f280c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36064.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O1 -march=core2" } */ + +typedef long long ogg_int64_t; + +typedef struct vorbis_info +{ + long rate; +} vorbis_info; + +typedef struct OggVorbis_File +{ + int seekable; + int links; + ogg_int64_t *pcmlengths; + vorbis_info *vi; + int ready_state; +} OggVorbis_File; + +extern double ov_time_total (OggVorbis_File * vf, int i); +extern int ov_pcm_seek_page (OggVorbis_File * vf, ogg_int64_t pos); + +int +ov_time_seek_page (OggVorbis_File * vf, double seconds) +{ + int link = -1; + ogg_int64_t pcm_total = 0; + double time_total = 0.; + + if (vf->ready_state < 2) + return (-131); + if (!vf->seekable) + return (-138); + if (seconds < 0) + return (-131); + + for (link = 0; link < vf->links; link++) + { + double addsec = ov_time_total (vf, link); + if (seconds < time_total + addsec) + break; + time_total += addsec; + pcm_total += vf->pcmlengths[link * 2 + 1]; + } + + if (link == vf->links) + return (-131); + + { + ogg_int64_t target = + pcm_total + (seconds - time_total) * vf->vi[link].rate; + return (ov_pcm_seek_page (vf, target)); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36073.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36073.c new file mode 100644 index 000000000..b1587579e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36073.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O -march=core2 -mfpmath=sse,387 -ffast-math" } */ + +extern double log (double x); +extern int f (void); + +double cached_value; + +void g (void) +{ + cached_value = log (f ()); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36222-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36222-1.c new file mode 100644 index 000000000..2d4c5b9b7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36222-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef int __v4si __attribute__ ((__vector_size__ (16))); + +__m128i _mm_set_epi32 (int __q3, int __q2, int __q1, int __q0) +{ + return (__m128i)(__v4si){ __q0, __q1, __q2, __q3 }; +} + +/* { dg-final { scan-assembler-not "movdqa" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36246.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36246.c new file mode 100644 index 000000000..51b8c349b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36246.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -fomit-frame-pointer -mtune=generic" } */ + +typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef int __v4si __attribute__ ((__vector_size__ (16))); + +__m128i +_mm_set_epi32 (int __q3, int __q2, int __q1, int __q0) +{ + return (__m128i)(__v4si){ __q0, __q1, __q2, __q3 }; +} + +/* { dg-final { scan-assembler-not "movq" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36438.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36438.c new file mode 100644 index 000000000..38376b8c9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36438.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mmmx" } */ + +#include <mmintrin.h> + +extern __m64 SetS16 (unsigned short, unsigned short, + unsigned short, unsigned short); + +void foo(__m64* dest) +{ + __m64 mask = SetS16 (0x00FF, 0xFF00, 0x0000, 0x00FF); + + mask = _mm_slli_si64(mask, 8); + mask = _mm_slli_si64(mask, 8); + + *dest = mask; + + _mm_empty (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36502.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36502.c new file mode 100644 index 000000000..bc4c7ccf1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36502.c @@ -0,0 +1,7 @@ +/* PR target/36502 */ +/* { dg-do compile { target { *-*-darwin* && ilp32 } } } */ +/* { dg-options "-O -fomit-frame-pointer -fno-pic" } */ +int a; +void f() {a++;} +/* { dg-final { scan-assembler-not "esp" } } */ + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36533.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36533.c new file mode 100644 index 000000000..8d71ece19 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36533.c @@ -0,0 +1,174 @@ +/* PR target/36533 */ +/* { dg-do run { target { mmap && ilp32 } } } */ +/* { dg-options "-Os" } */ +#include <string.h> +#include <sys/mman.h> +#ifndef MAP_ANONYMOUS +#define MAP_ANONYMOUS MAP_ANON +#endif + +typedef struct S1 +{ + unsigned long s1; + struct S1 *s2; + char *s3; +} S1; + +typedef struct +{ + unsigned int s4; + unsigned int s5; + int s6; + unsigned int *s7; +} S2; + +typedef struct +{ + unsigned int s8; + unsigned short s9; + unsigned char s10; + unsigned char s11; + char s12[255]; +} S3; + +typedef struct +{ + unsigned int s4; + unsigned short s13; + unsigned short s14; +} S4; + +typedef struct +{ + char s15[16]; + unsigned long s16; +} S5; + +typedef struct +{ + char s15[48]; + S5 *s17; +} S6; + +typedef struct +{ + S1 *s18; +} S7; + +__attribute__((regparm (3), noinline)) int +fn1 (const char *x, void *y, S1 *z) +{ + asm volatile ("" : : : "memory"); + return *x + (y != 0); +} + +__attribute__((regparm (3), noinline)) int +fn2 (const char *x, int y, S2 *z) +{ + asm volatile ("" : : : "memory"); + return 0; +} + +static inline __attribute__ ((always_inline)) unsigned int +fn4 (unsigned short x) +{ + unsigned len = x; + if (len == ((1 << 16) - 1)) + return 1 << 16; + return len; +} + +static inline __attribute__ ((always_inline)) S3 * +fn3 (S3 *p) +{ + return (S3 *) ((char *) p + fn4 (p->s9)); +} + +__attribute__((regparm (3), noinline)) int +fn5 (void) +{ + asm volatile ("" : : : "memory"); + return 0; +} + +static inline __attribute__ ((always_inline)) int +fn6 (S3 *w, int x, S2 *y, S4 *z) +{ + int a = 2; + char *b = (char *) w; + S2 c = *y; + + while ((char *) w < b + x - 2 * sizeof (S4)) + { + if (w->s10 && w->s8) + { + fn2 (w->s12, w->s10, &c); + z--; + z->s4 = c.s4; + z->s13 = (unsigned short) ((char *) w - b); + z->s14 = w->s9; + a++; + fn5 (); + } + + w = fn3 (w); + } + return a; +} + +__attribute__((regparm (3), noinline)) unsigned int +test (void *u, S6 *v, S1 **w, S7 *x, S2 *y, S1 *z) +{ + unsigned b = v->s17->s16; + unsigned a; + S4 *c; + unsigned d, e, f, i; + + fn1 (__func__, u, x->s18); + c = (S4 *) (z->s3 + b); + a = fn6 ((S3 *) (*w)->s3, b, y, c); + c -= a; + f = 0; + e = 2; + for (i = a - 1; ; i--) + { + if (f + (unsigned short) (c[i].s14 / 2) > b / 2) + break; + f += c[i].s14; + e++; + } + d = a - e; + return c[d].s4; +} + +int main (void) +{ + char *p = mmap (NULL, 131072, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + S1 wb, z, *w; + S6 v; + S7 x; + S2 y; + S5 vb; + S4 s4; + if (p == MAP_FAILED) + return 0; + if (munmap (p + 65536, 65536) < 0) + return 0; + memset (&wb, 0, sizeof (wb)); + memset (&z, 0, sizeof (z)); + memset (&v, 0, sizeof (v)); + memset (&x, 0, sizeof (x)); + memset (&y, 0, sizeof (y)); + memset (&vb, 0, sizeof (vb)); + memset (&s4, 0, sizeof (s4)); + s4.s14 = 254; + z.s3 = p + 65536 - 2 * sizeof (S4); + w = &wb; + v.s17 = &vb; + vb.s16 = 2 * sizeof (S4); + memcpy (z.s3, &s4, sizeof (s4)); + memcpy (z.s3 + sizeof (s4), &s4, sizeof (s4)); + test ((void *) 0, &v, &w, &x, &y, &z); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36578-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36578-1.c new file mode 100644 index 000000000..5ede23a11 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36578-1.c @@ -0,0 +1,24 @@ +/* Test for unsafe floating-point conversions. PR 36578. */ +/* { dg-do run } */ +/* { dg-options "-msse2 -mfpmath=sse" } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-require-effective-target large_long_double } */ + +#include "sse2-check.h" + +extern void abort (void); +extern void exit (int); +extern int printf(const char *, ...); + +volatile double d1 = 1.0; +volatile double d2 = 0x1.00001p-53; +volatile double d3; + +static void +sse2_test (void) +{ + d3 = (double)((long double)d1 + (long double)d2); + if (d3 != d1) + abort (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36578-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36578-2.c new file mode 100644 index 000000000..bfde2cb0f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36578-2.c @@ -0,0 +1,29 @@ +/* Test for unsafe floating-point conversions. */ +/* { dg-do run } */ +/* { dg-options "-msse2 -mfpmath=sse" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +extern void abort (void); +extern void exit (int); +extern int printf(const char *, ...); + +volatile double d1 = 0x1.000001p0; +volatile double d2 = 0x1p-54; +volatile double d2d = 0x1p-52; +volatile float f = 0x1.000002p0f; +volatile float f2; + +static void +sse2_test (void) +{ + if (sizeof(long double) > sizeof(double) ) { + f2 = (float)((long double)d1 + (long double)d2); + } else { + f2 = (float)((long double)d1 + (long double)d2d); + } + if (f != f2) + abort (); + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36613.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36613.c new file mode 100644 index 000000000..e9d7d11ce --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36613.c @@ -0,0 +1,44 @@ +/* { dg-do run { target { { i?86-*-linux* x86_64-*-linux* } && ilp32 } } } */ +/* { dg-options "-Os" } */ +/* PR target/36613 */ + +extern void abort (void); + +static inline int +lshifts (int val, int cnt) +{ + if (val < 0) + return val; + return val << cnt; +} + +static inline unsigned int +lshiftu (unsigned int val, unsigned int cnt) +{ + if (cnt >= sizeof (unsigned int) * __CHAR_BIT__ + || val > ((__INT_MAX__ * 2U) >> cnt)) + return val; + return val << cnt; +} + +static inline int +rshifts (int val, unsigned int cnt) +{ + if (val < 0 || cnt >= sizeof (int) * __CHAR_BIT__) + return val; + return val >> cnt; +} + +int +foo (unsigned int val) +{ + return rshifts (1 + val, lshifts (lshiftu (val, val), 1)); +} + +int +main (void) +{ + if (foo (1) != 0) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36753.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36753.c new file mode 100644 index 000000000..2d43d42a0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36753.c @@ -0,0 +1,31 @@ +/* { dg-options "-O2" } */ +/* { dg-do run } */ + +#if defined __i386__ +#define REG "edi" +#else +#define REG "r14" +#endif + +register unsigned long *ds asm(REG); + +extern void abort (void); + +__attribute__ ((noinline)) void +test (void) +{ + *++ds = 31337; +} + +int +main () +{ + unsigned long stack[2]; + stack[0] = 0; + stack[1] = 0; + ds = stack; + test (); + if (ds != stack + 1 || *ds != 31337) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36786.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36786.c new file mode 100644 index 000000000..6b62e80e7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36786.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ + +typedef int DItype __attribute__ ((mode (DI))); +typedef unsigned int UDItype __attribute__ ((mode (DI))); +typedef int TItype __attribute__ ((mode (TI))); + +__floattisf (TItype u) +{ + DItype hi = u >> (8 * 8); + UDItype count, shift; + hi = u >> shift; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36992-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36992-1.c new file mode 100644 index 000000000..345c1f276 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36992-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } +/* { dg-options "-O2 -msse2" } */ + +#include <emmintrin.h> + +__m128i +test (__m128i b) +{ + return _mm_move_epi64 (b); +} + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+\[^\n\]*%xmm" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36992-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36992-2.c new file mode 100644 index 000000000..25ff34be1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr36992-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } +/* { dg-options "-O2 -msse4" } */ + +#include <emmintrin.h> + +__m128i +test (__m128i b) +{ + return _mm_move_epi64 (b); +} + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+\[^\n\]*%xmm" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37101.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37101.c new file mode 100644 index 000000000..8fd3bfc5f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37101.c @@ -0,0 +1,64 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -ftree-vectorize -march=nocona" } */ + +typedef __SIZE_TYPE__ size_t; +extern void *malloc (size_t); +extern void free (void *); + +typedef struct _Resource +{ + struct _Resource *next; + unsigned int id; +} ResourceRec, *ResourcePtr; + +typedef struct _ClientResource +{ + ResourcePtr *resources; + int elements; + int buckets; + int hashsize; +} ClientResourceRec; + +static ClientResourceRec clientTable[256]; + +void +RebuildTable (int client) +{ + int j; + ResourcePtr res, next; + ResourcePtr **tails, *resources; + ResourcePtr **tptr, *rptr; + + j = 2 * clientTable[client].buckets; + + tails = + (ResourcePtr **) malloc ((unsigned long) (j * sizeof (ResourcePtr *))); + resources = + (ResourcePtr *) malloc ((unsigned long) (j * sizeof (ResourcePtr))); + + for (rptr = resources, tptr = tails; --j >= 0; rptr++, tptr++) + { + *rptr = ((ResourcePtr) ((void *) 0)); + *tptr = rptr; + } + + clientTable[client].hashsize++; + for (j = clientTable[client].buckets, + rptr = clientTable[client].resources; --j >= 0; rptr++) + { + for (res = *rptr; res; res = next) + { + next = res->next; + res->next = ((ResourcePtr) ((void *) 0)); + tptr = &tails[Hash (client, res->id)]; + **tptr = res; + *tptr = &res->next; + } + } + free ((void *) tails); + clientTable[client].buckets *= 2; + free ((void *) clientTable[client].resources); + clientTable[client].resources = resources; +} + +/* { dg-final { scan-assembler-not "movlps" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37184.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37184.c new file mode 100644 index 000000000..14e11f707 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37184.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O1" } */ + +static inline unsigned int +rshift_u_s (unsigned int left, int right) +{ + return left >> right; +} + +unsigned int g_15; + +int func_29 (int p_30) +{ + unsigned int l_31; + unsigned long long int l_35 = 0x7736EAE11771B705LL; + unsigned int l_36 = 0xEDB553A8L; + + l_31 = g_15; + if ((l_31 < + (rshift_u_s ((g_15 - (g_15 >= l_35)), (l_36 <= 1)))) + mod_rhs (1)) + return 1; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37191.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37191.c new file mode 100644 index 000000000..b315ce072 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37191.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -mmmx" } */ +/* { dg-skip-if "no stdint" { vxworks_kernel } } */ + +#include <mmintrin.h> +#include <stddef.h> +#include <stdint.h> + +extern const uint64_t ff_bone; + +static inline void transpose4x4(uint8_t *dst, uint8_t *src, ptrdiff_t dst_stride, ptrdiff_t src_stride) { + __m64 row0 = _mm_cvtsi32_si64(*(unsigned*)(src + (0 * src_stride))); + __m64 row1 = _mm_cvtsi32_si64(*(unsigned*)(src + (1 * src_stride))); + __m64 row2 = _mm_cvtsi32_si64(*(unsigned*)(src + (2 * src_stride))); + __m64 row3 = _mm_cvtsi32_si64(*(unsigned*)(src + (3 * src_stride))); + __m64 tmp0 = _mm_unpacklo_pi8(row0, row1); + __m64 tmp1 = _mm_unpacklo_pi8(row2, row3); + __m64 row01 = _mm_unpacklo_pi16(tmp0, tmp1); + __m64 row23 = _mm_unpackhi_pi16(tmp0, tmp1); + *((unsigned*)(dst + (0 * dst_stride))) = _mm_cvtsi64_si32(row01); + *((unsigned*)(dst + (1 * dst_stride))) = _mm_cvtsi64_si32(_mm_unpackhi_pi32(row01, row01)); + *((unsigned*)(dst + (2 * dst_stride))) = _mm_cvtsi64_si32(row23); + *((unsigned*)(dst + (3 * dst_stride))) = _mm_cvtsi64_si32(_mm_unpackhi_pi32(row23, row23)); +} + +static inline void h264_loop_filter_chroma_intra_mmx2(uint8_t *pix, int stride, int alpha1, int beta1) +{ + asm volatile( + "" + :: "r"(pix-2*stride), "r"(pix), "r"((long)stride), + "m"(alpha1), "m"(beta1), "m"(ff_bone) + ); +} + +void h264_h_loop_filter_chroma_intra_mmx2(uint8_t *pix, int stride, int alpha, int beta) +{ + + uint8_t trans[8*4] __attribute__ ((aligned (8))); + transpose4x4(trans, pix-2, 8, stride); + transpose4x4(trans+4, pix-2+4*stride, 8, stride); + h264_loop_filter_chroma_intra_mmx2(trans+2*8, 8, alpha-1, beta-1); + transpose4x4(pix-2, trans, stride, 8); + transpose4x4(pix-2+4*stride, trans+4, stride, 8); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37197.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37197.c new file mode 100644 index 000000000..95565e802 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37197.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse4" } */ + +int testl (unsigned long *a, int b) +{ + return b ? 1 : __builtin_parityl (*a); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37216.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37216.c new file mode 100644 index 000000000..05eb2eea7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37216.c @@ -0,0 +1,18 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -msse2" } */ +/* { dg-options "-O3 -msse2 -mpe-aligned-commons" { target pe_aligned_commons } } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +int iarr[64]; +int iint = 0; + +void +sse2_test (void) +{ + int i; + + for (i = 0; i < 64; i++) + iarr[i] = -2; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37248-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37248-1.c new file mode 100644 index 000000000..4107fd6e2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37248-1.c @@ -0,0 +1,20 @@ +/* PR middle-end/37248 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ + +struct S +{ + unsigned char a : 1; + unsigned char b : 1; + unsigned char c : 1; +} s; + +int +foo (struct S x) +{ + return x.a && x.b && x.c; +} + +/* { dg-final { scan-tree-dump "& 7;" "optimized" } } */ +/* { dg-final { scan-tree-dump "== 7;" "optimized" } } */ +/* { dg-final { cleanup-tree-dump "optimized" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37248-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37248-2.c new file mode 100644 index 000000000..3ea4d6693 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37248-2.c @@ -0,0 +1,24 @@ +/* PR middle-end/37248 */ +/* { dg-do compile { target { ! default_packed } } } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ + +struct S +{ + unsigned char a : 1; + unsigned char b : 1; + unsigned char c : 1; + unsigned int d : 26; + unsigned char e : 1; + unsigned char f : 1; + unsigned char g : 1; +} s; + +int +foo (struct S x) +{ + return x.a && x.g && x.b && x.f && x.c && x.e; +} + +/* { dg-final { scan-tree-dump "& (3758096391|0x0e0000007);" "optimized" } } */ +/* { dg-final { scan-tree-dump "== (3758096391|0x0e0000007);" "optimized" } } */ +/* { dg-final { cleanup-tree-dump "optimized" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37248-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37248-3.c new file mode 100644 index 000000000..60ef71696 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37248-3.c @@ -0,0 +1,26 @@ +/* PR middle-end/37248 */ +/* { dg-do compile { target { ! default_packed } } } */ +/* { dg-options "-O2 -fdump-tree-optimized -mno-ms-bitfields" } */ + +struct S +{ + unsigned char a : 1; + unsigned char b : 1; + unsigned char c : 1; + unsigned int d : 6; + unsigned int e : 14; + unsigned int f : 6; + unsigned char g : 1; + unsigned char h : 1; + unsigned char i : 1; +} s; + +int +foo (struct S x) +{ + return x.a && x.i && x.b && x.h && x.c && x.g && x.e == 131; +} + +/* { dg-final { scan-tree-dump "& (3766484487|0x0e07ffe07);" "optimized" } } */ +/* { dg-final { scan-tree-dump "== (3758163463|0x0e0010607);" "optimized" } } */ +/* { dg-final { cleanup-tree-dump "optimized" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37275.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37275.c new file mode 100644 index 000000000..cf748879e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37275.c @@ -0,0 +1,138 @@ +/* PR middle-end/37275 */ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-g -dA -O2 -march=i686 -fstack-protector" } */ +/* { dg-require-visibility "" } */ + +typedef __SIZE_TYPE__ size_t; +extern void *memcpy (void *, const void *, size_t); +extern void *malloc (size_t); + +typedef int A; + +struct B +{ + int x; +}; + +struct C +{ + struct F *c1; + void *c2; +}; + +enum D +{ + D0, + D1 +}; + +struct E +{ + struct E *e1; + struct E *e2; + struct B e3; + void (*fn) (void *); + void *fn_data; + enum D e4; + _Bool e5; + _Bool e6; +}; + +struct F +{ + unsigned f1; + A f2; + int f3; +}; + +struct G +{ + void (*fn) (void *data); + void *data; + struct C g1; + struct E *t; +}; + +extern void fn1 (A * m); +static inline void +fn2 (A *x) +{ + if (!__sync_bool_compare_and_swap (x, 0, 1)) + fn1 (x); +} + +extern __thread struct G thr __attribute__ ((visibility ("hidden"))); +static inline struct G * +fn3 (void) +{ + return &thr; +} + +extern struct B *fn4 (void); +extern struct B a; + +static inline struct B * +fn5 (_Bool x) +{ + struct E *t = fn3 ()->t; + if (t) + return &t->e3; + else if (x) + return fn4 (); + else + return &a; +} + +void +fn6 (struct E *t, struct E *e1_t, + struct B *prev_e3) +{ + t->e1 = e1_t; + t->e3 = *prev_e3; + t->e4 = D0; + t->e5 = 0; + t->e6 = 0; + t->e2 = ((void *) 0); +} + +void +test (void (*fn) (void *), void *data, void (*cpyfn) (void *, void *), long x, long y, _Bool z) +{ + struct G *thr = fn3 (); + struct F *c1 = thr->g1.c1; + if (!z || c1 == 0 || (unsigned) c1->f3 > 64 * c1->f1) + { + struct E t; + + fn6 (&t, thr->t, fn5 (0)); + if (thr->t) + t.e6 = thr->t->e6; + thr->t = &t; + if (__builtin_expect (cpyfn != ((void *) 0), 0)) + { + char buf[x + y - 1]; + char *arg = (char *) (((unsigned long) buf + y - 1) + & ~(unsigned long) (y - 1)); + cpyfn (arg, data); + fn (arg); + } + } + else + { + struct E *t; + struct E *e1 = thr->t; + char *arg; + + t = malloc (sizeof (*t) + x + y - 1); + arg = (char *) (((unsigned long) (t + 1) + y - 1) + & ~(unsigned long) (y - 1)); + fn6 (t, e1, fn5 (0)); + thr->t = t; + if (cpyfn) + cpyfn (arg, data); + else + memcpy (arg, data, x); + thr->t = e1; + fn2 (&c1->f2); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37434-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37434-1.c new file mode 100644 index 000000000..b556bf084 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37434-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef short __v8hi __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); +__m128i Set_AC4R_SETUP_I( const short *val ) { + short D2073 = *val; + short D2076 = *(val + 2); + short D2079 = *(val + 4); + __v8hi D2094 = {D2073, D2076, D2079, 0, D2073, D2076, D2079, 0}; + return (__m128i)D2094; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37434-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37434-2.c new file mode 100644 index 000000000..00ff9fd2e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37434-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=core2 -msse2" } */ + +typedef short __v8hi __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); +__m128i Set_AC4R_SETUP_I( const short *val ) { + short D2073 = *val; + short D2076 = *(val + 2); + short D2079 = *(val + 4); + __v8hi D2094 = {D2073, D2076, D2079, 0, D2073, D2076, D2079, 0}; + return (__m128i)D2094; +} + +/* { dg-final { scan-assembler "pinsrw" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37434-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37434-3.c new file mode 100644 index 000000000..2cc597b04 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37434-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse4.1" } */ + +typedef char __v16qi __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); +__m128i Set_AC4R_SETUP_I( const char *val ) { + char D2073 = *val; + char D2074 = *(val + 1); + char D2075 = *(val + 2); + char D2076 = *(val + 3); + char D2077 = *(val + 4); + char D2078 = *(val + 5); + char D2079 = *(val + 6); + __v16qi D2094 = {D2073, D2074, D2075, D2076, D2077, D2078, D2079, 0, + D2073, D2074, D2075, D2076, D2077, D2078, D2079, 0}; + return (__m128i)D2094; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37434-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37434-4.c new file mode 100644 index 000000000..6848c6350 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37434-4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=core2 -msse4.1" } */ + +typedef char __v16qi __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); +__m128i Set_AC4R_SETUP_I( const char *val ) { + char D2073 = *val; + char D2074 = *(val + 1); + char D2075 = *(val + 2); + char D2076 = *(val + 3); + char D2077 = *(val + 4); + char D2078 = *(val + 5); + char D2079 = *(val + 6); + __v16qi D2094 = {D2073, D2074, D2075, D2076, D2077, D2078, D2079, 0, + D2073, D2074, D2075, D2076, D2077, D2078, D2079, 0}; + return (__m128i)D2094; +} + +/* { dg-final { scan-assembler "pinsrb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37843-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37843-1.c new file mode 100644 index 000000000..981988223 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37843-1.c @@ -0,0 +1,13 @@ +/* Test for stack alignment with sibcall optimization. */ +/* { dg-do compile { target nonpic } } */ +/* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=5" } */ +/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */ +/* { dg-final { scan-assembler "call\[\\t \]*_?foo" } } */ +/* { dg-final { scan-assembler-not "jmp\[\\t \]*_?foo" } } */ + +extern int foo (void); + +int bar (void) +{ + return foo(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37843-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37843-2.c new file mode 100644 index 000000000..fa177714a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37843-2.c @@ -0,0 +1,13 @@ +/* Test for stack alignment with sibcall optimization. */ +/* { dg-do compile { target nonpic } } */ +/* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */ +/* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */ +/* { dg-final { scan-assembler-not "call\[\\t \]*_?foo" } } */ +/* { dg-final { scan-assembler "jmp\[\\t \]*_?foo" } } */ + +extern int foo (void); + +int bar (void) +{ + return foo(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37843-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37843-3.c new file mode 100644 index 000000000..56f1170eb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37843-3.c @@ -0,0 +1,16 @@ +/* Test for stack alignment with sibcall optimization. */ +/* { dg-do compile { target { ia32 && nonpic } } } */ +/* { dg-options "-O2 -msse2 -mpreferred-stack-boundary=4 -mstackrealign" } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%\[re\]?sp" } } */ +/* { dg-final { scan-assembler-not "call\[\\t \]*_?foo" } } */ +/* { dg-final { scan-assembler "jmp\[\\t \]*_?foo" } } */ + +#include <emmintrin.h> + +extern int foo (__m128, __m128, __m128, __m128); + +int bar (__m128 x1, __m128 x2, __m128 x3, __m128 x4) +{ + return foo (x1, x2, x3, x4); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37843-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37843-4.c new file mode 100644 index 000000000..cd56bae41 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37843-4.c @@ -0,0 +1,14 @@ +/* Test for stack alignment with sibcall optimization. */ +/* { dg-do compile { target { ia32 && nonpic } } } */ +/* { dg-options "-O2 -msse2 -mpreferred-stack-boundary=4 -mstackrealign" } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%\[re\]?sp" } } */ +/* { dg-final { scan-assembler-not "call\[\\t \]*_?foo" } } */ +/* { dg-final { scan-assembler "jmp\[\\t \]*_?foo" } } */ + +extern int foo (void); + +int bar (void) +{ + return foo(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37870.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37870.c new file mode 100644 index 000000000..19cfb2058 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr37870.c @@ -0,0 +1,29 @@ +/* PR middle-end/37870 */ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +unsigned int +foo (long double x) +{ + struct { char a[8]; unsigned int b:7; } c; + __builtin_memcpy (&c, &x, sizeof (c)); + return c.b; +} + +unsigned int +bar (long double x) +{ + union { struct { char a[8]; unsigned int b:7; } c; long double d; } u; + u.d = x; + return u.c.b; +} + +int +main (void) +{ + if (foo (1.245L) != bar (1.245L) + || foo (245.67L) != bar (245.67L) + || foo (0.00567L) != bar (0.00567L)) + __builtin_abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38151-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38151-1.c new file mode 100644 index 000000000..6500a5029 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38151-1.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +void abort (void); + +struct S2848 +{ + unsigned int a; + _Complex int b; +}; + +struct S2848 s2848; + +void __attribute__((noinline)) +check2848 (struct S2848 arg0) +{ + if (arg0.b != s2848.b) + abort (); +} + +int main() +{ + s2848.a = 4027477739U; + s2848.b = (723419448 + -218144346 * __extension__ 1i); + + check2848 (s2848); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38240.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38240.c new file mode 100644 index 000000000..99e875894 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38240.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-msse" } */ + +typedef float V + __attribute__ ((__vector_size__ (16), __may_alias__)); + +V __attribute__((target("sse"))) f(const V *ptr) { return *ptr; } + +V g(const V *ptr) { return *ptr; } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38824.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38824.c new file mode 100644 index 000000000..9fbfc502d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38824.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse -mno-sse2" } */ + +typedef float v4sf __attribute__ ((__vector_size__ (16))); + +void bench_1(float * out, float * in, float f, unsigned int n) +{ + n /= 4; + v4sf scalar = { f, f, f, f }; + do + { + v4sf arg = *(v4sf *)in; + v4sf result = arg + scalar; + *(v4sf *) out = result; + in += 4; + out += 4; + } + while (--n); +} + +/* { dg-final { scan-assembler-not "addps\[^\\n\]*%\[er\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38931.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38931.c new file mode 100644 index 000000000..dd35dec75 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38931.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse" } */ + +typedef int __m64 __attribute__ ((__vector_size__ (8))); + +extern __m64 foo () ; + +void bar (const int input_bpl, const unsigned char *input, + unsigned char *output, unsigned long x1) +{ + unsigned char *pix_end_ptr = output + x1 * 4; + __m64 m_original = { 0, 0 }; + __m64 m_base_addr = __builtin_ia32_vec_init_v2si (0, input_bpl); + __m64 m_addr = __builtin_ia32_paddd (m_original, m_base_addr); + __m64 *a0 = (__m64 *) input; + + for (; output < pix_end_ptr; output += 4) + { + a0 = (__m64 *) (input + __builtin_ia32_vec_ext_v2si (m_addr, 0)); + m_addr = foo (); + __builtin_prefetch (a0, 0); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38988.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38988.c new file mode 100644 index 000000000..8449cc69c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr38988.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -fpic -mcmodel=large" } */ + +__extension__ typedef __SIZE_TYPE__ size_t; +typedef void (*func_ptr) (void); + +static func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) }; + +void +__do_global_dtors_aux (void) +{ + extern func_ptr __DTOR_END__[]; + size_t dtor_idx = 0; + const size_t max_idx = __DTOR_END__ - __DTOR_LIST__ - 1; + func_ptr f; + + while (dtor_idx < max_idx) + { + f = __DTOR_LIST__[++dtor_idx]; + f (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39013-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39013-1.c new file mode 100644 index 000000000..25f02fcdb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39013-1.c @@ -0,0 +1,15 @@ +/* PR target/39013 */ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpie -std=gnu89" } */ + +inline int foo (void); +extern inline int bar (void); + +int +main (void) +{ + return foo () + bar (); +} + +/* { dg-final { scan-assembler "foo@PLT" } } */ +/* { dg-final { scan-assembler "bar@PLT" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39013-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39013-2.c new file mode 100644 index 000000000..615d54900 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39013-2.c @@ -0,0 +1,15 @@ +/* PR target/39013 */ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fpie -std=gnu99" } */ + +inline int foo (void); /* { dg-warning "declared but never defined" } */ +extern inline int bar (void); /* { dg-warning "declared but never defined" } */ + +int +main (void) +{ + return foo () + bar (); +} + +/* { dg-final { scan-assembler "foo@PLT" } } */ +/* { dg-final { scan-assembler "bar@PLT" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39058.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39058.c new file mode 100644 index 000000000..2982e8d14 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39058.c @@ -0,0 +1,34 @@ +/* PR inline-asm/39058 */ +/* { dg-options "-O2" } */ + +double +f1 () +{ + double x; + asm ("" : "=r,r" (x) : "0,0" (x)); + return x; +} + +double +f2 () +{ + double x; + asm ("" : "=r" (x) : "0" (x)); + return x; +} + +double +f3 () +{ + double x, y; + asm ("" : "=r,r" (x), "=r,r" (y) : "%0,0" (x), "r,r" (0)); + return x; +} + +double +f4 () +{ + double x, y; + asm ("" : "=r" (x), "=r" (y) : "0" (x), "r" (0)); + return x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39082-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39082-1.c new file mode 100644 index 000000000..36d566dc1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39082-1.c @@ -0,0 +1,35 @@ +/* PR target/39082 */ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ + +union un +{ + long double x; + int i; +}; + +extern int bar1 (union un); +extern union un bar2 (int); + +int +foo1 (union un u) /* { dg-message "note: the ABI of passing union with long double has changed in GCC 4.4" } */ +{ + bar1 (u); + return u.i; +} + +int +foo2 (void) +{ + union un u; + u.i = 1; + return foo1 (u) + bar1 (u); +} + +int +foo3 (int x) +{ + union un u = bar2 (x); + return u.i; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39139.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39139.c new file mode 100644 index 000000000..e4cb845f9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39139.c @@ -0,0 +1,41 @@ +/* PR target/39139 */ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + +#ifdef __x86_64__ +# define AX_REG asm ("rax") +# define DI_REG asm ("rdi") +# define SI_REG asm ("rsi") +#else +# define AX_REG asm ("eax") +# define DI_REG asm ("edi") +# define SI_REG asm ("esi") +#endif + +__extension__ typedef __SIZE_TYPE__ size_t; + +static inline int +foo (unsigned int x, void *y) +{ + register size_t r AX_REG; + register size_t a1 DI_REG; + register size_t a2 SI_REG; + a1 = (size_t) x; + a2 = (size_t) y; + asm volatile ("" : "=r" (r), "+r" (a1), "+r" (a2) : : "memory"); + return (int) r; +} + +struct T { size_t t1, t2; unsigned int t3, t4, t5; }; + +int +bar (size_t x, unsigned int y, size_t u, unsigned int v) +{ + long r; + struct T e = { .t1 = x, .t2 = u }; + + if (x << y != u << v) + return 5; + r = foo (11, &e); + return e.t3 == x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39162.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39162.c new file mode 100644 index 000000000..c549106ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39162.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-psabi -msse2 -mno-avx" } */ +/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ + +typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__)); + +__m256i +bar (__m256i x) /* { dg-warning "AVX" "" } */ +{ + return x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-1.c new file mode 100644 index 000000000..16ba5d59f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-1.c @@ -0,0 +1,18 @@ +/* PR middle-end/39315 */ +/* { dg-do compile } */ +/* { dg-options "-O -msse2 -mtune=generic" } */ +/* { dg-final { scan-assembler-not "movups" } } */ +/* { dg-final { scan-assembler-not "movlps" } } */ +/* { dg-final { scan-assembler-not "movhps" } } */ +/* { dg-final { scan-assembler "movaps" } } */ + +typedef float __m128 __attribute__ ((__vector_size__ (16))); + +extern void bar (__m128 *); + +void +foo (__m128 *x) +{ + __m128 b = *x; + bar (&b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-2.c new file mode 100644 index 000000000..c1a3da75a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-2.c @@ -0,0 +1,16 @@ +/* PR middle-end/39315 */ +/* { dg-do run } */ +/* { dg-options "-O -msse2 -mtune=generic" } */ +/* { dg-require-effective-target sse2_runtime } */ +/* { dg-additional-sources pr39315-check.c } */ + +typedef float __m128 __attribute__ ((__vector_size__ (16))); + +extern void bar (__m128 *, int); + +void +foo (__m128 *x) +{ + __m128 b = *x; + bar (&b, __alignof__ (x)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-3.c new file mode 100644 index 000000000..3b61ad025 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-3.c @@ -0,0 +1,19 @@ +/* PR middle-end/39315 */ +/* { dg-do compile } */ +/* { dg-options "-O -msse2 -mtune=generic" } */ +/* { dg-final { scan-assembler-not "movups" } } */ +/* { dg-final { scan-assembler-not "movlps" } } */ +/* { dg-final { scan-assembler-not "movhps" } } */ +/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" { target { ! x86_64-*-mingw* } } } } */ +/* { dg-final { scan-assembler "movaps" } } */ + +typedef float __m128 __attribute__ ((__vector_size__ (16))); + +extern void bar (__m128 *); + +void +foo (__m128 *x) +{ + __m128 b __attribute__ ((aligned(128))) = *x; + bar (&b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-4.c new file mode 100644 index 000000000..77258a7c7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-4.c @@ -0,0 +1,16 @@ +/* PR middle-end/39315 */ +/* { dg-do run } */ +/* { dg-options "-O -msse2 -mtune=generic" } */ +/* { dg-require-effective-target sse2_runtime } */ +/* { dg-additional-sources pr39315-check.c } */ + +typedef float __m128 __attribute__ ((__vector_size__ (16))); + +extern void bar (__m128 *, int); + +void +foo (__m128 *x) +{ + __m128 b __attribute__ ((aligned(128))) = *x; + bar (&b, __alignof__ (x)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-check.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-check.c new file mode 100644 index 000000000..cb09d3f2b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39315-check.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ + +typedef float __m128 __attribute__ ((__vector_size__ (16))); +__extension__ typedef __PTRDIFF_TYPE__ ptrdiff_t; + +extern void foo (__m128 *); +extern void abort (void); + +__m128 y = { 0.0, 1.0, 2.0, 3.0 }; + +void +bar (__m128 *x, int align) +{ + if ((((ptrdiff_t) x) & (align - 1)) != 0) + abort (); + if (__builtin_memcmp (x, &y, sizeof (y)) != 0) + abort (); +} + +int +main () +{ + foo (&y); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39431.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39431.c new file mode 100644 index 000000000..0db7d5643 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39431.c @@ -0,0 +1,15 @@ +/* PR target/39431 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-options "-O2 -march=i686 -fpic" { target { ia32 && fpic } } } */ + +extern void bar (char *, int); + +int +foo (long long *p, long long oldv, long long *q, int n) +{ + char buf[n]; + bar (buf, n); + p[256 + n] = __sync_val_compare_and_swap (p + n, oldv, oldv + 6); + return __sync_bool_compare_and_swap (q + n, oldv, oldv + 8); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39445.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39445.c new file mode 100644 index 000000000..48e2d39a6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39445.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-Os -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +typedef struct { __m128 f __attribute__((packed)); } packed; + +__m128 __attribute__((noinline)) +foo (__m128 a1, __m128 a2, __m128 a3, __m128 a4, + __m128 a5, __m128 a6, __m128 a7, __m128 a8, + int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y) +{ + return y.f; +} + +void +sse2_test (void) +{ + packed x; + __m128 y = { 0 }; + x.f = y; + y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x); + if (__builtin_memcmp (&y, &x.f, sizeof (y)) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39482.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39482.c new file mode 100644 index 000000000..4e2dfa724 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39482.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-sse2" } */ + +extern double log (double __x); + +double foo (unsigned long int m_liOutputBufferLen) +{ + return log ((double) m_liOutputBufferLen); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39496.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39496.c new file mode 100644 index 000000000..e14c87513 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39496.c @@ -0,0 +1,35 @@ +/* PR target/39496 */ +/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && ia32 } } } */ +/* { dg-options "-O0 -fverbose-asm -fno-omit-frame-pointer -mtune=i686 -msse2 -mfpmath=sse" } */ +/* Verify that {foo,bar}{,2}param are all passed on the stack, using + normal calling conventions, when not optimizing. */ +/* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*fooparam," } } */ +/* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*barparam," } } */ +/* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*foo2param," } } */ +/* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*bar2param," } } */ + +static inline int foo (int fooparam) +{ + return fooparam; +} + +static int bar (int barparam) +{ + return foo (barparam); +} + +static inline double foo2 (double foo2param) +{ + return foo2param; +} + +static double bar2 (double bar2param) +{ + return foo2 (bar2param); +} + +int +main () +{ + return bar (0) + bar2 (0.0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39543-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39543-1.c new file mode 100644 index 000000000..a8442b2e6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39543-1.c @@ -0,0 +1,52 @@ +/* PR inline-asm/39543 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -fomit-frame-pointer" } */ + +float __attribute__ ((aligned (16))) s0[128]; +const float s1 = 0.707; +float s2[8] __attribute__ ((aligned (16))); +float s3[8] __attribute__ ((aligned (16))); +float s4[16] __attribute__ ((aligned (16))); +float s5[16] __attribute__ ((aligned (16))); + +void +foo (int k, float *x, float *y, const float *d, const float *z) +{ + float *a, *b, *c, *e; + + a = x + 2 * k; + b = a + 2 * k; + c = b + 2 * k; + e = y + 2 * k; + __asm__ volatile ("" + : "=m" (x[0]), "=m" (b[0]), "=m" (a[0]), "=m" (c[0]) + : "m" (y[0]), "m" (y[k * 2]), "m" (x[0]), "m" (a[0]) + : "memory"); + for (;;) + { + __asm__ volatile ("" + : + : "m" (y[2]), "m" (d[2]), "m" (e[2]), "m" (z[2]) + : "memory"); + if (!--k) + break; + } + __asm__ volatile ("" + : "=m" (x[2]), "=m" (x[10]), "=m" (x[6]), "=m" (x[14]) + : "m" (y[2]), "m" (y[6]), "m" (x[2]), "m" (x[6]), + "m" (y[18]), "m" (s1) + : "memory"); +} + +void +bar (float *a) +{ + foo (4, a, a + 16, s2, s3); + foo (8, a, a + 32, s4, s5); +} + +void +baz (void) +{ + bar (s0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39543-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39543-2.c new file mode 100644 index 000000000..7f4e5a42a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39543-2.c @@ -0,0 +1,52 @@ +/* PR inline-asm/39543 */ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */ + +float __attribute__ ((aligned (16))) s0[128]; +const float s1 = 0.707; +float s2[8] __attribute__ ((aligned (16))); +float s3[8] __attribute__ ((aligned (16))); +float s4[16] __attribute__ ((aligned (16))); +float s5[16] __attribute__ ((aligned (16))); + +void +foo (int k, float *x, float *y, const float *d, const float *z) +{ + float *a, *b, *c, *e; + + a = x + 2 * k; + b = a + 2 * k; + c = b + 2 * k; + e = y + 2 * k; + __asm__ volatile ("" + : "=m" (x[0]), "=m" (b[0]), "=m" (a[0]), "=m" (c[0]) + : "m" (y[0]), "m" (y[k * 2]), "m" (x[0]), "m" (a[0]) + : "memory"); + for (;;) + { + __asm__ volatile ("" + : + : "m" (y[2]), "m" (d[2]), "m" (e[2]), "m" (z[2]) + : "memory"); + if (!--k) + break; + } + __asm__ volatile ("" + : "=m" (x[2]), "=m" (x[10]), "=m" (x[6]), "=m" (x[14]) + : "m" (y[2]), "m" (y[6]), "m" (x[2]), "m" (x[6]), "m" (s1) + : "memory"); +} + +void +bar (float *a) +{ + foo (4, a, a + 16, s2, s3); + foo (8, a, a + 32, s4, s5); +} + +void +baz (void) +{ + bar (s0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39543-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39543-3.c new file mode 100644 index 000000000..4e103e671 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39543-3.c @@ -0,0 +1,42 @@ +/* PR inline-asm/39543 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int s[128]; + +void +f1 (void) +{ + int i; + asm volatile ("# %0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17" + : "=r" (i) + : "m" (s[0]), "m" (s[2]), "m" (s[4]), "m" (s[6]), "m" (s[8]), + "m" (s[10]), "m" (s[12]), "m" (s[14]), "m" (s[16]), "m" (s[18]), + "m" (s[20]), "m" (s[22]), "m" (s[24]), "m" (s[26]), "m" (s[28]), + "m" (s[30]), "m" (s[32])); + asm volatile ("# %0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17" + : "=r" (i) + : "m" (s[0]), "m" (s[2]), "m" (s[4]), "m" (s[6]), "m" (s[8]), + "m" (s[10]), "m" (s[12]), "m" (s[14]), "m" (s[16]), "m" (s[18]), + "m" (s[20]), "m" (s[22]), "m" (s[24]), "m" (s[26]), "m" (s[28]), + "m" (s[30]), "m" (s[32])); +} + +void +f2 (int *q) +{ + int i; + int *p = q + 32; + asm volatile ("# %0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17" + : "=r" (i) + : "m" (p[0]), "m" (p[2]), "m" (p[4]), "m" (p[6]), "m" (p[8]), + "m" (p[10]), "m" (p[12]), "m" (p[14]), "m" (p[16]), "m" (p[18]), + "m" (p[20]), "m" (p[22]), "m" (p[24]), "m" (p[26]), "m" (p[28]), + "m" (p[30]), "m" (p[32])); + asm volatile ("# %0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17" + : "=r" (i) + : "m" (p[0]), "m" (p[2]), "m" (p[4]), "m" (p[6]), "m" (p[8]), + "m" (p[10]), "m" (p[12]), "m" (p[14]), "m" (p[16]), "m" (p[18]), + "m" (p[20]), "m" (p[22]), "m" (p[24]), "m" (p[26]), "m" (p[28]), + "m" (p[30]), "m" (p[32])); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39545-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39545-1.c new file mode 100644 index 000000000..e7e41164b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39545-1.c @@ -0,0 +1,24 @@ +/* PR target/39545 */ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2" } */ + +struct flex +{ + int i; + int flex []; +}; + +int +foo (struct flex s) +{ + return s.i; +} + +struct flex +bar (int x) +{ /* { dg-message "note: the ABI of passing struct with a flexible array member has changed in GCC 4.4" } */ + struct flex s; + s.i = x; + return s; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39545-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39545-2.c new file mode 100644 index 000000000..46deecbe0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39545-2.c @@ -0,0 +1,18 @@ +/* PR target/39545 */ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2" } */ + +struct flex +{ + int i; + int flex []; +}; + +struct flex +foo (int x) +{ /* { dg-message "note: the ABI of passing struct with a flexible array member has changed in GCC 4.4" } */ + struct flex s; + s.i = x; + return s; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39592-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39592-1.c new file mode 100644 index 000000000..a7f37043b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39592-1.c @@ -0,0 +1,10 @@ +/* Test for ICE with C99-conforming excess precision and -msse. PR + 39592. */ +/* { dg-do compile } */ +/* { dg-options "-ansi -msse" } */ + +double +foo (unsigned long var) +{ + return var; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39678.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39678.c new file mode 100644 index 000000000..0548466d6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39678.c @@ -0,0 +1,19 @@ +/* PR target/39678 */ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2" } */ + +struct X { + char c; + __complex__ float val; +}; + +struct X +foo (float *p) +{ /* { dg-message "note: the ABI of passing structure with complex float member has changed in GCC 4.4" } */ + struct X x; + x.c = -3; + __real x.val = p[0]; + __imag x.val = p[1]; + return x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39804.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39804.c new file mode 100644 index 000000000..3ff247908 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39804.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O" } */ + +typedef unsigned char u8; +struct __large_struct { unsigned long buf[100]; }; +static inline __attribute__((always_inline)) unsigned long +__copy_from_user_inatomic(void *to, const void *from, unsigned long n) +{ + unsigned long ret = 0; + asm volatile("1: mov""b"" %2,%""b""1\n" "2:\n" + ".section .fixup,\"ax\"\n" + "3: mov %3,%0\n" + " xor""b"" %""b""1,%""b""1\n" + " jmp 2b\n" + ".previous\n" + " .section __ex_table,\"a\"\n" + " " ".balign 4" " " "\n" + " " ".long" " " "1b" "," "3b" "\n" + " .previous\n" + : "=r" (ret), "=q"(*(u8 *)to) + : "m" ((*(struct __large_struct *)(from))), "i" (1), "0" (ret)); + return ret; +} +void romchecksum(const unsigned char *rom, unsigned char c) +{ + unsigned char sum; + for (sum = 0; + !__copy_from_user_inatomic(&(c), ( typeof(c) *)(rom++), sizeof(c));) + sum += c; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39911.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39911.c new file mode 100644 index 000000000..8a78c0a28 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr39911.c @@ -0,0 +1,59 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2" } */ + +void +bar1 () +{ + char foo; + asm volatile ("mov%z0 %1, %0": "=m" (foo): "iq" (-23)); + asm volatile ("add%z0 %1, %0": "+m" (foo): "iq" (23)); + asm volatile ("mov%z0 %1, %0": "=q" (foo): "iq" (-23)); + asm volatile ("add%z0 %1, %0": "+q" (foo): "iq" (23)); +} + +void +bar2 () +{ + short foo; + asm volatile ("mov%z0 %1, %0": "=m" (foo): "ir" (-23)); + asm volatile ("add%z0 %1, %0": "+m" (foo): "ir" (23)); + asm volatile ("mov%z0 %1, %0": "=r" (foo): "ir" (-23)); + asm volatile ("add%z0 %1, %0": "+r" (foo): "ir" (23)); + + asm volatile ("pop%z0 %0": "=m" (foo)); + asm volatile ("pop%z0 %0": "=r" (foo)); +} + +void +bar3 () +{ + int foo; + asm volatile ("mov%z0 %1, %0": "=m" (foo): "ir" (-23)); + asm volatile ("add%z0 %1, %0": "+m" (foo): "ir" (23)); + asm volatile ("mov%z0 %1, %0": "=r" (foo): "ir" (-23)); + asm volatile ("add%z0 %1, %0": "+r" (foo): "ir" (23)); + +#ifndef __x86_64__ + if (sizeof (void *) == sizeof (int)) + { + asm volatile ("pop%z0 %0": "=m" (foo)); + asm volatile ("pop%z0 %0": "=r" (foo)); + } +#endif +} + +void +bar4 () +{ + if (sizeof (void *) == sizeof (long long)) + { + long long foo; + asm volatile ("mov%z0 %1, %0": "=m" (foo): "er" (-23)); + asm volatile ("add%z0 %1, %0": "+m" (foo): "er" (23)); + asm volatile ("mov%z0 %1, %0": "=r" (foo): "er" (-23)); + asm volatile ("add%z0 %1, %0": "+r" (foo): "er" (23)); + + asm volatile ("pop%z0 %0": "=m" (foo)); + asm volatile ("pop%z0 %0": "=r" (foo)); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40718.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40718.c new file mode 100644 index 000000000..1df3548e0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40718.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O1 -foptimize-sibling-calls" } */ + +void abort (void); + +struct S +{ + void (__attribute__((__stdcall__)) *f) (struct S *); + int i; +}; + +void __attribute__((__stdcall__)) +foo (struct S *s) +{ + s->i++; +} + +void __attribute__((__stdcall__)) +bar (struct S *s) +{ + foo(s); + s->f(s); +} + +int main (void) +{ + struct S s = { foo, 0 }; + + bar (&s); + if (s.i != 2) + abort (); + + return 0; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40809.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40809.c new file mode 100644 index 000000000..8b63e5526 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40809.c @@ -0,0 +1,24 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#define N 8 + +unsigned int u4[N] = { 4000000000u, 4000000000u, 4000000000u, 4000000000u, 4000000000u, 4000000000u, 4000000000u, 4000000000u }; +float f4[N]; + +static void +sse2_test (void) +{ + int j; + + for (j = 0; j < N; j++) + f4[j] = u4[j]; + + /* check results: */ + for (j = 0; j < N; j++) + if (f4[j] != 4000000000.0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40906-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40906-1.c new file mode 100644 index 000000000..233d8fdcb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40906-1.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -fomit-frame-pointer -fno-asynchronous-unwind-tables -mpush-args -mno-accumulate-outgoing-args" } */ +/* { dg-options "-O2 -fomit-frame-pointer -fno-asynchronous-unwind-tables -mpush-args" { target *-*-mingw* *-*-cygwin* } } */ + +void abort (void); + +void __attribute__((noinline)) +f (long double a) +{ + if (a != 1.23L) + abort (); +} + +int __attribute__((noinline)) +g (long double b) +{ + f (b); + return 0; +} + +int +main (void) +{ + g (1.23L); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40906-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40906-2.c new file mode 100644 index 000000000..58b076e1f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40906-2.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -Wno-psabi -fomit-frame-pointer -fno-asynchronous-unwind-tables -mpush-args -mno-accumulate-outgoing-args -m128bit-long-double" } */ +/* { dg-options "-O2 -Wno-psabi -fomit-frame-pointer -fno-asynchronous-unwind-tables -mpush-args -m128bit-long-double" { target *-*-mingw* *-*-cygwin* } } */ + +void abort (void); + +void __attribute__((noinline)) +f (long double a) +{ + if (a != 1.23L) + abort (); +} + +int __attribute__((noinline)) +g (long double b) +{ + f (b); + return 0; +} + +int +main (void) +{ + g (1.23L); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40906-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40906-3.c new file mode 100644 index 000000000..ac7d183b7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40906-3.c @@ -0,0 +1,26 @@ +/* { dg-do run { target *-*-linux* } } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -fomit-frame-pointer -fno-asynchronous-unwind-tables -msse2 -mpush-args -mno-accumulate-outgoing-args" } */ + +#include "sse2-check.h" + +void __attribute__((noinline)) +f (__float128 a) +{ + if (a != 1.23Q) + abort (); +} + +int __attribute__((noinline)) +g (__float128 b) +{ + f (b); + return 0; +} + +static void +sse2_test (void) +{ + g (1.23Q); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40934.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40934.c new file mode 100644 index 000000000..651172299 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40934.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -march=i586 -ffast-math" } */ + +extern double host_frametime; +extern float pitchvel; +V_DriftPitch (float delta, float move) +{ + if (!delta) + move = host_frametime; + if (delta > 0) + ; + else if (delta < 0 && move > -delta) + pitchvel = 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40957.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40957.c new file mode 100644 index 000000000..b7ee26dff --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr40957.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx" } */ + +typedef int __v8si __attribute__((__vector_size__(32))); +typedef long long __m256i __attribute__((__vector_size__(32), __may_alias__)); + +static __m256i +_mm256_set1_epi32 (int __A) +{ + return __extension__ (__m256i)(__v8si){ __A, __A, __A, __A, + __A, __A, __A, __A }; +} +__m256i +foo () +{ + return _mm256_set1_epi32 (-1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr41019.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr41019.c new file mode 100644 index 000000000..a6a2f4ee2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr41019.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2 -ftree-vectorize" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +long long int a[64]; + +void +sse2_test (void) +{ + int k; + + for (k = 0; k < 64; k++) + a[k] = a[k] != 5 ? 12 : 10; + + for (k = 0; k < 64; k++) + if (a[k] != 12) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr41442.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr41442.c new file mode 100644 index 000000000..feae791bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr41442.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef struct LINK link; +struct LINK +{ + link* next; +}; + +int haha(link* p1, link* p2) +{ + if ((p1->next && !p2->next) || p2->next) + return 0; + + return 1; +} + +/* { dg-final { scan-assembler-times "test|cmp" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr41900.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr41900.c new file mode 100644 index 000000000..a23214c76 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr41900.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -fomit-frame-pointer -mpreferred-stack-boundary=2" } */ + +int main () +{ + volatile unsigned code = 0xc3; + + ((void (*)(void)) &code) (); + return 0; +} + +/* { dg-final { scan-assembler-not "call\[ \\t\]+\\*%esp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr41985.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr41985.c new file mode 100644 index 000000000..b38b6dc42 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr41985.c @@ -0,0 +1,11 @@ +/* PR target/41985 */ +/* { dg-do compile } */ +/* { dg-options "" } */ + +int +main () +{ + int i; + asm volatile ("# %&": : "g" (i)); /* { dg-error "used without any local dynamic TLS references" } */ + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-1.c new file mode 100644 index 000000000..761b91b18 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-1.c @@ -0,0 +1,78 @@ +/* { dg-do run } */ +/* { dg-options "-O1 -msse2 -ftree-vectorize" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +unsigned int v1[] __attribute__ ((aligned(16))) = +{ + 0x80000000, 1, 0xa0000000, 2, + 3, 0xd0000000, 0xf0000000, 0xe0000000 +}; +unsigned int v2[] __attribute__ ((aligned(16))) = +{ + 4, 0xb0000000, 5, 0xc0000000, + 0xd0000000, 6, 7, 8 +}; + +unsigned int max[] = +{ + 0x80000000, 0xb0000000, 0xa0000000, 0xc0000000, + 0xd0000000, 0xd0000000, 0xf0000000, 0xe0000000 +}; + +unsigned int min[] = +{ + 4, 1, 5, 2, + 3, 6, 7, 8 +}; + +unsigned int res[8] __attribute__ ((aligned(16))); + +extern void abort (void); + +void +find_max (void) +{ + int i; + + for (i = 0; i < 8; i++) + res[i] = v1[i] < v2[i] ? v2[i] : v1[i]; +} + +void +find_min (void) +{ + int i; + + for (i = 0; i < 8; i++) + res[i] = v1[i] > v2[i] ? v2[i] : v1[i]; +} + +static void +TEST (void) +{ + int i; + int err = 0; + + find_max (); + for (i = 0; i < 8; i++) + if (res[i] != max[i]) + err++; + + find_min (); + for (i = 0; i < 8; i++) + if (res[i] != min[i]) + err++; + + if (err) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-1a.c new file mode 100644 index 000000000..cd77175f6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-1a.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O1 -msse4.1 -ftree-vectorize" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "pr42542-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-1b.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-1b.c new file mode 100644 index 000000000..7651f07a6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-1b.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -msse4.1 -ftree-vectorize" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "pr42542-1.c" + +/* { dg-final { scan-assembler "pmaxud" } } */ +/* { dg-final { scan-assembler "pminud" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-2.c new file mode 100644 index 000000000..80ed9c35b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-2.c @@ -0,0 +1,78 @@ +/* { dg-do run } */ +/* { dg-options "-O1 -msse2 -ftree-vectorize" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +unsigned short v1[] __attribute__ ((aligned(16))) = +{ + 0x8000, 0x9000, 1, 10, 0xa000, 0xb000, 2, 20, + 3, 30, 0xd000, 0xe000, 0xf000, 0xe000, 25, 30 +}; +unsigned short v2[] __attribute__ ((aligned(16))) = +{ + 4, 40, 0xb000, 0x8000, 5, 50, 0xc000, 0xf000, + 0xd000, 0xa000, 6, 65, 7, 75, 0xe000, 0xc000 +}; + +unsigned short max[] = +{ + 0x8000, 0x9000, 0xb000, 0x8000, 0xa000, 0xb000, 0xc000, 0xf000, + 0xd000, 0xa000, 0xd000, 0xe000, 0xf000, 0xe000, 0xe000, 0xc000 +}; + +unsigned short min[] = +{ + 4, 40, 1, 10, 5, 50, 2, 20, + 3, 30, 6, 65, 7, 75, 25, 30 +}; + +unsigned short res[16] __attribute__ ((aligned(16))); + +extern void abort (void); + +void +find_max (void) +{ + int i; + + for (i = 0; i < 16; i++) + res[i] = v1[i] < v2[i] ? v2[i] : v1[i]; +} + +void +find_min (void) +{ + int i; + + for (i = 0; i < 16; i++) + res[i] = v1[i] > v2[i] ? v2[i] : v1[i]; +} + +static void +TEST (void) +{ + int i; + int err = 0; + + find_max (); + for (i = 0; i < 16; i++) + if (res[i] != max[i]) + err++; + + find_min (); + for (i = 0; i < 16; i++) + if (res[i] != min[i]) + err++; + + if (err) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-2a.c new file mode 100644 index 000000000..bcefa9cfe --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-2a.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O1 -msse4.1 -ftree-vectorize" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "pr42542-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-2b.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-2b.c new file mode 100644 index 000000000..ddb539bf7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-2b.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -msse4.1 -ftree-vectorize" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "pr42542-2.c" + +/* { dg-final { scan-assembler "pmaxuw" } } */ +/* { dg-final { scan-assembler "pminuw" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-3.c new file mode 100644 index 000000000..372f2c1e1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-3.c @@ -0,0 +1,86 @@ +/* { dg-do run } */ +/* { dg-options "-O1 -msse2 -ftree-vectorize" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +unsigned char v1[] __attribute__ ((aligned(16))) = +{ + 0x80, 0xd0, 0x90, 0xa0, 1, 15, 10, 15, + 0xa0, 0xc0, 0xb0, 0xf0, 2, 25, 20, 35, + 3, 34, 30, 36, 0xd0, 0x80, 0xe0, 0xb0, + 0xf0, 0xe0, 0xe0, 0x80, 25, 34, 30, 40 +}; +unsigned char v2[] __attribute__ ((aligned(16))) = +{ + 4, 44, 40, 48, 0xb0, 0x80, 0x80, 0x90, + 5, 55, 50, 51, 0xc0, 0xb0, 0xf0, 0xd0, + 0xd0, 0x80, 0xa0, 0xf0, 6, 61, 65, 68, + 7, 76, 75, 81, 0xe0, 0xf0, 0xc0, 0x90 +}; + +unsigned char max[] = +{ + 0x80, 0xd0, 0x90, 0xa0, 0xb0, 0x80, 0x80, 0x90, + 0xa0, 0xc0, 0xb0, 0xf0, 0xc0, 0xb0, 0xf0, 0xd0, + 0xd0, 0x80, 0xa0, 0xf0, 0xd0, 0x80, 0xe0, 0xb0, + 0xf0, 0xe0, 0xe0, 0x80, 0xe0, 0xf0, 0xc0, 0x90 +}; + +unsigned char min[] = +{ + 4, 44, 40, 48, 1, 15, 10, 15, + 5, 55, 50, 51, 2, 25, 20, 35, + 3, 34, 30, 36, 6, 61, 65, 68, + 7, 76, 75, 81, 25, 34, 30, 40 +}; + +unsigned char res[32] __attribute__ ((aligned(16))); + +extern void abort (void); + +void +find_max (void) +{ + int i; + + for (i = 0; i < 32; i++) + res[i] = v1[i] < v2[i] ? v2[i] : v1[i]; +} + +void +find_min (void) +{ + int i; + + for (i = 0; i < 32; i++) + res[i] = v1[i] > v2[i] ? v2[i] : v1[i]; +} + +static void +TEST (void) +{ + int i; + int err = 0; + + find_max (); + for (i = 0; i < 32; i++) + if (res[i] != max[i]) + err++; + + find_min (); + for (i = 0; i < 32; i++) + if (res[i] != min[i]) + err++; + + if (err) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-3a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-3a.c new file mode 100644 index 000000000..754e59e84 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-3a.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -msse2 -ftree-vectorize" } */ + +#include "pr42542-3.c" + +/* { dg-final { scan-assembler "pmaxub" } } */ +/* { dg-final { scan-assembler "pminub" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-4.c new file mode 100644 index 000000000..afb298989 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-4.c @@ -0,0 +1,70 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */ + +#include "sse4_2-check.h" + +unsigned long long v1[] __attribute__ ((aligned(16))) = +{ + 0x8000000000000000ULL, 2, + 3, 0xd000000000000000ULL +}; +unsigned long long v2[] __attribute__ ((aligned(16))) = +{ + 4, 0xb000000000000000ULL, + 0xf000000000000000ULL, 6 +}; + +unsigned long long max[] = +{ + 0x8000000000000000ULL, 0xb000000000000000ULL, + 0xf000000000000000ULL, 0xd000000000000000ULL +}; + +unsigned long long min[] = +{ + 4, 2, + 3, 6 +}; + +unsigned long long res[4] __attribute__ ((aligned(16))); + +extern void abort (void); + +void +find_max (void) +{ + int i; + + for (i = 0; i < 4; i++) + res[i] = v1[i] < v2[i] ? v2[i] : v1[i]; +} + +void +find_min (void) +{ + int i; + + for (i = 0; i < 4; i++) + res[i] = v1[i] > v2[i] ? v2[i] : v1[i]; +} + +static void +sse4_2_test (void) +{ + int i; + int err = 0; + + find_max (); + for (i = 0; i < 4; i++) + if (res[i] != max[i]) + err++; + + find_min (); + for (i = 0; i < 4; i++) + if (res[i] != min[i]) + err++; + + if (err) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-4a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-4a.c new file mode 100644 index 000000000..bea6c1f50 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-4a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */ + +#include "pr42542-4.c" + +/* { dg-final { scan-assembler "pcmpgtq" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-5.c new file mode 100644 index 000000000..7d77a18ae --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-5.c @@ -0,0 +1,66 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */ + +#include "sse4_2-check.h" + +long long v1[] __attribute__ ((aligned(16))) = +{ + -3, 2, 3, -4 +}; +long long v2[] __attribute__ ((aligned(16))) = +{ + 4, -10, -20, 6 +}; + +long long max[] = +{ + 4, 2, 3, 6 +}; + +long long min[] = +{ + -3, -10, -20, -4 +}; + +long long res[4] __attribute__ ((aligned(16))); + +extern void abort (void); + +void +find_max (void) +{ + int i; + + for (i = 0; i < 4; i++) + res[i] = v1[i] < v2[i] ? v2[i] : v1[i]; +} + +void +find_min (void) +{ + int i; + + for (i = 0; i < 4; i++) + res[i] = v1[i] > v2[i] ? v2[i] : v1[i]; +} + +static void +sse4_2_test (void) +{ + int i; + int err = 0; + + find_max (); + for (i = 0; i < 4; i++) + if (res[i] != max[i]) + err++; + + find_min (); + for (i = 0; i < 4; i++) + if (res[i] != min[i]) + err++; + + if (err) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-5a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-5a.c new file mode 100644 index 000000000..bba0a118e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42542-5a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */ + +#include "pr42542-5.c" + +/* { dg-final { scan-assembler "pcmpgtq" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42549.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42549.c new file mode 100644 index 000000000..733853cdc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42549.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-require-effective-target 3dnow } */ +/* { dg-options "-O2 -m3dnow" } */ + +#include "mmx-3dnow-check.h" + +#include <mm3dnow.h> + +typedef union { + float f[2]; + __m64 v; +} vec_t; + +void __attribute__ ((noinline)) +Butterfly_3 (__m64 * D, __m64 SC) +{ + __m64 T, T1; + + T = _m_pfmul (D[1], SC); + T1 = D[0]; + D[0] = _m_pfadd (T1, T); + D[1] = _m_pfsub (T1, T); +} + +static void +mmx_3dnow_test (void) +{ + vec_t D[2] = { { .f = { 2.0f, 3.0f } }, + { .f = { 4.0f, 5.0f } } }; + + const vec_t SC = { .f = { 1.0f, 1.0f } }; + + Butterfly_3 (&D[0].v, SC.v); + _m_femms (); + + if (D[1].f[0] != -2.0f || D[1].f[1] != -2.0f) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42589.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42589.c new file mode 100644 index 000000000..863372b56 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42589.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i486" } } */ +/* { dg-options "-O2 -march=i486" } */ + +void +foo (unsigned long long *p) +{ + unsigned long long tmp; + tmp = *p; + tmp = (tmp >> 32) | (tmp << 32); + tmp = (((tmp & 0xff00ff00ff00ff00ULL) >> 8) + | ((tmp & 71777214294589695ULL) << 8)); + *p = (((tmp & 0xffff0000ffff0000ULL) >> 16) + | ((tmp & 281470681808895ULL) << 16)); +} + +/* { dg-final { scan-assembler-times "bswap" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42881.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42881.c new file mode 100644 index 000000000..c8ad09d20 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42881.c @@ -0,0 +1,15 @@ +/* PR target/42881 */ +/* { dg-do run } */ +/* { dg-options "-O0 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" +static void +sse2_test (void) +{ + double a[2]; + __m128d x = _mm_set1_pd(3); + _mm_storeu_pd(a,x); + if (a[0] != 3.0 || a[1] != 3.0) + __builtin_abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42891.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42891.c new file mode 100644 index 000000000..e3c7b9cf8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr42891.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +union B { int i; float f; }; + +extern void bar (void); + +void +foo (union B x, union B y) +{ + if (!(y.f > x.i)) + bar (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43067.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43067.c new file mode 100644 index 000000000..7abb00279 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43067.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -mxop -ftree-vectorize -fschedule-insns" } */ + +union { + int i32[10240]; + long long i64[10240]; +} a, b, c; + +void imul32_to_64 (void) +{ + int i; + + for (i = 0; i < 10240; i++) + a.i64[i] = (long long) b.i32[i] * c.i32[i]; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43107.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43107.c new file mode 100644 index 000000000..879652931 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43107.c @@ -0,0 +1,20 @@ +/* PR target/43107 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx" } */ + +extern void bar (float b[4][4]); + +void +foo () +{ + float a[4][4], b[4][4]; + int i, j; + for (i = 0; i < 4; i++) + { + for (j = 0; j < 4; j++) + a[i][j] = 0; + for (j = 0; j < 4; j++) + b[i][j] = a[i][j]; + } + bar (b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43508.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43508.c new file mode 100644 index 000000000..c43982b3c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43508.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-g -O -msse3" } */ + +typedef float v4sf __attribute__ ((__vector_size__ (16))); +typedef int v4si __attribute__ ((__vector_size__ (16))); + +v4sf bar(int); + +v4sf foo(v4si vi) +{ + int x = __builtin_ia32_vec_ext_v4si (vi, 0); + return bar(x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43524.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43524.c new file mode 100644 index 000000000..b2662702a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43524.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mstack-arg-probe" } */ + +extern void bar (void); + +void foo (int i) +{ + bar (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43528.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43528.c new file mode 100644 index 000000000..f33d96b19 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43528.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-mms-bitfields" } */ + +struct S { int i[(1LL << 60) - 1]; }; diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43638.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43638.c new file mode 100644 index 000000000..9af06aede --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43638.c @@ -0,0 +1,9 @@ +/* PR target/43638 */ +/* { dg-do compile } */ + +void +foo (void) +{ + int x; + __asm __volatile ("mov $0,%e0" : "=r" (x)); /* { dg-error "invalid operand code" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43653.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43653.c new file mode 100644 index 000000000..22928edac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43653.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -ftree-vectorize -msse" } */ + +typedef struct {} S; + +void *foo() +{ + S a[64], *p[64]; + int i; + + for (i = 0; i < 64; i++) + p[i] = &a[i]; + return p[0]; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43662.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43662.c new file mode 100644 index 000000000..2896a1a52 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43662.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2" } */ + +void __attribute__ ((ms_abi)) foo (void) +{ +} + +typedef struct _IAVIStreamImpl +{ + int sInfo; + int has; +} IAVIStreamImpl; + +extern int __attribute__ ((ms_abi)) aso (void *); +extern int sre (void *); + +int AVIFILE_OpenCompressor (IAVIStreamImpl *This) +{ + if (This->has != 0) + aso (&This->has); + sre (&This->sInfo); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43668.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43668.c new file mode 100644 index 000000000..b6c2114fd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43668.c @@ -0,0 +1,10 @@ +/* PR target/43668 */ +/* { dg-do run } */ +/* { dg-options "-fschedule-insns" } */ + +int foo(int i, ...) { + return i; +} +int main() { + return foo(0, 0.0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43671.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43671.c new file mode 100644 index 000000000..388cd65e0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43671.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-mtune=i686 -O1 -fpeel-loops -fschedule-insns2 -ftree-vectorize -fsched2-use-superblocks" } */ + +extern void abort (); + +int main () +{ + struct { + char ca[16]; + } s; + int i; + + for (i = 0; i < 16; i++) + { + s.ca[i] = 5; + } + + + for (i = 0; i < 16; i++) + { + if (s.ca[i] != 5) + abort (); + } + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43766.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43766.c new file mode 100644 index 000000000..8ac16137f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43766.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-options "-O2 -msse -mregparm=3" { target ia32 } } */ + +void p (int *a, int i) +{ + __builtin_prefetch (&a[i]); +} + +/* { dg-final { scan-assembler-not "lea\[lq\]?\[ \t\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43799.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43799.c new file mode 100644 index 000000000..de9022d0c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43799.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-options "-O -fschedule-insns" } */ + +int f4 (int i, ...) +{ + int y = 0; + __builtin_va_list ap; + __builtin_va_start(ap, i); + if (i == 5) y = __builtin_va_arg(ap, double); + __builtin_va_end(ap); + return y; +} + +int main (void) +{ + if (f4 (5, 7.0) != 7) + __builtin_abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43869.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43869.c new file mode 100644 index 000000000..4157db1d1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr43869.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target lp64 } } */ + +int __attribute__((__noinline__)) +bugged(float f1, float f2, float f3, float f4, + float f5, float f6, float f7, float f8) +{ + return f1 || f2 || f3 || f4 || f5 != 1. || f6 != 1. || f7 != 1. || f8 != 1.; +} + +int __attribute__((__noinline__, __ms_abi__)) isbugged(void) +{ + return bugged(0, 0, 0, 0, 1., 1., 1., 1.); +} + +int main() +{ + return isbugged(); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44071.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44071.c new file mode 100644 index 000000000..514c5e2fd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44071.c @@ -0,0 +1,103 @@ +/* PR middle-end/44071 */ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +static inline int +f1 (void) +{ + asm goto ("jmp %l[l1]" : : : : l1, l2); + __builtin_unreachable (); + l1: + return 1; + l2: + return 0; +} + +__attribute__((noinline)) int +b1 (int x) +{ + if (f1 () || x == 6) + x = 1; + else + x = 2; + return x; +} + +static inline int +f2 (void) +{ + asm goto ("jmp %l[l2]" : : : : l1, l2); + __builtin_unreachable (); + l1: + return 1; + l2: + return 0; +} + +__attribute__((noinline)) int +b2 (int x) +{ + if (f2 () || x == 6) + x = 1; + else + x = 2; + return x; +} + +static inline int +f3 (void) +{ + asm goto ("jmp %l[l1]" : : : : l1, l2); + l1: + return 1; + l2: + return 0; +} + +__attribute__((noinline)) int +b3 (int x) +{ + if (f3 () || x == 6) + x = 1; + else + x = 2; + return x; +} + +static inline int +f4 (void) +{ + asm goto ("jmp %l[l2]" : : : : l1, l2); + l1: + return 1; + l2: + return 0; +} + +__attribute__((noinline)) int +b4 (int x) +{ + if (f4 () || x == 6) + x = 1; + else + x = 2; + return x; +} + +extern void abort (void); + +int +main (void) +{ + int x; + asm ("" : "=r" (x) : "0" (0)); + if (b1 (x) != 1 || b1 (x + 6) != 1) + abort (); + if (b2 (x) != 2 || b2 (x + 6) != 1) + abort (); + if (b3 (x) != 1 || b3 (x + 6) != 1) + abort (); + if (b4 (x) != 2 || b4 (x + 6) != 1) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44130.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44130.c new file mode 100644 index 000000000..3e50c7b15 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44130.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */ +/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-32,\[\\t \]*%\[re\]?sp" } } */ +/* { dg-final { scan-assembler "vmovaps\[\\t \]*%ymm" } } */ + +extern void abort (void); + +static float Yf[] = { 2.0, -2.0, -2.0, -2.0, -2.0, 2.0, -0.0, __builtin_inff () }; +static const float Zf[] = { 1.0, -1.0, -1.0, -0.0, -0.0, 0.0, -__builtin_inff (), __builtin_nanf ("") }; + +void testf (void) +{ + float xxxxx[8]; + int i; + xxxxx[0] = __builtin_copysignf (1.0, Yf[0]); + xxxxx[1] = __builtin_copysignf (1.0, Yf[1]); + xxxxx[2] = __builtin_copysignf (-1.0, Yf[2]); + xxxxx[3] = __builtin_copysignf (0.0, Yf[3]); + xxxxx[4] = __builtin_copysignf (-0.0, Yf[4]); + xxxxx[5] = __builtin_copysignf (-0.0, Yf[5]); + xxxxx[6] = __builtin_copysignf (__builtin_inff (), Yf[6]); + xxxxx[7] = __builtin_copysignf (-__builtin_nanf (""), Yf[7]); + for (i = 0; i < 8; ++i) + if (__builtin_memcmp (xxxxx+i, Zf+i, sizeof(float)) != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44144.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44144.c new file mode 100644 index 000000000..8db0f4f3c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44144.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */ + +void +foo (char * dest, int xcount, int ycount) +{ + int x, y; + for (y = 0; y < ycount; y++) + for (x = 0; x < xcount; x++) + dest[x + y*2] = 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44180.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44180.c new file mode 100644 index 000000000..c327e94bb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44180.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */ + +#include "avx-check.h" + +#define N 16 + +float b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45}; +float c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; +float d[N] = {0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30}; + +static void +__attribute__ ((noinline)) +avx_test () +{ + int i; + float a[N]; + + /* Strided access. Vectorizable on platforms that support load of strided + accesses (extract of even/odd vector elements). */ + for (i = 0; i < N/2; i++) + { + a[i] = b[2*i+1] * c[2*i+1] - b[2*i] * c[2*i]; + d[i] = b[2*i] * c[2*i+1] + b[2*i+1] * c[2*i]; + } + + /* Check results. */ + for (i = 0; i < N/2; i++) + { + if (a[i] != b[2*i+1] * c[2*i+1] - b[2*i] * c[2*i] + || d[i] != b[2*i] * c[2*i+1] + b[2*i+1] * c[2*i]) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44223.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44223.c new file mode 100644 index 000000000..3b8030c1b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44223.c @@ -0,0 +1,36 @@ +/* PR debug/44223 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -fsched-pressure -fschedule-insns -fpic -march=core2 -g" { target fpic } } */ + +struct S { unsigned int s1; int s2; }; +struct T { int t; }; + +extern void extfn (struct S *); + +static inline void +foo (struct S *s, unsigned char *x, int y) +{ + s->s2 = 32; +} + +static inline void +bar (struct S *s, int n, unsigned int x) +{ + unsigned int s1; + int s2; + s1 = s->s1; + s2 = s->s2; + if (n < s2) + s1 = (s1 << n) | x; + s->s1 = s1; +} + +int +baz (struct T *u, unsigned char *v, int w) +{ + struct S y; + foo (&y, v, 7); + bar (&y, 12, 0xfff); + bar (&y, 2, u->t); + extfn (&y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44481.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44481.c new file mode 100644 index 000000000..701268b56 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44481.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +static inline unsigned +parity (unsigned x) +{ + return (unsigned) __builtin_parity (x); +} + +unsigned +f (unsigned rpoly) +{ + return parity (rpoly & 1) ^ parity (rpoly & 6); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44546.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44546.c new file mode 100644 index 000000000..517446fdc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44546.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -ffast-math -mfpmath=387" } */ + +typedef __SIZE_TYPE__ size_t; +typedef struct +{ + float *ewgts; +} vtx_data; + +extern void *zmalloc (size_t); +extern int whatever (vtx_data *); + +float * +compute_apsp_artifical_weights_packed (vtx_data * graph, int n) +{ + float *weights; + + weights = (float *) zmalloc (n * sizeof (float)); + weights[n] = + whatever (graph) > graph[n].ewgts[n] ? + whatever (graph) : graph[n].ewgts[n]; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44578.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44578.c new file mode 100644 index 000000000..20f76c31c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44578.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mtune=athlon64" } */ + +extern void abort (void); + +long double +__attribute__((noinline, noclone)) +test (float num) +{ + unsigned int i; + + if (num < 0.0) + num = 0.0; + + __builtin_memcpy (&i, &num, sizeof(unsigned int)); + + return (long double)(unsigned long long) i; +} + +int +main () +{ + long double x; + + x = test (0.0); + + if (x != 0.0) + abort (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44942.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44942.c new file mode 100644 index 000000000..d8164845c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44942.c @@ -0,0 +1,44 @@ +/* PR target/44942 */ +/* { dg-do run { target { ! { ia32 } } } } */ + +#include <stdarg.h> +#include <emmintrin.h> + +void +test1 (double a, double b, double c, double d, double e, double f, + double g, __m128d h, ...) +{ + double i; + va_list ap; + + va_start (ap, h); + i = va_arg (ap, double); + if (i != 1234.0) + __builtin_abort (); + va_end (ap); +} + +void +test2 (double a, double b, double c, double d, double e, double f, double g, + __m128d h, double i, __m128d j, double k, __m128d l, + double m, __m128d n, ...) +{ + double o; + va_list ap; + + va_start (ap, n); + o = va_arg (ap, double); + if (o != 1234.0) + __builtin_abort (); + va_end (ap); +} + +int +main () +{ + __m128d m = _mm_set1_pd (7.0); + test1 (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, m, 1234.0); + test2 (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, m, 0.0, m, + 0.0, m, 0.0, m, 1234.0); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44948-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44948-1a.c new file mode 100644 index 000000000..db58c04c4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44948-1a.c @@ -0,0 +1,18 @@ +/* PR target/44948 */ +/* { dg-do run } */ +/* { dg-options "-O -Wno-psabi -mtune=generic" } */ +/* { dg-require-effective-target avx_runtime } */ +/* { dg-additional-sources pr44948-1b.c } */ + +#pragma GCC target ("avx") + +struct A { long b[8] __attribute__((aligned (32))); }; +void foo (long double, struct A); + +int +main (void) +{ + struct A a = { { 0, 1, 2, 3, 4, 5, 6, 7 } }; + foo (8.0L, a); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44948-1b.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44948-1b.c new file mode 100644 index 000000000..1e2d4d3c5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44948-1b.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mno-avx -Wno-psabi -mtune=generic" } */ + +struct A { long b[8] __attribute__((aligned (32))); }; + +void +foo (long double x, struct A y) +{ + int i; + if (x != 8.0L) + __builtin_abort (); + for (i = 0; i < 8; i++) + if (y.b[i] != i) + __builtin_abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44948-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44948-2a.c new file mode 100644 index 000000000..d84d1a6b9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44948-2a.c @@ -0,0 +1,21 @@ +/* PR target/44948 */ +/* { dg-do run } */ +/* { dg-options "-O -Wno-psabi -mno-sse -mtune=generic" } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target sse2_runtime } */ +/* { dg-additional-sources pr44948-2b.c } */ + +#pragma GCC target ("sse2") + +struct A +{ + float V4SF __attribute__ ((vector_size (16))); +}; + +int +main (void) +{ + struct A a = { { 0, 1, 2, 3 } }; + foo (8.0L, a, 8.0L); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44948-2b.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44948-2b.c new file mode 100644 index 000000000..fa1769b62 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr44948-2b.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mno-sse -Wno-psabi -mtune=generic" } */ + +struct A +{ + float V4SF __attribute__ ((vector_size (16))); +}; + +void +foo (long double x, struct A y, long double z) +{ + int i; + struct A a = { { 0, 1, 2, 3 } }; + + if (x != 8.0L || z != 8.0L) + __builtin_abort (); + if (__builtin_memcmp (&a, &y, sizeof (a))) + __builtin_abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45206.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45206.c new file mode 100644 index 000000000..7dd4bd263 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45206.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -fno-omit-frame-pointer" } */ + +struct _Unwind_Context { void *ra; }; + +long uw_install_context_1 (struct _Unwind_Context *, struct _Unwind_Context *); + +void _Unwind_RaiseException(void) +{ + struct _Unwind_Context this_context, cur_context; + long offset = uw_install_context_1 (&this_context, &cur_context); + void *handler = __builtin_frob_return_addr ((&cur_context)->ra); + + __builtin_eh_return (offset, handler); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45213.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45213.c new file mode 100644 index 000000000..c575fb550 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45213.c @@ -0,0 +1,9 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os -fno-omit-frame-pointer" } */ + +void f (float, float, float, float, float, float, float, float, float, float); + +void g (void) +{ + f (0, 0, 0, 0, 0, 0, 0, 0, -1, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45234.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45234.c new file mode 100644 index 000000000..3996fa27f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45234.c @@ -0,0 +1,18 @@ +/* PR middle-end/45234 */ +/* { dg-do compile } */ +/* { dg-options "-march=i586" { target ia32 } } */ + +struct S { union { double b[4]; } a[18]; } s, a[5]; +void foo (struct S); +struct S bar (struct S, struct S *, struct S); + +void +foo (struct S arg) +{ +} + +void +baz (void) +{ + foo (bar (s, &a[1], a[2])); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45296.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45296.c new file mode 100644 index 000000000..307ee012a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45296.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "" } */ + +register long double F80 asm("st"); /* { dg-error "stack register" } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45336-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45336-1.c new file mode 100644 index 000000000..db6c9400d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45336-1.c @@ -0,0 +1,16 @@ +/* PR target/45336 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse4 -mtune=generic" } */ +/* { dg-final { scan-assembler-not "movsbl" } } */ +/* { dg-final { scan-assembler-not "movswl" } } */ +/* { dg-final { scan-assembler-not "movzbl" } } */ +/* { dg-final { scan-assembler-not "movzwl" } } */ +/* { dg-final { scan-assembler-not "cwtl" } } */ +/* { dg-final { scan-assembler "pextrb" } } */ +/* { dg-final { scan-assembler "pextrw" } } */ +/* { dg-final { scan-assembler "pextrd" { target { ! x86_64-*-mingw* } } } } */ + +#include <smmintrin.h> +unsigned int foo8(__m128i x) { return _mm_extract_epi8(x, 4); } +unsigned int foo16(__m128i x) { return _mm_extract_epi16(x, 3); } +unsigned int foo32(__m128i x) { return _mm_extract_epi32(x, 2); } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45336-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45336-2.c new file mode 100644 index 000000000..3e51591fc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45336-2.c @@ -0,0 +1,20 @@ +/* PR target/45336 */ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -msse4 -mtune=generic" } */ +/* { dg-final { scan-assembler-not "movsbl" } } */ +/* { dg-final { scan-assembler-not "movswl" } } */ +/* { dg-final { scan-assembler-not "movzbl" } } */ +/* { dg-final { scan-assembler-not "movzwl" } } */ +/* { dg-final { scan-assembler-not "cwtl" } } */ +/* { dg-final { scan-assembler-not "cltq" } } */ +/* { dg-final { scan-assembler "pextrb" } } */ +/* { dg-final { scan-assembler "pextrw" } } */ +/* { dg-final { scan-assembler "pextrd" { target { ! x86_64-*-mingw* } } } } */ + +#include <smmintrin.h> +unsigned long long int foo8(__m128i x) { return _mm_extract_epi8(x, 4); } +unsigned long long int foo16(__m128i x) { return _mm_extract_epi16(x, 3); } +unsigned long long int foo32(__m128i x) +{ + return (unsigned int) _mm_extract_epi32(x, 2); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45336-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45336-3.c new file mode 100644 index 000000000..b2168c006 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45336-3.c @@ -0,0 +1,13 @@ +/* PR target/45336 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse4 -mtune=generic" } */ +/* { dg-final { scan-assembler "movsbl" } } */ +/* { dg-final { scan-assembler "(movswl|cwtl)" } } */ +/* { dg-final { scan-assembler "pextrb" } } */ +/* { dg-final { scan-assembler "pextrw" } } */ +/* { dg-final { scan-assembler "pextrd" { target { ! x86_64-*-mingw* } } } } */ + +#include <smmintrin.h> +int foo8(__m128i x) { return (char) _mm_extract_epi8(x, 4); } +int foo16(__m128i x) { return (short) _mm_extract_epi16(x, 3); } +int foo32(__m128i x) { return _mm_extract_epi32(x, 2); } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45336-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45336-4.c new file mode 100644 index 000000000..8b66a6a1d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45336-4.c @@ -0,0 +1,14 @@ +/* PR target/45336 */ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -msse4 -mtune=generic" } */ +/* { dg-final { scan-assembler "movsbq" } } */ +/* { dg-final { scan-assembler "movswq" } } */ +/* { dg-final { scan-assembler "(cltq|movslq)" } } */ +/* { dg-final { scan-assembler "pextrb" } } */ +/* { dg-final { scan-assembler "pextrw" } } */ +/* { dg-final { scan-assembler "pextrd" { target { ! x86_64-*-mingw* } } } } */ + +#include <smmintrin.h> +long long int foo8(__m128i x) { return (char) _mm_extract_epi8(x, 4); } +long long int foo16(__m128i x) { return (short) _mm_extract_epi16(x, 3); } +long long int foo32(__m128i x) { return (int) _mm_extract_epi32(x, 2); } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45352-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45352-1.c new file mode 100644 index 000000000..5cd1bd842 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45352-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-mtune=amdfam10 -O3 -fpeel-loops -fselective-scheduling2 -fsel-sched-pipelining -fPIC" } */ + +static int FIR_Tab_16[16][16]; + +void +V_Pass_Avrg_16_C_ref (int *Dst, int *Src, int W, int BpS, int Rnd) +{ + while (W-- > 0) + { + int i, k; + int Sums[16] = { }; + for (i = 0; i < 16; ++i) + for (k = 0; k < 16; ++k) + Sums[k] += FIR_Tab_16[i][k] * Src[i]; + for (i = 0; i < 16; ++i) + Dst[i] = Sums[i] + Src[i]; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45352-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45352-2.c new file mode 100644 index 000000000..52e5522a8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45352-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -mtune=amdfam10 -fexpensive-optimizations -fgcse -foptimize-register-move -freorder-blocks -fschedule-insns2 -funswitch-loops -fgcse-las -fselective-scheduling2 -fsel-sched-pipelining -funroll-all-loops" } */ + +typedef char uint8_t; +typedef uint32_t; +typedef vo_frame_t; +__extension__ typedef __SIZE_TYPE__ size_t; + +struct vo_frame_s +{ + uint8_t base[3]; + int pitches[3];}; +typedef struct +{ +void + (*proc_macro_block) + (void); +} +xine_xvmc_t; +typedef struct +{ + uint8_t ref[2][3]; +int pmv; +} +motion_t; +typedef struct +{ + uint32_t bitstream_buf; + int bitstream_bits; + uint8_t * bitstream_ptr; + uint8_t dest[3]; + int pitches[3]; + int offset; + motion_t b_motion; + motion_t f_motion; + int v_offset; + int coded_picture_width; + int picture_structure; +struct vo_frame_s *current_frame;} +picture_t; +typedef struct +{ +int xvmc_last_slice_code;} +mpeg2dec_accel_t; +static int bitstream_init (picture_t * picture, void *start) +{ + picture->bitstream_ptr = start; + return (int) (size_t) start; +} +static slice_xvmc_init (picture_t * picture, int code) +{ + int offset; + struct vo_frame_s *forward_reference_frame; + offset = picture->picture_structure == 2; + picture->pitches[0] = picture->current_frame->pitches[0]; + picture->pitches[1] = picture->current_frame->pitches[1]; + if (picture) + picture->f_motion.ref + [0] + [0] + = (char) (size_t) (forward_reference_frame->base + (offset ? picture->pitches[0] : 0)); + picture->f_motion.ref[0][1] = (offset); + if (picture->picture_structure) + picture->pitches[0] <<= picture->pitches[1] <<= 1; + offset = 0; + while (1) + { + if (picture->bitstream_buf >= 0x08000000) + break; + switch (picture->bitstream_buf >> 12) + { + case 8: + offset += 33; + picture->bitstream_buf + |= + picture->bitstream_ptr[1] << picture->bitstream_bits; + } + } + picture->offset = (offset); + while (picture->offset - picture->coded_picture_width >= 0) + { + picture->offset -= picture->coded_picture_width; + if (picture->current_frame) + { + picture->dest[0] += picture->pitches[0]; + picture->dest[1] += picture->pitches[1]; + } + picture->v_offset += 16; + } +} + +void +mpeg2_xvmc_slice + (mpeg2dec_accel_t * accel, picture_t * picture, int code, uint8_t buffer,int mba_inc) +{ + xine_xvmc_t * xvmc = (xine_xvmc_t *) (size_t) bitstream_init (picture, (void *) (size_t) buffer); + slice_xvmc_init (picture, code); + while (1) + { + if (picture) + break; + switch (picture->bitstream_buf) + { + case 8: + mba_inc += accel->xvmc_last_slice_code = code; + xvmc->proc_macro_block (); + while (mba_inc) + ; + } + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45352.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45352.c new file mode 100644 index 000000000..ef710ce6b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45352.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=amdfam10 -fselective-scheduling2 -fsel-sched-pipelining -funroll-all-loops" } */ + +struct S +{ + struct + { + int i; + } **p; + int x; + int y; +}; + +extern int baz (void); +extern int bar (void *, int, int); + +void +foo (struct S *s) +{ + int i; + for (i = 0; i < s->x; i++) + bar (s->p[i], baz (), s->y); + for (i = 0; i < s->x; i++) + s->p[i]->i++; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45500.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45500.c new file mode 100644 index 000000000..46e5100ae --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45500.c @@ -0,0 +1,6 @@ +/* PR debug/45500 */ +/* { dg-do compile } */ +/* { dg-options "-g -msse" } */ + +typedef char V __attribute__ ((__vector_size__ (16))); +static const V s = { '\n', '\r', '?', '\\' }; diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45617.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45617.c new file mode 100644 index 000000000..58f977289 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45617.c @@ -0,0 +1,22 @@ +/* PR rtl-optimization/45617 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int f1 (int x) +{ + return (x >> 23) > 12; +} +int f2 (int x) +{ + return x > ((13 << 23) - 1); +} +int f3 (int x) +{ + return (x >> 23) >= 12; +} +int f4 (int x) +{ + return x >= (12 << 23); +} + +/* { dg-final { scan-assembler-not "sarl" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45670.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45670.c new file mode 100644 index 000000000..c50c4ba14 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45670.c @@ -0,0 +1,23 @@ +/* PR target/45670 */ +/* { dg-do compile } */ +/* { dg-options "-Os -mtune=generic" } */ + +struct S +{ + float *buf; + int size; +}; + +void +foo (struct S *s) +{ + int i; + for (i = 0; i < s->size; ++i) + s->buf[i] = 0; +} + +/* Ensure we don't generate + lea (reg1,4),reg2; add (reg3),reg2; movl $0, (reg2) + instead of smaller + mov (reg3),reg2; movl $0, (reg2,reg1,4) */ +/* { dg-final { scan-assembler-not "lea\[lq\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45739.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45739.c new file mode 100644 index 000000000..bb36318a5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45739.c @@ -0,0 +1,24 @@ +/* PR rtl-optimization/45739 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +#include <emmintrin.h> + +__m128i var; + +void +foo (void) +{ + __m128i zero = _mm_setzero_si128 (); + var = _mm_xor_si128 (zero, var); +} + +void +bar (void) +{ + __m128i zero = _mm_setzero_si128 (); + var = _mm_or_si128 (var, zero); +} + +/* { dg-final { scan-assembler-not "pxor\[^\n\]*xmm" } } */ +/* { dg-final { scan-assembler-not "por\[^\n\]*xmm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45830.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45830.c new file mode 100644 index 000000000..85d5a3c5a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45830.c @@ -0,0 +1,31 @@ +/* PR target/45830 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-switchconv-all -mtune=generic" } */ + +int +foo (int *a) +{ + switch (*a) + { + case 0: + case 3: + case 1: + case 2: + case 4: + case 23: + case 26: + case 19: + case 5: + case 21: + case 20: + case 22: + case 27: + return 1; + default: + return 0; + } +} + +/* { dg-final { scan-tree-dump "expanding as bit test is preferable" "switchconv" } } */ +/* { dg-final { scan-assembler-not "CSWTCH" } } */ +/* { dg-final { cleanup-tree-dump "switchconv" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45852.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45852.c new file mode 100644 index 000000000..8b7bbfbe7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45852.c @@ -0,0 +1,16 @@ +/* PR middle-end/45852 */ +/* { dg-options "-O2 -mcmodel=small" } */ +/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && { ! { ia32 } } } } } */ +/* { dg-require-visibility "" } */ + +struct S { int s; }; + +volatile struct S globvar __attribute__((visibility ("hidden"))) = { -6 }; + +void +foo (void) +{ + globvar = globvar; +} + +/* { dg-final { scan-assembler-times "globvar.%?rip" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45903.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45903.c new file mode 100644 index 000000000..5cb642a4b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45903.c @@ -0,0 +1,44 @@ +/* PR tree-optimization/45903 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned long long a, b; +unsigned char c; + +void +f1 (void) +{ + c = (a >> 8) + (b >> 8); +} + +void +f2 (void) +{ + c = (a >> 8) | (b >> 8); +} + +void +f3 (void) +{ + c = (a >> 16) ^ (b >> 56); +} + +unsigned char +f4 (void) +{ + return (a >> 48) + (b >> 40); +} + +unsigned char +f5 (void) +{ + return (a >> 32) | (b >> 16); +} + +unsigned char +f6 (void) +{ + return (a >> 24) ^ (b >> 32); +} + +/* { dg-final { scan-assembler-not "shr\[qdl\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45913.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45913.c new file mode 100644 index 000000000..46b9c66f8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45913.c @@ -0,0 +1,23 @@ +/* PR target/45913 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fselective-scheduling2 -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops" } */ + +extern void bar (int, int); + +int ss[128]; + +void +foo (int i, int j, int k, int *p1, int *p2) +{ + int s[128]; + __builtin_memcpy (s, ss, sizeof s); + + while (i--) + { + int a = s[i]; + while (j--) + bar (k, p2[a]); + j = s[i] & 0xFF; + bar (p1[a], k); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45946.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45946.c new file mode 100644 index 000000000..81cd36026 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr45946.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target dfp } */ +/* { dg-options "-std=gnu99 -Os -fno-omit-frame-pointer" } */ + +void +__attribute__((noinline)) +bar (_Decimal128, _Decimal128, _Decimal128, _Decimal128, _Decimal128, + _Decimal128, _Decimal128, _Decimal128, _Decimal128); + +void +foo (void) +{ + bar (0, 0, 0, 0, 0, 0, 0, 0, 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46051.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46051.c new file mode 100644 index 000000000..2da432faa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46051.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */ + +double val1[4][2], val2[4][2], chk[4][2]; + +void +foo (void) +{ + int i, j; + for (i = 0; i < 4; i++) + { + double tmp = 0; + for (j = 0; j < 2; j++) + tmp += val1[i][j] * val2[i][j]; + for (j = 0; j < 2; j++) + chk[i][j] = tmp; + } +} + +float val1f[8][2], val2f[8][2], chkf[8][2]; + +void +foof (void) +{ + int i, j; + for (i = 0; i < 8; i++) + { + float tmp = 0; + for (j = 0; j < 2; j++) + tmp += val1f[i][j] * val2f[i][j]; + for (j = 0; j < 2; j++) + chkf[i][j] = tmp; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46084.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46084.c new file mode 100644 index 000000000..3ca22eb29 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46084.c @@ -0,0 +1,69 @@ +/* This test needs to use setrlimit to set the stack size, so it can + only run on Unix. */ +/* { dg-do run { target *-*-linux* *-*-solaris* *-*-darwin* } } */ +/* { dg-require-effective-target avx_runtime } */ +/* { dg-require-effective-target split_stack } */ +/* { dg-options "-fsplit-stack -O2 -mavx" } */ + +#include <stdlib.h> +#include <string.h> +#include <sys/types.h> +#include <sys/resource.h> + +/* Use a noinline function to ensure that the buffer is not removed + from the stack. */ +static void use_buffer (char *buf, size_t) __attribute__ ((noinline)); +static void +use_buffer (char *buf, size_t c) +{ + size_t i; + + for (i = 0; i < c; ++i) + buf[i] = (char) i; +} + +/* Each recursive call uses 10 * i bytes. We call it 1000 times, + using a total of 5,000,000 bytes. If -fsplit-stack is not working, + that will overflow our stack limit. */ + +static void +down1 (int i) +{ + char buf[10 * i]; + + if (i > 0) + { + use_buffer (buf, 10 * i); + down1 (i - 1); + } +} + +/* Same thing, using alloca. */ + +static void +down2 (int i) +{ + char *buf = alloca (10 * i); + + if (i > 0) + { + use_buffer (buf, 10 * i); + down2 (i - 1); + } +} + +int +main (void) +{ + struct rlimit r; + + /* We set a stack limit because we are usually invoked via make, and + make sets the stack limit to be as large as possible. */ + r.rlim_cur = 8192 * 1024; + r.rlim_max = 8192 * 1024; + if (setrlimit (RLIMIT_STACK, &r) != 0) + abort (); + down1 (1000); + down2 (1000); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46085-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46085-1.c new file mode 100644 index 000000000..0251556c5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46085-1.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic -ffast-math" } */ + +#include "avx-check.h" + +#define N 16 +#define DIFF 242 + +float b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45}; +float c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; + +void +main1 (float x, float max_result) +{ + int i; + float diff = 2; + float max = x; + float min = 10; + + for (i = 0; i < N; i++) { + diff += (b[i] - c[i]); + } + + for (i = 0; i < N; i++) { + max = max < c[i] ? c[i] : max; + } + + for (i = 0; i < N; i++) { + min = min > c[i] ? c[i] : min; + } + + /* check results: */ + if (diff != DIFF) + abort (); + if (max != max_result) + abort (); + if (min != 0) + abort (); +} + +static void +avx_test (void) +{ + main1 (100, 100); + main1 (0, 15); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46085-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46085-2.c new file mode 100644 index 000000000..568cdd96f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46085-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic -ffast-math" } */ + +#include "avx-check.h" + +#define N 16 +#define DIFF 242 + +double b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45}; +double c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; + +void +main1 (double x, double max_result) +{ + int i; + double diff = 2; + double max = x; + double min = 10; + + for (i = 0; i < N; i++) { + diff += (b[i] - c[i]); + } + + for (i = 0; i < N; i++) { + max = max < c[i] ? c[i] : max; + } + + for (i = 0; i < N; i++) { + min = min > c[i] ? c[i] : min; + } + + /* check results: */ + if (diff != DIFF) + abort (); + if (max != max_result) + abort (); + if (min != 0) + abort (); +} + +static void +avx_test (void) +{ + main1 (100, 100); + main1 (0, 15); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46095.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46095.c new file mode 100644 index 000000000..ab9501e78 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46095.c @@ -0,0 +1,12 @@ +/* PR debug/46095 */ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O -fschedule-insns2 -fno-omit-frame-pointer -fstack-protector" } */ + +extern void bar (char *); + +void +foo (void) +{ + char c[0x80000000UL]; + bar (c); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46098.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46098.c new file mode 100644 index 000000000..4cc07c255 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46098.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -ffloat-store" } */ + +typedef double v2df __attribute__((vector_size (16))); + +v2df foo (double *d) +{ + return __builtin_ia32_loadupd (d); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46153.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46153.c new file mode 100644 index 000000000..c6e0f52e8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46153.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-msse -ffloat-store" } */ + +typedef float v4sf __attribute__ ((__vector_size__ (16))); + +v4sf foo (v4sf a) +{ + return __builtin_ia32_movlhps (a, a); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46178.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46178.c new file mode 100644 index 000000000..661e3fd9e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46178.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O -m8bit-idiv -fira-algorithm=priority" } */ +/* This is the same as divmod-5.c, just with different options which + trigger an ICE. We don't look at the output. */ + +extern void foo (int, int, int, int, int, int); + +void +bar (int x, int y) +{ + foo (0, 0, 0, 0, x / y, x % y); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46226.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46226.c new file mode 100644 index 000000000..168d80e2b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46226.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-Os -fomit-frame-pointer -mno-accumulate-outgoing-args -fno-asynchronous-unwind-tables" } */ +/* { dg-options "-Os -fomit-frame-pointer -fno-asynchronous-unwind-tables" { target *-*-mingw* *-*-cygwin* } } */ + +extern void abort(void); + +static void *p[2]; + +void __attribute__((noinline)) +g(int x, ...) +{ + asm volatile ("" : : "g"(x)); +} + +void __attribute__((noinline)) +f(int x) +{ + p[0] = __builtin_return_address (0); + if (x == 0) + g(0); + g(1, 2, 3, 4, 5, 6, 7); + + asm goto ("jmp %l0" : : : : label); + abort (); + + label: + p[1] = __builtin_return_address (0); +} + +int main() +{ + f(1); + if (p[0] != p[1]) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46253.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46253.c new file mode 100644 index 000000000..406790aba --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46253.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O -g -mf16c -mtune=generic -dp" } */ + +typedef __m256i __attribute__ ((__vector_size__ (32))); + +__m256i bar (void); +void foo (void) +{ + int i = 0; + bar (); + __builtin_ia32_vzeroupper (); + while (++i); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46254.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46254.c new file mode 100644 index 000000000..512287a5b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46254.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -mcx16 -fpic -mcmodel=large" } */ + +__int128 i; + +void test () +{ + __sync_val_compare_and_swap (&i, i, i); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46285.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46285.c new file mode 100644 index 000000000..de705b08a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46285.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx -fsplit-stack -mtune=generic" } */ +/* { dg-require-effective-target split_stack } */ + +typedef char __m256 __attribute__ ((__vector_size__ (32))); +void foo (__m256 x) {} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46295.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46295.c new file mode 100644 index 000000000..4ac7c101a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46295.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mtune=generic -dp" } */ +/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ + +typedef double EXPRESS[5]; +void Parse_Rel_Factor (EXPRESS Express,int *Terms); +void Parse_Vector () +{ + EXPRESS Express; + int Terms; + for (Terms = 0; Terms < 5; Terms++) + Express[Terms] = 1.0; + Parse_Rel_Factor(Express,&Terms); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46419.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46419.c new file mode 100644 index 000000000..3b722283e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46419.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +#include <xmmintrin.h> + +void __attribute__((noinline)) +sse_test (void) +{ + char image[4]; + __m128 image4; + float out[4] __attribute__ ((aligned (16))); + int i; + + for (i = 0; i < 4; i++) + image[i] = i + 1; + + image4 = + _mm_cvtpi8_ps (_mm_setr_pi8 + (image[0], image[1], image[2], image[3], 0, 0, 0, 0)); + _mm_store_ps (out, image4); + _mm_empty (); + + for (i = 0; i < 4; i++) + if (out[i] != (float) (i + 1)) + abort (); + + image4 = + _mm_cvtpu8_ps (_mm_setr_pi8 + (image[0], image[1], image[2], image[3], 0, 0, 0, 0)); + _mm_store_ps (out, image4); + _mm_empty (); + + for (i = 0; i < 4; i++) + if (out[i] != (float) (i + 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46470.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46470.c new file mode 100644 index 000000000..11eb51a03 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46470.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* The pic register save adds unavoidable stack pointer references. */ +/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */ +/* These options are selected to ensure 1 word needs to be allocated + on the stack to maintain alignment for the call. This should be + transformed to push+pop. We also want to force unwind info updates. */ +/* { dg-options "-Os -fomit-frame-pointer -fasynchronous-unwind-tables" } */ +/* { dg-options "-Os -fomit-frame-pointer -mpreferred-stack-boundary=3 -fasynchronous-unwind-tables" { target ia32 } } */ +/* ms_abi has reserved stack-region. */ +/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */ +void f(); +void g() { f(); f(); } + +/* Both stack allocate and deallocate should be converted to push/pop. */ +/* { dg-final { scan-assembler-not "sp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46491.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46491.c new file mode 100644 index 000000000..82f704c26 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46491.c @@ -0,0 +1,22 @@ +/* PR tree-optimization/46491 */ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +extern void abort (void); + +__attribute__((noinline)) int +foo (int *p) +{ + int r; + asm ("movl $6, (%1)\n\txorl %0, %0" : "=r" (r) : "r" (p) : "memory"); + return r; +} + +int +main (void) +{ + int p = 8; + if ((foo (&p) ? : p) != 6) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46647.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46647.c new file mode 100644 index 000000000..c7e154287 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46647.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic" } */ + +char a[5]; +int +func1 (void) +{ + __builtin_memset (a,-1,sizeof (a)); + return 0; +} + +int a2[5]; +int +func2 (void) +{ + __builtin_memset (a2,-1,sizeof (a2)); + return 0; +} + +char a3[5]; +int +func3 (void) +{ + __builtin_memset (a3,0x8fffffff,sizeof (a3)); + return 0; +} + +char a4[5]; +int +func4 (void) +{ + __builtin_memset (a4,0x8fffff00,sizeof (a4)); + return 0; +} + +int a5[5]; +int +func5 (void) +{ + __builtin_memset (a5,0x8fffffff,sizeof (a5)); + return 0; +} + +/* { dg-final { scan-assembler-not "call\[\\t \]*_?memset" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46716.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46716.c new file mode 100644 index 000000000..29c5e1e49 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46716.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse -mno-sse2" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +typedef double V __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef union +{ + V x; + double a[2]; +} u; + +#define EMM_FLT8(a) ((double *)&(a)) + +void __attribute__ ((noinline)) +test (V s1, V s2) +{ + if (EMM_FLT8(s1)[0] != EMM_FLT8(s2)[0] + || EMM_FLT8(s1)[1] != EMM_FLT8(s2)[1]) + abort (); +} + +static void +sse_test (void) +{ + u s1; + + s1.a[0] = 1.0; + s1.a[1] = 2.0; + + test (s1.x, s1.x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46829.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46829.c new file mode 100644 index 000000000..d4c04d30f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46829.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fschedule-insns" } */ + +struct S +{ + int i, j; +}; + +extern struct S s[]; + +extern void bar (int, ...); + +void +foo (int n) +{ + while (s[n].i) + bar (0, n, s[n].j, s, s[n].i / s[n].j); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46843.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46843.c new file mode 100644 index 000000000..3b0d76d13 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46843.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fschedule-insns" } */ + +void foo (double *d1, double *u1, double *u2, double *d2, int s, int j, int i) +{ + int n = 1 << s; + double x = 0; + + for (; j < n; j++) + x += d1[j] * d2[i]; + d1[i] = x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46865-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46865-1.c new file mode 100644 index 000000000..220a1c077 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46865-1.c @@ -0,0 +1,31 @@ +/* PR rtl-optimization/46865 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern unsigned long f; + +#define m1(f) \ + if (f & 1) \ + asm volatile ("nop /* asmnop */\n"); \ + else \ + asm volatile ("nop /* asmnop */\n"); + +#define m2(f) \ + if (f & 1) \ + asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); \ + else \ + asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); + +void +foo (void) +{ + m1 (f); +} + +void +bar (void) +{ + m2 (f); +} + +/* { dg-final { scan-assembler-times "asmnop" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46865-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46865-2.c new file mode 100644 index 000000000..4a91f7c96 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46865-2.c @@ -0,0 +1,32 @@ +/* PR rtl-optimization/46865 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -save-temps" } */ + +extern unsigned long f; + +#define m1(f) \ + if (f & 1) \ + asm volatile ("nop /* asmnop */\n"); \ + else \ + asm volatile ("nop /* asmnop */\n"); + +#define m2(f) \ + if (f & 1) \ + asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); \ + else \ + asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); + +void +foo (void) +{ + m1 (f); +} + +void +bar (void) +{ + m2 (f); +} + +/* { dg-final { scan-assembler-times "asmnop" 2 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46880.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46880.c new file mode 100644 index 000000000..bc6d64299 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46880.c @@ -0,0 +1,28 @@ +/* PR target/46880 */ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-require-effective-target sse2_runtime } */ + +typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef double (*T)[2]; + +static __attribute__ ((noinline, noclone)) __m128d +foo (__m128d c, __m128d d) +{ + T cp = (T) &c; + T dp = (T) &d; + __m128d e = { (*cp)[1], (*dp)[1] }; + return e; +} + +int +main () +{ + __m128d c = { 1.0, 2.0 }; + __m128d d = { 3.0, 4.0 }; + union { __m128d x; double d[2]; } u; + u.x = foo (c, d); + if (u.d[0] != 2.0 || u.d[1] != 4.0) + __builtin_abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46939.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46939.c new file mode 100644 index 000000000..0fd8607bb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr46939.c @@ -0,0 +1,121 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +__extension__ typedef __SIZE_TYPE__ size_t; + +int +php_filter_parse_int (char const *str, unsigned int str_len, long *ret) +{ + long ctx_value; + int sign; + int digit; + char const *end; + int tmp; + char const *tmp___0; + char const *tmp___1; + + sign = 0; + digit = 0; + end = str + str_len; + switch ((int) *str) + { + case 45: + sign = 1; + case 43: + str++; + default:; + break; + } + if ((size_t) str < (size_t) end) + { + if ((int const) *str >= 49) + { + if ((int const) *str <= 57) + { + if (sign) + { + tmp = -1; + } + else + { + tmp = 1; + } + tmp___0 = str; + str++; + ctx_value = (long) (tmp * (int) ((int const) *tmp___0 - 48)); + } + else + { + return (-1); + } + } + else + { + return (-1); + } + } + else + { + return (-1); + } + if (end - str > 19) + { + return (-1); + } + while ((size_t) str < (size_t) end) + { + if ((int const) *str >= 48) + { + if ((int const) *str <= 57) + { + tmp___1 = str; + str++; + digit = (int) ((int const) *tmp___1 - 48); + if (!sign) + { + if (ctx_value <= + (9223372036854775807L - (long) digit) / 10L) + { + ctx_value = ctx_value * 10L + (long) digit; + } + else + { + goto _L; + } + } + else + { + _L: + if (sign) + { + if (ctx_value >= + ((-0x7FFFFFFFFFFFFFFF - 1) + (long) digit) / 10L) + { + ctx_value = ctx_value * 10L - (long) digit; + } + else + { + return (-1); + } + } + else + { + return (-1); + } + } + } + else + { + return (-1); + } + } + else + { + return (-1); + } + } + *ret = ctx_value; + return (1); +} + +/* { dg-final { scan-assembler-not "idiv" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47312.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47312.c new file mode 100644 index 000000000..03769a1cf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47312.c @@ -0,0 +1,25 @@ +/* PR target/47312 */ +/* { dg-do link } */ +/* { dg-require-effective-target lto } */ +/* { dg-require-effective-target xop } */ +/* { dg-require-effective-target c99_runtime } */ +/* { dg-options "-O -flto -mno-sse3 -mxop" } */ +/* { dg-add-options c99_runtime } */ + +extern double fma (double, double, double); +extern float fmaf (float, float, float); +extern long double fmal (long double, long double, long double); + +volatile float f; +volatile double d; +volatile long double ld; + +int +main () +{ + f = fmaf (f, f, f); + d = fma (d, d, d); + ld = fmal (ld, ld, ld); + __asm__ volatile ("" : : "r" (&f), "r" (&d), "r" (&ld) : "memory"); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47315.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47315.c new file mode 100644 index 000000000..871d3f1bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47315.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mvzeroupper" } */ + +__attribute__ ((__target__ ("avx"))) +float bar (float f) {} + +void foo (float f) +{ + bar (f); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47381.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47381.c new file mode 100644 index 000000000..c4b2127c2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47381.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=atom" } */ + +struct foo_t { + int limit; +} foo[3]; +void +bar () { + int i; + for (i = 0; i < 3; i++) { + __builtin_memset (&foo[i], 0, sizeof(*foo)); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47449.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47449.c new file mode 100644 index 000000000..99ef32f26 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47449.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void bar (void *, void *); +int +foo (void *p1, void *p2) +{ + int ret1, ret2; + __asm ("" : "=D" (ret1), "=S" (ret2)); + bar (p1, p2); + return ret1 + ret2; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47502-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47502-1.c new file mode 100644 index 000000000..727afe944 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47502-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +void +foo (const void *xxxxx, void *yyyyy, long y) +{ + asm volatile ("" :: "c" ((xxxxx)), "d" ((yyyyy)), "S" (y)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47502-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47502-2.c new file mode 100644 index 000000000..a8dc1ca01 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47502-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-pic" } */ + +int +foo (int how, const void *set, void *oset) +{ + int resultvar; + asm volatile ("" + : "=a" (resultvar) + : "0" (14) , "b" (how), "c" ((set)), "d" ((oset)), "S" (65 / 8) : "memory", "cc"); + return resultvar; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47564.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47564.c new file mode 100644 index 000000000..5d3f25d10 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47564.c @@ -0,0 +1,42 @@ +/* PR target/47564 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +static inline unsigned long long +foo (const unsigned char *p) +{ + return 1; +} + +__attribute__ ((__target__ ("sse4"))) void +bar (unsigned long long *x, const void *b, long long m) +{ + const unsigned char *p = (const unsigned char *) b; + const unsigned char *e = p + m; + unsigned int l = *x; + unsigned long long n = l; + + if ((e - p) >= 8192) + { + while ((e - p) >= 128) + { + n = __builtin_ia32_crc32di (n, foo (p)); + n = __builtin_ia32_crc32di (n, foo (p)); + n = __builtin_ia32_crc32di (n, foo (p)); + n = __builtin_ia32_crc32di (n, foo (p)); + n = __builtin_ia32_crc32di (n, foo (p)); + n = __builtin_ia32_crc32di (n, foo (p)); + n = __builtin_ia32_crc32di (n, foo (p)); + n = __builtin_ia32_crc32di (n, foo (p)); + n = __builtin_ia32_crc32di (n, foo (p)); + } + } + + while ((e - p) >= 16) + { + n = __builtin_ia32_crc32di (n, foo (p)); + n = __builtin_ia32_crc32di (n, foo (p)); + } + l = n; + *x = l; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47581.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47581.c new file mode 100644 index 000000000..dfc02a144 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47581.c @@ -0,0 +1,10 @@ +/* PR middle-end/47581 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fomit-frame-pointer -mpreferred-stack-boundary=4 -mincoming-stack-boundary=4" } */ +/* { dg-final { scan-assembler-not "(sub|add)l\[\\t \]*\\$\[0-9\]*,\[\\t \]*%\[re\]?sp" } } */ + +unsigned +foo (unsigned a, unsigned b) +{ + return ((unsigned long long) a * (unsigned long long) b) >> 32; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47665.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47665.c new file mode 100644 index 000000000..10fabb517 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47665.c @@ -0,0 +1,11 @@ +/* PR target/47665 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +#include <emmintrin.h> + +__m128d +foo (double *x, __m128i y) +{ + return _mm_load_pd (x + _mm_cvtsi128_si32 (_mm_srli_si128 (_mm_slli_epi32 (y, 2), 0))); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47780.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47780.c new file mode 100644 index 000000000..89fe4093d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47780.c @@ -0,0 +1,14 @@ +/* PR debug/47780 */ +/* { dg-do compile } */ +/* { dg-options "-O -fgcse -fgcse-las -fstack-protector-all -fno-tree-ccp -fno-tree-dominator-opts -fcompare-debug -Wno-psabi" } */ + +typedef int V2SF __attribute__ ((vector_size (128))); + +V2SF +foo (int x, V2SF a) +{ + V2SF b = a + (V2SF) {}; + while (x--) + a += b; + return a; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47800.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47800.c new file mode 100644 index 000000000..45c817bc6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47800.c @@ -0,0 +1,15 @@ +/* PR target/47800 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=nocona" } */ + +int +foo (unsigned char *x, unsigned char *y) +{ + unsigned char a; + for (a = 0; x < y; x++) + if (a & 0x80) + a = (unsigned char) (a << 1) + 1 + *x; + else + a = (unsigned char) (a << 1) + *x; + return a; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47809.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47809.c new file mode 100644 index 000000000..5832a65d8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr47809.c @@ -0,0 +1,13 @@ +/* PR c/47809 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +#include <emmintrin.h> +double bar (double, double); + +__m128d +foo (__m128d x) +{ + x *= (__m128d) { bar (1.0, 1.0), 0.0 }; + return (__m128d) ((__m128i) x ^ (__m128i) { 0, 0}); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48037-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48037-1.c new file mode 100644 index 000000000..1b64a7d19 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48037-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O -fno-math-errno" } */ + +typedef double __m128d __attribute__((vector_size(16))); +__m128d vsqrt1 (__m128d const x) +{ + double const* __restrict__ const y = (double const*)&x; + double const a = __builtin_sqrt(y[0]); + double const b = __builtin_sqrt(y[1]); + return (__m128d) { a, b }; +} + +/* Verify we do not spill x to the stack. */ +/* { dg-final { scan-assembler-not "%rsp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-1.c new file mode 100644 index 000000000..d9eef495c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__)); +typedef float __v2sf __attribute__ ((__vector_size__ (8))); +typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef float __v4sf __attribute__ ((__vector_size__ (16))); +void +_mm_storeh_pi (__m64 *__P, __m128 __A) +{ + __builtin_ia32_storehps ((__v2sf *)__P, (__v4sf)__A); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-2.c new file mode 100644 index 000000000..2b41c0bba --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__)); +typedef char __v8qi __attribute__ ((__vector_size__ (8))); +void +_mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P) +{ + __builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-3.c new file mode 100644 index 000000000..423c59804 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse3" } */ + +void +_mm_monitor (void const * __P, unsigned int __E, unsigned int __H) +{ + __builtin_ia32_monitor (__P, __E, __H); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-4.c new file mode 100644 index 000000000..df465a313 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -msse2" } */ + +void +_mm_clflush (void const *__A) +{ + __builtin_ia32_clflush (__A); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-5.c new file mode 100644 index 000000000..d6ed8e5fc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48084-5.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mrdrnd" } */ + +int +_rdrand16_step (unsigned short *__P) +{ + return __builtin_ia32_rdrand16_step (__P); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48237.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48237.c new file mode 100644 index 000000000..e20446eab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48237.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fcaller-saves -fschedule-insns2 -fselective-scheduling2 -mtune=core2" } */ + +union double_union +{ + double d; + int i[2]; +}; + +void bar (int, ...); + +void +foo (double d) +{ + union double_union du = { d }; + while (1) + { + du.i[1] -= 0x100000L; + bar (0, du.d); + du.d += d; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48335-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48335-1.c new file mode 100644 index 000000000..08c5284ea --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48335-1.c @@ -0,0 +1,32 @@ +/* PR middle-end/48335 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-tree-sra -msse2" } */ + +#include <emmintrin.h> + +typedef __float128 T __attribute__((may_alias)); + +struct S +{ + _Complex double d __attribute__((aligned (16))); +}; + +void bar (struct S); + +void +f1 (T x) +{ + struct S s; + *(T *) &s.d = x; + __real__ s.d *= 7.0; + bar (s); +} + +void +f2 (__m128d x) +{ + struct S s; + _mm_store_pd ((double *) &s.d, x); + __real__ s.d *= 7.0; + bar (s); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48389.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48389.c new file mode 100644 index 000000000..2ac18cdbe --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48389.c @@ -0,0 +1,13 @@ +/* PR middle-end/48389 */ +/* { dg-do compile } */ +/* { dg-options "-O -mtune=pentiumpro -Wno-abi" } */ +/* { dg-require-effective-target ia32 } */ +typedef float V2SF __attribute__ ((vector_size (128))); +V2SF foo (int x, V2SF a) +{ + V2SF b = {}; + if (x & 42) + b = a; + a += b; + return a; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48678.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48678.c new file mode 100644 index 000000000..6f6727fff --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48678.c @@ -0,0 +1,16 @@ +/* PR target/48678 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +#include <emmintrin.h> + +typedef short T __attribute__((may_alias)); +struct S { __m128i d; }; + +__m128i +foo (short *x, struct S *y, __m128i *z) +{ + struct S s = *y; + ((T *) &s.d)[0] = *x; + return _mm_cmpeq_epi16 (s.d, *z); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48688.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48688.c new file mode 100644 index 000000000..f4d663a21 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48688.c @@ -0,0 +1,24 @@ +/* PR target/48688 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int fn1 (int x) { return (x << 3) | 5; } +int fn2 (int x) { return (x * 8) | 5; } +int fn3 (int x) { return (x << 3) + 5; } +int fn4 (int x) { return (x * 8) + 5; } +int fn5 (int x) { return (x << 3) ^ 5; } +int fn6 (int x) { return (x * 8) ^ 5; } +long fn7 (long x) { return (x << 3) | 5; } +long fn8 (long x) { return (x * 8) | 5; } +long fn9 (long x) { return (x << 3) + 5; } +long fn10 (long x) { return (x * 8) + 5; } +long fn11 (long x) { return (x << 3) ^ 5; } +long fn12 (long x) { return (x * 8) ^ 5; } +long fn13 (unsigned x) { return (x << 3) | 5; } +long fn14 (unsigned x) { return (x * 8) | 5; } +long fn15 (unsigned x) { return (x << 3) + 5; } +long fn16 (unsigned x) { return (x * 8) + 5; } +long fn17 (unsigned x) { return (x << 3) ^ 5; } +long fn18 (unsigned x) { return (x * 8) ^ 5; } + +/* { dg-final { scan-assembler-not "\[ \t\]x?or\[bwlq\]\[ \t\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48708.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48708.c new file mode 100644 index 000000000..355c2b269 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48708.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +#include <emmintrin.h> + +typedef long long T __attribute__((may_alias)); +struct S { __m128i d; }; + +__m128i +foo (long long *x, struct S *y, __m128i *z) +{ + struct S s = *y; + ((T *) &s.d)[0] = *x; + return _mm_cmpeq_epi16 (s.d, *z); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48721.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48721.c new file mode 100644 index 000000000..f37a16949 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48721.c @@ -0,0 +1,51 @@ +/* PR rtl-optimization/48721 */ +/* { dg-do compile } */ +/* { dg-options "-O -foptimize-sibling-calls -fsched2-use-superblocks -fschedule-insns2 -mtune=core2" } */ + +extern unsigned char a[]; +extern int b[], d[], e[], f[], g[], *h[], m[], *n[], o[]; +extern char c[]; + +struct S +{ + unsigned char s1; + int s2, s3, s4, s5, s6, s7, s8; +}; + +__attribute__((noinline, noclone)) int +foo (int x) +{ + return 0; +} + +int +bar (int x, struct S *y) +{ + int z; + switch (x) + { + case 1: + case 2: + { + int t2, t4, t5, t6, t7, t8; + z = o[y->s8 * 6]; + t8 = *n[m[x] * 5]; + t4 = *h[y->s7]; + t7 = z; + z = g[f[x] + y->s6]; + t6 = e[y->s5]; + t5 = d[c[x] + y->s3 * 17]; + if (z) + t2 = b[z]; + if (a[z] != y->s1) + return foo (x); + y->s8 = t8; + y->s4 = t4; + y->s7 = t7; + y->s6 = t6; + y->s5 = t5; + y->s2 = t2; + } + } + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48722.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48722.c new file mode 100644 index 000000000..a35fe7e22 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48722.c @@ -0,0 +1,13 @@ +/* PR middle-end/48722 */ +/* { dg-do compile } */ +/* { dg-options "-Os -mno-push-args" } */ + +extern long long a; +extern int b; +void bar (int, long long); + +void +foo (void) +{ + bar (a > 0x85, b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48723.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48723.c new file mode 100644 index 000000000..ad102090e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr48723.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-fstack-check -mavx" } */ + +struct S0 +{ + int f0, f1, f2, f3; +} g_106; + +struct S0 +func_99 () +{ + return (g_106); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49002-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49002-1.c new file mode 100644 index 000000000..7553e8290 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49002-1.c @@ -0,0 +1,16 @@ +/* PR target/49002 */ +/* { dg-do compile } */ +/* { dg-options "-O -mavx" } */ + +#include <immintrin.h> + +void foo(const __m128d *from, __m256d *to, int s) +{ + __m256d var = _mm256_castpd128_pd256(from[0]); + var = _mm256_insertf128_pd(var, from[s], 1); + to[0] = var; +} + +/* Ensure we load into xmm, not ymm. */ +/* { dg-final { scan-assembler-not "vmovapd\[\t \]*\[^,\]*,\[\t \]*%ymm" } } */ +/* { dg-final { scan-assembler "vmovapd\[\t \]*\[^,\]*,\[\t \]*%xmm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49002-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49002-2.c new file mode 100644 index 000000000..b0e10091b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49002-2.c @@ -0,0 +1,14 @@ +/* PR target/49002 */ +/* { dg-do compile } */ +/* { dg-options "-O -mavx" } */ + +#include <immintrin.h> + +void foo(const __m128d from, __m256d *to) +{ + *to = _mm256_castpd128_pd256(from); +} + +/* Ensure we store ymm, not xmm. */ +/* { dg-final { scan-assembler-not "vmovapd\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */ +/* { dg-final { scan-assembler "vmovapd\[\t \]*%ymm\[0-9\]\+,\[^,\]*" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49095.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49095.c new file mode 100644 index 000000000..b7d1fb280 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49095.c @@ -0,0 +1,73 @@ +/* PR rtl-optimization/49095 */ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ +/* { dg-options "-Os -mregparm=2" { target ia32 } } */ + +void foo (void *); + +int * +f1 (int *x) +{ + if (!--*x) + foo (x); + return x; +} + +int +g1 (int x) +{ + if (!--x) + foo ((void *) 0); + return x; +} + +#define F(T, OP, OPN) \ +T * \ +f##T##OPN (T *x, T y) \ +{ \ + *x OP y; \ + if (!*x) \ + foo (x); \ + return x; \ +} \ + \ +T \ +g##T##OPN (T x, T y) \ +{ \ + x OP y; \ + if (!x) \ + foo ((void *) 0); \ + return x; \ +} \ + \ +T * \ +h##T##OPN (T *x) \ +{ \ + *x OP 24; \ + if (!*x) \ + foo (x); \ + return x; \ +} \ + \ +T \ +i##T##OPN (T x, T y) \ +{ \ + x OP 24; \ + if (!x) \ + foo ((void *) 0); \ + return x; \ +} + +#define G(T) \ +F (T, +=, plus) \ +F (T, -=, minus) \ +F (T, &=, and) \ +F (T, |=, or) \ +F (T, ^=, xor) + +G (char) +G (short) +G (int) +G (long) + +/* { dg-final { scan-assembler-not "test\[lq\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49168-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49168-1.c new file mode 100644 index 000000000..9676dc85a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49168-1.c @@ -0,0 +1,11 @@ +/* PR target/49168 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -mtune=generic" } */ +/* { dg-final { scan-assembler-not "movdqa\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */ +/* { dg-final { scan-assembler "movdqu\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */ + +void +flt128_va (void *mem, __float128 d) +{ + __builtin_memcpy (mem, &d, sizeof (d)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49504.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49504.c new file mode 100644 index 000000000..503e6c238 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49504.c @@ -0,0 +1,18 @@ +/* PR target/49504 */ +/* { dg-do run { target { x32 } } } */ +/* { dg-options "-O" } */ + +unsigned long long +foo (const void* p, unsigned long long q) +{ + unsigned long long a = (((unsigned long long) ((unsigned long) p)) + q) >> 32; + return a; +} + +int +main () +{ + if (foo (foo, 0x100000000ULL) != 0x1) + __builtin_abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49567.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49567.c new file mode 100644 index 000000000..309deb479 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49567.c @@ -0,0 +1,13 @@ +/* PR debug/49567 */ +/* { dg-do compile } */ +/* { dg-options "-g -O2 -msse4" } */ + +#include <x86intrin.h> + +__m128 +foo (__m128i x) +{ + __m128i y; + y = _mm_cvtepi16_epi32 (x); + return _mm_cvtepi32_ps (y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49715-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49715-1.c new file mode 100644 index 000000000..d959f9e37 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49715-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse -mfpmath=sse" } */ + +float func(unsigned x) +{ + return (x & 0xfffff) * 0.01f; +} + +/* { dg-final { scan-assembler-times "cvtsi2ss" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49715-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49715-2.c new file mode 100644 index 000000000..76d713790 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49715-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +double func(unsigned long long x) +{ + if (x <= 0x7ffffffffffffffeULL) + return (x + 1) * 0.01; + return 0.0; +} + +/* { dg-final { scan-assembler-times "cvtsi2sdq" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49781-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49781-1.c new file mode 100644 index 000000000..60f9d50d8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49781-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fpic -mtune=generic" } */ +/* { dg-require-effective-target fpic } */ + +static int heap[2*(256 +1+29)+1]; +static int heap_len; +static int heap_max; +void +foo (int elems) +{ + int n, m; + int max_code = -1; + int node = elems; + heap_len = 0, heap_max = (2*(256 +1+29)+1); + for (n = 0; n < elems; n++) + heap[++heap_len] = max_code = n; + do { + n = heap[1]; + heap[1] = heap[heap_len--]; + m = heap[1]; + heap[--heap_max] = n; + heap[--heap_max] = m; + } while (heap_len >= 2); +} + +/* { dg-final { scan-assembler-not "lea\[lq\]?\[ \t\]\\((%|)r\[a-z0-9\]*" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49866.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49866.c new file mode 100644 index 000000000..823305df7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49866.c @@ -0,0 +1,23 @@ +/* PR target/49866 */ +/* { dg-do assemble } */ +/* { dg-options "-O2 -mcmodel=large" { target lp64 } } */ + +void fn (void *, int, int); +int fn2 (void); +void baz (int); + +static void +foo (void *x, int y) +{ + int i; + for (i = 0; i < y; i++) + fn (x, fn2 (), i); +} + +void +bar (int u, int v, int w, void *x) +{ + baz (u); + foo (x, w); + baz (u); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49920.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49920.c new file mode 100644 index 000000000..ef2a18512 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49920.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target ia32 } */ + +typedef __SIZE_TYPE__ size_t; +extern void *malloc (size_t); + +register unsigned int MR_mr0 asm ("esi"); +register unsigned int MR_mr1 asm ("edi"); + +void ml_backend__ml_closure_gen_module11 (void) +{ + unsigned int MR_tempr1, MR_tempr2, MR_tempr3; + + MR_tempr1 = (unsigned int)((char *) malloc (sizeof (unsigned int)) + 4); + MR_tempr3 = ((unsigned int *) MR_mr0)[0]; + + ((unsigned int *) (MR_tempr1 - 4))[0] = MR_tempr3; + + MR_tempr2 = (unsigned int)((char *) malloc (2 * sizeof (unsigned int))); + + ((unsigned int *) MR_tempr2)[1] = MR_tempr1; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49927.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49927.c new file mode 100644 index 000000000..5850597d6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr49927.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ + +char a[1][1]; +long long b; + +void +foo (void) +{ + --a[b][b]; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50038.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50038.c new file mode 100644 index 000000000..e111574c4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50038.c @@ -0,0 +1,20 @@ +/* PR target/50038 */ +/* { dg-options "-O2" } */ + +void +test (int len, unsigned char *in, unsigned char *out) +{ + int i; + unsigned char xr, xg; + unsigned char xy=0; + for (i = 0; i < len; i++) + { + xr = *in++; + xg = *in++; + xy = (unsigned char) ((19595 * xr + 38470 * xg) >> 16); + + *out++ = xy; + } +} + +/* { dg-final { scan-assembler-times "movzbl" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50155.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50155.c new file mode 100644 index 000000000..c641d4c47 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50155.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mno-avx2" } */ + +void +foo (int x, double *a, double *b, double c) +{ + int i; + + for (i = 0; i < x; i++) + *a++ = *b++ * i / c; +} + +/* { dg-final { scan-assembler-not "vpaddd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50202.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50202.c new file mode 100644 index 000000000..2023ec86d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50202.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fno-tree-dse -fno-dce -msse4" } */ +/* { dg-require-effective-target sse4 } */ + +typedef char __v16qi __attribute__ ((__vector_size__ (16))); + +__v16qi v; +int i; + +void +foo (void) +{ + i = __builtin_ia32_pcmpistri128 (v, v, 255); + i = 255; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50482.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50482.c new file mode 100644 index 000000000..64c2686bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50482.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse4" } */ + +void +test (int code, unsigned int * image, int * colors) +{ + int i; + + for (i = 0; i < code; ++i) + image[i] = (colors[i] < 0 ? ~(unsigned int) 0 : colors[i]); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50603.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50603.c new file mode 100644 index 000000000..101ef8548 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50603.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +extern int *foo; + +int +bar (int x) +{ + return foo[x]; +} +/* { dg-final { scan-assembler-not "lea\[lq\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50712.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50712.c new file mode 100644 index 000000000..90cc75db3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50712.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2" } */ + +typedef __builtin_va_list __va_list; +typedef __va_list __gnuc_va_list; +typedef __gnuc_va_list va_list; +struct MSVCRT__iobuf { }; +typedef struct MSVCRT__iobuf MSVCRT_FILE; +typedef union _printf_arg { } printf_arg; +MSVCRT_FILE MSVCRT__iob[20]; +int pf_print_a (va_list *); +int __attribute__((__cdecl__)) +MSVCRT_vfprintf_s(MSVCRT_FILE* file, const char *format, va_list valist) +{ + if(!((file != ((void *)0)) + || (MSVCRT__invalid_parameter(((void *)0), ((void *)0), + ((void *)0), 0, 0),0))) + return -1; + return pf_printf_a(&valist); +} +int __attribute__((__cdecl__)) +MSVCRT_vprintf_s(const char *format, va_list valist) +{ + return MSVCRT_vfprintf_s((MSVCRT__iob+1),format,valist); +} +int __attribute__((__cdecl__)) +MSVCRT_fprintf_s(MSVCRT_FILE* file, const char *format, ...) +{ + va_list valist; + va_start (valist, format); + return MSVCRT_vfprintf_s(file, format, valist); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50725.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50725.c new file mode 100644 index 000000000..c9ca7d947 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50725.c @@ -0,0 +1,48 @@ +/* PR target/50725 */ +/* { dg-do run { target avx_runtime } } */ +/* { dg-options "-O2 -mavx" } */ + +extern void abort (void); + +typedef int __attribute__((vector_size (32))) m256i; + +__attribute__((noinline, noclone)) void +foo (int *x, m256i *y) +{ + asm volatile ("" : : "r" (x), "r" (y) : "memory"); +} + +__attribute__((noinline, noclone)) int +bar (int x) +{ + if (x > 20) + return 24; + m256i i; + foo (__builtin_alloca (x), &i); + return 128; +} + +__attribute__((noinline, noclone)) int +baz (int d0, int d1, int d2, int d3, int d4, int d5, int x) +{ + if (x > 20) + return 24; + m256i i; + d0 += d1 + d2 + d3 + d4 + d5; d1 += d0; + foo (__builtin_alloca (x), &i); + return 128; +} + +int +main () +{ + if (bar (22) != 24 || bar (20) != 128) + abort (); +#ifdef __x86_64__ + register long long r10 __asm__ ("r10") = 0xdeadbeefdeadbeefULL; + asm volatile ("" : "+r" (r10)); +#endif + if (baz (0, 0, 0, 0, 0, 0, 22) != 24 || baz (0, 0, 0, 0, 0, 0, 20) != 128) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50766.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50766.c new file mode 100644 index 000000000..9923de424 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50766.c @@ -0,0 +1,17 @@ +/* PR target/50766 */ +/* { dg-do assemble } */ +/* { dg-options "-mbmi2" } */ +/* { dg-require-effective-target bmi2 } */ + +#include <x86intrin.h> + +unsigned z; + +void +foo () +{ + unsigned x = 0x23593464; + unsigned y = 0xF9494302; + z = _pext_u32(x, y); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50788.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50788.c new file mode 100644 index 000000000..29a19634c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr50788.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -fpeel-loops -fstack-protector-all" } */ + +typedef long long __m256i __attribute__ ((__vector_size__ (32))); +typedef double __m256d __attribute__ ((__vector_size__ (32))); + +__m256d foo (__m256d *__P, __m256i __M) +{ + return __builtin_ia32_maskloadpd256 ( __P, __M); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr51235.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr51235.c new file mode 100644 index 000000000..c99d5c0e7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr51235.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O -ftree-vectorize -mxop -mavx2" } */ + +void *foo (int count, void **list) +{ + void *minaddr = list[0]; + int i; + + for (i = 1; i < count; i++) + { + void *addr = list[i]; + if (addr < minaddr) + minaddr = addr; + } + + return minaddr; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr51236.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr51236.c new file mode 100644 index 000000000..63bfaeeb0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr51236.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O -ftree-vectorize -mavx2" } */ + +long foo (long *p, int i) +{ + long x = 0; + + while (--i) + x ^= p[i]; + + return x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr51393.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr51393.c new file mode 100644 index 000000000..51175c87a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr51393.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O -mavx" } */ + +#include "avx-check.h" +#include <immintrin.h> + +static void +__attribute__((noinline)) +avx_test (void) +{ + long long in = 0x800000000ll; + long long out; + + __m256i zero = _mm256_setzero_si256(); + __m256i tmp = _mm256_insert_epi64 (zero, in, 0); + out = _mm256_extract_epi64(tmp, 0); + + if (in != out) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr51987.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr51987.c new file mode 100644 index 000000000..6ac2e6395 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr51987.c @@ -0,0 +1,33 @@ +/* PR tree-optimization/51987 */ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-options "-O3" } */ + +extern void abort (void); +union U { unsigned long long l; struct { unsigned int l, h; } i; }; + +__attribute__((noinline, noclone)) void +foo (char *x, char *y) +{ + int i; + for (i = 0; i < 64; i++) + { + union U u; + asm ("movl %1, %k0; salq $32, %0" : "=r" (u.l) : "r" (i)); + x[i] = u.i.h; + union U v; + asm ("movl %1, %k0; salq $32, %0" : "=r" (v.l) : "r" (i)); + y[i] = v.i.h; + } +} + +int +main () +{ + char a[64], b[64]; + int i; + foo (a, b); + for (i = 0; i < 64; i++) + if (a[i] != i || b[i] != i) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52146.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52146.c new file mode 100644 index 000000000..4eb91c06d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52146.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mx32" } */ + +void +test1 (void) +{ + int* apic_tpr_addr = (int *) 0xfee00080; + *apic_tpr_addr += 4; +} + +void +test2 (void) +{ + int* apic_tpr_addr = (int *) 0xfee00080; + *apic_tpr_addr = 0; +} + +/* { dg-final { scan-assembler-not "\[,\\t \]+-18874240" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52330.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52330.c new file mode 100644 index 000000000..22ba0b21a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52330.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O0" } */ + +void foo (int a) +{ + asm volatile ("# %H0" : : "r" (a)); /* { dg-error "not an offsettable" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52698.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52698.c new file mode 100644 index 000000000..d84685cb3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52698.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mx32 -maddress-mode=long" } */ + +extern void abort (void); +static __thread unsigned char foo [32] +__attribute__ ((tls_model ("initial-exec"), aligned (sizeof (void *)))); + +void +test2 (void) +{ + unsigned int s; + for (s = 0; s < sizeof (foo); ++s) + { + if (foo [s] != s) + abort (); + foo [s] = sizeof (foo) - s; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52736.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52736.c new file mode 100644 index 000000000..f35c1fd6c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52736.c @@ -0,0 +1,29 @@ +/* PR target/52736 */ +/* { dg-do run } */ +/* { dg-options "-O1 -msse2" } */ +/* { dg-require-effective-target sse2_runtime } */ + +#include <x86intrin.h> + +typedef double D __attribute__((may_alias)); +__attribute__((aligned(16))) static const double r[4] = { 1., 5., 1., 3. }; + +__attribute__((noinline, noclone)) +void +foo (int x) +{ + asm volatile ("" : "+g" (x) : : "memory"); + if (x != 3) + __builtin_abort (); +} + +int +main () +{ + __m128d t = _mm_set1_pd (5.); + ((D *)(&t))[0] = 1.; + foo (_mm_movemask_pd (_mm_cmpeq_pd (t, _mm_load_pd (&r[0])))); + ((D *)(&t))[1] = 3.; + foo (_mm_movemask_pd (_mm_cmpeq_pd (t, _mm_load_pd (&r[2])))); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52754.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52754.c new file mode 100644 index 000000000..0f2dbff2d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52754.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fpredictive-commoning -msse2 -std=c99" } */ +/* { dg-require-effective-target sse2 } */ + +#include <x86intrin.h> + +#include "isa-check.h" +#include "sse-os-support.h" + +int main() +{ + const float mem[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; + + unsigned int indexes[8]; + for (unsigned int i = 0; i < 8; ++i) indexes[i] = i; + + check_isa (); + + if (!sse_os_support ()) + exit (0); + + __m128 x = _mm_setr_ps(0, 1, 2, 3); + for (unsigned int i = 0; i + 4 < 6; ++i) { + const unsigned int *ii = &indexes[i]; + const __m128 tmp = _mm_setr_ps(mem[ii[0]], mem[ii[1]], mem[ii[2]], mem[ii[3]]); + if (0xf != _mm_movemask_ps(_mm_cmpeq_ps(tmp, x))) { + __builtin_abort(); + } + x = _mm_add_ps(x, _mm_set1_ps(1)); + } + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52857-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52857-1.c new file mode 100644 index 000000000..16fd78f96 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52857-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-g -O -mx32 -maddress-mode=long" } */ + +extern void get_BID128 (int *); +void +__bid128_div (void) +{ + int res; + get_BID128 (&res); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52857-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52857-2.c new file mode 100644 index 000000000..879240a75 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52857-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-g -O -mx32 -maddress-mode=long" } */ + +void uw_init_context_1 (void *); +void _Unwind_ForcedUnwind (void) +{ + uw_init_context_1 (__builtin_dwarf_cfa ()); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52876.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52876.c new file mode 100644 index 000000000..6d5e47a94 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52876.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { x32 } } } */ +/* { dg-options "-O2 -mx32 -maddress-mode=long" } */ + +extern void abort (void); + +long long li; + +long long +__attribute__ ((noinline)) +testfunc (void* addr) +{ + li = (long long)(int)addr; + li &= 0xffffffff; + return li; +} + +int main (void) +{ + volatile long long rv_test; + rv_test = testfunc((void*)0x87651234); + if (rv_test != 0x87651234ULL) + abort (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52882.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52882.c new file mode 100644 index 000000000..5f0f12a72 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52882.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +struct S1 { + int f0; + int f1; +}; + +int fn1 (); +void fn2 (struct S1); + +void +fn3 () { + struct S1 a = { 1, 0 }; + if (fn1 ()) + fn2 (a); + for (; a.f1;) { + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52883.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52883.c new file mode 100644 index 000000000..766e87ee1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr52883.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +int a, b, d, e, f, i, j, k, l, m; +unsigned c; +int g[] = { }, h[0]; + +int +fn1 () { + return 0; +} + +void +fn2 () { + c = 0; + e = 0; + for (;; e = 0) + if (f > j) { + k = fn1 (); + l = (d || k) * b; + m = l * a; + h[0] = m <= i; + } else + i = g[c]; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53249.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53249.c new file mode 100644 index 000000000..c41d3e9ed --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53249.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-O2 -mx32 -ftls-model=initial-exec -maddress-mode=short" } */ + +struct gomp_task +{ + struct gomp_task *parent; +}; + +struct gomp_thread +{ + int foo1; + struct gomp_task *task; +}; + +extern __thread struct gomp_thread gomp_tls_data; + +void +__attribute__ ((noinline)) +gomp_end_task (void) +{ + struct gomp_thread *thr = &gomp_tls_data; + struct gomp_task *task = thr->task; + + thr->task = task->parent; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53315.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53315.c new file mode 100644 index 000000000..350efa724 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53315.c @@ -0,0 +1,27 @@ +/* PR target/53315 and PR target/53291 */ +/* { dg-do run } */ +/* { dg-options "-O2 -mrtm" } */ +/* { dg-require-effective-target rtm } */ + +#include <x86intrin.h> +#include "rtm-check.h" + +static void +rtm_test (void) +{ + int flag = -1; + unsigned status; + + if ((status = _xbegin ()) == _XBEGIN_STARTED) + { + flag = _xtest (); + _xend (); + } + else + return; + + if (flag != 1) + abort (); + if (_xtest () != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53366-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53366-1.c new file mode 100644 index 000000000..c24a594b8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53366-1.c @@ -0,0 +1,5 @@ +/* PR tree-optimization/53366 */ +/* { dg-do run { target avx_runtime } } */ +/* { dg-options "-O3 -mavx" } */ + +#include "../../gcc.dg/torture/pr53366-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53366-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53366-2.c new file mode 100644 index 000000000..77270a0b0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53366-2.c @@ -0,0 +1,5 @@ +/* PR tree-optimization/53366 */ +/* { dg-do run { target avx_runtime } } */ +/* { dg-options "-O3 -mavx" } */ + +#include "../../gcc.dg/torture/pr53366-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53397-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53397-1.c new file mode 100644 index 000000000..63650366c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53397-1.c @@ -0,0 +1,28 @@ +/* Prefetching when the step is loop invariant. */ +/* { dg-do compile } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O3 -msse2 -fprefetch-loop-arrays -fdump-tree-aprefetch-details --param min-insn-to-prefetch-ratio=3 --param simultaneous-prefetches=10 -fdump-tree-aprefetch-details" } */ + + +double data[16384]; +void prefetch_when_non_constant_step_is_invariant(int step, int n) +{ + int a; + int b; + for (a = 1; a < step; a++) { + for (b = 0; b < n; b += 2 * step) { + + int i = 2*(b + a); + int j = 2*(b + a + step); + + + data[j] = data[i]; + data[j+1] = data[i+1]; + } + } +} + +/* { dg-final { scan-tree-dump "Issued prefetch" "aprefetch" } } */ +/* { dg-final { scan-assembler "prefetcht0" } } */ + +/* { dg-final { cleanup-tree-dump "aprefetch" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53397-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53397-2.c new file mode 100644 index 000000000..b34fafc52 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53397-2.c @@ -0,0 +1,28 @@ +/* Not prefetching when the step is loop variant. */ +/* { dg-do compile } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O3 -msse2 -fprefetch-loop-arrays -fdump-tree-aprefetch-details --param min-insn-to-prefetch-ratio=3 --param simultaneous-prefetches=10 -fdump-tree-aprefetch-details" } */ + +double data[16384]; +void donot_prefetch_when_non_constant_step_is_variant(int step, int n) +{ + int a; + int b; + for (a = 1; a < step; a++,step*=2) { + for (b = 0; b < n; b += 2 * step) { + + int i = 2*(b + a); + int j = 2*(b + a + step); + + + data[j] = data[i]; + data[j+1] = data[i+1]; + } + } +} + +/* { dg-final { scan-tree-dump "Not prefetching" "aprefetch" } } */ +/* { dg-final { scan-tree-dump "loop variant step" "aprefetch" } } */ + +/* { dg-final { cleanup-tree-dump "aprefetch" } } */ + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53416.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53416.c new file mode 100644 index 000000000..68abe8bdd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53416.c @@ -0,0 +1,17 @@ +/* PR target/53416 */ +/* { dg-options "-O2 -mrdrnd" } */ + +int test (void) +{ + unsigned int number = 0; + int result0, result1, result2, result3; + + result0 = __builtin_ia32_rdrand32_step (&number); + result1 = __builtin_ia32_rdrand32_step (&number); + result2 = __builtin_ia32_rdrand32_step (&number); + result3 = __builtin_ia32_rdrand32_step (&number); + + return result0 + result1 +result2 + result3; +} + +/* { dg-final { scan-assembler-times "rdrand" 4 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53425-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53425-1.c new file mode 100644 index 000000000..00143f32a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53425-1.c @@ -0,0 +1,15 @@ +/* PR target/53425 */ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mno-sse" } */ +/* { dg-skip-if "no SSE vector" { x86_64-*-mingw* } } */ + +typedef double __v2df __attribute__ ((__vector_size__ (16))); + +extern __v2df x; + +extern void bar (__v2df); +void +foo (void) +{ + bar (x); /* { dg-message "warning: SSE vector argument without SSE enabled changes the ABI" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53425-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53425-2.c new file mode 100644 index 000000000..97523f35b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53425-2.c @@ -0,0 +1,15 @@ +/* PR target/53425 */ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mno-sse" } */ +/* { dg-skip-if "no SSE vector" { x86_64-*-mingw* } } */ + +typedef float __v2sf __attribute__ ((__vector_size__ (8))); + +extern __v2sf x; + +extern void bar (__v2sf); +void +foo (void) +{ + bar (x); /* { dg-message "warning: SSE vector argument without SSE enabled changes the ABI" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53698.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53698.c new file mode 100644 index 000000000..3acefba00 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53698.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O -mx32 -maddress-mode=long -fno-tree-dominator-opts" } */ + +extern char foo[]; + +void +test2 (void) +{ + int s; + for (s = 0;; ++s) + { + if (foo[s] != s) + __builtin_abort (); + foo[s] = s; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53712.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53712.c new file mode 100644 index 000000000..5c47e20c3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53712.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse4.2" } */ + +typedef char v16qi __attribute__ ((__vector_size__ (16))); + +int test (const char *s1, const char *s2) +{ + v16qi s1chars = __builtin_ia32_loaddqu ((const char *) s2); + v16qi s2chars = __builtin_ia32_loaddqu ((const char *) s1); + return __builtin_ia32_pcmpistri128 (s1chars, s2chars, 0); +} + +/* { dg-final { scan-assembler-times "movdqu" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53759.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53759.c new file mode 100644 index 000000000..b824b9845 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53759.c @@ -0,0 +1,17 @@ +/* PR target/53759 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx" } */ +/* { dg-require-effective-target avx } */ + +#include <xmmintrin.h> + +void +foo (__m128 *x, __m64 *y) +{ + __m128 a = _mm_setzero_ps (); + __m128 b = _mm_loadl_pi (a, y); + *x = _mm_add_ps (b, b); +} + +/* { dg-final { scan-assembler "vmovlps\[ \\t\]" } } */ +/* { dg-final { scan-assembler-not "vshufps\[ \\t\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53907.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53907.c new file mode 100644 index 000000000..27e2e0298 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr53907.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O -msse2" } */ + +#include <emmintrin.h> + +__extension__ typedef __UINTPTR_TYPE__ uintptr_t; + +__m128i x(char *s) +{ + __m128i sz,z,mvec; + s-=((uintptr_t) s)%16; + sz=_mm_load_si128((__m128i *)s); + return sz; +} + +/* { dg-final { scan-assembler "movdqa" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54157.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54157.c new file mode 100644 index 000000000..b5c4528b8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54157.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mx32 -maddress-mode=long -ftree-vectorize" } */ + +struct s2{ + int n[24 -1][24 -1][24 -1]; +}; + +struct test2{ + struct s2 e; +}; + +struct test2 tmp2[4]; + +void main1 () +{ + int i,j; + + for (i = 0; i < 24 -4; i++) + for (j = 0; j < 24 -4; j++) + tmp2[2].e.n[1][i][j] = 8; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54400.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54400.c new file mode 100644 index 000000000..5ed5ba066 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54400.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse3 -mfpmath=sse" } */ + +#include <x86intrin.h> + +double f (__m128d p) +{ + return p[0] - p[1]; +} + +double g1 (__m128d p) +{ + return p[0] + p[1]; +} + +double g2 (__m128d p) +{ + return p[1] + p[0]; +} + +__m128d h (__m128d p, __m128d q) +{ + __m128d r = { p[0] - p[1], q[0] - q[1] }; + return r; +} + +__m128d i1 (__m128d p, __m128d q) +{ + __m128d r = { p[0] + p[1], q[0] + q[1] }; + return r; +} + +__m128d i2 (__m128d p, __m128d q) +{ + __m128d r = { p[0] + p[1], q[1] + q[0] }; + return r; +} + +__m128d i3 (__m128d p, __m128d q) +{ + __m128d r = { p[1] + p[0], q[0] + q[1] }; + return r; +} + +__m128d i4 (__m128d p, __m128d q) +{ + __m128d r = { p[1] + p[0], q[1] + q[0] }; + return r; +} + +/* { dg-final { scan-assembler-times "hsubpd" 2 } } */ +/* { dg-final { scan-assembler-times "haddpd" 6 } } */ +/* { dg-final { scan-assembler-not "unpck" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54445-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54445-1.c new file mode 100644 index 000000000..ebac532eb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54445-1.c @@ -0,0 +1,25 @@ +/* { dg-do run { target tls_runtime } } */ +/* { dg-options "-O2" } */ +/* { dg-add-options tls } */ + +__thread unsigned char tls_array[64]; + +unsigned char +__attribute__ ((noinline)) +tls_array_lookup_with_negative_constant(long long int position) { + return tls_array[position - 1]; +} + +int +main () +{ + int i; + + for (i = 0; i < sizeof (tls_array) / sizeof (tls_array[0]); i++) + tls_array[i] = i; + + for (i = 0; i < sizeof (tls_array) / sizeof (tls_array[0]); i++) + if (i != tls_array_lookup_with_negative_constant (i + 1)) + __builtin_abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54445-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54445-2.c new file mode 100644 index 000000000..5151c1328 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54445-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { *-*-linux* && { ! { ia32 } } } } } */ +/* { dg-options "-O2 -fno-pic" } */ + +__thread unsigned char tls_array[64]; + +unsigned char +tls_array_lookup_with_negative_constant(long long int position) { + return tls_array[position - 1]; +} + +/* { dg-final { scan-assembler "mov(b|zbl)\[ \t\](%fs:)?tls_array@tpoff-1\\(%" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54457.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54457.c new file mode 100644 index 000000000..9abfbd320 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54457.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-O2 -mx32 -maddress-mode=short" } */ + +extern char array[40]; + +char foo (long long position) +{ + return array[position + 1]; +} + +/* { dg-final { scan-assembler-not "add\[lq\]?\[^\n\]*1" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54592.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54592.c new file mode 100644 index 000000000..20dc11c23 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54592.c @@ -0,0 +1,17 @@ +/* PR target/54592 */ +/* { dg-do compile } */ +/* { dg-options "-Os -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include <emmintrin.h> + +void +func (__m128i * foo, size_t a, size_t b, int *dst) +{ + __m128i x = foo[a]; + __m128i y = foo[b]; + __m128i sum = _mm_add_epi32 (x, y); + *dst = _mm_cvtsi128_si32 (sum); +} + +/* { dg-final { scan-assembler "paddd\[^\n\r\]*(\\(\[^\n\r\]*\\)|XMMWORD PTR)" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54703.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54703.c new file mode 100644 index 000000000..e30c293c0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr54703.c @@ -0,0 +1,36 @@ +/* PR target/54703 */ +/* { dg-do run { target sse2_runtime } } */ +/* { dg-options "-O -msse2" } */ +/* { dg-additional-options "-mavx -mtune=bdver1" { target avx_runtime } } */ + +extern void abort (void); +typedef double V __attribute__((vector_size(16))); + +union { + unsigned long long m[2]; + V v; +} u = { { 0xffffffffff000000ULL, 0xffffffffff000000ULL } }; + +static inline V +foo (V x) +{ + V y = __builtin_ia32_andpd (x, u.v); + V z = __builtin_ia32_subpd (x, y); + return __builtin_ia32_mulpd (y, z); +} + +void +test (V *x) +{ + V a = { 2.1, 2.1 }; + *x = foo (foo (a)); +} + +int +main () +{ + test (&u.v); + if (u.m[0] != 0x3acbf487f0a30550ULL || u.m[1] != u.m[0]) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55049-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55049-1.c new file mode 100644 index 000000000..cb7fb9b3f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55049-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -fPIC -mx32" } */ + +extern void __morestack_fail (const char *msg); +void +foo (void) +{ + static const char msg[] = "munmap of stack space failed: errno "; + __morestack_fail (msg); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55093.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55093.c new file mode 100644 index 000000000..3d32a5799 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55093.c @@ -0,0 +1,81 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mx32 -maddress-mode=long" } */ +/* { dg-skip-if "different ABI" { x86_64-*-mingw* } } */ + +typedef union tree_node *tree; +typedef const union tree_node *const_tree; +typedef struct { + unsigned long long low; + long long high; +} double_int; +struct real_value { +}; +struct real_format { + int has_signed_zero; +}; +extern const struct real_format * real_format_for_mode[]; +extern int real_isnegzero (const struct real_value *); +enum tree_code { REAL_CST, SSA_NAME }; +struct tree_base { + enum tree_code code : 16; + union { + unsigned int version; + } + u; +}; +extern void tree_check_failed (const_tree, const char *, int, const char *, ...) __attribute__ ((__noreturn__)); +union tree_node { + struct tree_base base; +}; +inline tree tree_check (tree __t, const char *__f, int __l, const char *__g, enum tree_code __c) { + if (((enum tree_code) (__t)->base.code) != __c) + tree_check_failed (__t, __f, __l, __g, __c, 0); + return __t; +} +struct prop_value_d { + int lattice_val; + tree value; + double_int mask; +}; +typedef struct prop_value_d prop_value_t; +static prop_value_t *const_val; +static void canonicalize_float_value (prop_value_t *); +typedef void (*ssa_prop_visit_stmt_fn) (prop_value_t); +typedef void (*ssa_prop_visit_phi_fn) (void); +typedef void (*ssa_prop_fold_stmt_fn) (void *gsi); +typedef void (*ssa_prop_get_value_fn) ( prop_value_t *val); +void ssa_propagate (ssa_prop_visit_stmt_fn, ssa_prop_visit_phi_fn); +int substitute_and_fold (ssa_prop_get_value_fn, ssa_prop_fold_stmt_fn); +void ccp_fold_stmt (void *); +static void get_constant_value (prop_value_t *val) { + canonicalize_float_value (val); +} +static void canonicalize_float_value (prop_value_t *val) { + int mode; + struct real_value d; + if (val->lattice_val != 1 + || ((enum tree_code) (val->value)->base.code) != REAL_CST) + return; + mode = val->lattice_val; + if (real_format_for_mode[mode]->has_signed_zero && real_isnegzero (&d)) + ccp_fold_stmt (0); +} +static void set_lattice_value (tree var, prop_value_t new_val) { + prop_value_t *old_val = &const_val[(tree_check ((var), "", + 0, "", + (SSA_NAME)))->base.u.version]; + canonicalize_float_value (&new_val); + canonicalize_float_value (old_val); +} +static void ccp_visit_phi_node (void) { + prop_value_t new_val; + set_lattice_value (0, new_val); +} +static void ccp_visit_stmt (prop_value_t v) { + set_lattice_value (0, v); +} +unsigned int do_ssa_ccp (void) { + ssa_propagate (ccp_visit_stmt, ccp_visit_phi_node); + substitute_and_fold (get_constant_value, ccp_fold_stmt); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55116-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55116-1.c new file mode 100644 index 000000000..de272445a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55116-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mx32 -maddress-mode=long" } */ + +int glob_int_arr[100]; +int glob_int = 4; + +void +expr_global (void) +{ + __builtin_prefetch (glob_int_arr + glob_int, 0, 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55116-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55116-2.c new file mode 100644 index 000000000..7ef8eade0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55116-2.c @@ -0,0 +1,86 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mx32 -maddress-mode=long" } */ + +typedef struct rtx_def *rtx; +enum rtx_code { MINUS }; +union rtunion_def { + rtx rt_rtx; +}; +typedef union rtunion_def rtunion; +struct rtx_def { + enum rtx_code code: 16; + union u { + rtunion fld[1]; + } + u; +}; +rtx simplify_binary_operation (enum rtx_code code, int mode, + rtx op0, rtx op1); +struct simplify_plus_minus_op_data { + rtx op; + short neg; +}; +void simplify_plus_minus (enum rtx_code code, int mode, rtx op0, rtx op1) +{ + struct simplify_plus_minus_op_data ops[8]; + rtx tem = (rtx) 0; + int n_ops = 2, input_ops = 2; + int changed, canonicalized = 0; + int i, j; + __builtin_memset (ops, 0, sizeof (ops)); + do + { + changed = 0; + for (i = 0; i < n_ops; i++) + { + rtx this_op = ops[i].op; + int this_neg = ops[i].neg; + enum rtx_code this_code = ((enum rtx_code) (this_op)->code); + switch (this_code) + { + case MINUS: + if (n_ops == 7) + return; + n_ops++; + input_ops++; + changed = 1; + canonicalized |= this_neg; + break; + } + } + } + while (changed); + do + { + j = n_ops - 1; + for (i = n_ops - 1; j >= 0; j--) + { + rtx lhs = ops[j].op, rhs = ops[i].op; + int lneg = ops[j].neg, rneg = ops[i].neg; + if (lhs != 0 && rhs != 0) + { + enum rtx_code ncode = MINUS; + if (((enum rtx_code) (lhs)->code) == MINUS) + tem = simplify_binary_operation (ncode, mode, lhs, rhs); + if (tem && ! (((enum rtx_code) (tem)->code) == MINUS + && ((((((tem)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx) == lhs + && ((((((tem)->u.fld[0]).rt_rtx))->u.fld[1]).rt_rtx) == rhs)) + { + lneg &= rneg; + ops[i].op = tem; + ops[i].neg = lneg; + ops[j].op = (rtx) 0; + changed = 1; + canonicalized = 1; + } + } + } + for (i = 0, j = 0; j < n_ops; j++) + if (ops[j].op) + { + ops[i] = ops[j]; + i++; + } + } + while (changed); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55130.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55130.c new file mode 100644 index 000000000..61b98dc93 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55130.c @@ -0,0 +1,15 @@ +/* PR middle-end/55130 */ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-O1 -mregparm=3 -mpreferred-stack-boundary=2" } */ + +extern void bar(long long); + +int foo(long long a, char b, long long c, long long d) +{ + if (c == 0) + c = d; + + bar(b + c); + + return a == d; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55141.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55141.c new file mode 100644 index 000000000..a45775599 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55141.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-options "-O -fno-split-wide-types" } */ + +typedef struct +{ + long int p_x, p_y; +} Point; + +static __attribute__ ((noinline, noclone)) + void foo (Point p0, Point p1, Point p2, Point p3) +{ + if (p0.p_x != 1 + || p1.p_x != 3 + || p2.p_x != 5 + || p3.p_x != 7) + __builtin_abort (); +} + +int +main (int argc, char *argv[]) +{ + Point p0, p1, p2, p3, p4, p5; + p0.p_x = 1; + p1.p_x = 3; + p2.p_x = 5; + p3.p_x = 7; + foo (p0, p1, p2, p3); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55142-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55142-1.c new file mode 100644 index 000000000..e6b5f126c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55142-1.c @@ -0,0 +1,35 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -mx32 -maddress-mode=long -fpic" } */ + +typedef int int32_t; +typedef unsigned int uint32_t; +typedef int32_t Elf32_Sword; +typedef struct +{ + Elf32_Sword d_tag; +} Elf32_Dyn; +struct link_map +{ + Elf32_Dyn *l_ld; + Elf32_Dyn *l_info[34]; +}; +extern struct link_map _dl_rtld_map __attribute__ ((visibility ("hidden"))); +static void elf_get_dynamic_info (struct link_map *l) +{ + Elf32_Dyn *dyn = l->l_ld; + Elf32_Dyn **info; + info = l->l_info; + while (dyn->d_tag != 0) + { + if ((uint32_t) (0x6ffffeff - dyn->d_tag) < 11) + info[0x6ffffeff - dyn->d_tag + 12] = dyn; + ++dyn; + } +} +void +foo (void) +{ + elf_get_dynamic_info (&_dl_rtld_map); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55142-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55142-2.c new file mode 100644 index 000000000..34f468719 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55142-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O3 -mx32 -maddress-mode=long -fpic" } */ +/* { dg-final { scan-assembler-not "movl\[\\t \]*%.*,\[\\t \]*-1073742592\\(%r(.x|.i|.p|\[1-9\]*)\\)" } } */ + +typedef int int32_t; +typedef unsigned int uint32_t; +typedef uint32_t Elf32_Word; +typedef int32_t Elf32_Sword; +typedef uint32_t Elf32_Addr; +typedef struct { + Elf32_Sword d_tag; + union { + Elf32_Word d_val; + Elf32_Addr d_ptr; + } d_un; +} Elf32_Dyn; +struct link_map { + Elf32_Dyn *l_ld; + Elf32_Dyn *l_info[34 + 16 + 3 + 12 + 11]; +}; +void +elf_get_dynamic_info (struct link_map *l) +{ + Elf32_Dyn *dyn = l->l_ld; + Elf32_Dyn **info = l->l_info; + typedef Elf32_Word d_tag_utype; + while (dyn->d_tag != 0) { + if ((d_tag_utype) (0x6ffffeff - dyn->d_tag) < 11) + info[(0x6ffffeff - dyn->d_tag) + 34 + 16 + 3 + 12] = dyn; + ++dyn; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55147.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55147.c new file mode 100644 index 000000000..5be02f11c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55147.c @@ -0,0 +1,25 @@ +/* PR target/55147 */ +/* { dg-do run } */ +/* { dg-options "-O1" } */ +/* { dg-additional-options "-march=i486" { target ia32 } } */ + +extern void abort (void); + +__attribute__((noclone, noinline)) unsigned int +foo (unsigned long long *p, int i) +{ + return __builtin_bswap64 (p[i]); +} + +int +main () +{ + unsigned long long p[64]; + int i; + for (i = 0; i < 64; i++) + p[i] = 0x123456789abcdef0ULL ^ (1ULL << i) ^ (1ULL << (63 - i)); + for (i = 0; i < 64; i++) + if (foo (p, i) != __builtin_bswap32 (p[i] >> 32)) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55151.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55151.c new file mode 100644 index 000000000..2bf68df4a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55151.c @@ -0,0 +1,13 @@ +/* PR rtl-optimization/55151 */ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-fPIC" } */ + +int a, b, c, d, e, f, g, h, i, j, k, l; +void f4 (void) +{ + __asm__ volatile ("":[a] "=r,m" (a),[b] "=r,m" (b),[c] "=r,m" (c), + [d] "=r,m" (d),[e] "=r,m" (e),[f] "=r,m" (f), + [g] "=r,m" (g),[h] "=r,m" (h),[i] "=r,m" (i), + [j] "=r,m" (j),[k] "=r,m" (k),[l] "=r,m" (l):"[a],m" (a), + "[j],m" (j), "[k],m" (k), "[l],m" (l)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55154.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55154.c new file mode 100644 index 000000000..2ed3f00ed --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55154.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -mcx16 -fpic -mcmodel=large -fno-split-wide-types" } */ + +__int128 i; + +void test () +{ + __sync_val_compare_and_swap (&i, i, i); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55247-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55247-2.c new file mode 100644 index 000000000..d91b504e6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55247-2.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-O2 -mx32 -mtune=generic -maddress-mode=long" } */ + +typedef unsigned int uint32_t; +typedef uint32_t Elf32_Word; +typedef uint32_t Elf32_Addr; +typedef struct { + Elf32_Word st_name; + Elf32_Addr st_value; + Elf32_Word st_size; + unsigned char st_other; +} Elf32_Sym; +typedef struct { + Elf32_Word r_info; +} +Elf32_Rela; +typedef struct { + union { + Elf32_Addr d_ptr; + } + d_un; +} Elf32_Dyn; +struct link_map { + Elf32_Dyn *l_info[34]; +}; +extern void symbind32 (Elf32_Sym *); +void +_dl_profile_fixup (struct link_map *l, Elf32_Word reloc_arg) +{ + const Elf32_Sym *const symtab = (const void *) l->l_info[6]->d_un.d_ptr; + const Elf32_Rela *const reloc = (const void *) (l->l_info[23]->d_un.d_ptr + reloc_arg * sizeof (Elf32_Rela)); + Elf32_Sym sym = symtab[(reloc->r_info) >> 8]; + symbind32 (&sym); +} + +/* { dg-final { scan-assembler-not "%xmm\[0-9\]" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55247.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55247.c new file mode 100644 index 000000000..6259ea4f7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55247.c @@ -0,0 +1,35 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-O2 -mno-sse -mno-mmx -mx32 -maddress-mode=long" } */ + +typedef unsigned int uint32_t; +typedef uint32_t Elf32_Word; +typedef uint32_t Elf32_Addr; +typedef struct { + Elf32_Word st_name; + Elf32_Addr st_value; + Elf32_Word st_size; + unsigned char st_other; +} Elf32_Sym; +typedef struct { + Elf32_Word r_info; +} +Elf32_Rela; +typedef struct { + union { + Elf32_Addr d_ptr; + } + d_un; +} Elf32_Dyn; +struct link_map { + Elf32_Dyn *l_info[34]; +}; +extern void symbind32 (Elf32_Sym *); +void +_dl_profile_fixup (struct link_map *l, Elf32_Word reloc_arg) +{ + const Elf32_Sym *const symtab = (const void *) l->l_info[6]->d_un.d_ptr; + const Elf32_Rela *const reloc = (const void *) (l->l_info[23]->d_un.d_ptr + reloc_arg * sizeof (Elf32_Rela)); + Elf32_Sym sym = symtab[(reloc->r_info) >> 8]; + symbind32 (&sym); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55277.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55277.c new file mode 100644 index 000000000..0bdcdc47f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55277.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O1" } */ + +int a, c; + +void f(long long p) +{ + long long b; + + if(b) + b = p ? : 0; + + for (; p; p++) + p *= a & (c = p *= !a < 2); + + a = b += !(b & 3740917449u); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55359.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55359.c new file mode 100644 index 000000000..222affc66 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55359.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ + +#include <x86intrin.h> + +__m128d +f (__m256d x) +{ + return *((__m128d*) ((double *) &x + 1)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55433.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55433.c new file mode 100644 index 000000000..b79b16dab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55433.c @@ -0,0 +1,12 @@ +/* { dg-do compile {target { *-*-darwin* } } } */ +/* { dg-options "-O1 -m32" } */ + +typedef unsigned long long tick_t; +extern int foo(void); +extern tick_t tick(void); +double test(void) { + struct { tick_t ticks; } st; + st.ticks = tick(); + foo(); + return (double)st.ticks; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55448.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55448.c new file mode 100644 index 000000000..874a5077f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55448.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx" } */ + +#include <immintrin.h> + +static inline __m256 add1(const __m256 *a, const __m256 *b) +{ + return _mm256_add_ps(*a, *b); +} + +void foo1(__m256 *a, const __m256 b) +{ + *a = add1(a, &b); +} + +static inline __m128 add2(const __m128 *a, const __m128 *b) +{ + return _mm_add_ps(*a, *b); +} + +void foo2(__m128 *a, const __m128 b) +{ + *a = add2(a, &b); +} + +/* { dg-final { scan-assembler-not "vmovups" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55458.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55458.c new file mode 100644 index 000000000..81d85ec8f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55458.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-fPIC" } */ + +int a, b, c; + +void +foo (void) +{ + asm volatile ("":"+m" (a), "+m" (b), "+m" (c)); /* { dg-error "operand has impossible constraints" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55512-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55512-1.c new file mode 100644 index 000000000..de88f60f0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55512-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +foo (int x) +{ + asm goto ("" : : "r" (x), "r" (x + 1), "r" (x + 2), "r" (x + 3), /* { dg-error "operand has impossible constraints" } */ + "r" (x + 4), "r" (x + 5), "r" (x + 6), "r" (x + 7), + "r" (x + 8), "r" (x + 9), "r" (x + 10), "r" (x + 11), + "r" (x + 12), "r" (x + 13), "r" (x + 14), "r" (x + 15) : : lab); + __builtin_unreachable (); + lab: + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55512-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55512-2.c new file mode 100644 index 000000000..114710c6d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55512-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +foo (int x) +{ + asm goto ("" : : "r" (x), "r" (x + 1), "r" (x + 2), "r" (x + 3), /* { dg-error "operand has impossible constraints" } */ + "r" (x + 4), "r" (x + 5), "r" (x + 6), "r" (x + 7), + "r" (x + 8), "r" (x + 9), "r" (x + 10), "r" (x + 11), + "r" (x + 12), "r" (x + 13), "r" (x + 14), "r" (x + 15) : : lab); + lab: + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55512-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55512-3.c new file mode 100644 index 000000000..2a351c3be --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55512-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +bar (int x) +{ + asm goto ("" : : "r" (x), "r" (x + 1), "r" (x + 2), "r" (x + 3), /* { dg-error "operand has impossible constraints" } */ + "r" (x + 4), "r" (x + 5), "r" (x + 6), "r" (x + 7), + "r" (x + 8), "r" (x + 9), "r" (x + 10), "r" (x + 11), + "r" (x + 12), "r" (x + 13), "r" (x + 14), "r" (x + 15), + "r" (x + 16) : : lab); + __builtin_unreachable (); + lab: + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55512-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55512-4.c new file mode 100644 index 000000000..250243afb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55512-4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +bar (int x) +{ + asm goto ("" : : "r" (x), "r" (x + 1), "r" (x + 2), "r" (x + 3), /* { dg-error "operand has impossible constraints" } */ + "r" (x + 4), "r" (x + 5), "r" (x + 6), "r" (x + 7), + "r" (x + 8), "r" (x + 9), "r" (x + 10), "r" (x + 11), + "r" (x + 12), "r" (x + 13), "r" (x + 14), "r" (x + 15), + "r" (x + 16) : : lab); + lab: + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55590-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55590-1.c new file mode 100644 index 000000000..a8dd91232 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55590-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx" } */ + +#include <immintrin.h> + +struct S +{ + __m128 a, b; +}; + +struct T +{ + int a; + struct S s; +}; + + +void foo (struct T *p, __m128 v) +{ + struct S s; + + s = p->s; + s.b = _mm_add_ps(s.b, v); + p->s = s; +} + +/* { dg-final { scan-assembler-not "vmovups" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55590-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55590-2.c new file mode 100644 index 000000000..afc0a6379 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55590-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx" } */ + +#include <immintrin.h> + +struct S +{ + __m128 a, b; +}; + +struct T +{ + int a; + struct S s[8]; +}; + + +void foo (struct T *p, int i, __m128 v) +{ + struct S s; + + s = p->s[i]; + s.b = _mm_add_ps(s.b, v); + p->s[i] = s; +} + +/* { dg-final { scan-assembler-not "vmovups" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55597.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55597.c new file mode 100644 index 000000000..0ed7a3a2e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55597.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -fPIC -mx32 -maddress-mode=long" } */ + +struct initial_sp +{ + void *sp; + int mask; +}; + +__thread struct initial_sp __morestack_initial_sp; + +void foo (int *); + +void __morestack_release_segments (void) +{ + foo (&__morestack_initial_sp.mask); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55672.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55672.c new file mode 100644 index 000000000..6f1c898c7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55672.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fstack-check=generic" } */ + +int main () +{ + int x[8]; + if (x[0] != 4) + __builtin_abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55686.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55686.c new file mode 100644 index 000000000..a263b08dd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55686.c @@ -0,0 +1,16 @@ +/* PR target/55686 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +foo (long x, long *y) +{ + long *a = y - 64, i; + for (i = 0; i < x; i++) + { + long v = y[i]; + *a++ = v; + } + register void **c __asm__ ("di"); + goto **c; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55775.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55775.c new file mode 100644 index 000000000..1902f6883 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55775.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +int *ptr; +int *fn1 (int *); +int fn2 (int, int); +int fn3 (void); +int fn4 (int); + +static int +foo (int x, int y, int z) +{ + int b; + asm ("" : "=a" (b), "=&d" (x) : "0" (y), "1" (x), "mr" (z)); + return x; +} + +static int +bar (int x, int y) +{ + int a; + if (!y) + { + for (a = 0; a <= (x >> 1); ) + ; + a = foo (y, fn2 (2, x), x); + if (x) + a = x; + return a; + } +} + +static int +baz (int x, int y) +{ + int *a = ptr; + int t, xk1 = fn3 (), xk = x * xk1; + for (t = 0; t < xk; t += xk1) + { + if (fn4 (a[2])) + return -y; + a = fn1 (a); + } + return 0; +} + +void +test (int x, long y, int z) +{ + int a = fn3 (); + int b; + int c = bar (x, z); + for (b = 0; b <= y; b++) + c = baz (x, c); + fn2 (c, a); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55829.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55829.c new file mode 100644 index 000000000..be70ba2f2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55829.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse3 -fno-expensive-optimizations" } */ + +typedef double __m128d __attribute__ ((__vector_size__ (16))); + +extern double p1[]; +extern double p2[]; +extern double ck[]; +extern int n; + +__attribute__((__noinline__, __noclone__)) int chk_pd (double *v1, double *v2) +{ + return v2[n] != v1[n]; +} + +static inline void sse3_test_movddup_reg_subsume_ldsd (double *i1, double *r) +{ + __m128d t1 = (__m128d){*i1, 0}; + __m128d t2 = __builtin_ia32_shufpd (t1, t1, 0); + __builtin_ia32_storeupd (r, t2); +} + +int sse3_test (void) +{ + int i = 0; + int fail = 0; + for (; i < 80; i += 1) + { + ck[0] = p1[0]; + fail += chk_pd (ck, p2); + sse3_test_movddup_reg_subsume_ldsd (p1, p2); + } + return fail; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55845.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55845.c new file mode 100644 index 000000000..daf04e54a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55845.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-O3 -ffast-math -fschedule-insns -mavx -mvzeroupper" } */ + +#include "avx-check.h" + +#define N 100 + +double +__attribute__((noinline)) +foo (int size, double *y, double *x) +{ + double sum = 0.0; + int i; + + for (i = 0; i < size; i++) + sum += y[i] * x[i]; + + return sum; +} + +static void +__attribute__ ((noinline)) +avx_test () +{ + double x[N], y[N]; + double s; + int i; + + for (i = 0; i < N; i++) + { + x[i] = i; + y[i] = i; + } + + s = foo (N, y, x); + + if (s != 328350.0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55934.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55934.c new file mode 100644 index 000000000..ea489559c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55934.c @@ -0,0 +1,11 @@ +/* PR inline-asm/55934 */ +/* { dg-do compile } */ +/* { dg-require-effective-target sse } */ +/* { dg-options "-std=c99 -msse" } */ +_Complex float +foo (void) +{ + _Complex float x; + __asm ("" : "=x" (x)); /* { dg-error "inconsistent .* constraint" } */ + return x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55981.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55981.c new file mode 100644 index 000000000..36498d63c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr55981.c @@ -0,0 +1,54 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2" } */ + +volatile int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p; + +volatile long long y; + +void +test () +{ + int a_ = a; + int b_ = b; + int c_ = c; + int d_ = d; + int e_ = e; + int f_ = f; + int g_ = g; + int h_ = h; + int i_ = i; + int j_ = j; + int k_ = k; + int l_ = l; + int m_ = m; + int n_ = n; + int o_ = o; + int p_ = p; + + int z; + + for (z = 0; z < 1000; z++) + { + __atomic_store_n (&y, 0x100000002ll, __ATOMIC_SEQ_CST); + __atomic_store_n (&y, 0x300000004ll, __ATOMIC_SEQ_CST); + } + + a = a_; + b = b_; + c = c_; + d = d_; + e = e_; + f = f_; + g = g_; + h = h_; + i = i_; + j = j_; + k = k_; + l = l_; + m = m_; + n = n_; + o = o_; + p = p_; +} + +/* { dg-final { scan-assembler-times "movabs" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56022.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56022.c new file mode 100644 index 000000000..db43162fb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56022.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx" } */ + +typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__)); +__attribute__((target("no-avx"))) static int currentImplementationSupported() +{} +__m256 foo0(__m256 a) {} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56028.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56028.c new file mode 100644 index 000000000..18ae25398 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56028.c @@ -0,0 +1,54 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2" } */ + +volatile int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p; + +volatile long long y; + +void +test () +{ + int a_ = a; + int b_ = b; + int c_ = c; + int d_ = d; + int e_ = e; + int f_ = f; + int g_ = g; + int h_ = h; + int i_ = i; + int j_ = j; + int k_ = k; + int l_ = l; + int m_ = m; + int n_ = n; + int o_ = o; + int p_ = p; + + int z; + + for (z = 0; z < 1000; z++) + { + y = 0x100000002ll; + y = 0x300000004ll; + } + + a = a_; + b = b_; + c = c_; + d = d_; + e = e_; + f = f_; + g = g_; + h = h_; + i = i_; + j = j_; + k = k_; + l = l_; + m = m_; + n = n_; + o = o_; + p = p_; +} + +/* { dg-final { scan-assembler-times "movabs" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56114.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56114.c new file mode 100644 index 000000000..43e62ae3b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56114.c @@ -0,0 +1,10 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -masm=intel" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target masm_intel } */ + +long +foo2 (void) +{ + return *(volatile int *) 0xFEE00000; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56148.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56148.c new file mode 100644 index 000000000..78d2efba1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56148.c @@ -0,0 +1,12 @@ +/* PR inline-asm/56148 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +foo (void) +{ + unsigned char e[16]; + unsigned long a, b, c, d; + __asm__ __volatile__ ("" : "=d" (a), "=&c" (c), "=&D" (d), "=&a" (b) + : "0" (-1U), "mr" (e), "1" (128 >> 5), "2" (e), "3" (-1U)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56151.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56151.c new file mode 100644 index 000000000..24a1b8ae4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56151.c @@ -0,0 +1,17 @@ +/* PR rtl-optimization/56151 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int vara, varb; + +void +foo (int i, int j) +{ + vara = varb | vara; +} + +/* Verify the above is compiled into movl varb, %reg; orl %reg, vara instead + of longer movl vara, %reg; orl varb, %reg; movl %reg, vara. */ +/* { dg-final { scan-assembler-not "mov\[^\n\r]*vara" { target nonpic } } } */ +/* { dg-final { scan-assembler-times "mov\[^\n\r]*varb" 1 { target nonpic } } } */ +/* { dg-final { scan-assembler-times "or\[^\n\r]*vara" 1 { target nonpic } } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56225.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56225.c new file mode 100644 index 000000000..638c0cef5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56225.c @@ -0,0 +1,12 @@ +/* PR target/56225 */ +/* { dg-do compile { target { ia32 } } } */ +/* { dg-options "-O2 -march=pentium3 -mtune=generic" } */ + +void bar (int); + +void +foo (int x, int y) +{ + __attribute__ ((vector_size (8 * sizeof (short)))) short s0 = { x }; + bar ((short) (long) &s0 + y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56246.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56246.c new file mode 100644 index 000000000..64a2527a5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56246.c @@ -0,0 +1,7 @@ +/* PR target/56225 */ +/* { dg-do compile { target { ia32 } } } */ +/* { dg-options "-O2 -fno-omit-frame-pointer -march=i686 -fpic" } */ + +void NoBarrier_AtomicExchange (long long *ptr) { + while (__sync_val_compare_and_swap (ptr, 1, 0) ); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56348.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56348.c new file mode 100644 index 000000000..af6382812 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56348.c @@ -0,0 +1,38 @@ +/* PR target/56348 */ +/* { dg-do compile { target { ia32 } } } */ +/* { dg-options "-O2 -fPIC -mfpmath=sse -msse2" } */ + +typedef unsigned int size_t; + +extern double fabs (double __x) __attribute__ ((__nothrow__, __leaf__)) + __attribute__ ((__const__)); + +typedef struct cholmod_sparse_struct +{ + size_t ncol; + void *p; +} cholmod_sparse; + +int cholmod_l_reallocate_sparse (size_t, cholmod_sparse *, void *); + +int +cholmod_l_drop (double tol, cholmod_sparse * A) +{ + double aij; + double *Ax; + long long *Ap, *Ai, *Anz; + long long packed, i, j, nrow, ncol, p, pend, nz, values; + Ap = A->p; + ncol = A->ncol; + nz = 0; + for (j = 0; j < ncol; j++) + for (; p < pend; p++) + { + i = Ai[p]; + aij = Ax[p]; + if (i <= j && (fabs (aij) > tol || ((aij) != (aij)))) + nz++; + } + Ap[ncol] = nz; + cholmod_l_reallocate_sparse (nz, A, 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56560.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56560.c new file mode 100644 index 000000000..5417cbdde --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56560.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx -mvzeroupper -dp" } */ + +extern void abort (void); + +typedef double vec_t __attribute__((vector_size(32))); + +struct S { int i1; int i2; int i3; }; + +extern int bar (vec_t, int, int, int, int, int, struct S); + +void foo (vec_t v, struct S s) +{ + int i = bar (v, 1, 2, 3, 4, 5, s); + if (i == 0) + abort (); +} + +/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56866.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56866.c new file mode 100644 index 000000000..fbd151745 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56866.c @@ -0,0 +1,16 @@ +/* PR target/56866 */ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O3 -mxop" } */ + +#define main xop_test_main +#include "../../gcc.c-torture/execute/pr56866.c" +#undef main + +#include "xop-check.h" + +static void +xop_test (void) +{ + xop_test_main (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56903.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56903.c new file mode 100644 index 000000000..9e6a1c391 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr56903.c @@ -0,0 +1,18 @@ +/* PR rtl-optimization/56903 */ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ +/* { dg-additional-options "-march=pentium3" { target ia32 } } */ + +int a, *b, c; +struct S { int s : 1; } *fn1 (void); +extern int fn3 (void), fn4 (int *); + +void +fn2 (void) +{ + int e = fn3 (); + char f = c + fn1 ()->s * 4; + if (*b && f == e) + a = *b; + fn4 (b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57003.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57003.c new file mode 100644 index 000000000..dfa6b8b50 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57003.c @@ -0,0 +1,54 @@ +/* PR rtl-optimization/57003 */ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#define N 2001 +unsigned short *b, *c, *d; + +__attribute__ ((noinline, noclone)) unsigned +bar (void) +{ + asm volatile ("" : : : "memory"); + return N; +} + +__attribute__ ((noinline, noclone)) unsigned short * +baz (unsigned long x) +{ + if (x != N * sizeof (unsigned short) + 20) + __builtin_abort (); + asm volatile ("" : : : "memory"); + return d; +} + +__attribute__ ((ms_abi, noinline, noclone)) +foo (void) +{ + unsigned d; + unsigned short *e; + if ((d = bar ())) + { + e = baz (d * sizeof (unsigned short) + 20); + __builtin_memcpy (e, b, d * sizeof (unsigned short)); + c = e; + } +} + +int +main () +{ + unsigned short a[2 * N]; + int i; + for (i = 0; i < 2 * N; i++) + a[i] = i + 1; + b = a; + d = a + N; + asm volatile ("" : : : "memory"); + foo (); + for (i = 0; i < N; i++) + if (a[i] != i + 1 || a[i + N] != i + 1) + __builtin_abort (); + if (c != a + N) + __builtin_abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57018.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57018.c new file mode 100644 index 000000000..fb0d849ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57018.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-Os -fomit-frame-pointer -fno-asynchronous-unwind-tables" } */ +/* { dg-additional-options "-march=i686" { target ia32 } } */ + +struct A { char a[16]; } a; + +void __attribute__((noinline, noclone)) +foo (struct A b) +{ + if (__builtin_memcmp (b.a, "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0", 16)) + __builtin_abort (); + asm volatile ("" : : : "memory"); +} + +void __attribute__((noinline, noclone)) +bar (struct A b) +{ + foo (a); + a = b; +} + +int +main () +{ + struct A b = { "\0\1\2\3\4\5\6\7\10\11\12\13\14\15\16\17" }; + bar (b); + if (__builtin_memcmp (a.a, b.a, 16)) + __builtin_abort (); + return 0; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57046.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57046.c new file mode 100644 index 000000000..0aa43f9df --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57046.c @@ -0,0 +1,77 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +struct emac { + unsigned reg[23]; +}; + +struct mop { + unsigned long long addr; + unsigned int size; +}; + +unsigned int __attribute__((__noinline__)) +level(const struct emac *obj) +{ + return 0; +} + +void __attribute__((__noinline__)) +info(struct emac *dev, unsigned long long addr) +{ + asm("" : : : "memory"); +} + +unsigned long long __attribute__((__noinline__)) +get_value(const struct mop *mop) +{ + return 0x1234567890abcdefull; +} + +int __attribute__((__noinline__)) +emac_operation(struct emac *obj, struct mop *mop) +{ + unsigned long long addr = mop->addr; + int index = addr >> 2; + unsigned int value, old_value; + + if (mop->size != 4) + return 0; + + if (index >= 23) { + if (level(obj) >= 1) + info(obj, addr); + return 0; + } + + value = get_value(mop); + old_value = obj->reg[index]; + + info(obj, 0); + + switch (index) { + case 0: + obj->reg[0] = old_value; + break; + case 7: + case 8: + obj->reg[index] = value; + break; + } + + return 0; +} + +int main(void) +{ + struct emac e = { { 0 } }; + struct mop mop = { 32, 4 }; + + e.reg[8] = 0xdeadbeef; + emac_operation(&e, &mop); + + if (e.reg[8] != 0x90abcdef) + __builtin_abort(); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57091.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57091.c new file mode 100644 index 000000000..4fc7ed769 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57091.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcmodel=large" { target lp64 } } */ +void (*bar)(); + +void foo (void) +{ + bar (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57097.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57097.c new file mode 100644 index 000000000..2f0093840 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57097.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fPIC" } */ +extern double ad[], bd[], cd[], dd[]; +extern long long all[], bll[], cll[], dll[]; + +int +main (int i, char **a) +{ + bd[i] = i + 64; + if (i % 3 == 0) + { + cd[i] = i; + } + dd[i] = i / 2; + ad[i] = i * 2; + if (i % 3 == 1) + { + dll[i] = 127; + } + dll[i] = i; + cll[i] = i * 2; + switch (i % 3) + { + case 0: + bll[i] = i + 64; + } + all[i] = i / 2; + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57098.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57098.c new file mode 100644 index 000000000..37598d7ce --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57098.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-msse4 -mcmodel=large" } */ + +typedef int V __attribute__((vector_size(16))); + +void foo (V *p, V *mask) +{ + *p = __builtin_shuffle (*p, *mask); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57106.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57106.c new file mode 100644 index 000000000..6fccd8aac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57106.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fschedule-insns -funroll-all-loops -fcompare-debug" } */ + +typedef void block128_f (int *, int); + +void +foo (int *out, int *iv, block128_f block) +{ + while (1) + { + *out = *out ^ *iv; + block (out, *out); + iv = out; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57264.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57264.c new file mode 100644 index 000000000..46fce7f04 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr57264.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -mcld" } */ + +void test (int x, int **pp) +{ + while (x) + { + int *ip = *pp; + int *op = *pp; + while (*ip) + { + int v = *ip++; + *op++ = v + 1; + } + } +} + +/* { dg-final { scan-assembler-not "stosl" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr9771-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr9771-1.c new file mode 100644 index 000000000..38586fe97 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/pr9771-1.c @@ -0,0 +1,53 @@ +/* PR rtl-optimization/9771 */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -fomit-frame-pointer -ffixed-ebp" } */ + +extern void abort(void); +extern void exit(int); + +register long *B asm ("ebp"); + +long x = 10; +long y = 20; + +void bar(void) +{ + B = &y; +} + +void foo() +{ + long *adr = B; + long save = *adr; + + *adr = 123; + + bar(); + + *adr = save; +} + +/* This must not be inlined becuase main() requires the frame pointer + for stack alignment. */ +void test(void) __attribute__((noinline)); +void test(void) +{ + B = &x; + + foo(); + + if (x != 10 || y != 20) + abort(); + + /* We can't return, as our caller may assume %ebp is preserved! */ + /* We could save/restore it (like foo), but its easier to exit. */ + exit(0); +} + +int main() +{ + test(); + return 0; + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/prefetchw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/prefetchw-1.c new file mode 100644 index 000000000..d0babe4d1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/prefetchw-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mprfchw -O2" } */ +/* { dg-final { scan-assembler "\[ \\t\]+prefetchw\[ \\t\]+" } } */ + +#include <x86intrin.h> + +void *p; + +void extern +prefetchw__test (void) +{ + _m_prefetchw (p); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/quad-sse.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/quad-sse.c new file mode 100644 index 000000000..4b6fe7925 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/quad-sse.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +__float128 x, y; + +__float128 test_1(void) +{ + return -x; +} + +__float128 test_2(void) +{ + return __builtin_fabsq (x); +} + +__float128 test_3(void) +{ + return __builtin_copysignq (x, y); +} + +/* { dg-final { scan-assembler-not "call.*(neg|fabs|copysign)" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdfsbase-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdfsbase-1.c new file mode 100644 index 000000000..2ed33cd47 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdfsbase-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "rdfsbase\[ \t]+(%|)eax" } } */ + +#include <immintrin.h> + +unsigned int +read_fs_base32 (void) +{ + return _readfsbase_u32 (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdfsbase-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdfsbase-2.c new file mode 100644 index 000000000..f319cea57 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdfsbase-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "rdfsbase\[ \t]+(%|)rax" } } */ + +#include <immintrin.h> + +unsigned long long +read_fs_base64 (void) +{ + return _readfsbase_u64 (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdgsbase-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdgsbase-1.c new file mode 100644 index 000000000..cb2a3d581 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdgsbase-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "rdgsbase\[ \t]+(%|)eax" } } */ + +#include <immintrin.h> + +unsigned int +read_gs_base32 (void) +{ + return _readgsbase_u32 (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdgsbase-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdgsbase-2.c new file mode 100644 index 000000000..d514cd961 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdgsbase-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "rdgsbase\[ \t]+(%|)rax" } } */ + +#include <immintrin.h> + +unsigned long long +read_gs_base64 (void) +{ + return _readgsbase_u64 (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdrand-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdrand-1.c new file mode 100644 index 000000000..beec9f1b8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdrand-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mrdrnd -dp" } */ +/* { dg-final { scan-assembler-times "rdrandhi_1" 1 } } */ +/* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */ + +#include <immintrin.h> + +int +foo (unsigned short *x) +{ + return _rdrand16_step (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdrand-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdrand-2.c new file mode 100644 index 000000000..ea8e90649 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdrand-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mrdrnd -dp" } */ +/* { dg-final { scan-assembler-times "rdrandsi_1" 1 } } */ +/* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */ + +#include <immintrin.h> + +int +foo (unsigned int *x) +{ + return _rdrand32_step (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdrand-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdrand-3.c new file mode 100644 index 000000000..de0e730ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdrand-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mrdrnd -dp" } */ +/* { dg-final { scan-assembler-times "rdranddi_1" 1 } } */ +/* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */ + +#include <immintrin.h> + +int +foo (unsigned long long *x) +{ + return _rdrand64_step (x); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdseed16-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdseed16-1.c new file mode 100644 index 000000000..fe637f1ac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdseed16-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mrdseed -O2" } */ +/* { dg-final { scan-assembler "rdseed\[ \\t\]+" } } */ + +#include <x86intrin.h> + +void extern +rdseed_test (unsigned short *p) +{ + volatile int r; + r = _rdseed16_step (p); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdseed32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdseed32-1.c new file mode 100644 index 000000000..646dff26d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdseed32-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-mrdseed -O2" } */ +/* { dg-final { scan-assembler "rdseed\[ \\t\]+" } } */ + +#include <x86intrin.h> + +void extern +rdseed_test (unsigned int *p) +{ + volatile int r; + r = _rdseed32_step (p); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdseed64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdseed64-1.c new file mode 100644 index 000000000..bdacd7ad6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rdseed64-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mrdseed -O2" } */ +/* { dg-final { scan-assembler "rdseed\[ \\t\]+" } } */ + +#include <x86intrin.h> + +void extern +rdseed_test (unsigned long long *p) +{ + volatile int r; + r = _rdseed64_step (p); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-divf.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-divf.c new file mode 100644 index 000000000..b4447d33a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-divf.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */ + +float t1(float a, float b) +{ + return a / b; +} + +/* { dg-final { scan-assembler "rcpss" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-sqrtf.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-sqrtf.c new file mode 100644 index 000000000..859d2180a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-sqrtf.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */ + +extern float sqrtf (float); + +float t1(float a, float b) +{ + return a/sqrtf(b); +} + +float t2(float a, float b) +{ + return sqrtf(a/b); +} + +float t3(float a) +{ + return sqrtf(a); +} + +/* { dg-final { scan-assembler-times "rsqrtss" 3 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-vec-divf-avx.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-vec-divf-avx.c new file mode 100644 index 000000000..8aeec20d5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-vec-divf-avx.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx -mtune=generic -mfpmath=sse -mrecip" } */ + +float a[32]; +float b[32]; +float r[32]; + +void t1(void) +{ + int i; + + for (i = 0; i < 32; i++) + r[i] = a[i] / b[i]; +} + +/* { dg-final { scan-assembler "vrcpps\[ \\t\]+\[^\n\]*%ymm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-vec-divf.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-vec-divf.c new file mode 100644 index 000000000..fa126e45f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-vec-divf.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip -fno-common" } */ + +float a[4]; +float b[4]; +float r[4]; + +void t1(void) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = a[i] / b[i]; +} + +/* { dg-final { scan-assembler "rcpps" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c new file mode 100644 index 000000000..9cf3cc81b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx -mtune=generic -mfpmath=sse -mrecip" } */ + +float a[32]; +float b[32]; +float r[32]; + +extern float sqrtf (float); + +void t1(void) +{ + int i; + + for (i = 0; i < 32; i++) + r[i] = a[i] / sqrtf (b[i]); +} + +void t2(void) +{ + int i; + + for (i = 0; i < 32; i++) + r[i] = sqrtf (a[i] / b[i]); +} + +void t3(void) +{ + int i; + + for (i = 0; i < 32; i++) + r[i] = sqrtf (a[i]); +} + +/* { dg-final { scan-assembler-times "vrsqrtps\[ \\t\]+\[^\n\]*%ymm" 3 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c new file mode 100644 index 000000000..6c0d49b22 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip -fno-common" } */ + +float a[4]; +float b[4]; +float r[4]; + +extern float sqrtf (float); + +void t1(void) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = a[i] / sqrtf (b[i]); +} + +void t2(void) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = sqrtf (a[i] / b[i]); +} + +void t3(void) +{ + int i; + + for (i = 0; i < 4; i++) + r[i] = sqrtf (a[i]); +} + +/* { dg-final { scan-assembler-times "rsqrtps" 3 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/regparm-stdcall.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/regparm-stdcall.c new file mode 100644 index 000000000..fbb3be549 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/regparm-stdcall.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-options -mpreferred-stack-boundary=4 } */ +/* { dg-require-effective-target ia32 } */ + +extern void abort(void); + +void __attribute__((regparm(2), stdcall)) foo(int i, int j, float x) +{ + static int last_align = -1; + int dummy, align = (int)&dummy & 15; + if (last_align < 0) + last_align = align; + else if (align != last_align) + abort (); +} + +int main() +{ + foo(0,0,0.0); + foo(0,0,0.0); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/regparm.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/regparm.c new file mode 100644 index 000000000..4cfd11020 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/regparm.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-W -Wall" } */ + +/* Verify that GCC correctly detects non-matching regparm attributes. */ +int __attribute__((regparm(3))) f (void); /* { dg-message "note: previous" } */ + +int __attribute__((regparm(2))) f (void) { /* { dg-error "conflicting" } */ + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/reload-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/reload-1.c new file mode 100644 index 000000000..9c6cd3222 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/reload-1.c @@ -0,0 +1,115 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O3 -msse2 -fdump-rtl-csa" } */ +/* { dg-skip-if "no stdint" { vxworks_kernel } } */ + +#include <emmintrin.h> +#include <stdint.h> + +typedef __SIZE_TYPE__ size_t; +typedef float vFloat __attribute__ ((__vector_size__ (16))); +typedef double vDouble __attribute__ ((__vector_size__ (16))); +typedef struct buf +{ + void *data; + unsigned long h; + unsigned long w; + size_t bytes; +} buf; + +typedef struct job +{ + struct Job *next; + void * info; + long (*func)(struct Job *job); + long error; +} job; + +typedef struct fj +{ + job hd; + buf src; + buf dest; + float g; + unsigned int flags; +} fj; + +static const double r[256], t[256]; + +long bar (const buf *src, const buf *dest, float g, unsigned int flags) +{ + float *d0 = (float*) src->data; + float *d1 = (float*) dest->data; + uintptr_t w = dest->w; + uintptr_t idx; + vFloat p0; + static const vFloat m0; + static const vDouble p[3], m, b; + float *sr = d0; + float *dr = d1; + for( idx = 0; idx + 8 <= w; idx += 8 ) + { + vFloat f0 = _mm_loadu_ps (sr); + vFloat f1 = _mm_loadu_ps (sr + 4); + sr += 8; + vFloat fa0 = _mm_andnot_ps (m0, f0); + vFloat fa1 = _mm_andnot_ps (m0, f1); + vDouble v0 = _mm_cvtps_pd (fa0); + vDouble v1 = _mm_cvtps_pd (_mm_movehl_ps (fa0, fa0)); + vDouble v2 = _mm_cvtps_pd (fa1); + vDouble v3 = _mm_cvtps_pd (_mm_movehl_ps (fa1, fa1)); + vDouble vi0, vi1, vi2, vi3; + __m128i b0, b1, b2, b3; + b0 = _mm_packs_epi32 (_mm_packs_epi32 (b0, b1), _mm_packs_epi32 (b2, b3)); + b1 = _mm_srli_epi64 (b0, 32); + unsigned int i0 = _mm_cvtsi128_si32 (b0); + unsigned int i2 = _mm_cvtsi128_si32 (b1); + v0 -= _mm_loadh_pd (_mm_load_sd (r + (i0 & 0xff)), r + (i0 >> 16)); + v1 -= _mm_loadh_pd (_mm_load_sd (r + (i2 & 0xff)), r + (i2 >> 16)); + b0 = _mm_unpackhi_epi64 (b0, b0); + b1 = _mm_unpackhi_epi64 (b1, b1); + unsigned int i4 = _mm_cvtsi128_si32 (b0); + unsigned int i6 = _mm_cvtsi128_si32 (b1); + v2 -= _mm_loadh_pd (_mm_load_sd (r + (i4 & 0xff)), r + (i4 >> 16)); + v3 -= _mm_loadh_pd (_mm_load_sd (r + (i6 & 0xff)), r + (i6 >> 16)); + v0 = p[0] + (p[1] + p[2] * v0) * v0; + v1 = p[0] + (p[1] + p[2] * v1) * v1; + v2 = p[0] + (p[1] + p[2] * v2) * v2; + v3 = p[0] + (p[1] + p[2] * v3) * v3; + vi0 = (vDouble) _mm_slli_epi64 ((__m128i)((vi0 + b) + m), 52); + vi1 = (vDouble) _mm_slli_epi64 ((__m128i)((vi1 + b) + m), 52); + vi2 = (vDouble) _mm_slli_epi64 ((__m128i)((vi2 + b) + m), 52); + vi3 = (vDouble) _mm_slli_epi64 ((__m128i)((vi3 + b) + m), 52); + vi0 *= _mm_loadh_pd (_mm_load_sd (t + (i0 & 0xff)), t + (i0 >> 16)); + vi1 *= _mm_loadh_pd (_mm_load_sd (t + (i2 & 0xff)), t + (i2 >> 16)); + vi2 *= _mm_loadh_pd (_mm_load_sd (t + (i4 & 0xff)), t + (i4 >> 16)); + vi3 *= _mm_loadh_pd (_mm_load_sd (t + (i6 & 0xff)), t + (i6 >> 16)); + v0 *= vi0; + v1 *= vi1; + v2 *= vi2; + v3 *= vi3; + vFloat r0 = _mm_movelh_ps (_mm_cvtpd_ps( v0 ), _mm_cvtpd_ps (v1)); + vFloat r1 = _mm_movelh_ps (_mm_cvtpd_ps( v2 ), _mm_cvtpd_ps (v3)); + vFloat z0 = _mm_cmpeq_ps (f0, _mm_setzero_ps()); + vFloat z1 = _mm_cmpeq_ps (f1, _mm_setzero_ps()); + r0 = _mm_andnot_ps (z0, r0); + r1 = _mm_andnot_ps (z1, r1); + z0 = _mm_and_ps (z0, p0); + z1 = _mm_and_ps (z1, p0); + r0 = _mm_or_ps (r0, z0); + r1 = _mm_or_ps (r1, z1); + _mm_storeu_ps (dr, r0); + _mm_storeu_ps (dr + 4, r1); + dr += 8; + } + return 0; +} + +long foo (job *j ) +{ + fj *jd = (fj*) j; + return bar (&jd->src, &jd->dest, jd->g, jd->flags); +} + +/* { dg-final { scan-rtl-dump-not "deleted 1 dead insns" "csa" } } */ +/* { dg-final { cleanup-rtl-dump "csa" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/retarg.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/retarg.c new file mode 100644 index 000000000..a69b60fea --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/retarg.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +#include <string.h> + +void *p (void *x, void *y, int z) +{ + memcpy (x, y, z); + return x; +} + +/* { dg-final { scan-assembler-not "%\[re\]di" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rotate-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rotate-1.c new file mode 100644 index 000000000..23dc2ee67 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rotate-1.c @@ -0,0 +1,16 @@ +/* Verify that rolb instruction is emitted on IA-32/x86-64. */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void foo (unsigned char *); + +int +main (void) +{ + unsigned char c = 0; + foo (&c); + c = c >> 1 | c << 7; + return c; +} + +/* { dg-final { scan-assembler "rolb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rotate-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rotate-2.c new file mode 100644 index 000000000..71fd7edbd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rotate-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2" } */ + +typedef unsigned int UTItype __attribute__ ((mode (TI))); + +void foo (UTItype *); + +UTItype +test (void) +{ + UTItype c = 0; + foo (&c); + c = c >> 5 | c << 123; + return c; +} +/* { dg-final { scan-assembler-times "shrdq" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-check.h new file mode 100644 index 000000000..593b40391 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-check.h @@ -0,0 +1,32 @@ +#include <stdlib.h> +#include "cpuid.h" + +static void rtm_test (void); + +static void __attribute__ ((noinline)) do_test (void) +{ + rtm_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (__get_cpuid_max (0, NULL) >= 7) + { + __cpuid_count (7, 0, eax, ebx, ecx, edx); + if (ebx & bit_RTM) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + return 0; + } + } +#ifdef DEBUG + printf ("SKIPPED\n"); +#endif + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-xabort-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-xabort-1.c new file mode 100644 index 000000000..808095d27 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-xabort-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-mrtm" } */ +/* { dg-final { scan-assembler "\txabort" } } */ + +#include <immintrin.h> + +void +rtm_test (void) +{ + _xabort (13); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-xbegin-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-xbegin-1.c new file mode 100644 index 000000000..caced5f5f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-xbegin-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-mrtm" } */ +/* { dg-final { scan-assembler "\txbegin" } } */ + +#include <immintrin.h> + +unsigned int +rtm_test (void) +{ + return _xbegin (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-xend-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-xend-1.c new file mode 100644 index 000000000..2bd8a0a9c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-xend-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-mrtm" } */ +/* { dg-final { scan-assembler "\txend" } } */ + +#include <immintrin.h> + +void +rtm_test (void) +{ + _xend (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-xtest-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-xtest-1.c new file mode 100644 index 000000000..cdf346fcb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/rtm-xtest-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-mrtm -dp" } */ +/* { dg-final { scan-assembler "\txtest" } } */ + +#include <immintrin.h> + +int +rtm_xtest (void) +{ + return _xtest (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v16qi-1.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v16qi-1.h new file mode 100644 index 000000000..79556e874 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v16qi-1.h @@ -0,0 +1,30 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include CHECK_H + +static __m128i +__attribute__((noinline)) +foo (char *v) +{ + return _mm_set_epi8 (v[15], v[14], v[13], v[12], + v[11], v[10], v[9], v[8], + v[7], v[6], v[5], v[4], + v[3], v[2], v[1], v[0]); +} + +static void +TEST (void) +{ + char v[16] = + { + -3, 60, 48, 104, -90, 37, -48, 78, + 4, 33, 81, 4, -89, 17, 8, 68 + }; + union128i_b u; + + u.x = foo (v); + if (check_union128i_b (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v16qi-2.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v16qi-2.h new file mode 100644 index 000000000..9768806c5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v16qi-2.h @@ -0,0 +1,30 @@ +#include CHECK_H + +static __m128i +__attribute__((noinline)) +foo (char x1, char x2, char x3, char x4, + char x5, char x6, char x7, char x8, + char x9, char x10, char x11, char x12, + char x13, char x14, char x15, char x16) +{ + return _mm_set_epi8 (x1, x2, x3, x4, x5, x6, x7, x8, + x9, x10, x11, x12, x13, x14, x15, x16); +} + +static void +TEST (void) +{ + char v[16] = + { + -3, 60, 48, 104, -90, 37, -48, 78, + 4, 33, 81, 4, -89, 17, 8, 68 + }; + union128i_b u; + + u.x = foo (v[15], v[14], v[13], v[12], + v[11], v[10], v[9], v[8], + v[7], v[6], v[5], v[4], + v[3], v[2], v[1], v[0]); + if (check_union128i_b (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v16qi-3.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v16qi-3.h new file mode 100644 index 000000000..faf3cd344 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v16qi-3.h @@ -0,0 +1,63 @@ +#include CHECK_H + +static __m128i +__attribute__((noinline)) +foo (char x, int i) +{ + switch (i) + { + case 15: + return _mm_set_epi8 (x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 14: + return _mm_set_epi8 (1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 13: + return _mm_set_epi8 (1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 12: + return _mm_set_epi8 (1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 11: + return _mm_set_epi8 (1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 10: + return _mm_set_epi8 (1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 9: + return _mm_set_epi8 (1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1); + case 8: + return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1); + case 7: + return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1); + case 6: + return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1); + case 5: + return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1); + case 4: + return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1); + case 3: + return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1); + case 2: + return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1); + case 1: + return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1); + case 0: + return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x); + default: + abort (); + } +} + +static void +TEST (void) +{ + char e = 0x13; + char v[16]; + union128i_b u; + int i, j; + + for (i = 0; i < ARRAY_SIZE (v); i++) + { + for (j = 0; j < ARRAY_SIZE (v); j++) + v[j] = 1; + v[i] = e; + u.x = foo (e, i); + if (check_union128i_b (u, v)) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v8hi-1.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v8hi-1.h new file mode 100644 index 000000000..87762b82e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v8hi-1.h @@ -0,0 +1,19 @@ +#include CHECK_H + +static __m128i +__attribute__((noinline)) +foo (short *v) +{ + return _mm_set_epi16 (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]); +} + +static void +TEST (void) +{ + short v[8] = { -3, 6000, 48, 104, -90, 34567, -1248, 34678 }; + union128i_w u; + + u.x = foo (v); + if (check_union128i_w (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v8hi-2.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v8hi-2.h new file mode 100644 index 000000000..835e7b4d6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/set-v8hi-2.h @@ -0,0 +1,21 @@ +#include CHECK_H + +__m128i +__attribute__((noinline)) +foo (short x1, short x2, short x3, short x4, + short x5, short x6, short x7, short x8) +{ + return _mm_set_epi16 (x1, x2, x3, x4, x5, x6, x7, x8); +} + +static void +TEST (void) +{ + short v[8] = { -3, 2, 1, 9, 23, -173, -13, 69 }; + union128i_w u; + + u.x = foo (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]); + + if (check_union128i_w (u, v)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/shift_mask.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/shift_mask.c new file mode 100644 index 000000000..29c84bd1d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/shift_mask.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int test_sal (int a, int c) +{ + return a << (c & 0x1f); +} + +int test_sar (int a, int c) +{ + return a >> (c & 0x1f); +} + +unsigned int test_shr (unsigned int a, int c) +{ + return a >> (c & 0x1f); +} + +unsigned int test_rol (unsigned int a, int c) +{ + int z = c & 0x1f; + return (a << z) | (a >> (32 - z)); +} + +unsigned int test_ror (unsigned int a, int c) +{ + int z = c & 0x1f; + return (a >> z) | (a << (32 - z)); +} + +/* { dg-final { scan-assembler-not "and" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/shuf-concat.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/shuf-concat.c new file mode 100644 index 000000000..04ed4a9db --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/shuf-concat.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O -msse2 -mfpmath=sse" } */ + +typedef double v2df __attribute__ ((__vector_size__ (16))); + +v2df f(double d,double e){ + v2df x={-d,d}; + v2df y={-e,e}; + return __builtin_ia32_shufpd(x,y,1); +} + +/* { dg-final { scan-assembler-not "\tv?shufpd\[ \t\]" } } */ +/* { dg-final { scan-assembler-times "\tv?unpcklpd\[ \t\]" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sibcall-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sibcall-5.c new file mode 100644 index 000000000..7cf67dbe1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sibcall-5.c @@ -0,0 +1,44 @@ +/* Check that indirect sibcalls understand regparm. */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2" } */ + +extern void abort (void); + +int (*f)(int, int) __attribute__((regparm(2))); +int (*g)(int, int, int) __attribute__((regparm(3))); + +int __attribute__((noinline)) +foo(void) +{ + return f(1, 2); +} + +int __attribute__((noinline)) +bar(void) +{ + return g(1, 2, 3); +} + +int __attribute__((regparm(2))) +f1(int x, int y) +{ + return x*3 + y; +} + +int __attribute__((regparm(3))) +g1(int x, int y, int z) +{ + return x*9 + y*3 + z; +} + +int main() +{ + f = f1; + g = g1; + if (foo() != 1*3 + 2) + abort (); + if (bar() != 1*9 + 2*3 + 3) + abort (); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/signbit-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/signbit-1.c new file mode 100644 index 000000000..3f31f5e2d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/signbit-1.c @@ -0,0 +1,29 @@ +/* PR optimization/8746 */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O1 -mtune=i586" } */ + +extern void abort (void); + +unsigned char r0; + +int foo(int x) +{ + unsigned char r = x&0xf0; + + if (!(r&0x80)) + { + r0 = r; + return 0; + } + else + return 1; +} + +int main(void) +{ + if (foo(0x80) != 1) + abort(); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/signbit-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/signbit-2.c new file mode 100644 index 000000000..bc8e4f824 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/signbit-2.c @@ -0,0 +1,29 @@ +/* PR optimization/8746 */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O1 -mtune=i586" } */ + +extern void abort (void); + +unsigned short r0; + +int foo(int x) +{ + unsigned short r = x&0xf000; + + if (!(r&0x8000)) + { + r0 = r; + return 0; + } + else + return 1; +} + +int main(void) +{ + if (foo(0x8000) != 1) + abort(); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/signbit-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/signbit-3.c new file mode 100644 index 000000000..8f1de5129 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/signbit-3.c @@ -0,0 +1,33 @@ +/* PR optimization/8746 */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O1 -mtune=i586" } */ + +extern void abort (void); + +volatile int j; + +void f0() { j=0; } +void f1() { j=1; } + +int foo(int x) +{ + if ((short int)(x&0x8000) > (short int)0) + { + f0(); + return 0; + } + else + { + f1(); + return 1; + } +} + +int main(void) +{ + if (foo(0x8000) != 1) + abort(); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-1.c new file mode 100644 index 000000000..afae22d37 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-1.c @@ -0,0 +1,25 @@ +/* PR 12902 */ +/* { dg-do compile } */ +/* { dg-options "-O1 -msse" } */ + +#include <xmmintrin.h> + +typedef union +{ + int i[4]; + float f[4]; + __m128 v; +} vector4_t; + +void +swizzle (const void *a, vector4_t * b, vector4_t * c) +{ + b->v = _mm_loadl_pi (b->v, (__m64 *) a); + c->v = _mm_loadl_pi (c->v, ((__m64 *) a) + 1); +} + +/* While one legal rendering of each statement would be movaps;movlps;movaps, + we can implmenent this with just movlps;movlps. Since we do now, anything + less would be a regression. */ +/* { dg-final { scan-assembler-not "movaps" } } */ +/* { dg-final { scan-assembler "movlps" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-10.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-10.c new file mode 100644 index 000000000..798551db2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-10.c @@ -0,0 +1,32 @@ +/* PR 17930 */ +/* { dg-do run } */ +/* { dg-options "-O1 -msse2 -mfpmath=sse -mno-accumulate-outgoing-args -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer" } */ +/* { dg-options "-O1 -msse2 -mfpmath=sse -fno-omit-frame-pointer" { target *-*-mingw* *-*-cygwin* } } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +typedef _Complex double complex_16; + +void __attribute__((noinline)) +test (complex_16 a[5][5]) +{ + int i, j, k; + complex_16 x; + + for (j = 0; j < 5; j++) + for (i = 0; i < 5; i++) + { + for (k = 0; k < j - 1; ++k) + x = a[k][i] * ~a[k][j]; + a[j][i] = x; + } +} + +static void +sse2_test (void) +{ + static complex_16 work[5][5]; + + test (work); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-11.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-11.c new file mode 100644 index 000000000..c764c0be5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-11.c @@ -0,0 +1,75 @@ +/* PR rtl-optimization/21239 */ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <emmintrin.h> + +void +foo (unsigned int x, double *y, const double *z) +{ + __m128d tmp; + while (x) + { + tmp = _mm_load_sd (z); + _mm_store_sd (y, tmp); + --x; ++z; ++y; + } +} + +void +bar (unsigned int x, float *y, const float *z) +{ + __m128 tmp; + unsigned int i; + for (i = 0; i < x; ++i) + { + tmp = (__m128) { *z, 0, 0, 0 }; + *y = __builtin_ia32_vec_ext_v4sf (tmp, 0); + ++z; ++y; + } + for (i = 0; i < x; ++i) + { + tmp = (__m128) { 0, *z, 0, 0 }; + *y = __builtin_ia32_vec_ext_v4sf (tmp, 1); + ++z; ++y; + } + for (i = 0; i < x; ++i) + { + tmp = (__m128) { 0, 0, *z, 0 }; + *y = __builtin_ia32_vec_ext_v4sf (tmp, 2); + ++z; ++y; + } + for (i = 0; i < x; ++i) + { + tmp = (__m128) { 0, 0, 0, *z }; + *y = __builtin_ia32_vec_ext_v4sf (tmp, 3); + ++z; ++y; + } +} + +static void +sse2_test (void) +{ + unsigned int i; + double a[16], b[16]; + float c[16], d[16]; + for (i = 0; i < 16; ++i) + { + a[i] = 1; + b[i] = 2; + c[i] = 3; + d[i] = 4; + } + foo (16, a, b); + bar (4, c, d); + for (i = 0; i < 16; ++i) + { + if (a[i] != 2) + abort (); + if (c[i] != 4) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-12.c new file mode 100644 index 000000000..c1c5745ef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-12.c @@ -0,0 +1,10 @@ +/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, + xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, + popcntintrin.h and mm_malloc.h are usable + with -O -std=c89 -pedantic-errors. */ +/* { dg-do compile } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt" } */ + +#include <x86intrin.h> + +int dummy; diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-13.c new file mode 100644 index 000000000..1d777d12e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-13.c @@ -0,0 +1,184 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt" } */ + +#include <mm_malloc.h> + +/* Test that the intrinsics compile with optimization. All of them + are defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h, + mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, + tbmintrin.h, lwpintrin.h, popcntintrin.h, fmaintrin.h and mm_malloc.h + that reference the proper builtin functions. + + Defining away "extern" and "__inline" results in all of them being + compiled as proper functions. */ + +#define extern +#define __inline + +/* Following intrinsics require immediate arguments. */ + +/* ammintrin.h */ +#define __builtin_ia32_extrqi(X, I, L) __builtin_ia32_extrqi(X, 1, 1) +#define __builtin_ia32_insertqi(X, Y, I, L) __builtin_ia32_insertqi(X, Y, 1, 1) + +/* immintrin.h */ +#define __builtin_ia32_blendpd256(X, Y, M) __builtin_ia32_blendpd256(X, Y, 1) +#define __builtin_ia32_blendps256(X, Y, M) __builtin_ia32_blendps256(X, Y, 1) +#define __builtin_ia32_dpps256(X, Y, M) __builtin_ia32_dpps256(X, Y, 1) +#define __builtin_ia32_shufpd256(X, Y, M) __builtin_ia32_shufpd256(X, Y, 1) +#define __builtin_ia32_shufps256(X, Y, M) __builtin_ia32_shufps256(X, Y, 1) +#define __builtin_ia32_cmpsd(X, Y, O) __builtin_ia32_cmpsd(X, Y, 1) +#define __builtin_ia32_cmpss(X, Y, O) __builtin_ia32_cmpss(X, Y, 1) +#define __builtin_ia32_cmppd(X, Y, O) __builtin_ia32_cmppd(X, Y, 1) +#define __builtin_ia32_cmpps(X, Y, O) __builtin_ia32_cmpps(X, Y, 1) +#define __builtin_ia32_cmppd256(X, Y, O) __builtin_ia32_cmppd256(X, Y, 1) +#define __builtin_ia32_cmpps256(X, Y, O) __builtin_ia32_cmpps256(X, Y, 1) +#define __builtin_ia32_vextractf128_pd256(X, N) __builtin_ia32_vextractf128_pd256(X, 1) +#define __builtin_ia32_vextractf128_ps256(X, N) __builtin_ia32_vextractf128_ps256(X, 1) +#define __builtin_ia32_vextractf128_si256(X, N) __builtin_ia32_vextractf128_si256(X, 1) +#define __builtin_ia32_vpermilpd(X, N) __builtin_ia32_vpermilpd(X, 1) +#define __builtin_ia32_vpermilpd256(X, N) __builtin_ia32_vpermilpd256(X, 1) +#define __builtin_ia32_vpermilps(X, N) __builtin_ia32_vpermilps(X, 1) +#define __builtin_ia32_vpermilps256(X, N) __builtin_ia32_vpermilps256(X, 1) +#define __builtin_ia32_vpermil2pd(X, Y, C, I) __builtin_ia32_vpermil2pd(X, Y, C, 1) +#define __builtin_ia32_vpermil2pd256(X, Y, C, I) __builtin_ia32_vpermil2pd256(X, Y, C, 1) +#define __builtin_ia32_vpermil2ps(X, Y, C, I) __builtin_ia32_vpermil2ps(X, Y, C, 1) +#define __builtin_ia32_vpermil2ps256(X, Y, C, I) __builtin_ia32_vpermil2ps256(X, Y, C, 1) +#define __builtin_ia32_vperm2f128_pd256(X, Y, C) __builtin_ia32_vperm2f128_pd256(X, Y, 1) +#define __builtin_ia32_vperm2f128_ps256(X, Y, C) __builtin_ia32_vperm2f128_ps256(X, Y, 1) +#define __builtin_ia32_vperm2f128_si256(X, Y, C) __builtin_ia32_vperm2f128_si256(X, Y, 1) +#define __builtin_ia32_vinsertf128_pd256(X, Y, C) __builtin_ia32_vinsertf128_pd256(X, Y, 1) +#define __builtin_ia32_vinsertf128_ps256(X, Y, C) __builtin_ia32_vinsertf128_ps256(X, Y, 1) +#define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1) +#define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1) +#define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1) +#define __builtin_ia32_vcvtps2ph(A, I) __builtin_ia32_vcvtps2ph(A, 1) +#define __builtin_ia32_vcvtps2ph256(A, I) __builtin_ia32_vcvtps2ph256(A, 1) + +/* wmmintrin.h */ +#define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1) +#define __builtin_ia32_pclmulqdq128(X, Y, I) __builtin_ia32_pclmulqdq128(X, Y, 1) + +/* smmintrin.h */ +#define __builtin_ia32_roundpd(V, M) __builtin_ia32_roundpd(V, 1) +#define __builtin_ia32_roundsd(D, V, M) __builtin_ia32_roundsd(D, V, 1) +#define __builtin_ia32_roundps(V, M) __builtin_ia32_roundps(V, 1) +#define __builtin_ia32_roundss(D, V, M) __builtin_ia32_roundss(D, V, 1) + +#define __builtin_ia32_pblendw128(X, Y, M) __builtin_ia32_pblendw128 (X, Y, 1) +#define __builtin_ia32_blendps(X, Y, M) __builtin_ia32_blendps(X, Y, 1) +#define __builtin_ia32_blendpd(X, Y, M) __builtin_ia32_blendpd(X, Y, 1) +#define __builtin_ia32_dpps(X, Y, M) __builtin_ia32_dpps(X, Y, 1) +#define __builtin_ia32_dppd(X, Y, M) __builtin_ia32_dppd(X, Y, 1) +#define __builtin_ia32_insertps128(D, S, N) __builtin_ia32_insertps128(D, S, 1) +#define __builtin_ia32_vec_ext_v4sf(X, N) __builtin_ia32_vec_ext_v4sf(X, 1) +#define __builtin_ia32_vec_set_v16qi(D, S, N) __builtin_ia32_vec_set_v16qi(D, S, 1) +#define __builtin_ia32_vec_set_v4si(D, S, N) __builtin_ia32_vec_set_v4si(D, S, 1) +#define __builtin_ia32_vec_set_v2di(D, S, N) __builtin_ia32_vec_set_v2di(D, S, 1) +#define __builtin_ia32_vec_ext_v16qi(X, N) __builtin_ia32_vec_ext_v16qi(X, 1) +#define __builtin_ia32_vec_ext_v4si(X, N) __builtin_ia32_vec_ext_v4si(X, 1) +#define __builtin_ia32_vec_ext_v2di(X, N) __builtin_ia32_vec_ext_v2di(X, 1) +#define __builtin_ia32_mpsadbw128(X, Y, M) __builtin_ia32_mpsadbw128(X, Y, 1) +#define __builtin_ia32_pcmpistrm128(X, Y, M) \ + __builtin_ia32_pcmpistrm128(X, Y, 1) +#define __builtin_ia32_pcmpistri128(X, Y, M) \ + __builtin_ia32_pcmpistri128(X, Y, 1) +#define __builtin_ia32_pcmpestrm128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestrm128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestri128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestri128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpistria128(X, Y, M) \ + __builtin_ia32_pcmpistria128(X, Y, 1) +#define __builtin_ia32_pcmpistric128(X, Y, M) \ + __builtin_ia32_pcmpistric128(X, Y, 1) +#define __builtin_ia32_pcmpistrio128(X, Y, M) \ + __builtin_ia32_pcmpistrio128(X, Y, 1) +#define __builtin_ia32_pcmpistris128(X, Y, M) \ + __builtin_ia32_pcmpistris128(X, Y, 1) +#define __builtin_ia32_pcmpistriz128(X, Y, M) \ + __builtin_ia32_pcmpistriz128(X, Y, 1) +#define __builtin_ia32_pcmpestria128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestria128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestric128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestric128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestrio128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestrio128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestris128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestris128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestriz128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestriz128(X, LX, Y, LY, 1) + +/* tmmintrin.h */ +#define __builtin_ia32_palignr128(X, Y, N) __builtin_ia32_palignr128(X, Y, 8) +#define __builtin_ia32_palignr(X, Y, N) __builtin_ia32_palignr(X, Y, 8) + +/* emmintrin.h */ +#define __builtin_ia32_psrldqi128(A, B) __builtin_ia32_psrldqi128(A, 8) +#define __builtin_ia32_pslldqi128(A, B) __builtin_ia32_pslldqi128(A, 8) +#define __builtin_ia32_pshufhw(A, N) __builtin_ia32_pshufhw(A, 0) +#define __builtin_ia32_pshuflw(A, N) __builtin_ia32_pshuflw(A, 0) +#define __builtin_ia32_pshufd(A, N) __builtin_ia32_pshufd(A, 0) +#define __builtin_ia32_vec_set_v8hi(A, D, N) \ + __builtin_ia32_vec_set_v8hi(A, D, 0) +#define __builtin_ia32_vec_ext_v8hi(A, N) __builtin_ia32_vec_ext_v8hi(A, 0) +#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0) + +/* xmmintrin.h */ +#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, A, _MM_HINT_NTA) +#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0) +#define __builtin_ia32_vec_set_v4hi(A, D, N) \ + __builtin_ia32_vec_set_v4hi(A, D, 0) +#define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0) +#define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0) + +/* xopintrin.h */ +#define __builtin_ia32_vprotbi(A, N) __builtin_ia32_vprotbi (A,1) +#define __builtin_ia32_vprotwi(A, N) __builtin_ia32_vprotwi (A,1) +#define __builtin_ia32_vprotdi(A, N) __builtin_ia32_vprotdi (A,1) +#define __builtin_ia32_vprotqi(A, N) __builtin_ia32_vprotqi (A,1) + +/* lwpintrin.h */ +#define __builtin_ia32_lwpval32(D2, D1, F) __builtin_ia32_lwpval32 (D2, D1, 1) +#define __builtin_ia32_lwpval64(D2, D1, F) __builtin_ia32_lwpval64 (D2, D1, 1) +#define __builtin_ia32_lwpins32(D2, D1, F) __builtin_ia32_lwpins32 (D2, D1, 1) +#define __builtin_ia32_lwpins64(D2, D1, F) __builtin_ia32_lwpins64 (D2, D1, 1) + +/* tbmintrin.h */ +#define __builtin_ia32_bextri_u32(X, Y) __builtin_ia32_bextri_u32 (X, 1) +#define __builtin_ia32_bextri_u64(X, Y) __builtin_ia32_bextri_u64 (X, 1) + +/* avx2intrin.h */ +#define __builtin_ia32_mpsadbw256(X, Y, Z) __builtin_ia32_mpsadbw256 (X, Y, 1) +#define __builtin_ia32_palignr256(X, Y, Z) __builtin_ia32_palignr256 (X, Y, 8) +#define __builtin_ia32_pblendw256(X, Y, Z) __builtin_ia32_pblendw256 (X, Y, 1) +#define __builtin_ia32_pshufd256(X, Y) __builtin_ia32_pshufd256(X, 1) +#define __builtin_ia32_pshufhw256(X, Y) __builtin_ia32_pshufhw256(X, 1) +#define __builtin_ia32_pshuflw256(X, Y) __builtin_ia32_pshuflw256(X, 1) +#define __builtin_ia32_pslldqi256(X, Y) __builtin_ia32_pslldqi256(X, 8) +#define __builtin_ia32_psrldqi256(X, Y) __builtin_ia32_psrldqi256(X, 8) +#define __builtin_ia32_pblendd128(X, Y, Z) __builtin_ia32_pblendd128(X, Y, 1) +#define __builtin_ia32_pblendd256(X, Y, Z) __builtin_ia32_pblendd256(X, Y, 1) +#define __builtin_ia32_permdf256(X, Y) __builtin_ia32_permdf256(X, 1) +#define __builtin_ia32_permdi256(X, Y) __builtin_ia32_permdi256(X, 1) +#define __builtin_ia32_permti256(X, Y, Z) __builtin_ia32_permti256(X, Y, 1) +#define __builtin_ia32_extract128i256(X, Y) __builtin_ia32_extract128i256(X, 1) +#define __builtin_ia32_insert128i256(X, Y, Z) __builtin_ia32_insert128i256(X, Y, 1) +#define __builtin_ia32_gathersiv2df(X, Y, Z, K, M) __builtin_ia32_gathersiv2df(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4df(X, Y, Z, K, M) __builtin_ia32_gathersiv4df(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv2df(X, Y, Z, K, M) __builtin_ia32_gatherdiv2df(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4df(X, Y, Z, K, M) __builtin_ia32_gatherdiv4df(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4sf(X, Y, Z, K, M) __builtin_ia32_gathersiv4sf(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv8sf(X, Y, Z, K, M) __builtin_ia32_gathersiv8sf(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4sf(X, Y, Z, K, M) __builtin_ia32_gatherdiv4sf(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4sf256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4sf256(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv2di(X, Y, Z, K, M) __builtin_ia32_gathersiv2di(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4di(X, Y, Z, K, M) __builtin_ia32_gathersiv4di(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv2di(X, Y, Z, K, M) __builtin_ia32_gatherdiv2di(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4di(X, Y, Z, K, M) __builtin_ia32_gatherdiv4di(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4si(X, Y, Z, K, M) __builtin_ia32_gathersiv4si(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv8si(X, Y, Z, K, M) __builtin_ia32_gathersiv8si(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4si(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4si256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si256(X, Y, Z, K, 1) + +/* rtmintrin.h */ +#define __builtin_ia32_xabort (N) __builtin_ia32_xabort (1) diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-14.c new file mode 100644 index 000000000..331be0e19 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-14.c @@ -0,0 +1,193 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt" } */ + +#include <mm_malloc.h> + +/* Test that the intrinsics compile without optimization. All of them are + defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, + fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, + lwpintrin.h, fmaintrin.h and mm_malloc.h that reference the proper + builtin functions. + + Defining away "extern" and "__inline" results in all of them being compiled + as proper functions. */ + +#define extern +#define __inline + +#include <x86intrin.h> + +#define _CONCAT(x,y) x ## y + +#define test_0(func, type, imm) \ + type _CONCAT(_,func) (int const I) \ + { return func (imm); } + +#define test_1(func, type, op1_type, imm) \ + type _CONCAT(_,func) (op1_type A, int const I) \ + { return func (A, imm); } + +#define test_1x(func, type, op1_type, imm1, imm2) \ + type _CONCAT(_,func) (op1_type A, int const I, int const L) \ + { return func (A, imm1, imm2); } + +#define test_2(func, type, op1_type, op2_type, imm) \ + type _CONCAT(_,func) (op1_type A, op2_type B, int const I) \ + { return func (A, B, imm); } + +#define test_2x(func, type, op1_type, op2_type, imm1, imm2) \ + type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \ + { return func (A, B, imm1, imm2); } + +#define test_3(func, type, op1_type, op2_type, op3_type, imm) \ + type _CONCAT(_,func) (op1_type A, op2_type B, \ + op3_type C, int const I) \ + { return func (A, B, C, imm); } + +#define test_4(func, type, op1_type, op2_type, op3_type, op4_type, imm) \ + type _CONCAT(_,func) (op1_type A, op2_type B, \ + op3_type C, op4_type D, int const I) \ + { return func (A, B, C, D, imm); } + + +/* Following intrinsics require immediate arguments. They + are defined as macros for non-optimized compilations. */ + +/* ammintrin.h */ +test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1) +test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1) + +/* immintrin.h */ +test_2 (_mm256_blend_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_blend_ps, __m256, __m256, __m256, 1) +test_2 (_mm256_dp_ps, __m256, __m256, __m256, 1) +test_2 (_mm256_shuffle_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_shuffle_ps, __m256, __m256, __m256, 1) +test_2 (_mm_cmp_sd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_cmp_ss, __m128, __m128, __m128, 1) +test_2 (_mm_cmp_pd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_cmp_ps, __m128, __m128, __m128, 1) +test_2 (_mm256_cmp_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_cmp_ps, __m256, __m256, __m256, 1) +test_1 (_mm256_extractf128_pd, __m128d, __m256d, 1) +test_1 (_mm256_extractf128_ps, __m128, __m256, 1) +test_1 (_mm256_extractf128_si256, __m128i, __m256i, 1) +test_1 (_mm256_extract_epi8, int, __m256i, 20) +test_1 (_mm256_extract_epi16, int, __m256i, 13) +test_1 (_mm256_extract_epi32, int, __m256i, 6) +#ifdef __x86_64__ +test_1 (_mm256_extract_epi64, long long, __m256i, 2) +#endif +test_1 (_mm_permute_pd, __m128d, __m128d, 1) +test_1 (_mm256_permute_pd, __m256d, __m256d, 1) +test_1 (_mm_permute_ps, __m128, __m128, 1) +test_1 (_mm256_permute_ps, __m256, __m256, 1) +test_2 (_mm256_permute2f128_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_permute2f128_ps, __m256, __m256, __m256, 1) +test_2 (_mm256_permute2f128_si256, __m256i, __m256i, __m256i, 1) +test_2 (_mm256_insertf128_pd, __m256d, __m256d, __m128d, 1) +test_2 (_mm256_insertf128_ps, __m256, __m256, __m128, 1) +test_2 (_mm256_insertf128_si256, __m256i, __m256i, __m128i, 1) +test_2 (_mm256_insert_epi8, __m256i, __m256i, int, 30) +test_2 (_mm256_insert_epi16, __m256i, __m256i, int, 7) +test_2 (_mm256_insert_epi32, __m256i, __m256i, int, 3) +#ifdef __x86_64__ +test_2 (_mm256_insert_epi64, __m256i, __m256i, long long, 1) +#endif +test_1 (_mm256_round_pd, __m256d, __m256d, 1) +test_1 (_mm256_round_ps, __m256, __m256, 1) +test_1 (_cvtss_sh, unsigned short, float, 1) +test_1 (_mm_cvtps_ph, __m128i, __m128, 1) +test_1 (_mm256_cvtps_ph, __m128i, __m256, 1) +test_0 (_xabort, void, 1) + +/* wmmintrin.h */ +test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1) +test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1) + +/* smmintrin.h */ +test_1 (_mm_round_pd, __m128d, __m128d, 1) +test_1 (_mm_round_ps, __m128, __m128, 1) +test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_round_ss, __m128, __m128, __m128, 1) + +test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1) +test_2 (_mm_blend_ps, __m128, __m128, __m128, 1) +test_2 (_mm_blend_pd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_dp_ps, __m128, __m128, __m128, 1) +test_2 (_mm_dp_pd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_insert_ps, __m128, __m128, __m128, 1) +test_1 (_mm_extract_ps, int, __m128, 1) +test_2 (_mm_insert_epi8, __m128i, __m128i, int, 1) +test_2 (_mm_insert_epi32, __m128i, __m128i, int, 1) +#ifdef __x86_64__ +test_2 (_mm_insert_epi64, __m128i, __m128i, long long, 1) +#endif +test_1 (_mm_extract_epi8, int, __m128i, 1) +test_1 (_mm_extract_epi32, int, __m128i, 1) +#ifdef __x86_64__ +test_1 (_mm_extract_epi64, long long, __m128i, 1) +#endif +test_2 (_mm_mpsadbw_epu8, __m128i, __m128i, __m128i, 1) +test_2 (_mm_cmpistrm, __m128i, __m128i, __m128i, 1) +test_2 (_mm_cmpistri, int, __m128i, __m128i, 1) +test_4 (_mm_cmpestrm, __m128i, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestri, int, __m128i, int, __m128i, int, 1) +test_2 (_mm_cmpistra, int, __m128i, __m128i, 1) +test_2 (_mm_cmpistrc, int, __m128i, __m128i, 1) +test_2 (_mm_cmpistro, int, __m128i, __m128i, 1) +test_2 (_mm_cmpistrs, int, __m128i, __m128i, 1) +test_2 (_mm_cmpistrz, int, __m128i, __m128i, 1) +test_4 (_mm_cmpestra, int, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestrc, int, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) + +/* tmmintrin.h */ +test_2 (_mm_alignr_epi8, __m128i, __m128i, __m128i, 1) +test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1) + +/* emmintrin.h */ +test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1) +test_1 (_mm_srli_si128, __m128i, __m128i, 1) +test_1 (_mm_slli_si128, __m128i, __m128i, 1) +test_1 (_mm_extract_epi16, int, __m128i, 1) +test_2 (_mm_insert_epi16, __m128i, __m128i, int, 1) +test_1 (_mm_shufflehi_epi16, __m128i, __m128i, 1) +test_1 (_mm_shufflelo_epi16, __m128i, __m128i, 1) +test_1 (_mm_shuffle_epi32, __m128i, __m128i, 1) + +/* xmmintrin.h */ +test_2 (_mm_shuffle_ps, __m128, __m128, __m128, 1) +test_1 (_mm_extract_pi16, int, __m64, 1) +test_1 (_m_pextrw, int, __m64, 1) +test_2 (_mm_insert_pi16, __m64, __m64, int, 1) +test_2 (_m_pinsrw, __m64, __m64, int, 1) +test_1 (_mm_shuffle_pi16, __m64, __m64, 1) +test_1 (_m_pshufw, __m64, __m64, 1) +test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA) + +/* xopintrin.h */ +test_1 ( _mm_roti_epi8, __m128i, __m128i, 1) +test_1 ( _mm_roti_epi16, __m128i, __m128i, 1) +test_1 ( _mm_roti_epi32, __m128i, __m128i, 1) +test_1 ( _mm_roti_epi64, __m128i, __m128i, 1) +test_3 (_mm_permute2_pd, __m128d, __m128d, __m128d, __m128d, 1) +test_3 (_mm256_permute2_pd, __m256d, __m256d, __m256d, __m256d, 1) +test_3 (_mm_permute2_ps, __m128, __m128, __m128, __m128, 1) +test_3 (_mm256_permute2_ps, __m256, __m256, __m256, __m256, 1) + +/* lwpintrin.h */ +test_2 ( __lwpval32, void, unsigned int, unsigned int, 1) +test_2 ( __lwpins32, unsigned char, unsigned int, unsigned int, 1) +#ifdef __x86_64__ +test_2 ( __lwpval64, void, unsigned long long, unsigned int, 1) +test_2 ( __lwpins64, unsigned char, unsigned long long, unsigned int, 1) +#endif + +/* tbmintrin.h */ +test_1 ( __bextri_u32, unsigned int, unsigned int, 1) +#ifdef __x86_64__ +test_1 ( __bextri_u64, unsigned long long, unsigned long long, 1) +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-15.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-15.c new file mode 100644 index 000000000..5a1da7a75 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-15.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse -msse2" } */ + +/* Test that the intrinsics compile with optimization. These were not + tested in i386-sse-[12].c because these builtins require immediate + operands. */ + +#include <xmmintrin.h> + +__m128 +test_shuf (void) +{ + __m128 a = _mm_set1_ps (1.0); + __m128 b = _mm_set1_ps (2.0); + return _mm_shuffle_ps (a, b, _MM_SHUFFLE (0,1,2,3)); +} + +__m64 +test_ins_ext (__m64 a) +{ + return _mm_insert_pi16 (a, _mm_extract_pi16 (a, 0), 3); +} + +__m64 +test_shuf2 (__m64 a) +{ + return _mm_shuffle_pi16 (a, 0xA5); +} + +void +test_prefetch (char *p) +{ + _mm_prefetch (p, _MM_HINT_T0); + _mm_prefetch (p+4, _MM_HINT_T1); + _mm_prefetch (p+8, _MM_HINT_T2); + _mm_prefetch (p+12, _MM_HINT_NTA); +} + +__m128i +test__slli_si128 (__m128i a) +{ + return _mm_slli_si128 (a, 3); +} + +__m128i +test__srli_si128 (__m128i a) +{ + return _mm_srli_si128 (a, 3); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-16.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-16.c new file mode 100644 index 000000000..e429630cb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-16.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -msse" } */ + +typedef float __vr __attribute__ ((vector_size (16))); + +struct vector +{ + union + { + __vr v; + float f[4]; + }; +}; + +void +doit () +{ + float f[4]; + struct vector v; + + f[0] = 0; + f[1] = 1; + f[2] = 2; + f[3] = 3; + + v.v = __builtin_ia32_loadups (f); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-17.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-17.c new file mode 100644 index 000000000..3386a3b58 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-17.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ +#include "sse2-check.h" +#include <xmmintrin.h> +extern void abort(); +int untrue = 0; +typedef union { + __v4sf v; + float f[4]; +} u; +void foo (u, u) __attribute__((noinline)); +void foo (u a, u b) { + if (b.f[0] != 7.0 || b.f[1] != 8.0 || b.f[2] != 3.0 || b.f[3] != 4.0) + abort(); +} +void bar (__v4sf, __v4sf) __attribute__((noinline)); +void bar (__v4sf a __attribute((unused)), __v4sf b __attribute((unused))) { untrue = 0;} +__v4sf setupa () __attribute((noinline)); +__v4sf setupa () { __v4sf t = { 1.0, 2.0, 3.0, 4.0 }; return t; } +__v4sf setupb () __attribute((noinline)); +__v4sf setupb () { __v4sf t = { 5.0, 6.0, 7.0, 8.0 }; return t; } +void __attribute__((noinline)) +sse2_test(void) { + u a, b; + a.v = setupa (); + b.v = setupb (); + if (untrue) + bar(a.v, b.v); + b.v = (__v4sf) _mm_movehl_ps ((__m128)a.v, (__m128)b.v); + foo (a, b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-18.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-18.c new file mode 100644 index 000000000..6a1352b82 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-18.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <emmintrin.h> + +__m128i foo (char) __attribute__((noinline)); +__m128i foo (char x) { + return _mm_set1_epi8(x); +} +__m128i bar (char) __attribute__((noinline)); +__m128i bar (char x) { + return _mm_set_epi8 (x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x); +} + +static void +sse2_test (void) { + int i, j; + union u { __m128i v; char c[16]; }; + union u x, y; + + for (i = -128; i <= 127; i++) + { + x.v = foo ((char)i); + y.v = bar ((char)i); + for (j=0; j<16; j++) + if (x.c[j] != y.c[j]) + abort(); + } +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-19.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-19.c new file mode 100644 index 000000000..3025567fd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-19.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=x86-64" } } */ +/* { dg-options "-O3 -march=x86-64 -msse2 -mno-ssse3" } */ +/* { dg-final { scan-assembler "punpcklbw" } } */ +extern void abort(); +#include <emmintrin.h> +__m128i foo (char) __attribute__((noinline)); +__m128i foo (char x) { + return _mm_set1_epi8(x); +} +__m128i bar (char) __attribute__((noinline)); +__m128i bar (char x) { + return _mm_set_epi8 (x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x); +} + +main() { + int i, j; + union u { __m128i v; char c[16]; }; + union u x, y; + for (i = -128; i <= 127; i++) + { + x.v = foo ((char)i); + y.v = bar ((char)i); + for (j=0; j<16; j++) + if (x.c[j] != y.c[j]) + abort(); + } + return 0; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-2.c new file mode 100644 index 000000000..c2f3e0b17 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse" } */ + +#include <xmmintrin.h> +static const __m128 v_sign = {-.0f, -.0f, -.0f, -.0f}; +static const __m128 v_half = {0.5f, 0.5f, 0.5f, 0.5f}; +static const __m128 v_one = {1.0f, 1.0f, 1.0f, 1.0f}; +static inline __m128 insn_ABS (__m128 a) +{ + return _mm_andnot_ps (v_sign, a); +} +__m128 voodoo (__m128 a) +{ + __m128 x = insn_ABS (a), y = _mm_rsqrt_ps (x); + y = _mm_add_ps (_mm_mul_ps (_mm_sub_ps (_mm_setzero_ps(), _mm_sub_ps (_mm_mul_ps (x, _mm_add_ps (_mm_mul_ps (y, y), _mm_setzero_ps())), v_one)), _mm_add_ps (_mm_mul_ps (y, v_half), _mm_setzero_ps())), y); + return y; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-20.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-20.c new file mode 100644 index 000000000..fc0744f25 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-20.c @@ -0,0 +1,27 @@ +/* PR target/13685 */ +/* { dg-options "-Os -msse" } */ +/* { dg-require-effective-target sse } */ + +typedef float __m128 __attribute__ ((vector_size (16))); +typedef int __m64 __attribute__ ((vector_size (8))); + +int puts (const char *s); +void foo (__m128 *, __m64 *, int); + +int main (void) +{ + foo (0, 0, 0); + return 0; +} + +void foo (__m128 *dst, __m64 *src, int n) +{ + __m128 xmm0 = { 0 }; + while (n > 64) + { + puts (""); + xmm0 = __builtin_ia32_cvtpi2ps (xmm0, *src); + *dst = xmm0; + n --; + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-21.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-21.c new file mode 100644 index 000000000..d006cdc0a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-21.c @@ -0,0 +1,24 @@ +/* Test that we don't generate a fisttp instruction when -mno-sse3. */ +/* { dg-do compile } */ +/* { dg-options "-O -mfpmath=387 -march=nocona -mno-sse3 -mno-avx" } */ +/* { dg-final { scan-assembler-not "fisttp" } } */ +struct foo +{ + long a; + long b; +}; + +extern double c; + +extern unsigned long long baz (void); + +int +walrus (const struct foo *input) +{ + unsigned long long d; + + d = baz () + + (unsigned long long) (((double) input->a * 1000000000 + + (double) input->b) * c); + return (d ? 1 : 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-22.c new file mode 100644 index 000000000..8e4c4bd3e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-22.c @@ -0,0 +1,292 @@ +/* Same as sse-14, except converted to use #pragma GCC option. */ +/* { dg-do compile } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8" } */ + +#include <mm_malloc.h> + +/* Test that the intrinsics compile with optimization. All of them + are defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h, + mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, + tbmintrin.h, lwpintrin.h, popcntintrin.h, fmaintrin.h and mm_malloc.h + that reference the proper builtin functions. + + Defining away "extern" and "__inline" results in all of them being + compiled as proper functions. */ + +#define extern +#define __inline + +#define _CONCAT(x,y) x ## y + +#define test_0(func, type, imm) \ + type _CONCAT(_,func) (int const I) \ + { return func (imm); } + +#define test_1(func, type, op1_type, imm) \ + type _CONCAT(_,func) (op1_type A, int const I) \ + { return func (A, imm); } + +#define test_1x(func, type, op1_type, imm1, imm2) \ + type _CONCAT(_,func) (op1_type A, int const I, int const L) \ + { return func (A, imm1, imm2); } + +#define test_2(func, type, op1_type, op2_type, imm) \ + type _CONCAT(_,func) (op1_type A, op2_type B, int const I) \ + { return func (A, B, imm); } + +#define test_2x(func, type, op1_type, op2_type, imm1, imm2) \ + type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \ + { return func (A, B, imm1, imm2); } + +#define test_3(func, type, op1_type, op2_type, op3_type, imm) \ + type _CONCAT(_,func) (op1_type A, op2_type B, \ + op3_type C, int const I) \ + { return func (A, B, C, imm); } + +#define test_4(func, type, op1_type, op2_type, op3_type, op4_type, imm) \ + type _CONCAT(_,func) (op1_type A, op2_type B, \ + op3_type C, op4_type D, int const I) \ + { return func (A, B, C, D, imm); } + + +#ifndef DIFFERENT_PRAGMAS +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt") +#endif + +/* Following intrinsics require immediate arguments. They + are defined as macros for non-optimized compilations. */ + +/* mmintrin.h (MMX). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("mmx") +#endif +#include <mmintrin.h> + +/* mm3dnow.h (3DNOW). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("3dnow") +#endif +#include <mm3dnow.h> + +/* xmmintrin.h (SSE). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("sse") +#endif +#include <xmmintrin.h> +test_2 (_mm_shuffle_ps, __m128, __m128, __m128, 1) +test_1 (_mm_extract_pi16, int, __m64, 1) +test_1 (_m_pextrw, int, __m64, 1) +test_2 (_mm_insert_pi16, __m64, __m64, int, 1) +test_2 (_m_pinsrw, __m64, __m64, int, 1) +test_1 (_mm_shuffle_pi16, __m64, __m64, 1) +test_1 (_m_pshufw, __m64, __m64, 1) +test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA) + +/* emmintrin.h (SSE2). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("sse2") +#endif +#include <emmintrin.h> +test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1) +test_1 (_mm_srli_si128, __m128i, __m128i, 1) +test_1 (_mm_slli_si128, __m128i, __m128i, 1) +test_1 (_mm_extract_epi16, int, __m128i, 1) +test_2 (_mm_insert_epi16, __m128i, __m128i, int, 1) +test_1 (_mm_shufflehi_epi16, __m128i, __m128i, 1) +test_1 (_mm_shufflelo_epi16, __m128i, __m128i, 1) +test_1 (_mm_shuffle_epi32, __m128i, __m128i, 1) + +/* pmmintrin.h (SSE3). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("sse3") +#endif +#include <pmmintrin.h> + +/* tmmintrin.h (SSSE3). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("ssse3") +#endif +#include <tmmintrin.h> +test_2 (_mm_alignr_epi8, __m128i, __m128i, __m128i, 1) +test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1) + +/* ammintrin.h (SSE4A). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("sse4a") +#endif +#include <ammintrin.h> +test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1) +test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1) + +/* Note, nmmintrin.h includes smmintrin.h, and smmintrin.h + checks for the #ifdef. So just set the option to SSE4.2. */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("sse4.2") +#endif +#include <nmmintrin.h> +/* smmintrin.h (SSE4.2). */ +test_1 (_mm_round_pd, __m128d, __m128d, 1) +test_1 (_mm_round_ps, __m128, __m128, 1) +test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_round_ss, __m128, __m128, __m128, 1) + +test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1) +test_2 (_mm_blend_ps, __m128, __m128, __m128, 1) +test_2 (_mm_blend_pd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_dp_ps, __m128, __m128, __m128, 1) +test_2 (_mm_dp_pd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_insert_ps, __m128, __m128, __m128, 1) +test_1 (_mm_extract_ps, int, __m128, 1) +test_2 (_mm_insert_epi8, __m128i, __m128i, int, 1) +test_2 (_mm_insert_epi32, __m128i, __m128i, int, 1) +#ifdef __x86_64__ +test_2 (_mm_insert_epi64, __m128i, __m128i, long long, 1) +#endif +test_1 (_mm_extract_epi8, int, __m128i, 1) +test_1 (_mm_extract_epi32, int, __m128i, 1) +#ifdef __x86_64__ +test_1 (_mm_extract_epi64, long long, __m128i, 1) +#endif +test_2 (_mm_mpsadbw_epu8, __m128i, __m128i, __m128i, 1) +test_2 (_mm_cmpistrm, __m128i, __m128i, __m128i, 1) +test_2 (_mm_cmpistri, int, __m128i, __m128i, 1) +test_4 (_mm_cmpestrm, __m128i, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestri, int, __m128i, int, __m128i, int, 1) +test_2 (_mm_cmpistra, int, __m128i, __m128i, 1) +test_2 (_mm_cmpistrc, int, __m128i, __m128i, 1) +test_2 (_mm_cmpistro, int, __m128i, __m128i, 1) +test_2 (_mm_cmpistrs, int, __m128i, __m128i, 1) +test_2 (_mm_cmpistrz, int, __m128i, __m128i, 1) +test_4 (_mm_cmpestra, int, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestrc, int, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1) +test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) + +/* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM) */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm") +#endif +#include <immintrin.h> +test_1 (_cvtss_sh, unsigned short, float, 1) +test_1 (_mm_cvtps_ph, __m128i, __m128, 1) +test_1 (_mm256_cvtps_ph, __m128i, __m256, 1) + +/* avxintrin.h */ +test_2 (_mm256_blend_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_blend_ps, __m256, __m256, __m256, 1) +test_2 (_mm256_dp_ps, __m256, __m256, __m256, 1) +test_2 (_mm256_shuffle_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_shuffle_ps, __m256, __m256, __m256, 1) +test_2 (_mm_cmp_sd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_cmp_ss, __m128, __m128, __m128, 1) +test_2 (_mm_cmp_pd, __m128d, __m128d, __m128d, 1) +test_2 (_mm_cmp_ps, __m128, __m128, __m128, 1) +test_2 (_mm256_cmp_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_cmp_ps, __m256, __m256, __m256, 1) +test_1 (_mm256_extractf128_pd, __m128d, __m256d, 1) +test_1 (_mm256_extractf128_ps, __m128, __m256, 1) +test_1 (_mm256_extractf128_si256, __m128i, __m256i, 1) +test_1 (_mm256_extract_epi8, int, __m256i, 20) +test_1 (_mm256_extract_epi16, int, __m256i, 13) +test_1 (_mm256_extract_epi32, int, __m256i, 6) +#ifdef __x86_64__ +test_1 (_mm256_extract_epi64, long long, __m256i, 2) +#endif +test_1 (_mm_permute_pd, __m128d, __m128d, 1) +test_1 (_mm256_permute_pd, __m256d, __m256d, 1) +test_1 (_mm_permute_ps, __m128, __m128, 1) +test_1 (_mm256_permute_ps, __m256, __m256, 1) +test_2 (_mm256_permute2f128_pd, __m256d, __m256d, __m256d, 1) +test_2 (_mm256_permute2f128_ps, __m256, __m256, __m256, 1) +test_2 (_mm256_permute2f128_si256, __m256i, __m256i, __m256i, 1) +test_2 (_mm256_insertf128_pd, __m256d, __m256d, __m128d, 1) +test_2 (_mm256_insertf128_ps, __m256, __m256, __m128, 1) +test_2 (_mm256_insertf128_si256, __m256i, __m256i, __m128i, 1) +test_2 (_mm256_insert_epi8, __m256i, __m256i, int, 30) +test_2 (_mm256_insert_epi16, __m256i, __m256i, int, 7) +test_2 (_mm256_insert_epi32, __m256i, __m256i, int, 3) +#ifdef __x86_64__ +test_2 (_mm256_insert_epi64, __m256i, __m256i, long long, 1) +#endif +test_1 (_mm256_round_pd, __m256d, __m256d, 1) +test_1 (_mm256_round_ps, __m256, __m256, 1) + +/* avx2intrin.h */ +test_2 ( _mm256_mpsadbw_epu8, __m256i, __m256i, __m256i, 1) +test_2 ( _mm256_alignr_epi8, __m256i, __m256i, __m256i, 1) +test_2 ( _mm256_blend_epi16, __m256i, __m256i, __m256i, 1) +test_1 ( _mm256_shuffle_epi32, __m256i, __m256i, 1) +test_1 ( _mm256_shufflehi_epi16, __m256i, __m256i, 1) +test_1 ( _mm256_shufflelo_epi16, __m256i, __m256i, 1) +test_1 ( _mm256_slli_si256, __m256i, __m256i, 8) +test_1 ( _mm256_srli_si256, __m256i, __m256i, 8) +test_2 ( _mm_blend_epi32, __m128i, __m128i, __m128i, 1) +test_2 ( _mm256_blend_epi32, __m256i, __m256i, __m256, 1) +test_1 ( _mm256_permute4x64_pd, __m256d, __m256d, 1) +test_1 ( _mm256_permute4x64_epi64, __m256i, __m256i, 1) +test_2 ( _mm256_permute2x128_si256, __m256i, __m256i, __m256i, 1) +test_1 ( _mm256_extracti128_si256, __m128i, __m256i, 1) +test_2 ( _mm256_inserti128_si256, __m256i, __m256i, __m128i, 1) +test_2 ( _mm_i32gather_pd, __m128d, double const *, __m128i, 1) +test_2 ( _mm256_i32gather_pd, __m256d, double const *, __m128i, 1) +test_2 ( _mm_i64gather_pd, __m128d, double const *, __m128i, 1) +test_2 ( _mm256_i64gather_pd, __m256d, double const *, __m256i, 1) +test_2 ( _mm_i32gather_ps, __m128, float const *, __m128i, 1) +test_2 ( _mm256_i32gather_ps, __m256, float const *, __m256i, 1) +test_2 ( _mm_i64gather_ps, __m128, float const *, __m128i, 1) +test_2 ( _mm256_i64gather_ps, __m128, float const *, __m256i, 1) +test_2 ( _mm_i32gather_epi64, __m128i, long long int const *, __m128i, 1) +test_2 ( _mm256_i32gather_epi64, __m256i, long long int const *, __m128i, 1) +test_2 ( _mm_i64gather_epi64, __m128i, long long int const *, __m128i, 1) +test_2 ( _mm256_i64gather_epi64, __m256i, long long int const *, __m256i, 1) +test_2 ( _mm_i32gather_epi32, __m128i, int const *, __m128i, 1) +test_2 ( _mm256_i32gather_epi32, __m256i, int const *, __m256i, 1) +test_2 ( _mm_i64gather_epi32, __m128i, int const *, __m128i, 1) +test_2 ( _mm256_i64gather_epi32, __m128i, int const *, __m256i, 1) + +/* rtmintrin.h */ +test_0 ( _xabort, void, 1) + +/* wmmintrin.h (AES/PCLMUL). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("aes,pclmul") +#endif +#include <wmmintrin.h> +test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1) +test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1) + +/* popcnintrin.h (POPCNT). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("popcnt") +#endif +#include <popcntintrin.h> + +/* x86intrin.h (FMA4/XOP/LWP/BMI/BMI2/TBM/LZCNT/FMA). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,rdseed,prfchw,adx,fxsr,xsaveopt") +#endif +#include <x86intrin.h> +/* xopintrin.h */ +test_1 ( _mm_roti_epi8, __m128i, __m128i, 1) +test_1 ( _mm_roti_epi16, __m128i, __m128i, 1) +test_1 ( _mm_roti_epi32, __m128i, __m128i, 1) +test_1 ( _mm_roti_epi64, __m128i, __m128i, 1) +test_3 (_mm_permute2_pd, __m128d, __m128d, __m128d, __m128d, 1) +test_3 (_mm256_permute2_pd, __m256d, __m256d, __m256d, __m256d, 1) +test_3 (_mm_permute2_ps, __m128, __m128, __m128, __m128, 1) +test_3 (_mm256_permute2_ps, __m256, __m256, __m256, __m256, 1) + +/* lwpintrin.h */ +test_2 ( __lwpval32, void, unsigned int, unsigned int, 1) +test_2 ( __lwpins32, unsigned char, unsigned int, unsigned int, 1) +#ifdef __x86_64__ +test_2 ( __lwpval64, void, unsigned long long, unsigned int, 1) +test_2 ( __lwpins64, unsigned char, unsigned long long, unsigned int, 1) +#endif + +/* tbmintrin.h */ +test_1 ( __bextri_u32, unsigned int, unsigned int, 1) +#ifdef __x86_64__ +test_1 ( __bextri_u64, unsigned long long, unsigned long long, 1) +#endif diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-22a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-22a.c new file mode 100644 index 000000000..688908f9e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-22a.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8" } */ + +#define DIFFERENT_PRAGMAS + +#include "sse-22.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-23.c new file mode 100644 index 000000000..069f8e7cb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-23.c @@ -0,0 +1,190 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8" } */ + +#include <mm_malloc.h> + +/* Test that the intrinsics compile with optimization. All of them + are defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h, + mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, + tbmintrin.h, lwpintrin.h, popcntintrin.h, fmaintrin.h and mm_malloc.h + that reference the proper builtin functions. + + Defining away "extern" and "__inline" results in all of them being + compiled as proper functions. */ + +#define extern +#define __inline + +/* Following intrinsics require immediate arguments. */ + +/* ammintrin.h */ +#define __builtin_ia32_extrqi(X, I, L) __builtin_ia32_extrqi(X, 1, 1) +#define __builtin_ia32_insertqi(X, Y, I, L) __builtin_ia32_insertqi(X, Y, 1, 1) + +/* wmmintrin.h */ +#define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1) +#define __builtin_ia32_pclmulqdq128(X, Y, I) __builtin_ia32_pclmulqdq128(X, Y, 1) + +/* smmintrin.h */ +#define __builtin_ia32_roundpd(V, M) __builtin_ia32_roundpd(V, 1) +#define __builtin_ia32_roundsd(D, V, M) __builtin_ia32_roundsd(D, V, 1) +#define __builtin_ia32_roundps(V, M) __builtin_ia32_roundps(V, 1) +#define __builtin_ia32_roundss(D, V, M) __builtin_ia32_roundss(D, V, 1) + +#define __builtin_ia32_pblendw128(X, Y, M) __builtin_ia32_pblendw128 (X, Y, 1) +#define __builtin_ia32_blendps(X, Y, M) __builtin_ia32_blendps(X, Y, 1) +#define __builtin_ia32_blendpd(X, Y, M) __builtin_ia32_blendpd(X, Y, 1) +#define __builtin_ia32_dpps(X, Y, M) __builtin_ia32_dpps(X, Y, 1) +#define __builtin_ia32_dppd(X, Y, M) __builtin_ia32_dppd(X, Y, 1) +#define __builtin_ia32_insertps128(D, S, N) __builtin_ia32_insertps128(D, S, 1) +#define __builtin_ia32_vec_ext_v4sf(X, N) __builtin_ia32_vec_ext_v4sf(X, 1) +#define __builtin_ia32_vec_set_v16qi(D, S, N) __builtin_ia32_vec_set_v16qi(D, S, 1) +#define __builtin_ia32_vec_set_v4si(D, S, N) __builtin_ia32_vec_set_v4si(D, S, 1) +#define __builtin_ia32_vec_set_v2di(D, S, N) __builtin_ia32_vec_set_v2di(D, S, 1) +#define __builtin_ia32_vec_ext_v16qi(X, N) __builtin_ia32_vec_ext_v16qi(X, 1) +#define __builtin_ia32_vec_ext_v4si(X, N) __builtin_ia32_vec_ext_v4si(X, 1) +#define __builtin_ia32_vec_ext_v2di(X, N) __builtin_ia32_vec_ext_v2di(X, 1) +#define __builtin_ia32_mpsadbw128(X, Y, M) __builtin_ia32_mpsadbw128(X, Y, 1) +#define __builtin_ia32_pcmpistrm128(X, Y, M) \ + __builtin_ia32_pcmpistrm128(X, Y, 1) +#define __builtin_ia32_pcmpistri128(X, Y, M) \ + __builtin_ia32_pcmpistri128(X, Y, 1) +#define __builtin_ia32_pcmpestrm128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestrm128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestri128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestri128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpistria128(X, Y, M) \ + __builtin_ia32_pcmpistria128(X, Y, 1) +#define __builtin_ia32_pcmpistric128(X, Y, M) \ + __builtin_ia32_pcmpistric128(X, Y, 1) +#define __builtin_ia32_pcmpistrio128(X, Y, M) \ + __builtin_ia32_pcmpistrio128(X, Y, 1) +#define __builtin_ia32_pcmpistris128(X, Y, M) \ + __builtin_ia32_pcmpistris128(X, Y, 1) +#define __builtin_ia32_pcmpistriz128(X, Y, M) \ + __builtin_ia32_pcmpistriz128(X, Y, 1) +#define __builtin_ia32_pcmpestria128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestria128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestric128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestric128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestrio128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestrio128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestris128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestris128(X, LX, Y, LY, 1) +#define __builtin_ia32_pcmpestriz128(X, LX, Y, LY, M) \ + __builtin_ia32_pcmpestriz128(X, LX, Y, LY, 1) + +/* tmmintrin.h */ +#define __builtin_ia32_palignr128(X, Y, N) __builtin_ia32_palignr128(X, Y, 8) +#define __builtin_ia32_palignr(X, Y, N) __builtin_ia32_palignr(X, Y, 8) + +/* emmintrin.h */ +#define __builtin_ia32_psrldqi128(A, B) __builtin_ia32_psrldqi128(A, 8) +#define __builtin_ia32_pslldqi128(A, B) __builtin_ia32_pslldqi128(A, 8) +#define __builtin_ia32_pshufhw(A, N) __builtin_ia32_pshufhw(A, 0) +#define __builtin_ia32_pshuflw(A, N) __builtin_ia32_pshuflw(A, 0) +#define __builtin_ia32_pshufd(A, N) __builtin_ia32_pshufd(A, 0) +#define __builtin_ia32_vec_set_v8hi(A, D, N) \ + __builtin_ia32_vec_set_v8hi(A, D, 0) +#define __builtin_ia32_vec_ext_v8hi(A, N) __builtin_ia32_vec_ext_v8hi(A, 0) +#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0) + +/* xmmintrin.h */ +#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, A, _MM_HINT_NTA) +#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0) +#define __builtin_ia32_vec_set_v4hi(A, D, N) \ + __builtin_ia32_vec_set_v4hi(A, D, 0) +#define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0) +#define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0) + +/* immintrin.h */ +#define __builtin_ia32_blendpd256(X, Y, M) __builtin_ia32_blendpd256(X, Y, 1) +#define __builtin_ia32_blendps256(X, Y, M) __builtin_ia32_blendps256(X, Y, 1) +#define __builtin_ia32_dpps256(X, Y, M) __builtin_ia32_dpps256(X, Y, 1) +#define __builtin_ia32_shufpd256(X, Y, M) __builtin_ia32_shufpd256(X, Y, 1) +#define __builtin_ia32_shufps256(X, Y, M) __builtin_ia32_shufps256(X, Y, 1) +#define __builtin_ia32_cmpsd(X, Y, O) __builtin_ia32_cmpsd(X, Y, 1) +#define __builtin_ia32_cmpss(X, Y, O) __builtin_ia32_cmpss(X, Y, 1) +#define __builtin_ia32_cmppd(X, Y, O) __builtin_ia32_cmppd(X, Y, 1) +#define __builtin_ia32_cmpps(X, Y, O) __builtin_ia32_cmpps(X, Y, 1) +#define __builtin_ia32_cmppd256(X, Y, O) __builtin_ia32_cmppd256(X, Y, 1) +#define __builtin_ia32_cmpps256(X, Y, O) __builtin_ia32_cmpps256(X, Y, 1) +#define __builtin_ia32_vextractf128_pd256(X, N) __builtin_ia32_vextractf128_pd256(X, 1) +#define __builtin_ia32_vextractf128_ps256(X, N) __builtin_ia32_vextractf128_ps256(X, 1) +#define __builtin_ia32_vextractf128_si256(X, N) __builtin_ia32_vextractf128_si256(X, 1) +#define __builtin_ia32_vpermilpd(X, N) __builtin_ia32_vpermilpd(X, 1) +#define __builtin_ia32_vpermilpd256(X, N) __builtin_ia32_vpermilpd256(X, 1) +#define __builtin_ia32_vpermilps(X, N) __builtin_ia32_vpermilps(X, 1) +#define __builtin_ia32_vpermilps256(X, N) __builtin_ia32_vpermilps256(X, 1) +#define __builtin_ia32_vpermil2pd(X, Y, C, I) __builtin_ia32_vpermil2pd(X, Y, C, 1) +#define __builtin_ia32_vpermil2pd256(X, Y, C, I) __builtin_ia32_vpermil2pd256(X, Y, C, 1) +#define __builtin_ia32_vpermil2ps(X, Y, C, I) __builtin_ia32_vpermil2ps(X, Y, C, 1) +#define __builtin_ia32_vpermil2ps256(X, Y, C, I) __builtin_ia32_vpermil2ps256(X, Y, C, 1) +#define __builtin_ia32_vperm2f128_pd256(X, Y, C) __builtin_ia32_vperm2f128_pd256(X, Y, 1) +#define __builtin_ia32_vperm2f128_ps256(X, Y, C) __builtin_ia32_vperm2f128_ps256(X, Y, 1) +#define __builtin_ia32_vperm2f128_si256(X, Y, C) __builtin_ia32_vperm2f128_si256(X, Y, 1) +#define __builtin_ia32_vinsertf128_pd256(X, Y, C) __builtin_ia32_vinsertf128_pd256(X, Y, 1) +#define __builtin_ia32_vinsertf128_ps256(X, Y, C) __builtin_ia32_vinsertf128_ps256(X, Y, 1) +#define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1) +#define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1) +#define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1) +#define __builtin_ia32_vcvtps2ph(A, I) __builtin_ia32_vcvtps2ph(A, 1) +#define __builtin_ia32_vcvtps2ph256(A, I) __builtin_ia32_vcvtps2ph256(A, 1) + +/* xopintrin.h */ +#define __builtin_ia32_vprotbi(A, B) __builtin_ia32_vprotbi(A,1) +#define __builtin_ia32_vprotwi(A, B) __builtin_ia32_vprotwi(A,1) +#define __builtin_ia32_vprotdi(A, B) __builtin_ia32_vprotdi(A,1) +#define __builtin_ia32_vprotqi(A, B) __builtin_ia32_vprotqi(A,1) + +/* lwpintrin.h */ +#define __builtin_ia32_lwpval32(D2, D1, F) __builtin_ia32_lwpval32 (D2, D1, 1) +#define __builtin_ia32_lwpval64(D2, D1, F) __builtin_ia32_lwpval64 (D2, D1, 1) +#define __builtin_ia32_lwpins32(D2, D1, F) __builtin_ia32_lwpins32 (D2, D1, 1) +#define __builtin_ia32_lwpins64(D2, D1, F) __builtin_ia32_lwpins64 (D2, D1, 1) + +/* tbmintrin.h */ +#define __builtin_ia32_bextri_u32(X, Y) __builtin_ia32_bextr_u32 (X, 1) +#define __builtin_ia32_bextri_u64(X, Y) __builtin_ia32_bextr_u64 (X, 1) + +/* avx2intrin.h */ +#define __builtin_ia32_mpsadbw256(X, Y, Z) __builtin_ia32_mpsadbw256 (X, Y, 1) +#define __builtin_ia32_palignr256(X, Y, Z) __builtin_ia32_palignr256 (X, Y, 8) +#define __builtin_ia32_pblendw256(X, Y, Z) __builtin_ia32_pblendw256 (X, Y, 1) +#define __builtin_ia32_pshufd256(X, Y) __builtin_ia32_pshufd256(X, 1) +#define __builtin_ia32_pshufhw256(X, Y) __builtin_ia32_pshufhw256(X, 1) +#define __builtin_ia32_pshuflw256(X, Y) __builtin_ia32_pshuflw256(X, 1) +#define __builtin_ia32_pslldqi256(X, Y) __builtin_ia32_pslldqi256(X, 8) +#define __builtin_ia32_psrldqi256(X, Y) __builtin_ia32_psrldqi256(X, 8) +#define __builtin_ia32_pblendd128(X, Y, Z) __builtin_ia32_pblendd128(X, Y, 1) +#define __builtin_ia32_pblendd256(X, Y, Z) __builtin_ia32_pblendd256(X, Y, 1) +#define __builtin_ia32_permdf256(X, Y) __builtin_ia32_permdf256(X, 1) +#define __builtin_ia32_permdi256(X, Y) __builtin_ia32_permdi256(X, 1) +#define __builtin_ia32_permti256(X, Y, Z) __builtin_ia32_permti256(X, Y, 1) +#define __builtin_ia32_extract128i256(X, Y) __builtin_ia32_extract128i256(X, 1) +#define __builtin_ia32_insert128i256(X, Y, Z) __builtin_ia32_insert128i256(X, Y, 1) +#define __builtin_ia32_gathersiv2df(X, Y, Z, K, M) __builtin_ia32_gathersiv2df(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4df(X, Y, Z, K, M) __builtin_ia32_gathersiv4df(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv2df(X, Y, Z, K, M) __builtin_ia32_gatherdiv2df(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4df(X, Y, Z, K, M) __builtin_ia32_gatherdiv4df(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4sf(X, Y, Z, K, M) __builtin_ia32_gathersiv4sf(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv8sf(X, Y, Z, K, M) __builtin_ia32_gathersiv8sf(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4sf(X, Y, Z, K, M) __builtin_ia32_gatherdiv4sf(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4sf256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4sf256(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv2di(X, Y, Z, K, M) __builtin_ia32_gathersiv2di(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4di(X, Y, Z, K, M) __builtin_ia32_gathersiv4di(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv2di(X, Y, Z, K, M) __builtin_ia32_gatherdiv2di(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4di(X, Y, Z, K, M) __builtin_ia32_gatherdiv4di(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv4si(X, Y, Z, K, M) __builtin_ia32_gathersiv4si(X, Y, Z, K, 1) +#define __builtin_ia32_gathersiv8si(X, Y, Z, K, M) __builtin_ia32_gathersiv8si(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4si(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si(X, Y, Z, K, 1) +#define __builtin_ia32_gatherdiv4si256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si256(X, Y, Z, K, 1) + +/* rtmintrin.h */ +#define __builtin_ia32_xabort(M) __builtin_ia32_xabort(1) + +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt") +#include <wmmintrin.h> +#include <smmintrin.h> +#include <mm3dnow.h> +#include <x86intrin.h> diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-24.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-24.c new file mode 100644 index 000000000..daeb968a2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-24.c @@ -0,0 +1,5 @@ +/* PR target/44338 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -ffp-contract=off" } */ + +#include "sse-23.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-3.c new file mode 100644 index 000000000..1be1d1aa2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-3.c @@ -0,0 +1,37 @@ +/* PR target/21149 */ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +#include <xmmintrin.h> + +void +__attribute__((noinline)) +check (__m128 x, float a, float b, float c, float d) +{ + union { __m128 m; float f[4]; } u; + u.m = x; + if (u.f[0] != a || u.f[1] != b || u.f[2] != c || u.f[3] != d) + abort (); +} + +static inline +void +foo (__m128 *x) +{ + __m128 y = _mm_setzero_ps (); + __m128 v = _mm_movehl_ps (y, *x); + __m128 w = _mm_movehl_ps (*x, y); + check (*x, 9, 1, 2, -3); + check (v, 2, -3, 0, 0); + check (w, 0, 0, 2, -3); +} + +static void +sse_test (void) +{ + __m128 y = _mm_set_ps (-3, 2, 1, 9); + foo (&y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-4.c new file mode 100644 index 000000000..394ad9d7e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-4.c @@ -0,0 +1,10 @@ +/* This testcase caused a buffer overflow in simplify_immed_subreg. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +#include <emmintrin.h> + +__m128i foo (__m128i x) +{ + return _mm_min_epu8 (x, _mm_set1_epi8 (10)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-5.c new file mode 100644 index 000000000..af935c2f0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-5.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-Winline -Wno-psabi -O2 -mno-sse" } */ + +typedef double v2df __attribute__ ((vector_size (16))); +v2df p; +q(v2df t) /* { dg-warning "SSE" "" } */ +{ + p=t; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-6.c new file mode 100644 index 000000000..77131d40d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-6.c @@ -0,0 +1,305 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <emmintrin.h> +#include <string.h> + +#define SHIFT (4) + +typedef union { + __m128i v; + unsigned int s[4]; + unsigned short int t[8]; + unsigned long long u[2]; + unsigned char c[16]; +}vecInLong; + +void sse2_tests (void) __attribute__((noinline)); +void dump128_16 (char *, char *, vecInLong); +void dump128_32 (char *, char *, vecInLong); +void dump128_64 (char *, char *, vecInLong); +void dump128_128 (char *, char *, vecInLong); +int check (const char *, const char *[]); + +char buf[8000]; +char comparison[8000]; +static int errors = 0; + +vecInLong a128, b128, c128, d128, e128, f128; +__m128i m128_16, m128_32, s128, m128_64, m128_128; +__m64 m64_16, s64, m64_32, m64_64; + +const char *reference_sse2[] = { + "_mm_srai_epi16 0012 0012 0012 0012 0012 0012 0012 0012 \n", + "_mm_sra_epi16 0012 0012 0012 0012 0012 0012 0012 0012 \n", + "_mm_srai_epi32 00123456 00123456 00123456 00123456 \n", + "_mm_sra_epi32 00123456 00123456 00123456 00123456 \n", + "_mm_srli_epi16 0012 0012 0012 0012 0012 0012 0012 0012 \n", + "_mm_srl_epi16 0012 0012 0012 0012 0012 0012 0012 0012 \n", + "_mm_srli_epi32 00123456 00123456 00123456 00123456 \n", + "_mm_srl_epi32 00123456 00123456 00123456 00123456 \n", + "_mm_srli_epi64 00123456789abcde 00123456789abcde \n", + "_mm_srl_epi64 00123456789abcde 00123456789abcde \n", + "_mm_srli_si128 (byte shift) 00000000ffeeddccbbaa998877665544\n", + "_mm_slli_epi16 1230 1230 1230 1230 1230 1230 1230 1230 \n", + "_mm_sll_epi16 1230 1230 1230 1230 1230 1230 1230 1230 \n", + "_mm_slli_epi32 12345670 12345670 12345670 12345670 \n", + "_mm_sll_epi32 12345670 12345670 12345670 12345670 \n", + "_mm_slli_epi64 123456789abcdef0 123456789abcdef0 \n", + "_mm_sll_epi64 123456789abcdef0 123456789abcdef0 \n", + "_mm_sll_si128 (byte shift) bbaa9988776655443322110000000000\n", + "_mm_shuffle_epi32 ffeeddcc bbaa9988 77665544 33221100 \n", + "_mm_shuffelo_epi16 7766 5544 3322 1100 9988 bbaa ddcc ffee \n", + "_mm_shuffehi_epi16 1100 3322 5544 7766 ffee ddcc bbaa 9988 \n", + "" +}; + +static void +sse2_test (void) +{ + a128.s[0] = 0x01234567; + a128.s[1] = 0x01234567; + a128.s[2] = 0x01234567; + a128.s[3] = 0x01234567; + + m128_32 = a128.v; + + d128.u[0] = 0x0123456789abcdefULL; + d128.u[1] = 0x0123456789abcdefULL; + + m128_64 = d128.v; + + /* This is the 128-bit constant 0x00112233445566778899aabbccddeeff, + expressed as two little-endian 64-bit words. */ + e128.u[0] = 0x7766554433221100ULL; + e128.u[1] = 0xffeeddccbbaa9988ULL; + + f128.t[0] = 0x0123; + f128.t[1] = 0x0123; + f128.t[2] = 0x0123; + f128.t[3] = 0x0123; + f128.t[4] = 0x0123; + f128.t[5] = 0x0123; + f128.t[6] = 0x0123; + f128.t[7] = 0x0123; + + m128_16 = f128.v; + + m128_128 = e128.v; + + b128.s[0] = SHIFT; + b128.s[1] = 0; + b128.s[2] = 0; + b128.s[3] = 0; + + s128 = b128.v; + + sse2_tests(); + check (buf, reference_sse2); +#ifdef DEBUG + printf ("sse2 testing:\n"); + printf (buf); + printf ("\ncomparison:\n"); + printf (comparison); +#endif + buf[0] = '\0'; + + if (errors != 0) + abort (); +} + +void __attribute__((noinline)) +sse2_tests (void) +{ + /* psraw */ + c128.v = _mm_srai_epi16 (m128_16, SHIFT); + dump128_16 (buf, "_mm_srai_epi16", c128); + c128.v = _mm_sra_epi16 (m128_16, s128); + dump128_16 (buf, "_mm_sra_epi16", c128); + + /* psrad */ + c128.v = _mm_srai_epi32 (m128_32, SHIFT); + dump128_32 (buf, "_mm_srai_epi32", c128); + c128.v = _mm_sra_epi32 (m128_32, s128); + dump128_32 (buf, "_mm_sra_epi32", c128); + + /* psrlw */ + c128.v = _mm_srli_epi16 (m128_16, SHIFT); + dump128_16 (buf, "_mm_srli_epi16", c128); + c128.v = _mm_srl_epi16 (m128_16, s128); + dump128_16 (buf, "_mm_srl_epi16", c128); + + /* psrld */ + c128.v = _mm_srli_epi32 (m128_32, SHIFT); + dump128_32 (buf, "_mm_srli_epi32", c128); + c128.v = _mm_srl_epi32 (m128_32, s128); + dump128_32 (buf, "_mm_srl_epi32", c128); + + /* psrlq */ + c128.v = _mm_srli_epi64 (m128_64, SHIFT); + dump128_64 (buf, "_mm_srli_epi64", c128); + c128.v = _mm_srl_epi64 (m128_64, s128); + dump128_64 (buf, "_mm_srl_epi64", c128); + + /* psrldq */ + c128.v = _mm_srli_si128 (m128_128, SHIFT); + dump128_128 (buf, "_mm_srli_si128 (byte shift) ", c128); + + /* psllw */ + c128.v = _mm_slli_epi16 (m128_16, SHIFT); + dump128_16 (buf, "_mm_slli_epi16", c128); + c128.v = _mm_sll_epi16 (m128_16, s128); + dump128_16 (buf, "_mm_sll_epi16", c128); + + /* pslld */ + c128.v = _mm_slli_epi32 (m128_32, SHIFT); + dump128_32 (buf, "_mm_slli_epi32", c128); + c128.v = _mm_sll_epi32 (m128_32, s128); + dump128_32 (buf, "_mm_sll_epi32", c128); + + /* psllq */ + c128.v = _mm_slli_epi64 (m128_64, SHIFT); + dump128_64 (buf, "_mm_slli_epi64", c128); + c128.v = _mm_sll_epi64 (m128_64, s128); + dump128_64 (buf, "_mm_sll_epi64", c128); + + /* pslldq */ + c128.v = _mm_slli_si128 (m128_128, SHIFT); + dump128_128 (buf, "_mm_sll_si128 (byte shift)", c128); + + /* Shuffle constant 0x1b == 0b_00_01_10_11, e.g. swap words: ABCD => DCBA. */ + + /* pshufd */ + c128.v = _mm_shuffle_epi32 (m128_128, 0x1b); + dump128_32 (buf, "_mm_shuffle_epi32", c128); + + /* pshuflw */ + c128.v = _mm_shufflelo_epi16 (m128_128, 0x1b); + dump128_16 (buf, "_mm_shuffelo_epi16", c128); + + /* pshufhw */ + c128.v = _mm_shufflehi_epi16 (m128_128, 0x1b); + dump128_16 (buf, "_mm_shuffehi_epi16", c128); +} + +void +dump128_16 (char *buf, char *name, vecInLong x) +{ + int i; + char *p = buf + strlen (buf); + + sprintf (p, "%s ", name); + p += strlen (p); + + for (i=0; i<8; i++) + { + sprintf (p, "%4.4x ", x.t[i]); + p += strlen (p); + } + strcat (p, "\n"); +} + +void +dump128_32 (char *buf, char *name, vecInLong x) +{ + int i; + char *p = buf + strlen (buf); + + sprintf (p, "%s ", name); + p += strlen (p); + + for (i=0; i<4; i++) + { + sprintf (p, "%8.8x ", x.s[i]); + p += strlen (p); + } + strcat (p, "\n"); +} + +void +dump128_64 (char *buf, char *name, vecInLong x) +{ + int i; + char *p = buf + strlen (buf); + + sprintf (p, "%s ", name); + p += strlen (p); + + for (i=0; i<2; i++) + { +#if defined(_WIN32) && !defined(__CYGWIN__) + sprintf (p, "%16.16I64x ", x.u[i]); +#else + sprintf (p, "%16.16llx ", x.u[i]); +#endif + p += strlen (p); + } + strcat (p, "\n"); +} + +void +dump128_128 (char *buf, char *name, vecInLong x) +{ + int i; + char *p = buf + strlen (buf); + + sprintf (p, "%s ", name); + p += strlen (p); + + for (i=15; i>=0; i--) + { + /* This is cheating; we don't have a 128-bit int format code. + Running the loop backwards to compensate for the + little-endian layout. */ + sprintf (p, "%2.2x", x.c[i]); + p += strlen (p); + } + strcat (p, "\n"); +} + +int +check (const char *input, const char *reference[]) +{ + int broken, i, j, len; + const char *p_input; + char *p_comparison; + int new_errors = 0; + + p_comparison = &comparison[0]; + p_input = input; + + for (i = 0; *reference[i] != '\0'; i++) + { + broken = 0; + len = strlen (reference[i]); + for (j = 0; j < len; j++) + { + /* Ignore the terminating NUL characters at the end of every string in 'reference[]'. */ + if (!broken && *p_input != reference[i][j]) + { + *p_comparison = '\0'; + strcat (p_comparison, " >>> "); + p_comparison += strlen (p_comparison); + new_errors++; + broken = 1; + } + *p_comparison = *p_input; + p_comparison++; + p_input++; + } + if (broken) + { + *p_comparison = '\0'; + strcat (p_comparison, "expected:\n"); + strcat (p_comparison, reference[i]); + p_comparison += strlen (p_comparison); + } + } + *p_comparison = '\0'; + strcat (p_comparison, new_errors ? "failure\n\n" : "O.K.\n\n") ; + errors += new_errors; + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-7.c new file mode 100644 index 000000000..30e2c13ba --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-7.c @@ -0,0 +1,124 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +#include <xmmintrin.h> +#include <string.h> + +#define SHIFT (4) + +typedef union { + __m64 v; + unsigned char c[8]; + unsigned short int s[4]; + unsigned long long t; + unsigned int u[2]; +}vecInWord; + +void sse_tests (void) __attribute__((noinline)); +void dump64_16 (char *, char *, vecInWord); +int check (const char *, const char *[]); + +char buf[8000]; +char comparison[8000]; +static int errors = 0; + +vecInWord c64, e64; +__m64 m64_64; + +const char *reference_sse[] = { + "_mm_shuffle_pi16 0123 4567 89ab cdef \n", + "" +}; + +static void +sse_test (void) +{ + e64.t = 0x0123456789abcdefULL; + + m64_64 = e64.v; + + sse_tests(); + check (buf, reference_sse); +#ifdef DEBUG + printf ("sse testing:\n"); + printf (buf); + printf ("\ncomparison:\n"); + printf (comparison); +#endif + buf[0] = '\0'; + + if (errors != 0) + abort (); +} + +void __attribute__((noinline)) +sse_tests (void) +{ + /* pshufw */ + c64.v = _mm_shuffle_pi16 (m64_64, 0x1b); + dump64_16 (buf, "_mm_shuffle_pi16", c64); +} + +void +dump64_16 (char *buf, char *name, vecInWord x) +{ + int i; + char *p = buf + strlen (buf); + + sprintf (p, "%s ", name); + p += strlen (p); + + for (i=0; i<4; i++) + { + sprintf (p, "%4.4x ", x.s[i]); + p += strlen (p); + } + strcat (p, "\n"); +} + +int +check (const char *input, const char *reference[]) +{ + int broken, i, j, len; + const char *p_input; + char *p_comparison; + int new_errors = 0; + + p_comparison = &comparison[0]; + p_input = input; + + for (i = 0; *reference[i] != '\0'; i++) + { + broken = 0; + len = strlen (reference[i]); + for (j = 0; j < len; j++) + { + /* Ignore the terminating NUL characters at the end of every string in 'reference[]'. */ + if (!broken && *p_input != reference[i][j]) + { + *p_comparison = '\0'; + strcat (p_comparison, " >>> "); + p_comparison += strlen (p_comparison); + new_errors++; + broken = 1; + } + *p_comparison = *p_input; + p_comparison++; + p_input++; + } + if (broken) + { + *p_comparison = '\0'; + strcat (p_comparison, "expected:\n"); + strcat (p_comparison, reference[i]); + p_comparison += strlen (p_comparison); + } + } + *p_comparison = '\0'; + strcat (p_comparison, new_errors ? "failure\n\n" : "O.K.\n\n") ; + errors += new_errors; + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-8.c new file mode 100644 index 000000000..31e8c32fb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-8.c @@ -0,0 +1,14 @@ +/* PR target/14343 */ +/* Origin: <Pawe Sikora <pluto@ds14.agh.edu.pl> */ + +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-march=pentium3" } */ + +int main() +{ + typedef long long int v __attribute__ ((vector_size (16))); + v a, b; + a = b; + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-9.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-9.c new file mode 100644 index 000000000..e1a0a2270 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-9.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +#include <xmmintrin.h> +#include <stddef.h> +#include <string.h> + +static void +sse_test (void) +{ + int alignment, n; + void *ptr; + int errors = 0; + const char test [] = "This is a test."; + + for (alignment = 1; alignment <= (1 << 20); alignment += alignment) + { + ptr = _mm_malloc (alignment, alignment); + if (((ptrdiff_t) ptr) & (alignment - 1)) + abort (); + if (ptr) + { + n = alignment > sizeof test ? sizeof test : alignment; + memcpy (ptr, test, n); + if (memcmp (ptr, test, n) != 0) + errors++; + _mm_free (ptr); + } + else + errors++; + } + + if (errors != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-addps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-addps-1.c new file mode 100644 index 000000000..b280667b5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-addps-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_add_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + int i; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-addss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-addss-1.c new file mode 100644 index 000000000..43aa2d53e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-addss-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_add_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] + s2.a[0]; + e[1] = s1.a[1]; + e[2] = s1.a[2]; + e[3] = s1.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-andnps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-andnps-1.c new file mode 100644 index 000000000..eeeec020a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-andnps-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_andnot_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + int source1[4]={34, 545, 955, 67}; + int source2[4]={67, 4, 57, 897}; + int e[4]; + + s1.x = _mm_loadu_ps ((float *)source1); + s2.x = _mm_loadu_ps ((float *)source2); + u.x = test (s1.x, s2.x); + + e[0] = (~source1[0]) & source2[0]; + e[1] = (~source1[1]) & source2[1]; + e[2] = (~source1[2]) & source2[2]; + e[3] = (~source1[3]) & source2[3]; + + if (check_union128 (u, (float *)e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-andps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-andps-1.c new file mode 100644 index 000000000..6094dba7d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-andps-1.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_and_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + union + { + float f[4]; + int i[4]; + }source1, source2, e; + + s1.x = _mm_set_ps (34, 545, 955, 67); + s2.x = _mm_set_ps (67, 4, 57, 897); + + _mm_storeu_ps (source1.f, s1.x); + _mm_storeu_ps (source2.f, s2.x); + + u.x = test (s1.x, s2.x); + + e.i[0] = source1.i[0] & source2.i[0]; + e.i[1] = source1.i[1] & source2.i[1]; + e.i[2] = source1.i[2] & source2.i[2]; + e.i[3] = source1.i[3] & source2.i[3]; + + if (check_union128 (u, e.f)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-check.h new file mode 100644 index 000000000..11b71bc3e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-check.h @@ -0,0 +1,28 @@ +#include <stdlib.h> +#include "m128-check.h" +#include "cpuid.h" +#include "sse-os-support.h" + +static void sse_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + sse_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run SSE test only if host has SSE support. */ + if ((edx & bit_SSE) && sse_os_support ()) + do_test (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cmpss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cmpss-1.c new file mode 100644 index 000000000..45438bcd1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cmpss-1.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse -std=c99" } */ +/* { dg-require-effective-target sse } */ +/* { dg-require-effective-target c99_runtime } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <math.h> + +float s1[]={2134.3343, 6678.346, 453.345635, 54646.464356}; +float s2[]={41124.234, 6678.346, 8653.65635, 856.43576}; +int dd[] = {1, 2, 3, 4}; +float d[4]; +union{int i[4]; float f[4];} e; + +void check(char *id) +{ + if(checkVi((int*)d, e.i, 4)){ + printf("mm_cmp%s_ss FAILED\n", id); + } +} + +static void +TEST () +{ + __m128 source1, source2, dest; + int i; + +#define CMP(cmp, rel) \ + e.i[0] = rel ? -1 : 0; \ + dest = _mm_loadu_ps((float*)dd); \ + source1 = _mm_loadu_ps(s1); \ + source2 = _mm_loadu_ps(s2); \ + dest = _mm_cmp##cmp##_ss(source1, source2); \ + _mm_storeu_ps(d, dest); \ + check("" #cmp ""); + + for(i = 1; i < 4; i++) e.f[i] = s1[i]; + + CMP(eq, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]); + CMP(lt, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]); + CMP(le, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]); + CMP(unord, isunordered(s1[0], s2[0])); + CMP(neq, isunordered(s1[0], s2[0]) || s1[0] != s2[0]); + CMP(nlt, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]); + CMP(nle, isunordered(s1[0], s2[0]) || s1[0] > s2[0]); + CMP(ord, !isunordered(s1[0], s2[0])); + + CMP(ge, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]); + CMP(gt, isunordered(s1[0], s2[0]) || s1[0] > s2[0]); + CMP(nge, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]); + CMP(ngt, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-1.c new file mode 100644 index 000000000..ff623aa8b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-1.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_comieq_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] == s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-2.c new file mode 100644 index 000000000..d674bed00 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-2.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_comilt_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] < s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-3.c new file mode 100644 index 000000000..d2301ad8e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-3.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_comile_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] <= s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-4.c new file mode 100644 index 000000000..7f372e249 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-4.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_comigt_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] > s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-5.c new file mode 100644 index 000000000..104fdd701 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-5.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_comige_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] >= s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-6.c new file mode 100644 index 000000000..8229b7d55 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-comiss-6.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_comineq_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] != s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c new file mode 100644 index 000000000..5b1cfe795 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +extern float copysignf (float, float); + +#define N 16 + +float a[N] = {-0.1f,-3.2f,-6.3f,-9.4f,-12.5f,-15.6f,-18.7f,-21.8f,24.9f,27.1f,30.2f,33.3f,36.4f,39.5f,42.6f,45.7f}; +float b[N] = {-1.2f,3.4f,-5.6f,7.8f,-9.0f,1.0f,-2.0f,3.0f,-4.0f,-5.0f,6.0f,7.0f,-8.0f,-9.0f,10.0f,11.0f}; +float r[N]; + +static void +TEST (void) +{ + int i; + + for (i = 0; i < N; i++) + r[i] = copysignf (a[i], b[i]); + + /* check results: */ + for (i = 0; i < N; i++) + if (r[i] != copysignf (a[i], b[i])) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c new file mode 100644 index 000000000..740227fee --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 p, int b) +{ + return _mm_cvtsi32_ss (p, b); +} + +static void +TEST (void) +{ + union128 u, s1; + int b = 498; + float e[4] = { 24.43, 68.346, 43.35, 546.46 }; + + s1.x = _mm_set_ps (e[3], e[2], e[1], e[0]); + u.x = test (s1.x, b); + e[0] = (float)b; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c new file mode 100644 index 000000000..76ce912a4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c @@ -0,0 +1,37 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target sse } */ +/* { dg-options "-O2 -msse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 p, long long b) +{ + return _mm_cvtsi64_ss (p, b); +} + +static void +TEST (void) +{ + union128 u, s1; + long long b = 4294967295133LL; + float e[4] = { 24.43, 68.346, 43.35, 546.46 }; + + s1.x = _mm_set_ps (e[3], e[2], e[1], e[0]); + u.x = test (s1.x, b); + e[0] = (float)b; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c new file mode 100644 index 000000000..3f8c549c9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 p) +{ + return _mm_cvtss_si32 (p); +} + +static void +TEST (void) +{ + union128 s1; + int d; + int e; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + d = test (s1.x); + e = (int)s1.a[0]; + + if (e != d) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c new file mode 100644 index 000000000..909c3880e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c @@ -0,0 +1,37 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target sse } */ +/* { dg-options "-O2 -msse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static long long +__attribute__((noinline, unused)) +test (__m128 p) +{ + return _mm_cvtss_si64 (p); +} + +static void +TEST (void) +{ + union128 s1; + long long d; + long long e; + + s1.x = _mm_set_ps (344.4, 68.346, 43.35, 429496729501.4); + d = test (s1.x); + e = (long long)s1.a[0]; + + if (e != d) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c new file mode 100644 index 000000000..667806d97 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 p) +{ + return _mm_cvttss_si32 (p); +} + +static void +TEST (void) +{ + union128 s1; + int d; + int e; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + d = test (s1.x); + e = (int)s1.a[0]; + + if (e != d) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c new file mode 100644 index 000000000..cbfdddd40 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c @@ -0,0 +1,37 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target sse } */ +/* { dg-options "-O2 -msse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static long long +__attribute__((noinline, unused)) +test (__m128 p) +{ + return _mm_cvttss_si64 (p); +} + +static void +TEST (void) +{ + union128 s1; + long long d; + long long e; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 429496729501.4); + d = test (s1.x); + e = (long long)s1.a[0]; + + if (e != d) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-divps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-divps-1.c new file mode 100644 index 000000000..321bb5ac7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-divps-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_div_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576); + s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] / s2.a[0]; + e[1] = s1.a[1] / s2.a[1]; + e[2] = s1.a[2] / s2.a[2]; + e[3] = s1.a[3] / s2.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-divss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-divss-1.c new file mode 100644 index 000000000..1427e4f1a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-divss-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_div_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576); + s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] / s2.a[0]; + e[1] = s1.a[1]; + e[2] = s1.a[2]; + e[3] = s1.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c new file mode 100644 index 000000000..f25131547 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c @@ -0,0 +1,68 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <mmintrin.h> + +static void +__attribute__((noinline)) +check (__m64 x, unsigned short *v, int j) +{ + union + { + __m64 x; + unsigned short i[8]; + } u; + unsigned int i; + + u.x = x; + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (i == j) + { + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]); +#endif + abort (); + } + } + else if (u.i[i] != 0) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0\n", i, u.i[i]); +#endif + abort (); + } +} + +static void +__attribute__((noinline)) +test (unsigned short *v) +{ + __m64 x; + + x = _mm_set_pi16 (0, 0, 0, v[0]); + check (x, v, 0); + x = _mm_set_pi16 (0, 0, v[1], 0); + check (x, v, 1); + x = _mm_set_pi16 (0, v[2], 0, 0); + check (x, v, 2); + x = _mm_set_pi16 (v[3], 0, 0, 0); + check (x, v, 3); +} + +static void +sse_test (void) +{ + unsigned short v[4] + = { 0x7B5B, 0x5465, 0x7374, 0x5665}; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c new file mode 100644 index 000000000..eea03ecad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c @@ -0,0 +1,67 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <xmmintrin.h> + +static void +__attribute__((noinline)) +check (__m128 x, float *v, int j) +{ + union + { + __m128 x; + float f[4]; + } u; + unsigned int i; + + u.x = x; + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (i == j) + { + if (v[i] != u.f[i]) + { +#ifdef DEBUG + printf ("%i: %f != %f\n", i, v[i], u.f[i]); +#endif + abort (); + } + } + else if (u.f[i] != 0) + { +#ifdef DEBUG + printf ("%i: %f != 0\n", i, u.f[i]); +#endif + abort (); + } +} + +static void +__attribute__((noinline)) +test (float *v) +{ + __m128 x; + + x = _mm_set_ps (0, 0, 0, v[0]); + check (x, v, 0); + x = _mm_set_ps (0, 0, v[1], 0); + check (x, v, 1); + x = _mm_set_ps (0, v[2], 0, 0); + check (x, v, 2); + x = _mm_set_ps (v[3], 0, 0, 0); + check (x, v, 3); +} + +static void +sse_test (void) +{ + float v[4] = { -3, 2, 1, 9 }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-maxps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-maxps-1.c new file mode 100644 index 000000000..9a82f665a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-maxps-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_max_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + int i; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] > s2.a[i] ? s1.a[i]:s2.a[i]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-maxss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-maxss-1.c new file mode 100644 index 000000000..7b88dfce7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-maxss-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_max_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] > s2.a[0] ? s1.a[0]:s2.a[0]; + e[1] = s1.a[1]; + e[2] = s1.a[2]; + e[3] = s1.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-minps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-minps-1.c new file mode 100644 index 000000000..452df8318 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-minps-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_min_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + int i; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] < s2.a[i] ? s1.a[i]:s2.a[i]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-minss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-minss-1.c new file mode 100644 index 000000000..b7288f859 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-minss-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_min_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] < s2.a[0] ? s1.a[0]:s2.a[0]; + e[1] = s1.a[1]; + e[2] = s1.a[2]; + e[3] = s1.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movaps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movaps-1.c new file mode 100644 index 000000000..ed3562ba5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movaps-1.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (float *e) +{ + return _mm_load_ps (e); +} + +static void +TEST (void) +{ + union128 u; + float e[4] __attribute__ ((aligned (16))) = {2134.3343,1234.635654, 1.2234, 876.8976}; + + u.x = test (e); + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movaps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movaps-2.c new file mode 100644 index 000000000..fcfa80beb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movaps-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static void +__attribute__((noinline, unused)) +test (float *e, __m128 a) +{ + _mm_store_ps (e, a); +} + +static void +TEST (void) +{ + union128 u; + float e[4] __attribute__ ((aligned (16))) = {0.0}; + + u.x = _mm_set_ps (2134.3343,1234.635654, 1.414, 3.3421); + + test (e, u.x); + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c new file mode 100644 index 000000000..4d7b3edc2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_movehl_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + u.x = test (s1.x, s2.x); + + e[0] = s2.a[2]; + e[1] = s2.a[3]; + e[2] = s1.a[2]; + e[3] = s1.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movhps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movhps-1.c new file mode 100644 index 000000000..44b885927 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movhps-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 a, __m64 *p) +{ + return _mm_loadh_pi (a, p); +} + +static void +TEST (void) +{ + union128 u, s1; + float d[2] = {24.43, 68.346}; + float e[4] = {1.17, 2.16, 3.15, 4.14}; + + s1.x = _mm_set_ps (5.13, 6.12, 7.11, 8.9); + u.x = _mm_loadu_ps (e); + + u.x = test (s1.x, (__m64 *)d); + + e[0] = s1.a[0]; + e[1] = s1.a[1]; + e[2] = d[0]; + e[3] = d[1]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movhps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movhps-2.c new file mode 100644 index 000000000..11ab38397 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movhps-2.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static void +__attribute__((noinline, unused)) +test (__m64 *p, __m128 a) +{ + return _mm_storeh_pi (p, a); +} + +static void +TEST (void) +{ + union128 s1; + float e[2]; + float d[2]; + + s1.x = _mm_set_ps (5.13, 6.12, 7.11, 8.9); + + test ((__m64 *)d, s1.x); + + e[0] = s1.a[2]; + e[1] = s1.a[3]; + + if (checkVf (d, e, 2)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c new file mode 100644 index 000000000..4ce3edf59 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 a, __m128 b) +{ + return _mm_movelh_ps (a, b); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + u.x = _mm_set1_ps (0.0); + + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0]; + e[1] = s1.a[1]; + e[2] = s2.a[0]; + e[3] = s2.a[1]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c new file mode 100644 index 000000000..8557a3021 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 a) +{ + return _mm_movemask_ps (a); +} + +static void +TEST (void) +{ + union128 u; + float s[4] = {2134.3343,1234.635654, 1.2234, 876.8976}; + int d; + int e = 0; + int i; + + u.x = _mm_loadu_ps (s); + d = test (u.x); + + for (i = 0; i < 4; i++) + if (s[i] < 0) + e |= (1 << i); + + if (checkVi (&d, &e, 1)) + abort (); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movntps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movntps-1.c new file mode 100644 index 000000000..067f29616 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movntps-1.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static void +__attribute__((noinline, unused)) +test (float *p, __m128 s) +{ + return _mm_stream_ps (p, s); +} + +static void +TEST (void) +{ + union128 u; + float e[4] __attribute__ ((aligned(16))); + + u.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + test (e, u.x); + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movss-1.c new file mode 100644 index 000000000..ee53d5faf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movss-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (float *e) +{ + return _mm_load_ss (e); +} + +static void +TEST (void) +{ + union128 u; + float e[4] = {1.1, 2.2, 3.3, 4.4}; + + u.x = _mm_set_ps (2134.3343,1234.635654, 1.2234, 876.8976); + + u.x = test (e); + + e[1] = u.a[1]; + e[2] = u.a[2]; + e[3] = u.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movss-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movss-2.c new file mode 100644 index 000000000..638666594 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movss-2.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static void +__attribute__((noinline, unused)) +test (float *e, __m128 a) +{ + return _mm_store_ss (e, a); +} + +static void +TEST (void) +{ + union128 u; + float d[1]; + float e[1]; + + u.x = _mm_set_ps (2134.3343,1234.635654, 1.2234, 876.8976); + + test (d, u.x); + + e[0] = u.a[0]; + + if (checkVf (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movss-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movss-3.c new file mode 100644 index 000000000..a090aada7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movss-3.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 a, __m128 b) +{ + return _mm_move_ss (a, b); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (2134.3343,1234.635654, 1.2234, 876.8976); + s2.x = _mm_set_ps (1.1, 2.2, 3.3, 4.4); + u.x = _mm_set_ps (5.5, 6.6, 7.7, 8.8); + u.x = test (s1.x, s2.x); + + e[0] = s2.a[0]; + e[1] = s1.a[1]; + e[2] = s1.a[2]; + e[3] = s1.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movups-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movups-1.c new file mode 100644 index 000000000..7ea912289 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movups-1.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (float *e) +{ + return _mm_loadu_ps (e); +} + +static void +TEST (void) +{ + union128 u; + float e[4] = {2134.3343,1234.635654, 1.2234, 876.8976}; + + u.x = test (e); + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movups-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movups-2.c new file mode 100644 index 000000000..188967a2a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-movups-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static void +__attribute__((noinline, unused)) +test (float *e, __m128 a) +{ + _mm_storeu_ps (e, a); +} + +static void +TEST (void) +{ + union128 u; + float e[4] = {0.0}; + + u.x = _mm_set_ps (2134.3343,1234.635654, 1.414, 3.3421); + + test (e, u.x); + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-mulps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-mulps-1.c new file mode 100644 index 000000000..de66a28e1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-mulps-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_mul_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576); + s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] * s2.a[0]; + e[1] = s1.a[1] * s2.a[1]; + e[2] = s1.a[2] * s2.a[2]; + e[3] = s1.a[3] * s2.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-mulss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-mulss-1.c new file mode 100644 index 000000000..99161a811 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-mulss-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_mul_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576); + s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] * s2.a[0]; + e[1] = s1.a[1]; + e[2] = s1.a[2]; + e[3] = s1.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-orps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-orps-1.c new file mode 100644 index 000000000..605603726 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-orps-1.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_or_ps (s1, s2); +} + +static void +TEST (void) +{ + union { + float f[4]; + int i[4]; + }source1, source2, e; + + union128 u, s1, s2; + int i; + + s1.x = _mm_set_ps (24.43, 168.346, 43.35, 546.46); + s2.x = _mm_set_ps (10.17, 2.16, 3.15, 4.14); + + _mm_storeu_ps (source1.f, s1.x); + _mm_storeu_ps (source2.f, s2.x); + + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e.i[i] = source1.i[i] | source2.i[i]; + + if (check_union128 (u, e.f)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-os-support.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-os-support.h new file mode 100644 index 000000000..a2b4e2d3c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-os-support.h @@ -0,0 +1,55 @@ +#if defined(__sun__) && defined(__svr4__) +/* Make sure sigaction() is declared even with -std=c99. */ +#define __EXTENSIONS__ +#include <signal.h> +#include <ucontext.h> + +static volatile sig_atomic_t sigill_caught; + +static void +sigill_hdlr (int sig __attribute((unused)), + siginfo_t *sip __attribute__((unused)), + ucontext_t *ucp) +{ + sigill_caught = 1; + /* Set PC to the instruction after the faulting one to skip over it, + otherwise we enter an infinite loop. */ + ucp->uc_mcontext.gregs[EIP] += 4; + setcontext (ucp); +} +#endif + +/* Check if the OS supports executing SSE instructions. This function is + only used in sse-check.h, sse2-check.h, and sse3-check.h so far since + Solaris 8 and 9 won't run on newer CPUs anyway. */ + +static int +sse_os_support (void) +{ +#if defined(__sun__) && defined(__svr4__) + /* Solaris 2 before Solaris 9 4/04 cannot execute SSE instructions + even if the CPU supports them. Programs receive SIGILL instead, so + check for that at runtime. */ + + struct sigaction act, oact; + + act.sa_handler = sigill_hdlr; + sigemptyset (&act.sa_mask); + /* Need to set SA_SIGINFO so a ucontext_t * is passed to the handler. */ + act.sa_flags = SA_SIGINFO; + sigaction (SIGILL, &act, &oact); + + /* We need a single SSE instruction here so the handler can safely skip + over it. */ + __asm__ volatile ("movss %xmm2,%xmm1"); + + sigaction (SIGILL, &oact, NULL); + + if (sigill_caught) + exit (0); + else + return 1; +#else + return 1; +#endif /* __sun__ && __svr4__ */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c new file mode 100644 index 000000000..4d0783515 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1) +{ + return _mm_rcp_ps (s1); +} + +static void +TEST (void) +{ + union128 u, s1; + float e[4]; + int i; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + u.x = test (s1.x); + + for (i = 0; i < 4; i++) + { + __m128 tmp = _mm_load_ss (&s1.a[i]); + tmp = _mm_rcp_ss (tmp); + _mm_store_ss (&e[i], tmp); + } + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-recip-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-recip-vec.c new file mode 100644 index 000000000..de2f3d297 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-recip-vec.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +extern float sqrtf (float); +extern float fabsf (float); + +#define N 8 + +float a[N] = { 0.f, 18.f, 108.f, 324.f, 720.f, 1944.f, 3087.f, 5832.f }; +float b[N] = { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f }; +float r[N]; + +float rc[N] = { 0.f, 3.f, 6.f, 9.f, 12.f, 18.f, 21.f, 27.f }; + +static void +TEST (void) +{ + int i; + + for (i = 0; i < N; i++) + { + r[i] = sqrtf (a[i] / b[i]); + } + + /* check results: */ + for (i = 0; i < N; i++) + { + if (fabsf (r[i] - rc[i]) > 0.0001) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-recip.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-recip.c new file mode 100644 index 000000000..4f7d3bf3d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-recip.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +extern float sqrtf (float); +extern float fabsf (float); + +#define N 8 + +static void +sse_test (void) +{ + float a[N] = { 0.f, 18.f, 108.f, 324.f, 720.f, 1944.f, 3087.f, 5832.f }; + float b[N] = { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f }; + float r[N]; + + float rc[N] = { 0.f, 3.f, 6.f, 9.f, 12.f, 18.f, 21.f, 27.f }; + + int i; + + for (i = 0; i < N; i++) + { + r[i] = sqrtf (a[i] / b[i]); + } + + /* check results: */ + for (i = 0; i < N; i++) + { + if (fabsf (r[i] - rc[i]) > 0.0001) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c new file mode 100644 index 000000000..c2db72549 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1) +{ + return _mm_rsqrt_ps (s1); +} + +static void +TEST (void) +{ + union128 u, s1; + float e[4]; + int i; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + u.x = test (s1.x); + + for (i = 0; i < 4; i++) + { + __m128 tmp = _mm_load_ss (&s1.a[i]); + tmp = _mm_rsqrt_ss (tmp); + _mm_store_ss (&e[i], tmp); + } + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c new file mode 100644 index 000000000..5a0c9b95d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <xmmintrin.h> + +static void +__attribute__((noinline)) +test (float *v) +{ + union + { + __m128 x; + float f[4]; + } u; + unsigned int i; + + u.x = _mm_set_ps (v[3], v[2], v[1], v[0]); + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (v[i] != u.f[i]) + { +#ifdef DEBUG + printf ("%i: %f != %f\n", i, v[i], u.f[i]); +#endif + abort (); + } +} + +static void +sse_test (void) +{ + float v[4] = { -3, 2, 1, 9 }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c new file mode 100644 index 000000000..1dbd260e5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1) +{ + return _mm_sqrt_ps (s1); +} + +static void +TEST (void) +{ + union128 u, s1; + float e[4]; + int i; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + u.x = test (s1.x); + + for (i = 0; i < 4; i++) { + __m128 tmp = _mm_load_ss (&s1.a[i]); + tmp = _mm_sqrt_ss (tmp); + _mm_store_ss (&e[i], tmp); + } + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-subps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-subps-1.c new file mode 100644 index 000000000..e63e4784a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-subps-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_sub_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576); + s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] - s2.a[0]; + e[1] = s1.a[1] - s2.a[1]; + e[2] = s1.a[2] - s2.a[2]; + e[3] = s1.a[3] - s2.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-subss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-subss-1.c new file mode 100644 index 000000000..5d9a5f504 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-subss-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_sub_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576); + s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] - s2.a[0]; + e[1] = s1.a[1]; + e[2] = s1.a[2]; + e[3] = s1.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c new file mode 100644 index 000000000..4d72b0187 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_ucomieq_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] == s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c new file mode 100644 index 000000000..dc4ba8045 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_ucomilt_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] < s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c new file mode 100644 index 000000000..042898bf6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_ucomile_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] <= s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c new file mode 100644 index 000000000..a3f32bb35 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_ucomigt_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] > s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c new file mode 100644 index 000000000..821dd7726 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_ucomige_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] >= s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c new file mode 100644 index 000000000..602a923a0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_ucomineq_ss (s1, s2); +} + +static void +TEST (void) +{ + union128 s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] != s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c new file mode 100644 index 000000000..005924b5b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_unpackhi_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576); + s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[2]; + e[1] = s2.a[2]; + e[2] = s1.a[3]; + e[3] = s2.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c new file mode 100644 index 000000000..456ef201b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_unpacklo_ps (s1, s2); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4]; + + s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576); + s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0]; + e[1] = s2.a[0]; + e[2] = s1.a[1]; + e[3] = s2.a[1]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-vect-types.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-vect-types.c new file mode 100644 index 000000000..9cb6f3e07 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-vect-types.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -msse2" } */ + +#include <xmmintrin.h> + +__m128d foo1(__m128d z, __m128d a, int N) { + int i; + for (i=0; i<N; i++) { + a = _mm_add_ps(z, a); /* { dg-error "incompatible type" } */ + } + return a; +} +/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-xorps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-xorps-1.c new file mode 100644 index 000000000..8ec500838 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse-xorps-1.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target sse } */ + +#ifndef CHECK_H +#define CHECK_H "sse-check.h" +#endif + +#ifndef TEST +#define TEST sse_test +#endif + +#include CHECK_H + +#include <xmmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_xor_ps (s1, s2); +} + +static void +TEST (void) +{ + union { + float f[4]; + int i[4]; + }source1, source2, e; + + union128 u, s1, s2; + int i; + + s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46); + s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14); + + _mm_storeu_ps (source1.f, s1.x); + _mm_storeu_ps (source2.f, s2.x); + + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e.i[i] = source1.i[i] ^ source2.i[i]; + + if (check_union128 (u, e.f)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-addpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-addpd-1.c new file mode 100644 index 000000000..99ff02f1b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-addpd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_add_pd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] + s2.a[0]; + e[1] = s1.a[1] + s2.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-addsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-addsd-1.c new file mode 100644 index 000000000..2297539f5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-addsd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_add_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] + s2.a[0]; + e[1] = s1.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-andnpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-andnpd-1.c new file mode 100644 index 000000000..0250d6be1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-andnpd-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_andnot_pd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + long long source1[2]={34545, 95567}; + long long source2[2]={674, 57897}; + long long e[2]; + + s1.x = _mm_loadu_pd ((double *)source1); + s2.x = _mm_loadu_pd ((double *)source2); + u.x = test (s1.x, s2.x); + + e[0] = (~source1[0]) & source2[0]; + e[1] = (~source1[1]) & source2[1]; + + if (check_union128d (u, (double *)e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-andpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-andpd-1.c new file mode 100644 index 000000000..9f037ab5f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-andpd-1.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_and_pd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + + union + { + double d[2]; + long long ll[2]; + }source1, source2, e; + + s1.x = _mm_set_pd (34545, 95567); + s2.x = _mm_set_pd (674, 57897); + + _mm_storeu_pd (source1.d, s1.x); + _mm_storeu_pd (source2.d, s2.x); + + u.x = test (s1.x, s2.x); + + e.ll[0] = source1.ll[0] & source2.ll[0]; + e.ll[1] = source1.ll[1] & source2.ll[1]; + + if (check_union128d (u, e.d)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-check.h new file mode 100644 index 000000000..fd4a6ce1d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-check.h @@ -0,0 +1,28 @@ +#include <stdlib.h> +#include "cpuid.h" +#include "m128-check.h" +#include "sse-os-support.h" + +static void sse2_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + sse2_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run SSE2 test only if host has SSE2 support. */ + if ((edx & bit_SSE2) && sse_os_support ()) + do_test (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cmpsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cmpsd-1.c new file mode 100644 index 000000000..153fd2bf0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cmpsd-1.c @@ -0,0 +1,59 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2 -std=c99" } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-require-effective-target c99_runtime } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <math.h> + +double s1[] = {2134.3343, 6678.346}; +double s2[] = {41124.234, 6678.346}; +long long dd[] = {1, 2}, d[2]; +union{long long l[2]; double d[2];} e; + +void check(char *id) +{ + if(checkVl(d, e.l, 2)){ + printf("mm_cmp%s_sd FAILED\n", id); + } +} + +#define CMP(cmp, rel) \ + e.l[0] = rel ? -1 : 0; \ + dest = _mm_loadu_pd((double*)dd); \ + source1 = _mm_loadu_pd(s1); \ + source2 = _mm_loadu_pd(s2); \ + dest = _mm_cmp##cmp##_sd(source1, source2); \ + _mm_storeu_pd((double*) d, dest); \ + check("" #cmp ""); + +static void +TEST () +{ + __m128d source1, source2, dest; + + e.d[1] = s1[1]; + + CMP(eq, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]); + CMP(lt, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]); + CMP(le, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]); + CMP(unord, isunordered(s1[0], s2[0])); + CMP(neq, isunordered(s1[0], s2[0]) || s1[0] != s2[0]); + CMP(nlt, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]); + CMP(nle, isunordered(s1[0], s2[0]) || s1[0] > s2[0]); + CMP(ord, !isunordered(s1[0], s2[0])); + + CMP(ge, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]); + CMP(gt, isunordered(s1[0], s2[0]) || s1[0] > s2[0]); + CMP(nge, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]); + CMP(ngt, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-1.c new file mode 100644 index 000000000..7229906b0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-1.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_comieq_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_pd (2134.3343,2344.2354); + s2.x = _mm_set_pd (41124.234,2344.2354); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] == s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-2.c new file mode 100644 index 000000000..03b5b9eab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-2.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_comilt_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_pd (2134.3343,2344.2354); + s2.x = _mm_set_pd (41124.234,2344.2354); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] < s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-3.c new file mode 100644 index 000000000..720c63e24 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-3.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_comile_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_pd (2134.3343,2344.2354); + s2.x = _mm_set_pd (41124.234,2344.2354); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] <= s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-4.c new file mode 100644 index 000000000..e33ec7127 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-4.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_comigt_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_pd (2134.3343,12344.2354); + s2.x = _mm_set_pd (41124.234,2344.2354); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] > s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-5.c new file mode 100644 index 000000000..e41ee0c1f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-5.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_comige_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_pd (2134.3343,2344.2354); + s2.x = _mm_set_pd (41124.234,2344.2354); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] >= s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-6.c new file mode 100644 index 000000000..9d32b7ad1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-comisd-6.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_comineq_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_pd (2134.3343,2344.2354); + s2.x = _mm_set_pd (41124.234,2344.2354); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] != s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-copysign-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-copysign-vec.c new file mode 100644 index 000000000..b336b3284 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-copysign-vec.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-vectorize -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +extern double copysign (double, double); + +#define N 16 + +double a[N] = {-0.1,-3.2,-6.3,-9.4,-12.5,-15.6,-18.7,-21.8,24.9,27.1,30.2,33.3,36.4,39.5,42.6,45.7}; +double b[N] = {-1.2,3.4,-5.6,7.8,-9.0,1.0,-2.0,3.0,-4.0,-5.0,6.0,7.0,-8.0,-9.0,10.0,11.0}; +double r[N]; + +static void +TEST (void) +{ + int i; + + for (i = 0; i < N; i++) + r[i] = copysign (a[i], b[i]); + + /* check results: */ + for (i = 0; i < N; i++) + if (r[i] != copysign (a[i], b[i])) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvt-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvt-1.c new file mode 100644 index 000000000..4d5683108 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvt-1.c @@ -0,0 +1,111 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -msse2 -mno-avx" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#define N 16 +float f[N]; +double d[N]; +int n[N]; + +__attribute__((noinline)) void +f1 (void) +{ + int i; + for (i = 0; i < N; i++) + n[i] = d[i]; +} + +__attribute__((noinline)) void +f2 (void) +{ + int i; + for (i = 0; i < N; i++) + f[i] = n[i]; +} + +__attribute__((noinline)) void +f3 (void) +{ + int i; + for (i = 0; i < N; i++) + d[i] = f[i]; +} + +__attribute__((noinline)) void +f4 (void) +{ + int i; + for (i = 0; i < N; i++) + n[i] = f[i]; +} + +__attribute__((noinline)) void +f5 (void) +{ + int i; + for (i = 0; i < N; i++) + d[i] = n[i]; +} + +__attribute__((noinline)) void +f6 (void) +{ + int i; + for (i = 0; i < N; i++) + f[i] = d[i]; +} + +static void +TEST () +{ + int i; + for (i = 0; i < N; i++) + { + asm (""); + d[i] = i + 2.5; + } + f1 (); + for (i = 0; i < N; i++) + if (n[i] != i + 2) + abort (); + else + n[i] = i + 7; + f2 (); + for (i = 0; i < N; i++) + if (f[i] != i + 7) + abort (); + else + f[i] = i - 2.25f; + f3 (); + for (i = 0; i < N; i++) + if (d[i] != i - 2.25) + abort (); + else + f[i] = i + 3.5; + f4 (); + for (i = 0; i < N; i++) + if (n[i] != i + 3) + abort (); + else + n[i] = i + 9; + f5 (); + for (i = 0; i < N; i++) + if (d[i] != i + 9) + abort (); + else + d[i] = i - 7.25; + f6 (); + for (i = 0; i < N; i++) + if (f[i] != i - 7.25) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvt-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvt-2.c new file mode 100644 index 000000000..00f13254c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvt-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse2 -mno-sse3 -mtune=generic -fdump-tree-vect-details" } */ + +#include "sse2-cvt-1.c" + +/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 6 "vect" } } */ +/* { dg-final { scan-assembler "cvttpd2dq" } } */ +/* { dg-final { scan-assembler "cvtdq2ps" } } */ +/* { dg-final { scan-assembler "cvtps2pd" } } */ +/* { dg-final { scan-assembler "cvttps2dq" } } */ +/* { dg-final { scan-assembler "cvtdq2pd" } } */ +/* { dg-final { scan-assembler "cvtpd2ps" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvt-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvt-vec.c new file mode 100644 index 000000000..8a811a3de --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvt-vec.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2" } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <math.h> + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=sse"))) +TEST (void) +{ + double a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (float) a[i]; + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (float) a[i]) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtdq2pd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtdq2pd-1.c new file mode 100644 index 000000000..9d85f5cac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtdq2pd-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128i p) +{ + return _mm_cvtepi32_pd (p); +} + +static void +TEST (void) +{ + union128d u; + union128i_d s; + double e[2]; + + s.x = _mm_set_epi32 (123, 321, 456, 987); + + u.x = test (s.x); + + e[0] = (double)s.a[0]; + e[1] = (double)s.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtdq2ps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtdq2ps-1.c new file mode 100644 index 000000000..4b2965e6d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtdq2ps-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128i p) +{ + return _mm_cvtepi32_ps (p); +} + +static void +TEST (void) +{ + union128 u; + union128i_d s; + float e[4]; + + s.x = _mm_set_epi32 (123, 321, 456, 987); + + u.x = test (s.x); + + e[0] = (float)s.a[0]; + e[1] = (float)s.a[1]; + e[2] = (float)s.a[2]; + e[3] = (float)s.a[3]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtpd2dq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtpd2dq-1.c new file mode 100644 index 000000000..ebcf1539b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtpd2dq-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128d p) +{ + return _mm_cvtpd_epi32 (p); +} + +static void +TEST (void) +{ + union128i_d u; + union128d s; + int e[4] = {0}; + + s.x = _mm_set_pd (2.78, 7777768.82); + + u.x = test (s.x); + + e[0] = (int)(s.a[0] + 0.5); + e[1] = (int)(s.a[1] + 0.5); + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtpd2ps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtpd2ps-1.c new file mode 100644 index 000000000..15c8188cd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtpd2ps-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128 +__attribute__((noinline, unused)) +test (__m128d p) +{ + return _mm_cvtpd_ps (p); +} + +static void +TEST (void) +{ + union128 u; + union128d s; + float e[4] = {0}; + + s.x = _mm_set_pd (123.321, 456.987); + + u.x = test (s.x); + + e[0] = (float)s.a[0]; + e[1] = (float)s.a[1]; + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtps2dq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtps2dq-1.c new file mode 100644 index 000000000..e4dcd11fe --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtps2dq-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128 p) +{ + return _mm_cvtps_epi32 (p); +} + +static void +TEST (void) +{ + union128i_d u; + union128 s; + int e[4] = {0}; + + s.x = _mm_set_ps (2.78, 7777768.82, 2.331, 3.456); + + u.x = test (s.x); + + e[0] = (int)(s.a[0] + 0.5); + e[1] = (int)(s.a[1] + 0.5); + e[2] = (int)(s.a[2] + 0.5); + e[3] = (int)(s.a[3] + 0.5); + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtps2pd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtps2pd-1.c new file mode 100644 index 000000000..cdc6051d8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtps2pd-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128 p) +{ + return _mm_cvtps_pd (p); +} + +static void +TEST (void) +{ + union128d u; + union128 s; + double e[2]; + + s.x = _mm_set_ps (2.78, 7777768.82, 2.331, 3.456); + + u.x = test (s.x); + + e[0] = (double)s.a[0]; + e[1] = (double)s.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-1.c new file mode 100644 index 000000000..9c5a0e2b9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + + +static int +__attribute__((noinline, unused)) +test (__m128d p) +{ + return _mm_cvtsd_si32 (p); +} + +static void +TEST (void) +{ + union128d s; + int e; + int d; + + s.x = _mm_set_pd (123.321, 456.987); + + d = test (s.x); + + e = (int)(s.a[0] + 0.5); + + if (d != e) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c new file mode 100644 index 000000000..a79a25836 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static long long +__attribute__((noinline, unused)) +test (__m128d p) +{ + return _mm_cvtsd_si64 (p); +} + +static void +TEST (void) +{ + union128d s; + long long e; + long long d; + + s.x = _mm_set_pd (829496729501.4, 429496729501.4); + + d = test (s.x); + + e = (long long)(s.a[0] + 0.5); + + if (d != e) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsd2ss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsd2ss-1.c new file mode 100644 index 000000000..6f8a7a7b3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsd2ss-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + + +static __m128 +__attribute__((noinline, unused)) +test (__m128 p1, __m128d p2) +{ + return _mm_cvtsd_ss (p1, p2); +} + +static void +TEST (void) +{ + union128d s1; + union128 u, s2; + double source1[2] = {123.345, 67.3321}; + float e[4] = {5633.098, 93.21, 3.34, 4555.2}; + + s1.x = _mm_loadu_pd (source1); + s2.x = _mm_loadu_ps (e); + + u.x = test(s2.x, s1.x); + + e[0] = (float)source1[0]; + + if (check_union128(u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-1.c new file mode 100644 index 000000000..cda223ce5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-1.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d p, int b) +{ + return _mm_cvtsi32_sd (p, b); +} + +static void +TEST (void) +{ + union128d u, s; + int b = 128; + double e[2]; + + s.x = _mm_set_pd (123.321, 456.987); + + u.x = test (s.x, b); + e[0] = (double)b; + e[1] = s.a[1]; + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c new file mode 100644 index 000000000..ee047baa9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c @@ -0,0 +1,38 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d p, long long b) +{ + return _mm_cvtsi64_sd (p, b); +} + +static void +TEST (void) +{ + union128d u, s; + long long b = 42949672951333LL; + double e[2]; + + s.x = _mm_set_pd (123.321, 456.987); + + u.x = test (s.x, b); + e[0] = (double)b; + e[1] = s.a[1]; + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtss2sd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtss2sd-1.c new file mode 100644 index 000000000..eda870d4f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvtss2sd-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d a, __m128 b) +{ + return _mm_cvtss_sd (a, b); +} + +static void +TEST (void) +{ + union128d u, s1; + union128 s2; + double e[2]; + + s1.x = _mm_set_pd (123.321, 456.987); + s2.x = _mm_set_ps (123.321, 456.987, 666.45, 231.987); + + u.x = test (s1.x, s2.x); + + e[0] = (double)s2.a[0]; + e[1] = s1.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvttpd2dq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvttpd2dq-1.c new file mode 100644 index 000000000..eebc25950 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvttpd2dq-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128d p) +{ + return _mm_cvttpd_epi32 (p); +} + +static void +TEST (void) +{ + union128d s; + union128i_d u; + int e[4] = {0}; + + s.x = _mm_set_pd (123.321, 456.987); + + u.x = test (s.x); + + e[0] = (int)s.a[0]; + e[1] = (int)s.a[1]; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvttps2dq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvttps2dq-1.c new file mode 100644 index 000000000..d80a1a9ec --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvttps2dq-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128 p) +{ + return _mm_cvttps_epi32 (p); +} + +static void +TEST (void) +{ + union128 s; + union128i_d u; + int e[4] = {0}; + + s.x = _mm_set_ps (123.321, 456.987, 33.56, 7765.321); + + u.x = test (s.x); + + e[0] = (int)s.a[0]; + e[1] = (int)s.a[1]; + e[2] = (int)s.a[2]; + e[3] = (int)s.a[3]; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-1.c new file mode 100644 index 000000000..d04d6d420 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-1.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d p) +{ + return _mm_cvttsd_si32 (p); +} + +static void +TEST (void) +{ + union128d s; + int e; + int d; + + s.x = _mm_set_pd (123.321, 456.987); + + d = test (s.x); + e = (int)(s.a[0]); + + if (d != e) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c new file mode 100644 index 000000000..cd913a19f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c @@ -0,0 +1,38 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static long long +__attribute__((noinline, unused)) +test (__m128d p) +{ + return _mm_cvttsd_si64 (p); +} + +static void +TEST (void) +{ + union128d s; + long long e; + long long d; + + s.x = _mm_set_pd (123.321, 42949672339501.4); + + d = test (s.x); + e = (long long)(s.a[0]); + + if (d != e) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-divpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-divpd-1.c new file mode 100644 index 000000000..2cf160c9e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-divpd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_div_pd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] / s2.a[0]; + e[1] = s1.a[1] / s2.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-divsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-divsd-1.c new file mode 100644 index 000000000..fb72320d8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-divsd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_div_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] / s2.a[0]; + e[1] = s1.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-extract-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-extract-1.c new file mode 100644 index 000000000..f701cee8c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-extract-1.c @@ -0,0 +1,102 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2_runtime } */ + +extern void abort (void); +typedef unsigned long long uint64_t; + +#define vector(elcount, type) \ +__attribute__((vector_size((elcount)*sizeof(type)))) type + +#define FN(elcount, type, idx) \ +__attribute__((noinline, noclone)) \ +type f##type##elcount##_##idx (vector (elcount, type) x) { return x[idx] + 1; } +#define T2(elcount, type) \ + H (elcount, type) \ + F (elcount, type, 0) \ + F (elcount, type, 1) +#define T4(elcount, type) \ + T2 (elcount, type) \ + F (elcount, type, 2) \ + F (elcount, type, 3) +#define T8(elcount, type) \ + T4 (elcount, type) \ + F (elcount, type, 4) \ + F (elcount, type, 5) \ + F (elcount, type, 6) \ + F (elcount, type, 7) +#define T16(elcount, type) \ + T8 (elcount, type) \ + F (elcount, type, 8) \ + F (elcount, type, 9) \ + F (elcount, type, 10) \ + F (elcount, type, 11) \ + F (elcount, type, 12) \ + F (elcount, type, 13) \ + F (elcount, type, 14) \ + F (elcount, type, 15) +#define T32(elcount, type) \ + T16 (elcount, type) \ + F (elcount, type, 16) \ + F (elcount, type, 17) \ + F (elcount, type, 18) \ + F (elcount, type, 19) \ + F (elcount, type, 20) \ + F (elcount, type, 21) \ + F (elcount, type, 22) \ + F (elcount, type, 23) \ + F (elcount, type, 24) \ + F (elcount, type, 25) \ + F (elcount, type, 26) \ + F (elcount, type, 27) \ + F (elcount, type, 28) \ + F (elcount, type, 29) \ + F (elcount, type, 30) \ + F (elcount, type, 31) +#define TESTS_SSE2 \ +T2 (2, double) E \ +T2 (2, uint64_t) E \ +T4 (4, float) E \ +T4 (4, int) E \ +T8 (8, short) E \ +T16 (16, char) E +#define TESTS_AVX \ +T4 (4, double) E \ +T4 (4, uint64_t) E \ +T8 (8, float) E \ +T8 (8, int) E \ +T16 (16, short) E \ +T32 (32, char) E +#ifdef __AVX__ +#define TESTS TESTS_SSE2 TESTS_AVX +#else +#define TESTS TESTS_SSE2 +#endif + +#define F FN +#define H(elcount, type) +#define E +TESTS + +int +main () +{ +#undef F +#undef H +#undef E +#define H(elcount, type) \ + vector (elcount, type) v##type##elcount = { +#define E }; +#define F(elcount, type, idx) idx + 1, + TESTS +#undef F +#undef H +#undef E +#define H(elcount, type) +#define E +#define F(elcount, type, idx) \ + if (f##type##elcount##_##idx (v##type##elcount) != idx + 2) \ + abort (); + TESTS + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v16qi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v16qi-1.c new file mode 100644 index 000000000..652880046 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v16qi-1.c @@ -0,0 +1,77 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <emmintrin.h> + +static void +__attribute__((noinline)) +check (__m128i x, unsigned char *v, int j) +{ + union + { + __m128i x; + unsigned char i[16]; + } u; + unsigned int i; + + u.x = x; + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (i == j) + { + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]); +#endif + abort (); + } + } + else if (u.i[i] != 0) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0\n", i, u.i[i]); +#endif + abort (); + } +} + +static void +__attribute__((noinline)) +test (unsigned char *v) +{ + __m128i x; + + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[0]); + check (x, v, 0); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[1], 0); + check (x, v, 1); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[2], 0, 0); + check (x, v, 2); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[3], 0, 0, 0); + check (x, v, 3); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[4], 0, 0, 0, 0); + check (x, v, 4); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[5], 0, 0, 0, 0, 0); + check (x, v, 5); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, v[6], 0, 0, 0, 0, 0, 0); + check (x, v, 6); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, v[7], 0, 0, 0, 0, 0, 0, 0); + check (x, v, 7); +} + +static void +sse2_test (void) +{ + unsigned char v[16] + = { 0x7B, 0x5B, 0x54, 0x65, 0x73, 0x74, 0x56, 0x65, + 0x63, 0x74, 0x6F, 0x72, 0x5D, 0x53, 0x47, 0x5D }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v2di-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v2di-1.c new file mode 100644 index 000000000..ef1863c57 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v2di-1.c @@ -0,0 +1,64 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <emmintrin.h> + +static void +__attribute__((noinline)) +check (__m128i x, unsigned long long *v, int j) +{ + union + { + __m128i x; + unsigned long long i[2]; + } u; + unsigned int i; + + u.x = x; + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (i == j) + { + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]); +#endif + abort (); + } + } + else if (u.i[i] != 0) + { +#ifdef DEBUG + printf ("%i: 0x%llx != 0\n", i, u.i[i]); +#endif + abort (); + } +} + +static void +__attribute__((noinline)) +test (unsigned long long *v) +{ + __m128i x; + + x = _mm_set_epi64x (0, v[0]); + check (x, v, 0); + x = _mm_set_epi64x (v[1], 0); + check (x, v, 1); +} + +static void +sse2_test (void) +{ + unsigned long long v[2] + = { 0x7B5B546573745665LL, 0x63746F725D53475DLL }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c new file mode 100644 index 000000000..f4d3a9a8f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -msse4 -march=core2 -dp" } */ + +#include <emmintrin.h> + +__m128i +test (long long b) +{ + return _mm_cvtsi64_si128 (b); +} + +/* { dg-final { scan-assembler-times "\\*vec_concatv2di_rex64/4" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v4si-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v4si-1.c new file mode 100644 index 000000000..bcb94055c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v4si-1.c @@ -0,0 +1,68 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <emmintrin.h> + +static void +__attribute__((noinline)) +check (__m128i x, unsigned int *v, int j) +{ + union + { + __m128i x; + unsigned int i[4]; + } u; + unsigned int i; + + u.x = x; + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (i == j) + { + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]); +#endif + abort (); + } + } + else if (u.i[i] != 0) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0\n", i, u.i[i]); +#endif + abort (); + } +} + +static void +__attribute__((noinline)) +test (unsigned int *v) +{ + __m128i x; + + x = _mm_set_epi32 (0, 0, 0, v[0]); + check (x, v, 0); + x = _mm_set_epi32 (0, 0, v[1], 0); + check (x, v, 1); + x = _mm_set_epi32 (0, v[2], 0, 0); + check (x, v, 2); + x = _mm_set_epi32 (v[3], 0, 0, 0); + check (x, v, 3); +} + +static void +sse2_test (void) +{ + unsigned int v[4] + = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v8hi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v8hi-1.c new file mode 100644 index 000000000..62734820d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-init-v8hi-1.c @@ -0,0 +1,77 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <emmintrin.h> + +static void +__attribute__((noinline)) +check (__m128i x, unsigned short *v, int j) +{ + union + { + __m128i x; + unsigned short i[8]; + } u; + unsigned int i; + + u.x = x; + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (i == j) + { + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]); +#endif + abort (); + } + } + else if (u.i[i] != 0) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0\n", i, u.i[i]); +#endif + abort (); + } +} + +static void +__attribute__((noinline)) +test (unsigned short *v) +{ + __m128i x; + + x = _mm_set_epi16 (0, 0, 0, 0, 0, 0, 0, v[0]); + check (x, v, 0); + x = _mm_set_epi16 (0, 0, 0, 0, 0, 0, v[1], 0); + check (x, v, 1); + x = _mm_set_epi16 (0, 0, 0, 0, 0, v[2], 0, 0); + check (x, v, 2); + x = _mm_set_epi16 (0, 0, 0, 0, v[3], 0, 0, 0); + check (x, v, 3); + x = _mm_set_epi16 (0, 0, 0, v[4], 0, 0, 0, 0); + check (x, v, 4); + x = _mm_set_epi16 (0, 0, v[5], 0, 0, 0, 0, 0); + check (x, v, 5); + x = _mm_set_epi16 (0, v[6], 0, 0, 0, 0, 0, 0); + check (x, v, 6); + x = _mm_set_epi16 (v[7], 0, 0, 0, 0, 0, 0, 0); + check (x, v, 7); +} + +static void +sse2_test (void) +{ + unsigned short v[8] + = { 0x7B5B, 0x5465, 0x7374, 0x5665, + 0x6374, 0x6F72, 0x5D53, 0x475D }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-insvhi.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-insvhi.c new file mode 100644 index 000000000..03a287042 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-insvhi.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> +#include <string.h> + +typedef short T __attribute__((may_alias)); +struct S { __m128i d; }; + +__m128i +__attribute__((noinline)) +foo (__m128i y, short x) +{ + struct S s; + + s.d = y; + ((T *) &s.d)[1] = x; + return s.d; +} + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + unsigned short s[8]; + } res, val, tmp; + unsigned short ins[4] = { 3, 4, 5, 6 }; + + val.i[0] = 0x35251505; + val.i[1] = 0x75655545; + val.i[2] = 0xB5A59585; + val.i[3] = 0xF5E5D5C5; + + res.x = foo (val.x, ins[3]); + + tmp.x = val.x; + tmp.s[1] = ins[3]; + if (memcmp (&tmp, &res, sizeof (tmp))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c new file mode 100644 index 000000000..111e9b274 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +extern long lrint (double); + +#define N 32 + +double a[N] = {0.4,3.5,6.6,9.4,12.5,15.6,18.4,21.5,24.6,27.4,30.5,33.6,36.4,39.5,42.6,45.4,0.5,3.6,6.4,9.5,12.6,15.4,18.5,21.6,24.4,27.5,30.6,33.4,36.5,39.6,42.4,45.5}; +long r[N]; + +static void +TEST (void) +{ + int i; + + for (i = 0; i < N; i++) + { + r[i] = lrint (a[i]); + } + + /* check results: */ + for (i = 0; i < N; i++) + { + if (r[i] != lrint (a[i])) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c new file mode 100644 index 000000000..ee917623c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +extern long lrintf (float); + +#define N 32 + +float a[N] = {0.4,3.5,6.6,9.4,12.5,15.6,18.4,21.5,24.6,27.4,30.5,33.6,36.4,39.5,42.6,45.4,0.5,3.6,6.4,9.5,12.6,15.4,18.5,21.6,24.4,27.5,30.6,33.4,36.5,39.6,42.4,45.5}; +long r[N]; + +static void +TEST (void) +{ + int i; + + for (i = 0; i < N; i++) + { + r[i] = lrintf (a[i]); + } + + /* check results: */ + for (i = 0; i < N; i++) + { + if (r[i] != lrintf (a[i])) + abort(); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-maskmovdqu.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-maskmovdqu.c new file mode 100644 index 000000000..b401c85b3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-maskmovdqu.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +#ifndef MASK +#define MASK 0x7986 +#endif + +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 7) + +void static +TEST (void) +{ + __m128i src, mask; + char s[16] = { 1,-2,3,-4,5,-6,7,-8,9,-10,11,-12,13,-14,15,-16 }; + char m[16]; + + char u[20] = { 0 }; + int i; + + for (i = 0; i < 16; i++) + m[i] = mask_v (i); + + src = _mm_loadu_si128 ((__m128i *)s); + mask = _mm_loadu_si128 ((__m128i *)m); + + _mm_maskmoveu_si128 (src, mask, u+3); + + for (i = 0; i < 16; i++) + if (u[i+3] != (m[i] ? s[i] : 0)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-maxpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-maxpd-1.c new file mode 100644 index 000000000..f6360c769 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-maxpd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_max_pd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] > s2.a[0] ? s1.a[0]:s2.a[0]; + e[1] = s1.a[1] > s2.a[1] ? s1.a[1]:s2.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-maxsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-maxsd-1.c new file mode 100644 index 000000000..24377cc25 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-maxsd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_max_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] > s2.a[0] ? s1.a[0]:s2.a[0]; + e[1] = s1.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-minpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-minpd-1.c new file mode 100644 index 000000000..e64091e19 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-minpd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_min_pd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] < s2.a[0] ? s1.a[0]:s2.a[0]; + e[1] = s1.a[1] < s2.a[1] ? s1.a[1]:s2.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-minsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-minsd-1.c new file mode 100644 index 000000000..3c34d98b9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-minsd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_min_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] < s2.a[0] ? s1.a[0]:s2.a[0]; + e[1] = s1.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-mmx.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-mmx.c new file mode 100644 index 000000000..fb226a8e8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-mmx.c @@ -0,0 +1,77 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <mmintrin.h> + +#define N 4 + +unsigned long long a[N], b[N], result[N]; + +unsigned long long check[N] = + { 0x101010101010100full, + 0x1010101010101010ull, + 0x1010101010101010ull, + 0x1010101010101010ull }; + +__m64 +unsigned_add3 (const __m64 * a, const __m64 * b, + __m64 * result, unsigned int count) +{ + __m64 _a, _b, one, sum, carry, onesCarry; + + unsigned int i; + + carry = _mm_setzero_si64 (); + + one = _mm_cmpeq_pi8 (carry, carry); + one = _mm_sub_si64 (carry, one); + + for (i = 0; i < count; i++) + { + _a = a[i]; + _b = b[i]; + + sum = _mm_add_si64 (_a, _b); + sum = _mm_add_si64 (sum, carry); + + result[i] = sum; + + onesCarry = _mm_and_si64 (_mm_xor_si64 (_a, _b), carry); + onesCarry = _mm_or_si64 (_mm_and_si64 (_a, _b), onesCarry); + onesCarry = _mm_and_si64 (onesCarry, one); + + _a = _mm_srli_si64 (_a, 1); + _b = _mm_srli_si64 (_b, 1); + + carry = _mm_add_si64 (_mm_add_si64 (_a, _b), onesCarry); + carry = _mm_srli_si64 (carry, 63); + } + + return carry; +} + +void __attribute__((noinline)) +sse2_test (void) +{ + unsigned long long carry; + int i; + + /* Really long numbers. */ + a[3] = a[2] = a[1] = a[0] = 0xd3d3d3d3d3d3d3d3ull; + b[3] = b[2] = b[1] = b[0] = 0x3c3c3c3c3c3c3c3cull; + + carry = (unsigned long long) unsigned_add3 + ((__m64 *)a, (__m64 *)b, (__m64 *)result, N); + + _mm_empty (); + + if (carry != 1) + abort (); + + for (i = 0; i < N; i++) + if (result [i] != check[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c new file mode 100644 index 000000000..b8b9dba0c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (double *e) +{ + return _mm_load_pd (e); +} + +static void +TEST (void) +{ + union128d u; + double e[2] __attribute__ ((aligned (8))) = {2134.3343,1234.635654}; + + u.x = test (e); + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c new file mode 100644 index 000000000..8298551ba --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static void +__attribute__((noinline, unused)) +test (double *e, __m128d a) +{ + _mm_store_pd (e, a); +} + +static void +TEST (void) +{ + union128d u; + double e[2] __attribute__ ((aligned (8))) = {0.0}; + + u.x = _mm_set_pd (2134.3343,1234.635654); + + test (e, u.x); + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movd-1.c new file mode 100644 index 000000000..67f0a87ea --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movd-1.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (int b) +{ + return _mm_cvtsi32_si128 (b); +} + +static void +TEST (void) +{ + union128i_d u; + int b = 128; + int e[4] = {0}; + + u.x = test (b); + + e[0] = b; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movd-2.c new file mode 100644 index 000000000..a12787b7a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movd-2.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128i b) +{ + return _mm_cvtsi128_si32 (b); +} + +static void +TEST (void) +{ + union128i_d u; + int e; + + u.x = _mm_set_epi32 (2134, -128, 655366, 9999); + e = test (u.x); + if (e != u.a[0]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movdqa-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movdqa-1.c new file mode 100644 index 000000000..7599b0523 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movdqa-1.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i *p) +{ + return _mm_load_si128 (p); +} + +static void +TEST (void) +{ + union128i_d u; + int e[4] __attribute__ ((aligned(16))) = {1, 2, 3, 4}; + + u.x = test ((__m128i *)e); + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movdqa-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movdqa-2.c new file mode 100644 index 000000000..ff6c91fda --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movdqa-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static void +__attribute__((noinline, unused)) +test (__m128i *p, __m128i a) +{ + return _mm_store_si128 (p, a); +} + +static void +TEST (void) +{ + union128i_d u; + int e[4] __attribute__ ((aligned(16))) = {0}; + + u.x = _mm_set_epi32 (1, 2, 3, 4); + + test ((__m128i *)e, u.x); + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movdqu-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movdqu-1.c new file mode 100644 index 000000000..0688dd9b0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movdqu-1.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i *p) +{ + return _mm_loadu_si128 (p); +} + +static void +TEST (void) +{ + union128i_d u; + int e[4] = {1, 2, 3, 4}; + + u.x = test ((__m128i *)e); + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movdqu-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movdqu-2.c new file mode 100644 index 000000000..20e79eac6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movdqu-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static void +__attribute__((noinline, unused)) +test (__m128i *p, __m128i a) +{ + return _mm_storeu_si128 (p, a); +} + +static void +TEST (void) +{ + union128i_d u; + int e[4] = {0}; + + u.x = _mm_set_epi32 (1, 2, 3, 4); + + test ((__m128i *)e, u.x); + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movhpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movhpd-1.c new file mode 100644 index 000000000..e906cbc2f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movhpd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mfpmath=sse -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, double *p) +{ + return _mm_loadh_pd (s1, p); +} + +static void +TEST (void) +{ + union128d u, s1; + double s2[2] = {41124.234,2344.2354}; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + u.x = test (s1.x, s2); + + e[0] = s1.a[0]; + e[1] = s2[0]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movhpd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movhpd-2.c new file mode 100644 index 000000000..e86259acb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movhpd-2.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mfpmath=sse -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static void +__attribute__((noinline, unused)) +test (double *p, __m128d a) +{ + return _mm_storeh_pd (p, a); +} + +static void +TEST (void) +{ + union128d s; + double d[1]; + double e[1]; + + s.x = _mm_set_pd (2134.3343,1234.635654); + test (d, s.x); + + e[0] = s.a[1]; + + if (e[0] != d[0]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movlpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movlpd-1.c new file mode 100644 index 000000000..9e7432b35 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movlpd-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d a, double *e) +{ + return _mm_loadl_pd (a, e); +} + +static void +TEST (void) +{ + union128d u, s1; + double d[2] = {2134.3343,1234.635654}; + double e[2]; + + s1.x = _mm_set_pd (41124.234,2344.2354); + u.x = _mm_loadu_pd (d); + + u.x = test (s1.x, d); + + e[0] = d[0]; + e[1] = s1.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movlpd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movlpd-2.c new file mode 100644 index 000000000..1bbb74123 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movlpd-2.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static void +__attribute__((noinline, unused)) +test (double *e, __m128d a) +{ + return _mm_storel_pd (e, a); +} + +static void +TEST (void) +{ + union128d u; + double e[2]; + + u.x = _mm_set_pd (41124.234,2344.2354); + + test (e, u.x); + + e[1] = u.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movmskpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movmskpd-1.c new file mode 100644 index 000000000..6a865fe75 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movmskpd-1.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d p) +{ + return _mm_movemask_pd (p); +} + +static void +TEST (void) +{ + double source[2] = {1.234, -2234.23}; + union128d s1; + int d; + int e; + + s1.x = _mm_loadu_pd (source); + + d = test (s1.x); + + e = 0; + if (source[0] < 0) + e |= 1; + + if (source[1] < 0) + e |= 1 << 1; + + if (checkVi (&d, &e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movntdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movntdq-1.c new file mode 100644 index 000000000..4435ad806 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movntdq-1.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static void +__attribute__((noinline, unused)) +test (__m128i *p, __m128i s) +{ + return _mm_stream_si128 (p, s); +} + +static void +TEST (void) +{ + union128i_d u; + int e[4] __attribute__ ((aligned(16))); + + u.x = _mm_set_epi32 (21, 34, 334, 8567); + + test ((__m128i *)e, u.x); + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movntpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movntpd-1.c new file mode 100644 index 000000000..204174ecf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movntpd-1.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static void +__attribute__((noinline, unused)) +test (double *p, __m128d s) +{ + return _mm_stream_pd (p, s); +} + +static void +TEST (void) +{ + union128d u; + double e[2] __attribute__ ((aligned(16))); + + u.x = _mm_set_pd (2134.3343,1234.635654); + test (e, u.x); + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movq-1.c new file mode 100644 index 000000000..718b51a41 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movq-1.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i b) +{ + return _mm_move_epi64 (b); +} + +static void +TEST (void) +{ + union128i_q u, s1; + long long e[2] = {0}; + + s1.x = _mm_set_epi64x(12876, 3376590); + u.x = test (s1.x); + e[0] = s1.a[0]; + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movq-2.c new file mode 100644 index 000000000..e1e9b14cf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movq-2.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (long long b) +{ + return _mm_cvtsi64_si128 (b); +} + +static void +TEST (void) +{ + union128i_q u; + long long b = 4294967295133LL; + long long e[2] = {0}; + + u.x = test (b); + + e[0] = b; + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movq-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movq-3.c new file mode 100644 index 000000000..0a17e3e70 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movq-3.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static long long +__attribute__((noinline, unused)) +test (__m128i b) +{ + return _mm_cvtsi128_si64 (b); +} + +static void +TEST (void) +{ + union128i_q u; + long long e; + + u.x = _mm_set_epi64x (4294967295133LL, 3844294967295133LL); + e = test (u.x); + if (e != u.a[0]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movsd-1.c new file mode 100644 index 000000000..14342ea86 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movsd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (double *p) +{ + return _mm_load_sd (p); +} + +static void +TEST (void) +{ + union128d u; + double d[2] = {128.023, 3345.1234}; + double e[2]; + + u.x = _mm_loadu_pd (e); + u.x = test (d); + + e[0] = d[0]; + e[1] = 0.0; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movsd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movsd-2.c new file mode 100644 index 000000000..f1958f09d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movsd-2.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static void +__attribute__((noinline, unused)) +test (double *p, __m128d a) +{ + _mm_store_sd (p, a); +} + +static void +TEST (void) +{ + union128d u; + double d[1]; + double e[1]; + + u.x = _mm_set_pd (128.023, 3345.1234); + test (d, u.x); + + e[0] = u.a[0]; + + if (checkVd (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movupd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movupd-1.c new file mode 100644 index 000000000..6533b4c4b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movupd-1.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (double *e) +{ + return _mm_loadu_pd (e); +} + +static void +TEST (void) +{ + union128d u; + double e[2] = {2134.3343,1234.635654}; + + u.x = test (e); + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movupd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movupd-2.c new file mode 100644 index 000000000..c66e70c4d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-movupd-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static void +__attribute__((noinline, unused)) +test (double *e, __m128d a) +{ + _mm_storeu_pd (e, a); +} + +static void +TEST (void) +{ + union128d u; + double e[2] = {0.0}; + + u.x = _mm_set_pd (2134.3343,1234.635654); + + test (e, u.x); + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-mul-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-mul-1.c new file mode 100644 index 000000000..9cdc12763 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-mul-1.c @@ -0,0 +1,214 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O3 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <stdlib.h> + +/* mingw runtime don't provide random(). */ +#ifdef __MINGW32__ +#define random rand +#endif + +#define N 512 +static short a1[N], a2[N], a3[N]; +static unsigned short b1[N], b2[N], b3[N]; +static int c1[N], c2[N], c3[N]; +static unsigned int d1[N], d2[N], d3[N]; +static long long e1[N], e2[N], e3[N]; +static unsigned long long g1[N], g2[N], g3[N]; + +__attribute__((noinline, noclone)) void +f1 (void) +{ + int i; + for (i = 0; i < N; ++i) + a1[i] = a2[i] * a3[i]; +} + +__attribute__((noinline, noclone)) void +f2 (void) +{ + int i; + for (i = 0; i < N; ++i) + b1[i] = b2[i] * b3[i]; +} + +__attribute__((noinline, noclone)) void +f3 (void) +{ + int i; + for (i = 0; i < N; ++i) + c1[i] = c2[i] * c3[i]; +} + +__attribute__((noinline, noclone)) void +f4 (void) +{ + int i; + for (i = 0; i < N; ++i) + d1[i] = d2[i] * d3[i]; +} + +__attribute__((noinline, noclone)) void +f5 (void) +{ + int i; + for (i = 0; i < N; ++i) + e1[i] = e2[i] * e3[i]; +} + +__attribute__((noinline, noclone)) void +f6 (void) +{ + int i; + for (i = 0; i < N; ++i) + g1[i] = g2[i] * g3[i]; +} + +__attribute__((noinline, noclone)) void +f7 (void) +{ + int i; + for (i = 0; i < N; ++i) + c1[i] = a2[i] * a3[i]; +} + +__attribute__((noinline, noclone)) void +f8 (void) +{ + int i; + for (i = 0; i < N; ++i) + d1[i] = (unsigned int) b2[i] * b3[i]; +} + +__attribute__((noinline, noclone)) void +f9 (void) +{ + int i; + for (i = 0; i < N; ++i) + e1[i] = (long long) c2[i] * (long long) c3[i]; +} + +__attribute__((noinline, noclone)) void +f10 (void) +{ + int i; + for (i = 0; i < N; ++i) + g1[i] = (unsigned long long) d2[i] * (unsigned long long) d3[i]; +} + +__attribute__((noinline, noclone)) int +f11 (void) +{ + int i, r = 0; + for (i = 0; i < N; ++i) + r += a2[i] * a3[i]; + return r; +} + +__attribute__((noinline, noclone)) unsigned int +f12 (void) +{ + int i; + unsigned r = 0; + for (i = 0; i < N; ++i) + r += (unsigned int) b2[i] * b3[i]; + return r; +} + +__attribute__((noinline, noclone)) long long +f13 (void) +{ + int i; + long long r = 0; + for (i = 0; i < N; ++i) + r += (long long) c2[i] * (long long) c3[i]; + return r; +} + +__attribute__((noinline, noclone)) unsigned long long +f14 (void) +{ + int i; + unsigned long long r = 0; + for (i = 0; i < N; ++i) + r += (unsigned long long) d2[i] * (unsigned long long) d3[i]; + return r; +} + +static void +TEST (void) +{ + int i; + int s1 = 0; + unsigned int s2 = 0; + long long s3 = 0; + unsigned long long s4 = 0; + for (i = 0; i < N; ++i) + { + asm volatile ("" : : "r" (&s1) : "memory"); + asm volatile ("" : : "r" (&s2) : "memory"); + asm volatile ("" : : "r" (&s3) : "memory"); + asm volatile ("" : : "r" (&s4) : "memory"); + b2[i] = (int) random (); + b3[i] = (int) random (); + a2[i] = b2[i]; + a3[i] = b3[i]; + d2[i] = (((int) random ()) << 16) | b2[i]; + d3[i] = (((int) random ()) << 16) | b3[i]; + c2[i] = d2[i]; + c3[i] = d3[i]; + s1 += a2[i] * a3[i]; + s2 += (unsigned int) b2[i] * b3[i]; + s3 += (long long) c2[i] * (long long) c3[i]; + s4 += (unsigned long long) d2[i] * (unsigned long long) d3[i]; + } + f1 (); + f2 (); + f3 (); + f4 (); + f5 (); + f6 (); + for (i = 0; i < N; ++i) + { + if (a1[i] != (short) (a2[i] * a3[i])) + abort (); + if (b1[i] != (unsigned short) (b2[i] * b3[i])) + abort (); + if (c1[i] != c2[i] * c3[i]) + abort (); + if (d1[i] != d2[i] * d3[i]) + abort (); + if (e1[i] != e2[i] * e3[i]) + abort (); + if (g1[i] != g2[i] * g3[i]) + abort (); + } + f7 (); + f8 (); + f9 (); + f10 (); + for (i = 0; i < N; ++i) + { + if (c1[i] != a2[i] * a3[i]) + abort (); + if (d1[i] != b2[i] * b3[i]) + abort (); + if (e1[i] != (long long) c2[i] * (long long) c3[i]) + abort (); + if (g1[i] != (unsigned long long) d2[i] * (unsigned long long) d3[i]) + abort (); + } + if (f11 () != s1 || f12 () != s2 || f13 () != s3 || f14 () != s4) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-mulpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-mulpd-1.c new file mode 100644 index 000000000..737730e6f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-mulpd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_mul_pd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] * s2.a[0]; + e[1] = s1.a[1] * s2.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-mulsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-mulsd-1.c new file mode 100644 index 000000000..777b439f1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-mulsd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_mul_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] * s2.a[0]; + e[1] = s1.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-orpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-orpd-1.c new file mode 100644 index 000000000..1d88474aa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-orpd-1.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_or_pd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + + union + { + double d[2]; + long long ll[2]; + }d1, d2, e; + + s1.x = _mm_set_pd (1234, 44386); + s2.x = _mm_set_pd (5198, 23098); + + _mm_storeu_pd (d1.d, s1.x); + _mm_storeu_pd (d2.d, s2.x); + + u.x = test (s1.x, s2.x); + + e.ll[0] = d1.ll[0] | d2.ll[0]; + e.ll[1] = d1.ll[1] | d2.ll[1]; + + if (check_union128d (u, e.d)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-packssdw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-packssdw-1.c new file mode 100644 index 000000000..187b880db --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-packssdw-1.c @@ -0,0 +1,58 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_packs_epi32 (s1, s2); +} + +static void +TEST (void) +{ + union128i_d s1, s2; + union128i_w u; + short e[8]; + int i; + + s1.x = _mm_set_epi32 (2134, -128, 655366, 9999); + s2.x = _mm_set_epi32 (41124, 234, 2, -800900); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + { + if (s1.a[i] > 32767) + e[i] = 32767; + else if (s1.a[i] < -32768) + e[i] = -32768; + else + e[i] = s1.a[i]; + } + + for (i = 0; i < 4; i++) + { + if (s2.a[i] > 32767) + e[i+4] = 32767; + else if (s2.a[i] < -32768) + e[i+4] = -32768; + else + e[i+4] = s2.a[i]; + } + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-packsswb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-packsswb-1.c new file mode 100644 index 000000000..3643a8ac8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-packsswb-1.c @@ -0,0 +1,58 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_packs_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w s1, s2; + union128i_b u; + char e[16]; + int i; + + s1.x = _mm_set_epi16 (2134, -128, 1234, 6354, 1002, 3004, 4050, 9999); + s2.x = _mm_set_epi16 (41124, 234, 2344, 2354, 607, 1, 2, -8009); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + if (s1.a[i] > 127) + e[i] = 127; + else if (s1.a[i] < -128) + e[i] = -128; + else + e[i] = s1.a[i]; + } + + for (i = 0; i < 8; i++) + { + if (s2.a[i] > 127) + e[i+8] = 127; + else if (s2.a[i] < -128) + e[i+8] = -128; + else + e[i+8] = s2.a[i]; + } + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-packuswb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-packuswb-1.c new file mode 100644 index 000000000..6fd00ae6e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-packuswb-1.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_packus_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w s1, s2; + union128i_ub u; + unsigned char e[16]; + int i, tmp; + + s1.x = _mm_set_epi16 (1, 2, 3, 4, -5, -6, -7, -8); + s2.x = _mm_set_epi16 (-9, -10, -11, -12, 13, 14, 15, 16); + u.x = test (s1.x, s2.x); + + for (i=0; i<8; i++) + { + tmp = s1.a[i]<0 ? 0 : s1.a[i]; + tmp = tmp>255 ? 255 : tmp; + e[i] = tmp; + + tmp = s2.a[i]<0 ? 0 : s2.a[i]; + tmp = tmp>255 ? 255 : tmp; + e[i+8] = tmp; + } + + if (check_union128i_ub (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddb-1.c new file mode 100644 index 000000000..faea05cfc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddb-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_add_epi8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_b u, s1, s2; + char e[16]; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddd-1.c new file mode 100644 index 000000000..0c910c8cf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddd-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_add_epi32 (s1, s2); +} + +static void +TEST (void) +{ + union128i_d u, s1, s2; + int e[4]; + int i; + + s1.x = _mm_set_epi32 (30,90,-80,-40); + s2.x = _mm_set_epi32 (76, -100, -34, -78); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddq-1.c new file mode 100644 index 000000000..136397818 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddq-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_add_epi64 (s1, s2); +} + +static void +TEST (void) +{ + union128i_q u, s1, s2; + long long e[2]; + int i; + + s1.x = _mm_set_epi64x (90,-80); + s2.x = _mm_set_epi64x (76, -100); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 2; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddsb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddsb-1.c new file mode 100644 index 000000000..6b2195e66 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddsb-1.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_adds_epi8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_b u, s1, s2; + char e[16]; + int i, tmp; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 16; i++) + { + tmp = s1.a[i] + s2.a[i]; + + if (tmp > 127) + tmp = 127; + if (tmp < -128) + tmp = -128; + + e[i] = tmp; + } + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddsw-1.c new file mode 100644 index 000000000..5fec2f2a4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddsw-1.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_adds_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i, tmp; + + s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15); + s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + tmp = s1.a[i] + s2.a[i]; + + if (tmp > 32767) + tmp = 32767; + if (tmp < -32768) + tmp = -32768; + + e[i] = tmp; + } + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddusb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddusb-1.c new file mode 100644 index 000000000..807287e27 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddusb-1.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_adds_epu8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_b u, s1, s2; + char e[16] = {0}; + int i, tmp; + + s1.x = _mm_set_epi8 (30, 2, 3, 4, 10, 20, 30, 90, 80, 40, 100, 15, 98, 25, 98, 7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 16; i++) + { + tmp = s1.a[i] + s2.a[i]; + + if (tmp > 255) + tmp = -1; + if (tmp < 0) + tmp = 0; + + e[i] = tmp; + } + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddusw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddusw-1.c new file mode 100644 index 000000000..90a226950 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddusw-1.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_adds_epu16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i, tmp; + + s1.x = _mm_set_epi16 (10,20,30,90,80,40,100,15); + s2.x = _mm_set_epi16 (11, 98, 76, 100, 34, 78, 39, 14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + tmp = s1.a[i] + s2.a[i]; + + if (tmp > 65535) + tmp = -1; + + if (tmp < 0) + tmp = 0; + + e[i] = tmp; + } + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddw-1.c new file mode 100644 index 000000000..3ed73299b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-paddw-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_add_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i; + + s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15); + s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i] + s2.a[i]; + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pand-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pand-1.c new file mode 100644 index 000000000..a6a1702d3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pand-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_and_si128 (s1, s2); +} + +static void +TEST (void) +{ + union128i_b u, s1, s2; + char e[16]; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = s1.a[i] & s2.a[i]; + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pandn-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pandn-1.c new file mode 100644 index 000000000..d9c653fd5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pandn-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_andnot_si128 (s1, s2); +} + +static void +TEST (void) +{ + union128i_b u, s1, s2; + char e[16]; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = (~s1.a[i]) & s2.a[i]; + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pavgb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pavgb-1.c new file mode 100644 index 000000000..98b489437 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pavgb-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_avg_epu8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_ub u, s1, s2; + unsigned char e[16]; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,80,40,100,15,98, 25, 98,7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = (s1.a[i] + s2.a[i]+1)>>1; + + if (check_union128i_ub (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pavgw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pavgw-1.c new file mode 100644 index 000000000..4f9bf2199 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pavgw-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_avg_epu16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_uw u, s1, s2; + unsigned short e[8]; + int i; + + s1.x = _mm_set_epi16 (10,20,30,90,80,40,100,15); + s2.x = _mm_set_epi16 (11, 98, 76, 100, 34, 78, 39, 14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = (s1.a[i] + s2.a[i]+1)>>1; + + if (check_union128i_uw (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpeqb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpeqb-1.c new file mode 100644 index 000000000..7db34ba15 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpeqb-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_cmpeq_epi8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_b u, s1, s2; + char e[16]; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,80,40,100,15,98, 25, 98,7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = (s1.a[i] == s2.a[i]) ? -1:0; + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpeqd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpeqd-1.c new file mode 100644 index 000000000..d4018925f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpeqd-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_cmpeq_epi32 (s1, s2); +} + +static void +TEST (void) +{ + union128i_d u, s1, s2; + int e[4]; + int i; + + s1.x = _mm_set_epi32 (98, 25, 98,7); + s2.x = _mm_set_epi32 (88, 44, 33, 229); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = (s1.a[i] == s2.a[i]) ? -1:0; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpeqw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpeqw-1.c new file mode 100644 index 000000000..f3415831e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpeqw-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_cmpeq_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i; + + s1.x = _mm_set_epi16 (20,30,90,80,40,100,15,98); + s2.x = _mm_set_epi16 (34, 78, 39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = (s1.a[i] == s2.a[i]) ? -1:0; + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpgtb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpgtb-1.c new file mode 100644 index 000000000..34c74e8e6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpgtb-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_cmpgt_epi8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_b u, s1, s2; + char e[16]; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,80,40,100,15,98, 25, 98,7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = (s1.a[i] > s2.a[i]) ? -1:0; + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpgtd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpgtd-1.c new file mode 100644 index 000000000..8d0353636 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpgtd-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_cmpgt_epi32 (s1, s2); +} + +static void +TEST (void) +{ + union128i_d u, s1, s2; + int e[4]; + int i; + + s1.x = _mm_set_epi32 (98, 25, 98,7); + s2.x = _mm_set_epi32 (88, 44, 33, 229); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = (s1.a[i] > s2.a[i]) ? -1:0; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpgtw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpgtw-1.c new file mode 100644 index 000000000..835ba365b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pcmpgtw-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_cmpgt_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i; + + s1.x = _mm_set_epi16 (20,30,90,80,40,100,15,98); + s2.x = _mm_set_epi16 (34, 78, 39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = (s1.a[i] > s2.a[i]) ? -1:0; + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pinsrw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pinsrw.c new file mode 100644 index 000000000..16167437c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pinsrw.c @@ -0,0 +1,86 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -msse2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> +#include <string.h> + +#define msk0 0x00 +#define msk1 0x01 +#define msk2 0x02 +#define msk3 0x03 +#define msk4 0x04 +#define msk5 0x05 +#define msk6 0x06 +#define msk7 0x07 + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + unsigned short s[8]; + } res [8], val, tmp; + int masks[8]; + unsigned short ins[4] = { 3, 4, 5, 6 }; + int i; + + val.i[0] = 0x35251505; + val.i[1] = 0x75655545; + val.i[2] = 0xB5A59585; + val.i[3] = 0xF5E5D5C5; + + /* Check pinsrw imm8, r32, xmm. */ + res[0].x = _mm_insert_epi16 (val.x, ins[0], msk0); + res[1].x = _mm_insert_epi16 (val.x, ins[0], msk1); + res[2].x = _mm_insert_epi16 (val.x, ins[0], msk2); + res[3].x = _mm_insert_epi16 (val.x, ins[0], msk3); + res[4].x = _mm_insert_epi16 (val.x, ins[0], msk4); + res[5].x = _mm_insert_epi16 (val.x, ins[0], msk5); + res[6].x = _mm_insert_epi16 (val.x, ins[0], msk6); + res[7].x = _mm_insert_epi16 (val.x, ins[0], msk7); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + masks[4] = msk4; + masks[5] = msk5; + masks[6] = msk6; + masks[7] = msk7; + + for (i = 0; i < 8; i++) + { + tmp.x = val.x; + tmp.s[masks[i]] = ins[0]; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } + + /* Check pinsrw imm8, m16, xmm. */ + for (i = 0; i < 8; i++) + { + res[i].x = _mm_insert_epi16 (val.x, ins[i % 2], msk0); + masks[i] = msk0; + } + + for (i = 0; i < 8; i++) + { + tmp.x = val.x; + tmp.s[masks[i]] = ins[i % 2]; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmaddwd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmaddwd-1.c new file mode 100644 index 000000000..c26d02b39 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmaddwd-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_madd_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w s1, s2; + union128i_d u; + int e[4]; + int i; + + s1.x = _mm_set_epi16 (2134,3343,1234,6354, 1, 3, 4, 5); + s2.x = _mm_set_epi16 (41124,234,2344,2354,9, -1, -8, -10); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = (s1.a[i*2] * s2.a[i*2])+(s1.a[(i*2) + 1] * s2.a[(i*2) + 1]); + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmaxsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmaxsw-1.c new file mode 100644 index 000000000..836f2c6d8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmaxsw-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_max_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i; + + s1.x = _mm_set_epi16 (1,2,3,4,5,6,7,8); + s2.x = _mm_set_epi16 (8,7,6,5,4,3,2,1); + u.x = test (s1.x, s2.x); + + for (i=0; i<8; i++) + e[i] = s1.a[i]>s2.a[i]?s1.a[i]:s2.a[i]; + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmaxub-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmaxub-1.c new file mode 100644 index 000000000..6447aa30b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmaxub-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_max_epu8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_ub u, s1, s2; + unsigned char e[16]; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16); + s2.x = _mm_set_epi8 (16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1); + u.x = test (s1.x, s2.x); + + for (i=0; i<16; i++) + e[i] = s1.a[i]>s2.a[i]?s1.a[i]:s2.a[i]; + + if (check_union128i_ub (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pminsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pminsw-1.c new file mode 100644 index 000000000..5c553d1b6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pminsw-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_min_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i; + + s1.x = _mm_set_epi16 (1,2,3,4,5,6,7,8); + s2.x = _mm_set_epi16 (8,7,6,5,4,3,2,1); + u.x = test (s1.x, s2.x); + + for (i=0; i<8; i++) + e[i] = s1.a[i]<s2.a[i]?s1.a[i]:s2.a[i]; + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pminub-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pminub-1.c new file mode 100644 index 000000000..6c4598cc4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pminub-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_min_epu8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_ub u, s1, s2; + unsigned char e[16]; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16); + s2.x = _mm_set_epi8 (16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1); + u.x = test (s1.x, s2.x); + + for (i=0; i<16; i++) + e[i] = s1.a[i]<s2.a[i]?s1.a[i]:s2.a[i]; + + if (check_union128i_ub (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmovmskb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmovmskb-1.c new file mode 100644 index 000000000..fce068c09 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmovmskb-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_movemask_epi8 (s1); +} + +static void +TEST (void) +{ + union128i_b s1; + int i, u, e=0; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7); + u = test (s1.x); + + for (i = 0; i < 16; i++) + if (s1.a[i] & (1<<7)) + e = e | (1<<i); + + if (checkVi (&u, &e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmulhuw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmulhuw-1.c new file mode 100644 index 000000000..f77ec6afd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmulhuw-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_mulhi_epu16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_uw u, s1, s2; + unsigned short e[8]; + int i, tmp; + + s1.x = _mm_set_epi16 (10,2067,3033,90,80,40,1000,15); + s2.x = _mm_set_epi16 (11, 9834, 7444, 10222, 34, 7833, 39, 14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + tmp = s1.a[i] * s2.a[i]; + + e[i] = (tmp & 0xffff0000)>>16; + } + + if (check_union128i_uw (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmulhw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmulhw-1.c new file mode 100644 index 000000000..ac3838930 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmulhw-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_mulhi_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i, tmp; + + s1.x = _mm_set_epi16 (10,2067,-3033,90,80,40,-1000,15); + s2.x = _mm_set_epi16 (11, 9834, 7444, -10222, 34, -7833, 39, 14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + tmp = s1.a[i] * s2.a[i]; + + e[i] = (tmp & 0xffff0000)>>16; + } + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmullw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmullw-1.c new file mode 100644 index 000000000..38014b788 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmullw-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_mullo_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i, tmp; + + s1.x = _mm_set_epi16 (10,2067,-3033,90,80,40,-1000,15); + s2.x = _mm_set_epi16 (11, 9834, 7444, -10222, 34, -7833, 39, 14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + tmp = s1.a[i] * s2.a[i]; + + e[i] = tmp; + } + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmuludq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmuludq-1.c new file mode 100644 index 000000000..51540c143 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pmuludq-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_mul_epu32 (s1, s2); +} + +static void +TEST (void) +{ + union128i_d s1, s2; + union128i_q u; + long long e[2]; + + s1.x = _mm_set_epi32 (10,2067,3033,905); + s2.x = _mm_set_epi32 (11, 9834, 7444, 10222); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] * s2.a[0]; + e[1] = s1.a[2] * s2.a[2]; + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-por-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-por-1.c new file mode 100644 index 000000000..a5a0183bb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-por-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_or_si128 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i; + + s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15); + s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + e[i] = s1.a[i] | s2.a[i]; + } + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psadbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psadbw-1.c new file mode 100644 index 000000000..83e83cb16 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psadbw-1.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_sad_epu8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_ub s1, s2; + union128i_w u; + short e[8] = {0}; + unsigned char tmp[16]; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16); + s2.x = _mm_set_epi8 (16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 16; i++) + tmp [i] = __builtin_abs (s1.a[i] - s2.a[i]); + + for (i = 0; i < 8; i++) + e[0] += tmp[i]; + + for (i = 8; i < 16; i++) + e[4] += tmp[i]; + + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pshufd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pshufd-1.c new file mode 100644 index 000000000..b0f8834c8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pshufd-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 0xec + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_shuffle_epi32 (s1, N); +} + +static void +TEST (void) +{ + union128i_d u, s1; + int e[4] = {0}; + int i; + + s1.x = _mm_set_epi32 (16,15,14,13); + u.x = test (s1.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[((N & (0x3<<(2*i)))>>(2*i))]; + + if (check_union128i_d(u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pshufhw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pshufhw-1.c new file mode 100644 index 000000000..cfff7577d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pshufhw-1.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 0xec + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_shufflehi_epi16 (s1, N); +} + +static void +TEST (void) +{ + union128i_q s1; + union128i_w u; + short e[8] = {0}; + int i; + int m1[4] = {0x3, 0x3<<2, 0x3<<4, 0x3<<6}; + int m2[4]; + + s1.x = _mm_set_epi64x (0xabcde,0xef58a234); + u.x = test (s1.x); + + for (i = 0; i < 4; i++) + e[i] = (s1.a[0]>>(16 * i)) & 0xffff; + + for (i = 0; i < 4; i++) + m2[i] = (N & m1[i])>>(2*i); + + for (i = 0; i < 4; i++) + e[i+4] = (s1.a[1] >> (16 * m2[i])) & 0xffff; + + if (check_union128i_w(u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pshuflw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pshuflw-1.c new file mode 100644 index 000000000..9915ca4ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pshuflw-1.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 0xec + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_shufflelo_epi16 (s1, N); +} + +static void +TEST (void) +{ + union128i_q s1; + union128i_w u; + short e[8] = {0}; + int i; + int m1[4] = {0x3, 0x3<<2, 0x3<<4, 0x3<<6}; + int m2[4]; + + s1.x = _mm_set_epi64x (0xabcde,0xef58a234); + u.x = test (s1.x); + + for (i = 0; i < 4; i++) + e[i+4] = (s1.a[1]>>(16 * i)) & 0xffff; + + for (i = 0; i < 4; i++) + m2[i] = (N & m1[i])>>(2*i); + + for (i = 0; i < 4; i++) + e[i] = (s1.a[0] >> (16 * m2[i])) & 0xffff; + + if (check_union128i_w(u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pslld-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pslld-1.c new file mode 100644 index 000000000..31474e323 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pslld-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 0xf + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_slli_epi32 (s1, N); +} + +static void +TEST (void) +{ + union128i_d u, s; + int e[4] = {0}; + int i; + + s.x = _mm_set_epi32 (1, -2, 3, 4); + + u.x = test (s.x); + + if (N < 32) + for (i = 0; i < 4; i++) + e[i] = s.a[i] << N; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pslld-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pslld-2.c new file mode 100644 index 000000000..17411415b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pslld-2.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i c) +{ + return _mm_sll_epi32 (s1, c); +} + +static void +TEST (void) +{ + union128i_d u, s; + union128i_q c; + int e[4] = {0}; + int i; + + s.x = _mm_set_epi32 (2, -3, 0x7000, 0x9000); + c.x = _mm_set_epi64x (12, 23); + + u.x = test (s.x, c.x); + + if (c.a[0] < 32) + for (i = 0; i < 4; i++) + e[i] = s.a[i] << c.a[0]; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pslldq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pslldq-1.c new file mode 100644 index 000000000..2d4dc1b9e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pslldq-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 0x5 + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_slli_si128 (s1, N); +} + +static void +TEST (void) +{ + union128i_b u, s; + char src[16] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + char e[16] = {0}; + int i; + + s.x = _mm_loadu_si128 ((__m128i *)src); + + u.x = test (s.x); + + for (i = 0; i < 16-N; i++) + e[i+N] = src[i]; + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psllq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psllq-1.c new file mode 100644 index 000000000..a07cfc4da --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psllq-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 60 + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_slli_epi64 (s1, N); +} + +static void +TEST (void) +{ + union128i_q u, s; + long long e[2] = {0}; + int i; + + s.x = _mm_set_epi64x (-1, 0xf); + + u.x = test (s.x); + + if (N < 64) + for (i = 0; i < 2; i++) + e[i] = s.a[i] << N; + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psllq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psllq-2.c new file mode 100644 index 000000000..6792fd325 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psllq-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i c) +{ + return _mm_sll_epi64 (s1, c); +} + +static void +TEST (void) +{ + union128i_q u, s, c; + long long e[2] = {0}; + int i; + + s.x = _mm_set_epi64x (-1, 0xf); + c.x = _mm_set_epi64x (60,50); + + u.x = test (s.x, c.x); + + if (c.a[0] < 64) + for (i = 0; i < 2; i++) + e[i] = s.a[i] << c.a[0]; + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psllw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psllw-1.c new file mode 100644 index 000000000..3153ec455 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psllw-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_slli_epi16 (s1, N); +} + +static void +TEST (void) +{ + union128i_w u, s; + short e[8] = {0}; + int i; + + s.x = _mm_set_epi16 (1, 2, 3, 4, 5, 6, 0x7000, 0x9000); + + u.x = test (s.x); + + if (N < 16) + for (i = 0; i < 8; i++) + e[i] = s.a[i] << N; + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psllw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psllw-2.c new file mode 100644 index 000000000..e3170405e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psllw-2.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i c) +{ + return _mm_sll_epi16 (s1, c); +} + +static void +TEST (void) +{ + union128i_w u, s; + union128i_q c; + short e[8] = {0}; + int i; + + s.x = _mm_set_epi16 (1, 2, 3, 4, 5, 6, 0x7000, 0x9000); + c.x = _mm_set_epi64x (12, 13); + + u.x = test (s.x, c.x); + + if (c.a[0] < 16) + for (i = 0; i < 8; i++) + e[i] = s.a[i] << c.a[0]; + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrad-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrad-1.c new file mode 100644 index 000000000..ea27439ae --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrad-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 0xf + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_srai_epi32 (s1, N); +} + +static void +TEST (void) +{ + union128i_d u, s; + int e[4] = {0}; + int i; + + s.x = _mm_set_epi32 (1, -2, 3, 4); + + u.x = test (s.x); + + if (N < 32) + for (i = 0; i < 4; i++) + e[i] = s.a[i] >> N; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrad-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrad-2.c new file mode 100644 index 000000000..0b8d5b888 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrad-2.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i count) +{ + return _mm_sra_epi32 (s1, count); +} + +static void +TEST (void) +{ + union128i_d u, s; + union128i_q c; + int e[4] = {0}; + int i; + + s.x = _mm_set_epi32 (1, -2, 3, 4); + c.x = _mm_set_epi64x (16, 29); + + u.x = test (s.x, c.x); + + if (c.a[0] < 32) + for (i = 0; i < 4; i++) + e[i] = s.a[i] >> c.a[0]; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psraw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psraw-1.c new file mode 100644 index 000000000..49db1b2c6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psraw-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_srai_epi16 (s1, N); +} + +static void +TEST (void) +{ + union128i_w u, s; + short e[8] = {0}; + int i; + + s.x = _mm_set_epi16 (1, -2, 3, 4, -5, 6, 0x7000, 0x9000); + + u.x = test (s.x); + + if (N < 16) + for (i = 0; i < 8; i++) + e[i] = s.a[i] >> N; + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psraw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psraw-2.c new file mode 100644 index 000000000..8aa6681b3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psraw-2.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i c) +{ + return _mm_sra_epi16 (s1, c); +} + +static void +TEST (void) +{ + union128i_w u, s; + union128i_q c; + short e[8] = {0}; + int i; + + s.x = _mm_set_epi16 (1, -2, 3, 4, 5, 6, -0x7000, 0x9000); + c.x = _mm_set_epi64x (12, 13); + + u.x = test (s.x, c.x); + + if (c.a[0] < 16) + for (i = 0; i < 8; i++) + e[i] = s.a[i] >> c.a[0]; + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrld-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrld-1.c new file mode 100644 index 000000000..d310fc452 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrld-1.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 0xf + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_srli_epi32 (s1, N); +} + +static void +TEST (void) +{ + union128i_d u, s; + int e[4] = {0}; + unsigned int tmp; + int i; + + s.x = _mm_set_epi32 (1, -2, 3, 4); + + u.x = test (s.x); + + if (N < 32) + for (i = 0; i < 4; i++) { + tmp = s.a[i]; + e[i] = tmp >> N; + } + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrld-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrld-2.c new file mode 100644 index 000000000..a5ddce1f3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrld-2.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i c) +{ + return _mm_srl_epi32 (s1, c); +} + +static void +TEST (void) +{ + union128i_d u, s; + union128i_q c; + int e[4] = {0}; + unsigned int tmp; + int i; + + s.x = _mm_set_epi32 (2, -3, 0x7000, 0x9000); + c.x = _mm_set_epi64x (12, 23); + + u.x = test (s.x, c.x); + + if (c.a[0] < 32) + for (i = 0; i < 4; i++) { + tmp = s.a[i]; + e[i] = tmp >> c.a[0]; + } + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrldq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrldq-1.c new file mode 100644 index 000000000..c4484bc30 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrldq-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 0x5 + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_srli_si128 (s1, N); +} + +static void +TEST (void) +{ + union128i_b u, s; + char src[16] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}; + char e[16] = {0}; + int i; + + s.x = _mm_loadu_si128 ((__m128i *)src); + + u.x = test (s.x); + + for (i = 0; i < 16-N; i++) + e[i] = src[i+N]; + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrlq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrlq-1.c new file mode 100644 index 000000000..12ace3775 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrlq-1.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 60 + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_srli_epi64 (s1, N); +} + +static void +TEST (void) +{ + union128i_q u, s; + long long e[2] = {0}; + unsigned long long tmp; + int i; + + s.x = _mm_set_epi64x (-1, 0xf); + + u.x = test (s.x); + + if (N < 64) + for (i = 0; i < 2; i++) { + tmp = s.a[i]; + e[i] = tmp >> N; + } + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrlq-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrlq-2.c new file mode 100644 index 000000000..ee4fb0472 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrlq-2.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i c) +{ + return _mm_srl_epi64 (s1, c); +} + +static void +TEST (void) +{ + union128i_q u, s, c; + long long e[2] = {0}; + unsigned long long tmp; + int i; + + s.x = _mm_set_epi64x (-1, 0xf); + c.x = _mm_set_epi64x (60,50); + + u.x = test (s.x, c.x); + + if (c.a[0] < 64) + for (i = 0; i < 2; i++){ + tmp = s.a[i]; + e[i] =tmp >> c.a[0]; + } + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrlw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrlw-1.c new file mode 100644 index 000000000..d51ee45ba --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrlw-1.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1) +{ + return _mm_srli_epi16 (s1, N); +} + +static void +TEST (void) +{ + union128i_w u, s; + short e[8] = {0}; + unsigned short tmp; + int i; + + s.x = _mm_set_epi16 (1, -2, 3, -4, 5, 6, 0x7000, 0x9000); + + u.x = test (s.x); + + if (N < 16) + for (i = 0; i < 8; i++) + { + tmp = s.a[i]; + e[i] = tmp >> N; + } + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrlw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrlw-2.c new file mode 100644 index 000000000..0d4004c3e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psrlw-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i c) +{ + return _mm_srl_epi16 (s1, c); +} + +static void +TEST (void) +{ + union128i_w u, s; + union128i_q c; + short e[8] = {0}; + unsigned short tmp; + int i; + + s.x = _mm_set_epi16 (1, -2, 3, 4, 5, 6, -0x7000, 0x9000); + c.x = _mm_set_epi64x (12, 13); + + u.x = test (s.x, c.x); + + if (c.a[0] < 16) + for (i = 0; i < 8; i++) + { + tmp = s.a[i]; + e[i] = tmp >> c.a[0]; + } + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubb-1.c new file mode 100644 index 000000000..a416f57a5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubb-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_sub_epi8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_b u, s1, s2; + char e[16]; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = s1.a[i] - s2.a[i]; + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubd-1.c new file mode 100644 index 000000000..9700a7791 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubd-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_sub_epi32 (s1, s2); +} + +static void +TEST (void) +{ + union128i_d u, s1, s2; + int e[4]; + int i; + + s1.x = _mm_set_epi32 (30,90,-80,-40); + s2.x = _mm_set_epi32 (76, -100, -34, -78); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + e[i] = s1.a[i] - s2.a[i]; + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubq-1.c new file mode 100644 index 000000000..a31ec689c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubq-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_sub_epi64 (s1, s2); +} + +static void +TEST (void) +{ + union128i_q u, s1, s2; + long long e[2]; + int i; + + s1.x = _mm_set_epi64x (90,-80); + s2.x = _mm_set_epi64x (76, -100); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 2; i++) + e[i] = s1.a[i] - s2.a[i]; + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubsb-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubsb-1.c new file mode 100644 index 000000000..88308cb10 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubsb-1.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_subs_epi8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_b u, s1, s2; + char e[16]; + int i, tmp; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 16; i++) + { + tmp = s1.a[i] - s2.a[i]; + + if (tmp > 127) + tmp = 127; + if (tmp < -128) + tmp = -128; + + e[i] = tmp; + } + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubsw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubsw-1.c new file mode 100644 index 000000000..a0f421538 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubsw-1.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_subs_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i, tmp; + + s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15); + s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + tmp = s1.a[i] - s2.a[i]; + + if (tmp > 32767) + tmp = 32767; + if (tmp < -32768) + tmp = -32768; + + e[i] = tmp; + } + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubw-1.c new file mode 100644 index 000000000..dbf08ade1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-psubw-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_sub_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i; + + s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15); + s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + e[i] = s1.a[i] - s2.a[i]; + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckhbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckhbw-1.c new file mode 100644 index 000000000..33f30202d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckhbw-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_unpackhi_epi8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_b u, s1, s2; + char e[16]; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + e[2*i] = s1.a[8+i]; + e[2*i + 1] = s2.a[8+i]; + } + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckhdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckhdq-1.c new file mode 100644 index 000000000..26689aa43 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckhdq-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_unpackhi_epi32 (s1, s2); +} + +static void +TEST (void) +{ + union128i_d u, s1, s2; + int e[4]; + int i; + + s1.x = _mm_set_epi32 (10,20,-80,-40); + s2.x = _mm_set_epi32 (11, -34, -78, -39); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 2; i++) + { + e[2*i] = s1.a[2+i]; + e[2*i+1] = s2.a[2+i]; + } + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckhqdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckhqdq-1.c new file mode 100644 index 000000000..4dbd46bda --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckhqdq-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_unpackhi_epi64 (s1, s2); +} + +static void +TEST (void) +{ + union128i_q u, s1, s2; + long long e[2]; + + s1.x = _mm_set_epi64x (10,-40); + s2.x = _mm_set_epi64x (1134, -7839); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[1]; + e[1] = s2.a[1]; + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckhwd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckhwd-1.c new file mode 100644 index 000000000..11fd91e20 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckhwd-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_unpackhi_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i; + + s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15); + s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + { + e[2*i] = s1.a[4+i]; + e[2*i+1] = s2.a[4+i]; + } + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpcklbw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpcklbw-1.c new file mode 100644 index 000000000..d3d5a71aa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpcklbw-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_unpacklo_epi8 (s1, s2); +} + +static void +TEST (void) +{ + union128i_b u, s1, s2; + char e[16]; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 8; i++) + { + e[2*i] = s1.a[i]; + e[2*i + 1] = s2.a[i]; + } + + if (check_union128i_b (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckldq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckldq-1.c new file mode 100644 index 000000000..c24ee1ee5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpckldq-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_unpacklo_epi32 (s1, s2); +} + +static void +TEST (void) +{ + union128i_d u, s1, s2; + int e[4]; + int i; + + s1.x = _mm_set_epi32 (10,20,-80,-40); + s2.x = _mm_set_epi32 (11, -34, -78, -39); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 2; i++) + { + e[2*i] = s1.a[i]; + e[2*i+1] = s2.a[i]; + } + + if (check_union128i_d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpcklqdq-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpcklqdq-1.c new file mode 100644 index 000000000..ce9b88599 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpcklqdq-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_unpacklo_epi64 (s1, s2); +} + +static void +TEST (void) +{ + union128i_q u, s1, s2; + long long e[2]; + + s1.x = _mm_set_epi64x (10,-40); + s2.x = _mm_set_epi64x (1134, -7839); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0]; + e[1] = s2.a[0]; + + if (check_union128i_q (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpcklwd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpcklwd-1.c new file mode 100644 index 000000000..6736186a0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-punpcklwd-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_unpacklo_epi16 (s1, s2); +} + +static void +TEST (void) +{ + union128i_w u, s1, s2; + short e[8]; + int i; + + s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15); + s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 4; i++) + { + e[2*i] = s1.a[i]; + e[2*i+1] = s2.a[i]; + } + + if (check_union128i_w (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pxor-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pxor-1.c new file mode 100644 index 000000000..c9d2b90b7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-pxor-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128i +__attribute__((noinline, unused)) +test (__m128i s1, __m128i s2) +{ + return _mm_xor_si128 (s1, s2); +} + +static void +TEST (void) +{ + union128i_ub u, s1, s2; + unsigned char e[16] = {0}; + int i; + + s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,80,40,100,15,98, 25, 98,7); + s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119); + u.x = test (s1.x, s2.x); + + for (i = 0; i < 16; i++) + e[i] = s1.a[i] ^ s2.a[i]; + + if (check_union128i_ub (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c new file mode 100644 index 000000000..c1f5d0f74 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <emmintrin.h> + +static void +__attribute__((noinline)) +test (unsigned int *v) +{ + union + { + __m128i x; + unsigned int i[4]; + } u; + unsigned int i; + + u.x = _mm_set_epi32 (v[3], v[2], v[1], v[0]); + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]); +#endif + abort (); + } +} + +static void +sse2_test (void) +{ + unsigned int v[4] + = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c new file mode 100644 index 000000000..ac32015a7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <emmintrin.h> + +static void +__attribute__((noinline)) +test (unsigned long long *v) +{ + union + { + __m128i x; + unsigned long long i[2]; + } u; + unsigned int i; + + u.x = _mm_set_epi64x (v[1], v[0]); + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]); +#endif + abort (); + } +} + +static void +sse2_test (void) +{ + unsigned long long v[2] + = { 0x7B5B546573745665LL, 0x63746F725D53475DLL }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-1.c new file mode 100644 index 000000000..cc0af7c9f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#define CHECK_H "sse2-check.h" +#define TEST sse2_test + +#include "set-v16qi-1.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-2.c new file mode 100644 index 000000000..01f2699b7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#define CHECK_H "sse2-check.h" +#define TEST sse2_test + +#include "set-v16qi-2.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-3.c new file mode 100644 index 000000000..3c3ae26fb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-3.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#define CHECK_H "sse2-check.h" +#define TEST sse2_test + +#include "set-v16qi-3.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1.c new file mode 100644 index 000000000..e4231a4f7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#define CHECK_H "sse2-check.h" +#define TEST sse2_test + +#include "set-v8hi-1.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c new file mode 100644 index 000000000..b2a8778db --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mtune=core2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#define CHECK_H "sse2-check.h" +#define TEST sse2_test + +#include "set-v8hi-1.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2.c new file mode 100644 index 000000000..2d500b791 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#define CHECK_H "sse2-check.h" +#define TEST sse2_test + +#include "set-v8hi-2.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c new file mode 100644 index 000000000..1afe68bcf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mtune=core2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#define CHECK_H "sse2-check.h" +#define TEST sse2_test + +#include "set-v8hi-2.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-shufpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-shufpd-1.c new file mode 100644 index 000000000..0a05680a4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-shufpd-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define N 0xab + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_shuffle_pd (s1, s2, N); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2] = {0.0}; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (453.345635,54646.464356); + u.x = test (s1.x, s2.x); + + e[0] = (N & (1 << 0)) ? s1.a[1] : s1.a[0]; + e[1] = (N & (1 << 1)) ? s2.a[1] : s2.a[0]; + + if (check_union128d(u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-shufps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-shufps-1.c new file mode 100644 index 000000000..6095aaa29 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-shufps-1.c @@ -0,0 +1,58 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#define MASK 0xab + +#include CHECK_H + +#include <emmintrin.h> + +float select4(const float *src, unsigned int control) +{ + switch(control) { + case 0: + return src[0]; + case 1: + return src[1]; + case 2: + return src[2]; + case 3: + return src[3]; + } + return -1; +} + +static __m128 +__attribute__((noinline, unused)) +test (__m128 s1, __m128 s2) +{ + return _mm_shuffle_ps (s1, s2, MASK); +} + +static void +TEST (void) +{ + union128 u, s1, s2; + float e[4] = {0.0}; + + s1.x = _mm_set_ps (1.1, 1.2, 1.3, 1.4); + s2.x = _mm_set_ps (2.1, 2.2, 2.3, 2.4); + u.x = test (s1.x, s2.x); + + e[0] = select4(s1.a, (MASK >> 0) & 0x3); + e[1] = select4(s1.a, (MASK >> 2) & 0x3); + e[2] = select4(s2.a, (MASK >> 4) & 0x3); + e[3] = select4(s2.a, (MASK >> 6) & 0x3); + + if (check_union128(u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-sqrtpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-sqrtpd-1.c new file mode 100644 index 000000000..edbf829e1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-sqrtpd-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> +#include <math.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1) +{ + return _mm_sqrt_pd (s1); +} + +static void +TEST (void) +{ + union128d u, s1; + double e[2]; + int i; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + u.x = test (s1.x); + + for (i = 0; i < 2; i++) + { + __m128d tmp = _mm_load_sd (&s1.a[i]); + tmp = _mm_sqrt_sd (tmp, tmp); + _mm_store_sd (&e[i], tmp); + } + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-subpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-subpd-1.c new file mode 100644 index 000000000..6a91e218a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-subpd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_sub_pd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] - s2.a[0]; + e[1] = s1.a[1] - s2.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-subsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-subsd-1.c new file mode 100644 index 000000000..954f81ad5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-subsd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_sub_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0] - s2.a[0]; + e[1] = s1.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-1.c new file mode 100644 index 000000000..0bf8708f8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-1.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_ucomieq_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_pd (2134.3343,2344.2354); + s2.x = _mm_set_pd (41124.234,2344.2354); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] == s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-2.c new file mode 100644 index 000000000..fd566f059 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-2.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_ucomilt_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_pd (2134.3343,12344.2354); + s2.x = _mm_set_pd (41124.234,2344.2354); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] < s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-3.c new file mode 100644 index 000000000..df9e09bce --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-3.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_ucomile_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d s1, s2; + int d[1] = {0}; + int e[1] = {0}; + + s1.x = _mm_set_pd (2134.3343,12344.2354); + s2.x = _mm_set_pd (41124.234,2344.2354); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] <= s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-4.c new file mode 100644 index 000000000..f65572a4f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-4.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_ucomigt_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_pd (2134.3343,12344.2354); + s2.x = _mm_set_pd (41124.234,2344.2354); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] > s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-5.c new file mode 100644 index 000000000..b08c4416b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-5.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_ucomige_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_pd (2134.3343,12344.2354); + s2.x = _mm_set_pd (41124.234,2344.2354); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] >= s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-6.c new file mode 100644 index 000000000..bb0bee579 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-ucomisd-6.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static int +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_ucomineq_sd (s1, s2); +} + +static void +TEST (void) +{ + union128d s1, s2; + int d[1]; + int e[1]; + + s1.x = _mm_set_pd (2134.3343,12344.2354); + s2.x = _mm_set_pd (41124.234,2344.2354); + d[0] = test (s1.x, s2.x); + e[0] = s1.a[0] != s2.a[0]; + + if (checkVi (d, e, 1)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c new file mode 100644 index 000000000..a2676396c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +#include <emmintrin.h> + +__m128i +foo1 (__m128i s1, __m128i s2) +{ + return _mm_unpackhi_epi64 (s1, s2); +} + +__m128i +foo2 (__m128i s1, __m128i s2) +{ + return _mm_unpacklo_epi64 (s1, s2); +} + +/* { dg-final { scan-assembler "punpcklqdq" } } */ +/* { dg-final { scan-assembler "punpckhqdq" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-unpckhpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-unpckhpd-1.c new file mode 100644 index 000000000..a07302c4b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-unpckhpd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_unpackhi_pd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[1]; + e[1] = s2.a[1]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-unpcklpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-unpcklpd-1.c new file mode 100644 index 000000000..3562edc6f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-unpcklpd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_unpacklo_pd (s1, s2); +} + +static void +TEST (void) +{ + union128d u, s1, s2; + double e[2]; + + s1.x = _mm_set_pd (2134.3343,1234.635654); + s2.x = _mm_set_pd (41124.234,2344.2354); + u.x = test (s1.x, s2.x); + + e[0] = s1.a[0]; + e[1] = s2.a[0]; + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-1.c new file mode 100644 index 000000000..ab2ca5b22 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-1.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <emmintrin.h> + +#define msk0 0 +#define msk1 1 + +static void +sse2_test (void) +{ + union + { + __m128d x; + double d[2]; + } val1; + double res[2]; + int masks[2]; + int i; + + val1.d[0] = 23.; + val1.d[1] = 45; + + res[0] = __builtin_ia32_vec_ext_v2df ((__v2df)val1.x, msk0); + res[1] = __builtin_ia32_vec_ext_v2df ((__v2df)val1.x, msk1); + + masks[0] = msk0; + masks[1] = msk1; + + for (i = 0; i < 2; i++) + if (res[i] != val1.d [masks[i]]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-2.c new file mode 100644 index 000000000..6f5c514aa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <emmintrin.h> + +static void +sse2_test (void) +{ + union + { + __m128i x; + char c[16]; + short s[8]; + int i[4]; + long long ll[2]; + } val1; + long long res[2]; + int masks[2]; + int i; + + for (i = 0; i < 16; i++) + val1.c[i] = i; + + res[0] = __builtin_ia32_vec_ext_v2di ((__v2di)val1.x, 0); + res[1] = __builtin_ia32_vec_ext_v2di ((__v2di)val1.x, 1); + + for (i = 0; i < 2; i++) + masks[i] = i; + + for (i = 0; i < 2; i++) + if (res[i] != val1.ll [masks[i]]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-2a.c new file mode 100644 index 000000000..f230f27d4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-2a.c @@ -0,0 +1,5 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2 -mtune=atom" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-vec-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-3.c new file mode 100644 index 000000000..fa18de5a9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-3.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <emmintrin.h> + +static void +sse2_test (void) +{ + union + { + __m128i x; + char c[16]; + short s[8]; + int i[4]; + long long ll[2]; + } val1; + int res[4]; + int masks[4]; + int i; + + for (i = 0; i < 16; i++) + val1.c[i] = i; + + res[0] = __builtin_ia32_vec_ext_v4si ((__v4si)val1.x, 0); + res[1] = __builtin_ia32_vec_ext_v4si ((__v4si)val1.x, 1); + res[2] = __builtin_ia32_vec_ext_v4si ((__v4si)val1.x, 2); + res[3] = __builtin_ia32_vec_ext_v4si ((__v4si)val1.x, 3); + + for (i = 0; i < 4; i++) + masks[i] = i; + + for (i = 0; i < 4; i++) + if (res[i] != val1.i [masks[i]]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-4.c new file mode 100644 index 000000000..0867e9ca8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-4.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <emmintrin.h> + +static void +sse2_test (void) +{ + union + { + __m128i x; + char c[16]; + short s[8]; + int i[4]; + long long ll[2]; + } val1; + short res[8]; + int masks[8]; + int i; + + for (i = 0; i < 16; i++) + val1.c[i] = i; + + res[0] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 0); + res[1] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 1); + res[2] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 2); + res[3] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 3); + res[4] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 4); + res[5] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 5); + res[6] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 6); + res[7] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 7); + + for (i = 0; i < 8; i++) + masks[i] = i; + + for (i = 0; i < 8; i++) + if (res[i] != val1.s [masks[i]]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-5.c new file mode 100644 index 000000000..c676bbd3a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-5.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <emmintrin.h> + +static void +sse2_test (void) +{ + union + { + __m128i x; + char c[16]; + short s[8]; + int i[4]; + long long ll[2]; + } val1; + char res[16]; + int masks[16]; + int i; + + for (i = 0; i < 16; i++) + val1.c[i] = i; + + res[0] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 0); + res[1] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 1); + res[2] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 2); + res[3] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 3); + res[4] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 4); + res[5] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 5); + res[6] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 6); + res[7] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 7); + res[8] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 8); + res[9] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 9); + res[10] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 10); + res[11] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 11); + res[12] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 12); + res[13] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 13); + res[14] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 14); + res[15] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 15); + + for (i = 0; i < 16; i++) + masks[i] = i; + + for (i = 0; i < 16; i++) + if (res[i] != val1.c [masks[i]]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-6.c new file mode 100644 index 000000000..856c3e70c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-vec-6.c @@ -0,0 +1,70 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <emmintrin.h> +#include <string.h> + +static void +sse2_test (void) +{ + union + { + __m128i x; + char c[16]; + short s[8]; + int i[4]; + long long ll[2]; + } val1, res[16], tmp; + short ins[8] = { 8, 5, 9, 4, 2, 6, 1, 20 }; + int masks[8]; + int i; + + for (i = 0; i < 16; i++) + val1.c[i] = i; + + res[0].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x, + ins[0], 0); + res[1].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x, + ins[0], 1); + res[2].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x, + ins[0], 2); + res[3].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x, + ins[0], 3); + res[4].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x, + ins[0], 4); + res[5].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x, + ins[0], 5); + res[6].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x, + ins[0], 6); + res[7].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x, + ins[0], 7); + + for (i = 0; i < 8; i++) + masks[i] = i; + + for (i = 0; i < 8; i++) + { + tmp.x = val1.x; + tmp.s[masks[i]] = ins[0]; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } + + for (i = 0; i < 8; i++) + { + res[i].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x, + ins[i], 0); + masks[i] = 0; + } + + for (i = 0; i < 8; i++) + { + tmp.x = val1.x; + tmp.s[masks[i]] = ins[i]; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-xorpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-xorpd-1.c new file mode 100644 index 000000000..669f57149 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse2-xorpd-1.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#ifndef CHECK_H +#define CHECK_H "sse2-check.h" +#endif + +#ifndef TEST +#define TEST sse2_test +#endif + +#include CHECK_H + +#include <emmintrin.h> + +static __m128d +__attribute__((noinline, unused)) +test (__m128d s1, __m128d s2) +{ + return _mm_xor_pd (s1, s2); +} + +static void +TEST (void) +{ + union + { + double d[2]; + long long l[2]; + }source1, source2, e; + + union128d u, s1, s2; + int i; + + s1.x = _mm_set_pd (11.1321456, 2.287332); + s2.x = _mm_set_pd (3.37768, 4.43222234); + + _mm_storeu_pd (source1.d, s1.x); + _mm_storeu_pd (source2.d, s2.x); + + u.x = test (s1.x, s2.x); + + for (i = 0; i < 2; i++) + e.l[i] = source1.l[i] ^ source2.l[i]; + + if (check_union128d (u, e.d)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-addsubpd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-addsubpd.c new file mode 100644 index 000000000..147a1ecb8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-addsubpd.c @@ -0,0 +1,99 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse3 } */ +/* { dg-options "-O2 -msse3 -mfpmath=sse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse3-check.h" +#endif + +#ifndef TEST +#define TEST sse3_test +#endif + +#include CHECK_H + +#include <pmmintrin.h> + +static void +sse3_test_addsubpd (double *i1, double *i2, double *r) +{ + __m128d t1 = _mm_loadu_pd (i1); + __m128d t2 = _mm_loadu_pd (i2); + + t1 = _mm_addsub_pd (t1, t2); + + _mm_storeu_pd (r, t1); +} + +static void +sse3_test_addsubpd_subsume (double *i1, double *i2, double *r) +{ + __m128d t1 = _mm_load_pd (i1); + __m128d t2 = _mm_load_pd (i2); + + t1 = _mm_addsub_pd (t1, t2); + + _mm_storeu_pd (r, t1); +} + +static int +chk_pd (double *v1, double *v2) +{ + int i; + int n_fails = 0; + + for (i = 0; i < 2; i++) + if (v1[i] != v2[i]) + n_fails += 1; + + return n_fails; +} + +static double p1[2] __attribute__ ((aligned(16))); +static double p2[2] __attribute__ ((aligned(16))); +static double p3[2]; +static double ck[2]; + +double vals[80] = + { + 100.0, 200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5, + 1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52, + 32.6, 123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44, + 12.16, 52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785, + 541.3, 321.4, 231.4, 531.4, 71., 321., 231., -531., + 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, + 23.45, -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1, + 1.234, 2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912, + -9.32, -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95, + 9.32, 8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95 + }; + +static void +TEST (void) +{ + int i; + int fail = 0; + + for (i = 0; i < 80; i += 4) + { + p1[0] = vals[i+0]; + p1[1] = vals[i+1]; + + p2[0] = vals[i+2]; + p2[1] = vals[i+3]; + + ck[0] = p1[0] - p2[0]; + ck[1] = p1[1] + p2[1]; + + sse3_test_addsubpd (p1, p2, p3); + + fail += chk_pd (ck, p3); + + sse3_test_addsubpd_subsume (p1, p2, p3); + + fail += chk_pd (ck, p3); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-addsubps.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-addsubps.c new file mode 100644 index 000000000..604c40493 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-addsubps.c @@ -0,0 +1,105 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse3 } */ +/* { dg-options "-O2 -msse3 -mfpmath=sse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse3-check.h" +#endif + +#ifndef TEST +#define TEST sse3_test +#endif + +#include CHECK_H + +#include <pmmintrin.h> + +static void +sse3_test_addsubps (float *i1, float *i2, float *r) +{ + __m128 t1 = _mm_loadu_ps (i1); + __m128 t2 = _mm_loadu_ps (i2); + + t1 = _mm_addsub_ps (t1, t2); + + _mm_storeu_ps (r, t1); +} + +static void +sse3_test_addsubps_subsume (float *i1, float *i2, float *r) +{ + __m128 t1 = _mm_load_ps (i1); + __m128 t2 = _mm_load_ps (i2); + + t1 = _mm_addsub_ps (t1, t2); + + _mm_storeu_ps (r, t1); +} + +static int +chk_ps (float *v1, float *v2) +{ + int i; + int n_fails = 0; + + for (i = 0; i < 4; i++) + if (v1[i] != v2[i]) + n_fails += 1; + + return n_fails; +} + +static float p1[4] __attribute__ ((aligned(16))); +static float p2[4] __attribute__ ((aligned(16))); +static float p3[4]; +static float ck[4]; + +static float vals[80] = + { + 100.0, 200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5, + 1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52, + 32.6, 123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44, + 12.16, 52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785, + 541.3, 321.4, 231.4, 531.4, 71., 321., 231., -531., + 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, + 23.45, -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1, + 1.234, 2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912, + -9.32, -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95, + 9.32, 8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95 + }; + +static void +TEST (void) +{ + int i; + int fail = 0; + + for (i = 0; i < 80; i += 8) + { + p1[0] = vals[i+0]; + p1[1] = vals[i+1]; + p1[2] = vals[i+2]; + p1[3] = vals[i+3]; + + p2[0] = vals[i+4]; + p2[1] = vals[i+5]; + p2[2] = vals[i+6]; + p2[3] = vals[i+7]; + + ck[0] = p1[0] - p2[0]; + ck[1] = p1[1] + p2[1]; + ck[2] = p1[2] - p2[2]; + ck[3] = p1[3] + p2[3]; + + sse3_test_addsubps (p1, p2, p3); + + fail += chk_ps (ck, p3); + + sse3_test_addsubps_subsume (p1, p2, p3); + + fail += chk_ps (ck, p3); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-check.h new file mode 100644 index 000000000..5a0a0b1a0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-check.h @@ -0,0 +1,28 @@ +#include <stdio.h> +#include <stdlib.h> +#include "cpuid.h" +#include "sse-os-support.h" + +static void sse3_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + sse3_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run SSE3 test only if host has SSE3 support. */ + if ((ecx & bit_SSE3) && sse_os_support ()) + do_test (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-haddpd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-haddpd.c new file mode 100644 index 000000000..ae4f94a93 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-haddpd.c @@ -0,0 +1,98 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse3 } */ +/* { dg-options "-O2 -msse3 -mfpmath=sse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse3-check.h" +#endif + +#ifndef TEST +#define TEST sse3_test +#endif + +#include CHECK_H +#include <pmmintrin.h> + +static void +sse3_test_haddpd (double *i1, double *i2, double *r) +{ + __m128d t1 = _mm_loadu_pd (i1); + __m128d t2 = _mm_loadu_pd (i2); + + t1 = _mm_hadd_pd (t1, t2); + + _mm_storeu_pd (r, t1); +} + +static void +sse3_test_haddpd_subsume (double *i1, double *i2, double *r) +{ + __m128d t1 = _mm_load_pd (i1); + __m128d t2 = _mm_load_pd (i2); + + t1 = _mm_hadd_pd (t1, t2); + + _mm_storeu_pd (r, t1); +} + +static int +chk_pd (double *v1, double *v2) +{ + int i; + int n_fails = 0; + + for (i = 0; i < 2; i++) + if (v1[i] != v2[i]) + n_fails += 1; + + return n_fails; +} + +static double p1[2] __attribute__ ((aligned(16))); +static double p2[2] __attribute__ ((aligned(16))); +static double p3[2]; +static double ck[2]; + +static double vals[80] = + { + 100.0, 200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5, + 1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52, + 32.6, 123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44, + 12.16, 52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785, + 541.3, 321.4, 231.4, 531.4, 71., 321., 231., -531., + 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, + 23.45, -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1, + 1.234, 2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912, + -9.32, -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95, + 9.32, 8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95 + }; + +static void +TEST (void) +{ + int i; + int fail = 0; + + for (i = 0; i < 80; i += 4) + { + p1[0] = vals[i+0]; + p1[1] = vals[i+1]; + + p2[0] = vals[i+2]; + p2[1] = vals[i+3]; + + ck[0] = p1[0] + p1[1]; + ck[1] = p2[0] + p2[1]; + + sse3_test_haddpd (p1, p2, p3); + + fail += chk_pd (ck, p3); + + sse3_test_haddpd_subsume (p1, p2, p3); + + fail += chk_pd (ck, p3); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-haddps.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-haddps.c new file mode 100644 index 000000000..e944eab66 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-haddps.c @@ -0,0 +1,105 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse3 } */ +/* { dg-options "-O2 -msse3 -mfpmath=sse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse3-check.h" +#endif + +#ifndef TEST +#define TEST sse3_test +#endif + +#include CHECK_H + +#include <pmmintrin.h> + +static void +sse3_test_haddps (float *i1, float *i2, float *r) +{ + __m128 t1 = _mm_loadu_ps (i1); + __m128 t2 = _mm_loadu_ps (i2); + + t1 = _mm_hadd_ps (t1, t2); + + _mm_storeu_ps (r, t1); +} + +static void +sse3_test_haddps_subsume (float *i1, float *i2, float *r) +{ + __m128 t1 = _mm_load_ps (i1); + __m128 t2 = _mm_load_ps (i2); + + t1 = _mm_hadd_ps (t1, t2); + + _mm_storeu_ps (r, t1); +} + +static int +chk_ps(float *v1, float *v2) +{ + int i; + int n_fails = 0; + + for (i = 0; i < 4; i++) + if (v1[i] != v2[i]) + n_fails += 1; + + return n_fails; +} + +static float p1[4] __attribute__ ((aligned(16))); +static float p2[4] __attribute__ ((aligned(16))); +static float p3[4]; +static float ck[4]; + +static float vals[80] = + { + 100.0, 200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5, + 1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52, + 32.6, 123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44, + 12.16, 52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785, + 541.3, 321.4, 231.4, 531.4, 71., 321., 231., -531., + 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, + 23.45, -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1, + 1.234, 2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912, + -9.32, -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95, + 9.32, 8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95 + }; + +static void +TEST () +{ + int i; + int fail = 0; + + for (i = 0; i < 80; i += 8) + { + p1[0] = vals[i+0]; + p1[1] = vals[i+1]; + p1[2] = vals[i+2]; + p1[3] = vals[i+3]; + + p2[0] = vals[i+4]; + p2[1] = vals[i+5]; + p2[2] = vals[i+6]; + p2[3] = vals[i+7]; + + ck[0] = p1[0] + p1[1]; + ck[1] = p1[2] + p1[3]; + ck[2] = p2[0] + p2[1]; + ck[3] = p2[2] + p2[3]; + + sse3_test_haddps (p1, p2, p3); + + fail += chk_ps (ck, p3); + + sse3_test_haddps_subsume (p1, p2, p3); + + fail += chk_ps (ck, p3); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-hsubpd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-hsubpd.c new file mode 100644 index 000000000..37bd60c39 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-hsubpd.c @@ -0,0 +1,98 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse3 } */ +/* { dg-options "-O2 -msse3 -mfpmath=sse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse3-check.h" +#endif + +#ifndef TEST +#define TEST sse3_test +#endif + +#include CHECK_H +#include <pmmintrin.h> + +static void +sse3_test_hsubpd (double *i1, double *i2, double *r) +{ + __m128d t1 = _mm_loadu_pd (i1); + __m128d t2 = _mm_loadu_pd (i2); + + t1 = _mm_hsub_pd (t1, t2); + + _mm_storeu_pd (r, t1); +} + +static void +sse3_test_hsubpd_subsume (double *i1, double *i2, double *r) +{ + __m128d t1 = _mm_load_pd (i1); + __m128d t2 = _mm_load_pd (i2); + + t1 = _mm_hsub_pd (t1, t2); + + _mm_storeu_pd (r, t1); +} + +static int +chk_pd (double *v1, double *v2) +{ + int i; + int n_fails = 0; + + for (i = 0; i < 2; i++) + if (v1[i] != v2[i]) + n_fails += 1; + + return n_fails; +} + +static double p1[2] __attribute__ ((aligned(16))); +static double p2[2] __attribute__ ((aligned(16))); +static double p3[2]; +static double ck[2]; + +static double vals[80] = + { + 100.0, 200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5, + 1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52, + 32.6, 123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44, + 12.16, 52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785, + 541.3, 321.4, 231.4, 531.4, 71., 321., 231., -531., + 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, + 23.45, -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1, + 1.234, 2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912, + -9.32, -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95, + 9.32, 8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95 + }; + +static void +TEST (void) +{ + int i; + int fail = 0; + + for (i = 0; i < 80; i += 4) + { + p1[0] = vals[i+0]; + p1[1] = vals[i+1]; + + p2[0] = vals[i+2]; + p2[1] = vals[i+3]; + + ck[0] = p1[0] - p1[1]; + ck[1] = p2[0] - p2[1]; + + sse3_test_hsubpd (p1, p2, p3); + + fail += chk_pd (ck, p3); + + sse3_test_hsubpd_subsume (p1, p2, p3); + + fail += chk_pd (ck, p3); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-hsubps.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-hsubps.c new file mode 100644 index 000000000..1980638de --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-hsubps.c @@ -0,0 +1,106 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse3 } */ +/* { dg-options "-O2 -msse3 -mfpmath=sse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse3-check.h" +#endif + +#ifndef TEST +#define TEST sse3_test +#endif + +#include CHECK_H +#include <pmmintrin.h> + +static void +sse3_test_hsubps (float *i1, float *i2, float *r) +{ + __m128 t1 = _mm_loadu_ps (i1); + __m128 t2 = _mm_loadu_ps (i2); + + t1 = _mm_hsub_ps (t1, t2); + + _mm_storeu_ps (r, t1); +} + +static void +sse3_test_hsubps_subsume (float *i1, float *i2, float *r) +{ + __m128 t1 = _mm_load_ps (i1); + __m128 t2 = _mm_load_ps (i2); + + t1 = _mm_hsub_ps (t1, t2); + + _mm_storeu_ps (r, t1); +} + +static int +chk_ps (float *v1, float *v2) +{ + int i; + int n_fails = 0; + + for (i = 0; i < 4; i++) { + if (v1[i] != v2[i]) { + n_fails += 1; + } + } + + return n_fails; +} + +static float p1[4] __attribute__ ((aligned(16))); +static float p2[4] __attribute__ ((aligned(16))); +static float p3[4]; +static float ck[4]; + +static float vals[80] = + { + 100.0, 200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5, + 1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52, + 32.6, 123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44, + 12.16, 52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785, + 541.3, 321.4, 231.4, 531.4, 71., 321., 231., -531., + 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, + 23.45, -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1, + 1.234, 2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912, + -9.32, -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95, + 9.32, 8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95 + }; + +static void +TEST (void) +{ + int i; + int fail = 0; + + for (i = 0; i < 80; i += 8) + { + p1[0] = vals[i+0]; + p1[1] = vals[i+1]; + p1[2] = vals[i+2]; + p1[3] = vals[i+3]; + + p2[0] = vals[i+4]; + p2[1] = vals[i+5]; + p2[2] = vals[i+6]; + p2[3] = vals[i+7]; + + ck[0] = p1[0] - p1[1]; + ck[1] = p1[2] - p1[3]; + ck[2] = p2[0] - p2[1]; + ck[3] = p2[2] - p2[3]; + + sse3_test_hsubps (p1, p2, p3); + + fail += chk_ps (ck, p3); + + sse3_test_hsubps_subsume (p1, p2, p3); + + fail += chk_ps (ck, p3); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-lddqu.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-lddqu.c new file mode 100644 index 000000000..700bd571d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-lddqu.c @@ -0,0 +1,76 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse3 } */ +/* { dg-options "-O2 -msse3 -mfpmath=sse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse3-check.h" +#endif + +#ifndef TEST +#define TEST sse3_test +#endif + +#include CHECK_H +#include <pmmintrin.h> + +static void +sse3_test_lddqu (double *i1, double *r) +{ + __m128i t1 = _mm_lddqu_si128 ((__m128i *) i1); + + _mm_storeu_si128 ((__m128i *) r, t1); +} + +static int +chk_pd (double *v1, double *v2) +{ + int i; + int n_fails = 0; + + for (i = 0; i < 2; i++) + if (v1[i] != v2[i]) + n_fails += 1; + + return n_fails; +} + +static double p1[2]; +static double p2[2]; +static double ck[2]; + +static double vals[80] = + { + 100.0, 200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5, + 1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52, + 32.6, 123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44, + 12.16, 52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785, + 541.3, 321.4, 231.4, 531.4, 71., 321., 231., -531., + 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, + 23.45, -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1, + 1.234, 2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912, + -9.32, -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95, + 9.32, 8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95 + }; + +static void +TEST (void) +{ + int i; + int fail = 0; + + for (i = 0; i < 80; i += 2) + { + p1[0] = vals[i+0]; + p1[1] = vals[i+1]; + + sse3_test_lddqu (p1, p2); + + ck[0] = p1[0]; + ck[1] = p1[1]; + + fail += chk_pd (ck, p2); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-movddup.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-movddup.c new file mode 100644 index 000000000..cbf320666 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-movddup.c @@ -0,0 +1,133 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse3 } */ +/* { dg-options "-O2 -msse3 -mfpmath=sse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse3-check.h" +#endif + +#ifndef TEST +#define TEST sse3_test +#endif + +#include CHECK_H + +#include <pmmintrin.h> + +static void +sse3_test_movddup_mem (double *i1, double *r) +{ + __m128d t1 = _mm_loaddup_pd (i1); + + _mm_storeu_pd (r, t1); +} + +static double cnst1 [2] = {1.0, 1.0}; + +static void +sse3_test_movddup_reg (double *i1, double *r) +{ + __m128d t1 = _mm_loadu_pd (i1); + __m128d t2 = _mm_loadu_pd (&cnst1[0]); + + t1 = _mm_mul_pd (t1, t2); + t2 = _mm_movedup_pd (t1); + + _mm_storeu_pd (r, t2); +} + +static void +sse3_test_movddup_reg_subsume_unaligned (double *i1, double *r) +{ + __m128d t1 = _mm_loadu_pd (i1); + __m128d t2 = _mm_movedup_pd (t1); + + _mm_storeu_pd (r, t2); +} + +static void +sse3_test_movddup_reg_subsume_ldsd (double *i1, double *r) +{ + __m128d t1 = _mm_load_sd (i1); + __m128d t2 = _mm_movedup_pd (t1); + + _mm_storeu_pd (r, t2); +} + +static void +sse3_test_movddup_reg_subsume (double *i1, double *r) +{ + __m128d t1 = _mm_load_pd (i1); + __m128d t2 = _mm_movedup_pd (t1); + + _mm_storeu_pd (r, t2); +} + +static int +chk_pd (double *v1, double *v2) +{ + int i; + int n_fails = 0; + + for (i = 0; i < 2; i++) + if (v1[i] != v2[i]) + n_fails += 1; + + return n_fails; +} + +static double p1[2] __attribute__ ((aligned(16))); +static double p2[2]; +static double ck[2]; + +static double vals[80] = + { + 100.0, 200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5, + 1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52, + 32.6, 123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44, + 12.16, 52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785, + 541.3, 321.4, 231.4, 531.4, 71., 321., 231., -531., + 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, + 23.45, -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1, + 1.234, 2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912, + -9.32, -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95, + 9.32, 8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95 + }; + +static void +TEST (void) +{ + int i; + int fail = 0; + + for (i = 0; i < 80; i += 1) + { + p1[0] = vals[i+0]; + + ck[0] = p1[0]; + ck[1] = p1[0]; + + sse3_test_movddup_mem (p1, p2); + + fail += chk_pd (ck, p2); + + sse3_test_movddup_reg (p1, p2); + + fail += chk_pd (ck, p2); + + sse3_test_movddup_reg_subsume (p1, p2); + + fail += chk_pd (ck, p2); + + sse3_test_movddup_reg_subsume_unaligned (p1, p2); + + fail += chk_pd (ck, p2); + + sse3_test_movddup_reg_subsume_ldsd (p1, p2); + + fail += chk_pd (ck, p2); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-movshdup.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-movshdup.c new file mode 100644 index 000000000..0d30ccb5b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-movshdup.c @@ -0,0 +1,95 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse3 } */ +/* { dg-options "-O2 -msse3 -mfpmath=sse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse3-check.h" +#endif + +#ifndef TEST +#define TEST sse3_test +#endif + +#include CHECK_H + +#include <pmmintrin.h> + +static void +sse3_test_movshdup_reg (float *i1, float *r) +{ + __m128 t1 = _mm_loadu_ps (i1); + __m128 t2 = _mm_movehdup_ps (t1); + + _mm_storeu_ps (r, t2); +} + +static void +sse3_test_movshdup_reg_subsume (float *i1, float *r) +{ + __m128 t1 = _mm_load_ps (i1); + __m128 t2 = _mm_movehdup_ps (t1); + + _mm_storeu_ps (r, t2); +} + +static int +chk_ps (float *v1, float *v2) +{ + int i; + int n_fails = 0; + + for (i = 0; i < 4; i++) + if (v1[i] != v2[i]) + n_fails += 1; + + return n_fails; +} + +static float p1[4] __attribute__ ((aligned(16))); +static float p2[4]; +static float ck[4]; + +static float vals[80] = + { + 100.0, 200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5, + 1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52, + 32.6, 123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44, + 12.16, 52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785, + 541.3, 321.4, 231.4, 531.4, 71., 321., 231., -531., + 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, + 23.45, -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1, + 1.234, 2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912, + -9.32, -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95, + 9.32, 8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95 + }; + +static void +TEST (void) +{ + int i; + int fail = 0; + + for (i = 0; i < 80; i += 2) + { + p1[0] = 0.0; + p1[1] = vals[i+0]; + p1[2] = 1.0; + p1[3] = vals[i+1]; + + ck[0] = p1[1]; + ck[1] = p1[1]; + ck[2] = p1[3]; + ck[3] = p1[3]; + + sse3_test_movshdup_reg (p1, p2); + + fail += chk_ps (ck, p2); + + sse3_test_movshdup_reg_subsume (p1, p2); + + fail += chk_ps (ck, p2); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-movsldup.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-movsldup.c new file mode 100644 index 000000000..1ef2dd1b0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse3-movsldup.c @@ -0,0 +1,95 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse3 } */ +/* { dg-options "-O2 -msse3 -mfpmath=sse" } */ + +#ifndef CHECK_H +#define CHECK_H "sse3-check.h" +#endif + +#ifndef TEST +#define TEST sse3_test +#endif + +#include CHECK_H + +#include <pmmintrin.h> + +static void +sse3_test_movsldup_reg (float *i1, float *r) +{ + __m128 t1 = _mm_loadu_ps (i1); + __m128 t2 = _mm_moveldup_ps (t1); + + _mm_storeu_ps (r, t2); +} + +static void +sse3_test_movsldup_reg_subsume (float *i1, float *r) +{ + __m128 t1 = _mm_load_ps (i1); + __m128 t2 = _mm_moveldup_ps (t1); + + _mm_storeu_ps (r, t2); +} + +static int +chk_ps (float *v1, float *v2) +{ + int i; + int n_fails = 0; + + for (i = 0; i < 4; i++) + if (v1[i] != v2[i]) + n_fails += 1; + + return n_fails; +} + +static float p1[4] __attribute__ ((aligned(16))); +static float p2[4]; +static float ck[4]; + +static float vals[80] = + { + 100.0, 200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5, + 1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52, + 32.6, 123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44, + 12.16, 52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785, + 541.3, 321.4, 231.4, 531.4, 71., 321., 231., -531., + 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45, + 23.45, -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1, + 1.234, 2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912, + -9.32, -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95, + 9.32, 8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95 + }; + +static void +TEST (void) +{ + int i; + int fail = 0; + + for (i = 0; i < 80; i += 2) + { + p1[0] = vals[i+0]; + p1[1] = 0.0; + p1[2] = vals[i+1]; + p1[3] = 1.0; + + ck[0] = p1[0]; + ck[1] = p1[0]; + ck[2] = p1[2]; + ck[3] = p1[2]; + + sse3_test_movsldup_reg (p1, p2); + + fail += chk_ps (ck, p2); + + sse3_test_movsldup_reg_subsume (p1, p2); + + fail += chk_ps (ck, p2); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendpd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendpd.c new file mode 100644 index 000000000..aff188c63 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendpd.c @@ -0,0 +1,89 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +#define NUM 20 + +#ifndef MASK +#define MASK 0x03 +#endif + +static void +init_blendpd (double *src1, double *src2) +{ + int i, sign = 1; + + for (i = 0; i < NUM * 2; i++) + { + src1[i] = i * i * sign; + src2[i] = (i + 20) * sign; + sign = -sign; + } +} + +static int +check_blendpd (__m128d *dst, double *src1, double *src2) +{ + double tmp[2]; + int j; + + memcpy (&tmp[0], src1, sizeof (tmp)); + + for(j = 0; j < 2; j++) + if ((MASK & (1 << j))) + tmp[j] = src2[j]; + + return memcmp (dst, &tmp[0], sizeof (tmp)); +} + +static void +TEST (void) +{ + __m128d x, y; + union + { + __m128d x[NUM]; + double d[NUM * 2]; + } dst, src1, src2; + union + { + __m128d x; + double d[2]; + } src3; + int i; + + init_blendpd (src1.d, src2.d); + + /* Check blendpd imm8, m128, xmm */ + for (i = 0; i < NUM; i++) + { + dst.x[i] = _mm_blend_pd (src1.x[i], src2.x[i], MASK); + if (check_blendpd (&dst.x[i], &src1.d[i * 2], &src2.d[i * 2])) + abort (); + } + + /* Check blendpd imm8, xmm, xmm */ + src3.x = _mm_setzero_pd (); + + x = _mm_blend_pd (dst.x[2], src3.x, MASK); + y = _mm_blend_pd (src3.x, dst.x[2], MASK); + + if (check_blendpd (&x, &dst.d[4], &src3.d[0])) + abort (); + + if (check_blendpd (&y, &src3.d[0], &dst.d[4])) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c new file mode 100644 index 000000000..8fe71b71c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c @@ -0,0 +1,86 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#include <smmintrin.h> +#include <string.h> +#include <stdlib.h> + +/* mingw runtime don't provide random(). */ +#ifdef __MINGW32__ +#define random rand +#endif + +#define NUM 20 + +#undef MASK +#define MASK 0xe + +static void +init_blendps (float *src1, float *src2) +{ + int i, sign = 1; + + for (i = 0; i < NUM * 4; i++) + { + src1[i] = i * i * sign; + src2[i] = (i + 20) * sign; + sign = -sign; + } +} + +static int +check_blendps (__m128 *dst, float *src1, float *src2) +{ + float tmp[4]; + int j; + + memcpy (&tmp[0], src1, sizeof (tmp)); + for (j = 0; j < 4; j++) + if ((MASK & (1 << j))) + tmp[j] = src2[j]; + + return memcmp (dst, &tmp[0], sizeof (tmp)); +} + +static void +sse4_1_test (void) +{ + __m128 x, y; + union + { + __m128 x[NUM]; + float f[NUM * 4]; + } dst, src1, src2; + union + { + __m128 x; + float f[4]; + } src3; + int i; + + init_blendps (src1.f, src2.f); + + for (i = 0; i < 4; i++) + src3.f[i] = (int) random (); + + /* Check blendps imm8, m128, xmm */ + for (i = 0; i < NUM; i++) + { + dst.x[i] = _mm_blend_ps (src1.x[i], src2.x[i], MASK); + if (check_blendps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4])) + abort (); + } + + /* Check blendps imm8, xmm, xmm */ + x = _mm_blend_ps (dst.x[2], src3.x, MASK); + y = _mm_blend_ps (src3.x, dst.x[2], MASK); + + if (check_blendps (&x, &dst.f[8], &src3.f[0])) + abort (); + + if (check_blendps (&y, &src3.f[0], &dst.f[8])) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c new file mode 100644 index 000000000..3f4b335ac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c @@ -0,0 +1,95 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> +#include <stdlib.h> + +/* mingw runtime don't provide random(). */ +#ifdef __MINGW32__ +#define random rand +#endif + +#define NUM 20 + +#ifndef MASK +#define MASK 0x0f +#endif + +static void +init_blendps (float *src1, float *src2) +{ + int i, sign = 1; + + for (i = 0; i < NUM * 4; i++) + { + src1[i] = i * i * sign; + src2[i] = (i + 20) * sign; + sign = -sign; + } +} + +static int +check_blendps (__m128 *dst, float *src1, float *src2) +{ + float tmp[4]; + int j; + + memcpy (&tmp[0], src1, sizeof (tmp)); + for (j = 0; j < 4; j++) + if ((MASK & (1 << j))) + tmp[j] = src2[j]; + + return memcmp (dst, &tmp[0], sizeof (tmp)); +} + +static void +TEST (void) +{ + __m128 x, y; + union + { + __m128 x[NUM]; + float f[NUM * 4]; + } dst, src1, src2; + union + { + __m128 x; + float f[4]; + } src3; + int i; + + init_blendps (src1.f, src2.f); + + for (i = 0; i < 4; i++) + src3.f[i] = (int) random (); + + /* Check blendps imm8, m128, xmm */ + for (i = 0; i < NUM; i++) + { + dst.x[i] = _mm_blend_ps (src1.x[i], src2.x[i], MASK); + if (check_blendps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4])) + abort (); + } + + /* Check blendps imm8, xmm, xmm */ + x = _mm_blend_ps (dst.x[2], src3.x, MASK); + y = _mm_blend_ps (src3.x, dst.x[2], MASK); + + if (check_blendps (&x, &dst.f[8], &src3.f[0])) + abort (); + + if (check_blendps (&y, &src3.f[0], &dst.f[8])) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendvpd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendvpd.c new file mode 100644 index 000000000..8478234e2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendvpd.c @@ -0,0 +1,65 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#include <smmintrin.h> +#include <string.h> + +#define NUM 20 + +static void +init_blendvpd (double *src1, double *src2, double *mask) +{ + int i, msk, sign = 1; + + msk = -1; + for (i = 0; i < NUM * 2; i++) + { + if((i % 2) == 0) + msk++; + src1[i] = i* (i + 1) * sign; + src2[i] = (i + 20) * sign; + mask[i] = (i + 120) * i; + if( (msk & (1 << (i % 2)))) + mask[i] = -mask[i]; + sign = -sign; + } +} + +static int +check_blendvpd (__m128d *dst, double *src1, double *src2, + double *mask) +{ + double tmp[2]; + int j; + + memcpy (&tmp[0], src1, sizeof (tmp)); + for (j = 0; j < 2; j++) + if (mask [j] < 0.0) + tmp[j] = src2[j]; + + return memcmp (dst, &tmp[0], sizeof (tmp)); +} + +static void +sse4_1_test (void) +{ + union + { + __m128d x[NUM]; + double d[NUM * 2]; + } dst, src1, src2, mask; + int i; + + init_blendvpd (src1.d, src2.d, mask.d); + + for (i = 0; i < NUM; i++) + { + dst.x[i] = _mm_blendv_pd (src1.x[i], src2.x[i], mask.x[i]); + if (check_blendvpd (&dst.x[i], &src1.d[i * 2], &src2.d[i * 2], + &mask.d[i * 2])) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendvps.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendvps.c new file mode 100644 index 000000000..7ff464900 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-blendvps.c @@ -0,0 +1,65 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#include <smmintrin.h> +#include <string.h> + +#define NUM 20 + +static void +init_blendvps (float *src1, float *src2, float *mask) +{ + int i, msk, sign = 1; + + msk = -1; + for (i = 0; i < NUM * 4; i++) + { + if((i % 4) == 0) + msk++; + src1[i] = i* (i + 1) * sign; + src2[i] = (i + 20) * sign; + mask[i] = (i + 120) * i; + if( (msk & (1 << (i % 4)))) + mask[i] = -mask[i]; + sign = -sign; + } +} + +static int +check_blendvps (__m128 *dst, float *src1, float *src2, + float *mask) +{ + float tmp[4]; + int j; + + memcpy (&tmp[0], src1, sizeof (tmp)); + for (j = 0; j < 4; j++) + if (mask [j] < 0.0) + tmp[j] = src2[j]; + + return memcmp (dst, &tmp[0], sizeof (tmp)); +} + +static void +sse4_1_test (void) +{ + union + { + __m128 x[NUM]; + float f[NUM * 4]; + } dst, src1, src2, mask; + int i; + + init_blendvps (src1.f, src2.f, mask.f); + + for (i = 0; i < NUM; i++) + { + dst.x[i] = _mm_blendv_ps (src1.x[i], src2.x[i], mask.x[i]); + if (check_blendvps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], + &mask.f[i * 4])) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ceil-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ceil-sfix-vec.c new file mode 100644 index 000000000..ca07d9c00 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ceil-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double ceil (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) ceil (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) ceil (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ceil-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ceil-vec.c new file mode 100644 index 000000000..20bb2641f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ceil-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double ceil (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = ceil (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != ceil (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-sfix-vec.c new file mode 100644 index 000000000..b0559bf39 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float ceilf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) ceilf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) ceilf (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-vec.c new file mode 100644 index 000000000..314be91fa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float ceilf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = ceilf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != ceilf (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-check.h new file mode 100644 index 000000000..788f65d61 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-check.h @@ -0,0 +1,30 @@ +#include <stdlib.h> + +#include "cpuid.h" +#include "m128-check.h" + +static void sse4_1_test (void); + +#define MASK 0x2 + +static void +__attribute__ ((noinline)) +do_test (void) +{ + sse4_1_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run SSE4.1 test only if host has SSE4.1 support. */ + if (ecx & bit_SSE4_1) + do_test (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-cond-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-cond-1.c new file mode 100644 index 000000000..41e69e59f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-cond-1.c @@ -0,0 +1,75 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O3 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +extern void abort (void); +double ad[64], bd[64], cd[64], dd[64], ed[64]; +float af[64], bf[64], cf[64], df[64], ef[64]; +signed char ac[64], bc[64], cc[64], dc[64], ec[64]; +short as[64], bs[64], cs[64], ds[64], es[64]; +int ai[64], bi[64], ci[64], di[64], ei[64]; +long long all[64], bll[64], cll[64], dll[64], ell[64]; +unsigned char auc[64], buc[64], cuc[64], duc[64], euc[64]; +unsigned short aus[64], bus[64], cus[64], dus[64], eus[64]; +unsigned int au[64], bu[64], cu[64], du[64], eu[64]; +unsigned long long aull[64], bull[64], cull[64], dull[64], eull[64]; + +#define F(var) \ +__attribute__((noinline, noclone)) void \ +f##var (void) \ +{ \ + int i; \ + for (i = 0; i < 64; i++) \ + { \ + __typeof (a##var[0]) d = d##var[i], e = e##var[i]; \ + a##var[i] = b##var[i] > c##var[i] ? d : e; \ + } \ +} + +#define TESTS \ +F (d) F (f) F (c) F (s) F (i) F (ll) F (uc) F (us) F (u) F (ull) + +TESTS + +void +TEST () +{ + int i; + for (i = 0; i < 64; i++) + { +#undef F +#define F(var) \ + b##var[i] = i + 64; \ + switch (i % 3) \ + { \ + case 0: c##var[i] = i + 64; break; \ + case 1: c##var[i] = 127 - i; break; \ + case 2: c##var[i] = i; break; \ + } \ + d##var[i] = i / 2; \ + e##var[i] = i * 2; + TESTS + } +#undef F +#define F(var) f##var (); + TESTS + for (i = 0; i < 64; i++) + { + asm volatile ("" : : : "memory"); +#undef F +#define F(var) \ + if (a##var[i] != (b##var[i] > c##var[i] ? d##var[i] : e##var[i])) \ + abort (); + TESTS + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-dppd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-dppd-1.c new file mode 100644 index 000000000..b8e58d47a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-dppd-1.c @@ -0,0 +1,71 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define lmskN 0x00 +#define lmsk0 0x01 +#define lmsk1 0x02 +#define lmsk01 0x03 + +#define hmskA 0x30 +#define hmsk0 0x10 +#define hmsk1 0x20 +#define hmsk01 0x30 +#define hmskN 0x00 + +#ifndef HIMASK +#define HIMASK hmskA +#endif + +static void +TEST (void) +{ + union + { + __m128d x; + double d[2]; + } val1, val2, res[4]; + int masks[4]; + int i, j; + + val1.d[0] = 2.; + val1.d[1] = 3.; + + val2.d[0] = 10.; + val2.d[1] = 100.; + + res[0].x = _mm_dp_pd (val1.x, val2.x, HIMASK | lmskN); + res[1].x = _mm_dp_pd (val1.x, val2.x, HIMASK | lmsk0); + res[2].x = _mm_dp_pd (val1.x, val2.x, HIMASK | lmsk1); + res[3].x = _mm_dp_pd (val1.x, val2.x, HIMASK | lmsk01); + + masks[0] = HIMASK | lmskN; + masks[1] = HIMASK | lmsk0; + masks[2] = HIMASK | lmsk1; + masks[3] = HIMASK | lmsk01; + + for (i = 0; i < 4; i++) + { + double tmp = 0.; + + for (j = 0; j < 2; j++) + if (HIMASK & (0x10 << j)) + tmp = tmp + (val1.d[j] * val2.d[j]); + + for (j = 0; j < 2; j++) + if ((masks[i] & (1 << j)) && res[i].d[j] != tmp) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-dppd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-dppd-2.c new file mode 100644 index 000000000..6dc328c05 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-dppd-2.c @@ -0,0 +1,73 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#include <string.h> + +#define lmskN 0x00 +#define lmsk0 0x01 +#define lmsk1 0x02 +#define lmsk01 0x03 + +#define hmskA 0x30 +#define hmsk0 0x10 +#define hmsk1 0x20 +#define hmsk01 0x30 +#define hmskN 0x00 + +#ifndef HIMASK +#define HIMASK hmskA +#endif + +#ifndef LOMASK +#define LOMASK lmsk01 +#endif + +static void +TEST (void) +{ + union + { + __m128d x; + double d[2]; + } val1[4], val2[4], res[4], chk[4]; + int i, j; + double tmp; + + for (i = 0; i < 4; i++) + { + val1[i].d [0] = 2.; + val1[i].d [1] = 3.; + + val2[i].d [0] = 10.; + val2[i].d [1] = 100.; + + tmp = 0.; + for (j = 0; j < 2; j++) + if ((HIMASK & (0x10 << j))) + tmp += val1[i].d [j] * val2[i].d [j]; + + for (j = 0; j < 2; j++) + if ((LOMASK & (1 << j))) + chk[i].d[j] = tmp; + } + + for (i = 0; i < 4; i++) + { + res[i].x = _mm_dp_pd (val1[i].x, val2[i].x, HIMASK | LOMASK); + if (memcmp (&res[i], &chk[i], sizeof (chk[i]))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-dpps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-dpps-1.c new file mode 100644 index 000000000..77232567c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-dpps-1.c @@ -0,0 +1,114 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define lmskN 0x00 +#define lmsk0 0x01 +#define lmsk1 0x02 +#define lmsk2 0x04 +#define lmsk3 0x08 +#define lmsk01 0x03 +#define lmsk02 0x05 +#define lmsk03 0x09 +#define lmsk12 0x06 +#define lmsk13 0x0A +#define lmsk23 0x0C +#define lmskA 0x0F + +#define hmskN 0x00 +#define hmskA 0xF0 +#define hmsk0 0x10 +#define hmsk1 0x20 +#define hmsk2 0x40 +#define hmsk3 0x80 +#define hmsk01 0x30 +#define hmsk02 0x50 +#define hmsk03 0x90 +#define hmsk12 0x60 +#define hmsk13 0xA0 +#define hmsk23 0xC0 + +#ifndef HIMASK +#define HIMASK hmskA +#endif + +static void +TEST (void) +{ + union + { + __m128 x; + float f[4]; + } val1, val2, res[16]; + int masks[16]; + int i, j; + + val1.f[0] = 2.; + val1.f[1] = 3.; + val1.f[2] = 4.; + val1.f[3] = 5.; + + val2.f[0] = 10.; + val2.f[1] = 100.; + val2.f[2] = 1000.; + val2.f[3] = 10000.; + + res[0].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk0); + res[1].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk1); + res[2].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk2); + res[3].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk3); + res[4].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk01); + res[5].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk02); + res[6].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk03); + res[7].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk12); + res[8].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk13); + res[9].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk23); + res[10].x = _mm_dp_ps (val1.x, val2.x, HIMASK | (0x0F & ~lmsk0)); + res[11].x = _mm_dp_ps (val1.x, val2.x, HIMASK | (0x0F & ~lmsk1)); + res[12].x = _mm_dp_ps (val1.x, val2.x, HIMASK | (0x0F & ~lmsk2)); + res[13].x = _mm_dp_ps (val1.x, val2.x, HIMASK | (0x0F & ~lmsk3)); + res[14].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmskN); + res[15].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmskA); + + masks[0] = HIMASK | lmsk0; + masks[1] = HIMASK | lmsk1; + masks[2] = HIMASK | lmsk2; + masks[3] = HIMASK | lmsk3; + masks[4] = HIMASK | lmsk01; + masks[5] = HIMASK | lmsk02; + masks[6] = HIMASK | lmsk03; + masks[7] = HIMASK | lmsk12; + masks[8] = HIMASK | lmsk13; + masks[9] = HIMASK | lmsk23; + masks[10] = HIMASK | (0x0F & ~lmsk0); + masks[11] = HIMASK | (0x0F & ~lmsk1); + masks[12] = HIMASK | (0x0F & ~lmsk2); + masks[13] = HIMASK | (0x0F & ~lmsk3); + masks[14] = HIMASK | lmskN; + masks[15] = HIMASK | lmskA; + + for (i = 0; i <= 15; i++) + { + float tmp = 0.; + + for (j = 0; j < 4; j++) + if ((HIMASK & (0x10 << j))) + tmp += val1.f[j] * val2.f[j]; + + for (j = 0; j < 4; j++) + if ((masks[i] & (1 << j)) && res[i].f[j] != tmp) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-dpps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-dpps-2.c new file mode 100644 index 000000000..48483b6c8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-dpps-2.c @@ -0,0 +1,92 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#include <string.h> + +#define lmskN 0x00 +#define lmsk0 0x01 +#define lmsk1 0x02 +#define lmsk2 0x04 +#define lmsk3 0x08 +#define lmsk01 0x03 +#define lmsk02 0x05 +#define lmsk03 0x09 +#define lmsk12 0x06 +#define lmsk13 0x0A +#define lmsk23 0x0C +#define lmskA 0x0F + +#define hmskN 0x00 +#define hmskA 0xF0 +#define hmsk0 0x10 +#define hmsk1 0x20 +#define hmsk2 0x40 +#define hmsk3 0x80 +#define hmsk01 0x30 +#define hmsk02 0x50 +#define hmsk03 0x90 +#define hmsk12 0x60 +#define hmsk13 0xA0 +#define hmsk23 0xC0 + +#ifndef HIMASK +#define HIMASK hmskA +#endif + +#ifndef LOMASK +#define LOMASK lmskA +#endif + +static void +TEST (void) +{ + union + { + __m128 x; + float f[4]; + } val1[16], val2[16], res[16], chk[16]; + int i,j; + float tmp; + + for (i = 0; i < 16; i++) + { + val1[i].f[0] = 2.; + val1[i].f[1] = 3.; + val1[i].f[2] = 4.; + val1[i].f[3] = 5.; + + val2[i].f[0] = 10.; + val2[i].f[1] = 100.; + val2[i].f[2] = 1000.; + val2[i].f[3] = 10000.; + + tmp = 0.; + for (j = 0; j < 4; j++) + if ((HIMASK & (0x10 << j))) + tmp += val1[i].f [j] * val2[i].f [j]; + + for (j = 0; j < 4; j++) + if ((LOMASK & (1 << j))) + chk[i].f[j] = tmp; + } + + for (i = 0; i < 16; i++) + { + res[i].x = _mm_dp_ps (val1[i].x, val2[i].x, HIMASK | LOMASK); + if (memcmp (&res[i], &chk[i], sizeof (chk[i]))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-extractps.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-extractps.c new file mode 100644 index 000000000..d63296fe2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-extractps.c @@ -0,0 +1,72 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +int masks[4]; + +#define msk0 0x00 +#define msk1 0x01 +#define msk2 0x02 +#define msk3 0x03 + +static void +TEST (void) +{ + union + { + __m128 x; + float f[4]; + } val1, val2; + union + { + int i; + float f; + } res[4]; + float resm[4]; + int i; + + val1.f[0] = 10.; + val1.f[1] = 2.; + val1.f[2] = 3.; + val1.f[3] = 40.; + + val2.f[0] = 77.; + val2.f[1] = 21.; + val2.f[2] = 34.; + val2.f[3] = 49.; + + res[0].i = _mm_extract_ps (val1.x, msk0); + res[1].i = _mm_extract_ps (val1.x, msk1); + res[2].i = _mm_extract_ps (val1.x, msk2); + res[3].i = _mm_extract_ps (val1.x, msk3); + + _MM_EXTRACT_FLOAT (resm[0], val2.x, msk0); + _MM_EXTRACT_FLOAT (resm[1], val2.x, msk1); + _MM_EXTRACT_FLOAT (resm[2], val2.x, msk2); + _MM_EXTRACT_FLOAT (resm[3], val2.x, msk3); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + + for( i=0; i < 4; i++ ) + { + if (res[i].f != val1.f[masks[i]]) + abort (); + if (resm[i] != val2.f[masks[i]]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-floor-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-floor-sfix-vec.c new file mode 100644 index 000000000..2083a60e7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-floor-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double floor (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) floor (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) floor (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-floor-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-floor-vec.c new file mode 100644 index 000000000..d250413c1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-floor-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double floor (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = floor (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != floor (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-floorf-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-floorf-sfix-vec.c new file mode 100644 index 000000000..aa2976d5b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-floorf-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float floorf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) floorf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) floorf (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-floorf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-floorf-vec.c new file mode 100644 index 000000000..2f339f3b5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-floorf-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float floorf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = floorf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != floorf (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-init-v16qi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-init-v16qi-1.c new file mode 100644 index 000000000..6a3ccee58 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-init-v16qi-1.c @@ -0,0 +1,77 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <emmintrin.h> + +static void +__attribute__((noinline)) +check (__m128i x, unsigned char *v, int j) +{ + union + { + __m128i x; + unsigned char i[16]; + } u; + unsigned int i; + + u.x = x; + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (i == j) + { + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]); +#endif + abort (); + } + } + else if (u.i[i] != 0) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0\n", i, u.i[i]); +#endif + abort (); + } +} + +static void +__attribute__((noinline)) +test (unsigned char *v) +{ + __m128i x; + + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[0]); + check (x, v, 0); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[1], 0); + check (x, v, 1); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[2], 0, 0); + check (x, v, 2); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[3], 0, 0, 0); + check (x, v, 3); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[4], 0, 0, 0, 0); + check (x, v, 4); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[5], 0, 0, 0, 0, 0); + check (x, v, 5); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, v[6], 0, 0, 0, 0, 0, 0); + check (x, v, 6); + x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, v[7], 0, 0, 0, 0, 0, 0, 0); + check (x, v, 7); +} + +static void +sse4_1_test (void) +{ + unsigned char v[16] + = { 0x7B, 0x5B, 0x54, 0x65, 0x73, 0x74, 0x56, 0x65, + 0x63, 0x74, 0x6F, 0x72, 0x5D, 0x53, 0x47, 0x5D }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-init-v2di-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-init-v2di-1.c new file mode 100644 index 000000000..cd9fa7978 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-init-v2di-1.c @@ -0,0 +1,64 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <emmintrin.h> + +static void +__attribute__((noinline)) +check (__m128i x, unsigned long long *v, int j) +{ + union + { + __m128i x; + unsigned long long i[2]; + } u; + unsigned int i; + + u.x = x; + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (i == j) + { + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]); +#endif + abort (); + } + } + else if (u.i[i] != 0) + { +#ifdef DEBUG + printf ("%i: 0x%llx != 0\n", i, u.i[i]); +#endif + abort (); + } +} + +static void +__attribute__((noinline)) +test (unsigned long long *v) +{ + __m128i x; + + x = _mm_set_epi64x (0, v[0]); + check (x, v, 0); + x = _mm_set_epi64x (v[1], 0); + check (x, v, 1); +} + +static void +sse4_1_test (void) +{ + unsigned long long v[2] + = { 0x7B5B546573745665LL, 0x63746F725D53475DLL }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-init-v4sf-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-init-v4sf-1.c new file mode 100644 index 000000000..f97604235 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-init-v4sf-1.c @@ -0,0 +1,67 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <emmintrin.h> + +static void +__attribute__((noinline)) +check (__m128 x, float *v, int j) +{ + union + { + __m128 x; + float f[4]; + } u; + unsigned int i; + + u.x = x; + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (i == j) + { + if (v[i] != u.f[i]) + { +#ifdef DEBUG + printf ("%i: %f != %f\n", i, v[i], u.f[i]); +#endif + abort (); + } + } + else if (u.f[i] != 0) + { +#ifdef DEBUG + printf ("%i: %f != 0\n", i, u.f[i]); +#endif + abort (); + } +} + +static void +__attribute__((noinline)) +test (float *v) +{ + __m128 x; + + x = _mm_set_ps (0, 0, 0, v[0]); + check (x, v, 0); + x = _mm_set_ps (0, 0, v[1], 0); + check (x, v, 1); + x = _mm_set_ps (0, v[2], 0, 0); + check (x, v, 2); + x = _mm_set_ps (v[3], 0, 0, 0); + check (x, v, 3); +} + +static void +sse4_1_test (void) +{ + float v[4] = { -3, 2, 1, 9 }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-init-v4si-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-init-v4si-1.c new file mode 100644 index 000000000..63501b7ee --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-init-v4si-1.c @@ -0,0 +1,68 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <emmintrin.h> + +static void +__attribute__((noinline)) +check (__m128i x, unsigned int *v, int j) +{ + union + { + __m128i x; + unsigned int i[4]; + } u; + unsigned int i; + + u.x = x; + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (i == j) + { + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]); +#endif + abort (); + } + } + else if (u.i[i] != 0) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0\n", i, u.i[i]); +#endif + abort (); + } +} + +static void +__attribute__((noinline)) +test (unsigned int *v) +{ + __m128i x; + + x = _mm_set_epi32 (0, 0, 0, v[0]); + check (x, v, 0); + x = _mm_set_epi32 (0, 0, v[1], 0); + check (x, v, 1); + x = _mm_set_epi32 (0, v[2], 0, 0); + check (x, v, 2); + x = _mm_set_epi32 (v[3], 0, 0, 0); + check (x, v, 3); +} + +static void +sse4_1_test (void) +{ + unsigned int v[4] + = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insertps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insertps-1.c new file mode 100644 index 000000000..2f5741288 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insertps-1.c @@ -0,0 +1,79 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +#define msk0 0x01 +#define msk1 0x10 +#define msk2 0x29 +#define msk3 0x30 + +#define msk4 0xFC +#define msk5 0x05 +#define msk6 0x0A +#define msk7 0x0F + +static void +TEST (void) +{ + union + { + __m128 x; + float f[4]; + } res[8], val1, val2, tmp; + int masks[8]; + int i, j; + + val2.f[0] = 55.0; + val2.f[1] = 55.0; + val2.f[2] = 55.0; + val2.f[3] = 55.0; + + val1.f[0] = 1.; + val1.f[1] = 2.; + val1.f[2] = 3.; + val1.f[3] = 4.; + + res[0].x = _mm_insert_ps (val2.x, val1.x, msk0); + res[1].x = _mm_insert_ps (val2.x, val1.x, msk1); + res[2].x = _mm_insert_ps (val2.x, val1.x, msk2); + res[3].x = _mm_insert_ps (val2.x, val1.x, msk3); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + + for (i = 0; i < 4; i++) + res[i + 4].x = _mm_insert_ps (val2.x, val1.x, msk4); + + masks[4] = msk4; + masks[5] = msk4; + masks[6] = msk4; + masks[7] = msk4; + + for (i=0; i < 8; i++) + { + tmp = val2; + tmp.f[(masks[i] & 0x30) >> 4] = val1.f[(masks[i] & 0xC0) >> 6]; + + for (j = 0; j < 4; j++) + if (masks[i] & (0x1 << j)) + tmp.f[j] = 0.f; + + if (memcmp (&res[i], &tmp, sizeof (tmp))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insertps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insertps-2.c new file mode 100644 index 000000000..fbb96ca50 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insertps-2.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +static void +TEST (void) +{ + union + { + __m128 x; + float f[4]; + } vals[4], val; + int i, j; + + val.f[0]= 1.; + val.f[1]= 2.; + val.f[2]= 3.; + val.f[3]= 4.; + + vals[0].x = _MM_PICK_OUT_PS (val.x, 0); + vals[1].x = _MM_PICK_OUT_PS (val.x, 1); + vals[2].x = _MM_PICK_OUT_PS (val.x, 2); + vals[3].x = _MM_PICK_OUT_PS (val.x, 3); + + for (i = 0; i < 4; i++) + for (j = 0; j < 4; j++) + if ((j != 0 && vals[i].f[j] != 0) + || (j == 0 && vals[i].f[j] != val.f[i])) + abort (); + + if (_MM_MK_INSERTPS_NDX(0, 0, 0x1) != 0x01 + || _MM_MK_INSERTPS_NDX(0, 1, 0x2) != 0x12 + || _MM_MK_INSERTPS_NDX(0, 2, 0x3) != 0x23 + || _MM_MK_INSERTPS_NDX(0, 3, 0x4) != 0x34 + || _MM_MK_INSERTPS_NDX(1, 0, 0x5) != 0x45 + || _MM_MK_INSERTPS_NDX(1, 1, 0x6) != 0x56 + || _MM_MK_INSERTPS_NDX(2, 2, 0x7) != 0xA7 + || _MM_MK_INSERTPS_NDX(3, 3, 0x8) != 0xF8) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insertps-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insertps-3.c new file mode 100644 index 000000000..7c71664a7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insertps-3.c @@ -0,0 +1,5 @@ +/* { dg-do run { target ia32 } } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1 -mtune=geode" } */ + +#include "sse4_1-insertps-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insertps-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insertps-4.c new file mode 100644 index 000000000..30defca25 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insertps-4.c @@ -0,0 +1,92 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +#define msk0 0x41 +#define msk1 0x90 +#define msk2 0xe9 +#define msk3 0x70 + +#define msk4 0xFC +#define msk5 0x05 +#define msk6 0x0A +#define msk7 0x0F + +union + { + __m128 x; + float f[4]; + } val1; + +static void +TEST (void) +{ + union + { + __m128 x; + float f[4]; + } res[8], val2, tmp; + int masks[8]; + int i, j; + + val2.f[0] = 55.0; + val2.f[1] = 55.0; + val2.f[2] = 55.0; + val2.f[3] = 55.0; + + val1.f[0] = 1.; + val1.f[1] = 2.; + val1.f[2] = 3.; + val1.f[3] = 4.; + + asm volatile ("" : "+m" (val1)); + res[0].x = _mm_insert_ps (val2.x, val1.x, msk0); + asm volatile ("" : "+m" (val1)); + res[1].x = _mm_insert_ps (val2.x, val1.x, msk1); + asm volatile ("" : "+m" (val1)); + res[2].x = _mm_insert_ps (val2.x, val1.x, msk2); + asm volatile ("" : "+m" (val1)); + res[3].x = _mm_insert_ps (val2.x, val1.x, msk3); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + + for (i = 0; i < 4; i++) + { + asm volatile ("" : "+m" (val1)); + res[i + 4].x = _mm_insert_ps (val2.x, val1.x, msk4); + } + + masks[4] = msk4; + masks[5] = msk4; + masks[6] = msk4; + masks[7] = msk4; + + for (i=0; i < 8; i++) + { + tmp = val2; + tmp.f[(masks[i] & 0x30) >> 4] = val1.f[(masks[i] & 0xC0) >> 6]; + + for (j = 0; j < 4; j++) + if (masks[i] & (0x1 << j)) + tmp.f[j] = 0.f; + + if (memcmp (&res[i], &tmp, sizeof (tmp))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insvdi.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insvdi.c new file mode 100644 index 000000000..da090ba15 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insvdi.c @@ -0,0 +1,55 @@ +/* { dg-do run } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +typedef long T __attribute__((may_alias)); +struct S { __m128i d; }; + +__m128i +__attribute__((noinline)) +foo (__m128i y, long x) +{ + struct S s; + + s.d = y; + ((T *) &s.d)[1] = x; + return s.d; +} + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + unsigned long l[2]; + } res, val, tmp; + unsigned long ins[4] = { 3, 4, 5, 6 }; + + val.i[0] = 0x35251505; + val.i[1] = 0x75655545; + val.i[2] = 0xB5A59585; + val.i[3] = 0xF5E5D5C5; + + res.x = foo (val.x, ins[3]); + + tmp.x = val.x; + tmp.l[1] = ins[3]; + if (memcmp (&tmp, &res, sizeof (tmp))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insvqi.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insvqi.c new file mode 100644 index 000000000..784201e2d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insvqi.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +typedef char T __attribute__((may_alias)); +struct S { __m128i d; }; + +__m128i +__attribute__((noinline)) +foo (__m128i y, char x) +{ + struct S s; + + s.d = y; + ((T *) &s.d)[1] = x; + return s.d; +} + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + unsigned char c[16]; + } res, val, tmp; + unsigned char ins[4] = { 3, 4, 5, 6 }; + + val.i[0] = 0x35251505; + val.i[1] = 0x75655545; + val.i[2] = 0xB5A59585; + val.i[3] = 0xF5E5D5C5; + + res.x = foo (val.x, ins[3]); + + tmp.x = val.x; + tmp.c[1] = ins[3]; + if (memcmp (&tmp, &res, sizeof (tmp))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insvsi.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insvsi.c new file mode 100644 index 000000000..569b8f269 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-insvsi.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +typedef int T __attribute__((may_alias)); +struct S { __m128i d; }; + +__m128i +__attribute__((noinline)) +foo (__m128i y, int x) +{ + struct S s; + + s.d = y; + ((T *) &s.d)[1] = x; + return s.d; +} + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + } res, val, tmp; + unsigned int ins[4] = { 3, 4, 5, 6 }; + + val.i[0] = 0x35251505; + val.i[1] = 0x75655545; + val.i[2] = 0xB5A59585; + val.i[3] = 0xF5E5D5C5; + + res.x = foo (val.x, ins[3]); + + tmp.x = val.x; + tmp.i[1] = ins[3]; + if (memcmp (&tmp, &res, sizeof (tmp))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-movntdqa.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-movntdqa.c new file mode 100644 index 000000000..bc5cf2383 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-movntdqa.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +#define NUM 20 + +static void +init_movntdqa (int *src) +{ + int i, j, sign = 1; + + for (i = 0; i < NUM; i++) + for (j = 0; j < 4; j++) + { + src[i * 4 + j] = j * i * i * sign; + sign = -sign; + } +} + +static void +TEST (void) +{ + union + { + __m128i x[NUM]; + int i[NUM * 4]; + } dst, src; + int i; + + init_movntdqa (src.i); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_stream_load_si128 (&src.x[i]); + + for (i = 0; i < NUM; i++) + if (memcmp (&dst.x[i], &src.x[i], sizeof(src.x[i]))) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-mpsadbw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-mpsadbw.c new file mode 100644 index 000000000..0fc24e861 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-mpsadbw.c @@ -0,0 +1,130 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +#define msk0 0xC0 +#define msk1 0x01 +#define msk2 0xF2 +#define msk3 0x03 +#define msk4 0x84 +#define msk5 0x05 +#define msk6 0xE6 +#define msk7 0x67 + +static __m128i +compute_mpsadbw (unsigned char *v1, unsigned char *v2, int mask) +{ + union + { + __m128i x; + unsigned short s[8]; + } ret; + unsigned char s[4]; + int i, j; + int offs1, offs2; + + offs2 = 4 * (mask & 3); + for (i = 0; i < 4; i++) + s[i] = v2[offs2 + i]; + + offs1 = 4 * ((mask & 4) >> 2); + for (j = 0; j < 8; j++) + { + ret.s[j] = 0; + for (i = 0; i < 4; i++) + ret.s[j] += abs (v1[offs1 + j + i] - s[i]); + } + + return ret.x; +} + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + unsigned char c[16]; + } val1, val2, val3 [8]; + __m128i res[8], tmp; + unsigned char masks[8]; + int i; + + val1.i[0] = 0x35251505; + val1.i[1] = 0x75655545; + val1.i[2] = 0xB5A59585; + val1.i[3] = 0xF5E5D5C5; + + val2.i[0] = 0x31211101; + val2.i[1] = 0x71615141; + val2.i[2] = 0xB1A19181; + val2.i[3] = 0xF1E1D1C1; + + for (i=0; i < 8; i++) + switch (i % 3) + { + case 1: + val3[i].i[0] = 0xF1E1D1C1; + val3[i].i[1] = 0xB1A19181; + val3[i].i[2] = 0x71615141; + val3[i].i[3] = 0x31211101; + break; + default: + val3[i].x = val2.x; + break; + } + + /* Check mpsadbw imm8, xmm, xmm. */ + res[0] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk0); + res[1] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk1); + res[2] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk2); + res[3] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk3); + res[4] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk4); + res[5] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk5); + res[6] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk6); + res[7] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk7); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + masks[4] = msk4; + masks[5] = msk5; + masks[6] = msk6; + masks[7] = msk7; + + for (i=0; i < 8; i++) + { + tmp = compute_mpsadbw (val1.c, val2.c, masks[i]); + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } + + /* Check mpsadbw imm8, m128, xmm. */ + for (i=0; i < 8; i++) + { + res[i] = _mm_mpsadbw_epu8 (val1.x, val3[i].x, msk4); + masks[i] = msk4; + } + + for (i=0; i < 8; i++) + { + tmp = compute_mpsadbw (val1.c, val3[i].c, masks[i]); + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-mul-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-mul-1.c new file mode 100644 index 000000000..20d03a515 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-mul-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O3 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include "sse2-mul-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-packusdw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-packusdw.c new file mode 100644 index 000000000..f98157794 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-packusdw.c @@ -0,0 +1,73 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 64 + +static unsigned short +int_to_ushort (int iVal) +{ + unsigned short sVal; + + if (iVal < 0) + sVal = 0; + else if (iVal > 0xffff) + sVal = 0xffff; + else sVal = iVal; + + return sVal; +} + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 4]; + int i[NUM]; + } src1, src2; + union + { + __m128i x[NUM / 4]; + unsigned short s[NUM * 2]; + } dst; + int i, sign = 1; + + for (i = 0; i < NUM; i++) + { + src1.i[i] = i * i * sign; + src2.i[i] = (i + 20) * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 4) + dst.x[i / 4] = _mm_packus_epi32 (src1.x [i / 4], src2.x [i / 4]); + + for (i = 0; i < NUM; i ++) + { + int dstIndex; + unsigned short sVal; + + sVal = int_to_ushort (src1.i[i]); + dstIndex = (i % 4) + (i / 4) * 8; + if (sVal != dst.s[dstIndex]) + abort (); + + sVal = int_to_ushort (src2.i[i]); + dstIndex += 4; + if (sVal != dst.s[dstIndex]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pblendvb.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pblendvb.c new file mode 100644 index 000000000..58e94471e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pblendvb.c @@ -0,0 +1,70 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +#define NUM 20 + +static void +init_pblendvb (unsigned char *src1, unsigned char *src2, + unsigned char *mask) +{ + int i, sign = 1; + + for (i = 0; i < NUM * 16; i++) + { + src1[i] = i* i * sign; + src2[i] = (i + 20) * sign; + mask[i] = (i % 3) + ((i * (14 + sign)) + ^ (src1[i] | src2[i] | (i*3))); + sign = -sign; + } +} + +static int +check_pblendvb (__m128i *dst, unsigned char *src1, + unsigned char *src2, unsigned char *mask) +{ + unsigned char tmp[16]; + int j; + + memcpy (&tmp[0], src1, sizeof (tmp)); + for (j = 0; j < 16; j++) + if (mask [j] & 0x80) + tmp[j] = src2[j]; + + return memcmp (dst, &tmp[0], sizeof (tmp)); +} + +static void +TEST (void) +{ + union + { + __m128i x[NUM]; + unsigned char c[NUM * 16]; + } dst, src1, src2, mask; + int i; + + init_pblendvb (src1.c, src2.c, mask.c); + + for (i = 0; i < NUM; i++) + { + dst.x[i] = _mm_blendv_epi8 (src1.x[i], src2.x[i], mask.x[i]); + if (check_pblendvb (&dst.x[i], &src1.c[i * 16], &src2.c[i * 16], + &mask.c[i * 16])) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pblendw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pblendw-2.c new file mode 100644 index 000000000..eecc6edf6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pblendw-2.c @@ -0,0 +1,79 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#include <smmintrin.h> +#include <string.h> + +#define NUM 20 + +#undef MASK +#define MASK 0xfe + +static void +init_pblendw (short *src1, short *src2) +{ + int i, sign = 1; + + for (i = 0; i < NUM * 8; i++) + { + src1[i] = i * i * sign; + src2[i] = (i + 20) * sign; + sign = -sign; + } +} + +static int +check_pblendw (__m128i *dst, short *src1, short *src2) +{ + short tmp[8]; + int j; + + memcpy (&tmp[0], src1, sizeof (tmp)); + for (j = 0; j < 8; j++) + if ((MASK & (1 << j))) + tmp[j] = src2[j]; + + return memcmp (dst, &tmp[0], sizeof (tmp)); +} + +static void +sse4_1_test (void) +{ + __m128i x, y; + union + { + __m128i x[NUM]; + short s[NUM * 8]; + } dst, src1, src2; + union + { + __m128i x; + short s[8]; + } src3; + int i; + + init_pblendw (src1.s, src2.s); + + /* Check pblendw imm8, m128, xmm */ + for (i = 0; i < NUM; i++) + { + dst.x[i] = _mm_blend_epi16 (src1.x[i], src2.x[i], MASK); + if (check_pblendw (&dst.x[i], &src1.s[i * 8], &src2.s[i * 8])) + abort (); + } + + /* Check pblendw imm8, xmm, xmm */ + src3.x = _mm_setzero_si128 (); + + x = _mm_blend_epi16 (dst.x[2], src3.x, MASK); + y = _mm_blend_epi16 (src3.x, dst.x[2], MASK); + + if (check_pblendw (&x, &dst.s[16], &src3.s[0])) + abort (); + + if (check_pblendw (&y, &src3.s[0], &dst.s[16])) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pblendw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pblendw.c new file mode 100644 index 000000000..5f5a25353 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pblendw.c @@ -0,0 +1,88 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +#define NUM 20 + +#ifndef MASK +#define MASK 0x0f +#endif + +static void +init_pblendw (short *src1, short *src2) +{ + int i, sign = 1; + + for (i = 0; i < NUM * 8; i++) + { + src1[i] = i * i * sign; + src2[i] = (i + 20) * sign; + sign = -sign; + } +} + +static int +check_pblendw (__m128i *dst, short *src1, short *src2) +{ + short tmp[8]; + int j; + + memcpy (&tmp[0], src1, sizeof (tmp)); + for (j = 0; j < 8; j++) + if ((MASK & (1 << j))) + tmp[j] = src2[j]; + + return memcmp (dst, &tmp[0], sizeof (tmp)); +} + +static void +TEST (void) +{ + __m128i x, y; + union + { + __m128i x[NUM]; + short s[NUM * 8]; + } dst, src1, src2; + union + { + __m128i x; + short s[8]; + } src3; + int i; + + init_pblendw (src1.s, src2.s); + + /* Check pblendw imm8, m128, xmm */ + for (i = 0; i < NUM; i++) + { + dst.x[i] = _mm_blend_epi16 (src1.x[i], src2.x[i], MASK); + if (check_pblendw (&dst.x[i], &src1.s[i * 8], &src2.s[i * 8])) + abort (); + } + + /* Check pblendw imm8, xmm, xmm */ + src3.x = _mm_setzero_si128 (); + + x = _mm_blend_epi16 (dst.x[2], src3.x, MASK); + y = _mm_blend_epi16 (src3.x, dst.x[2], MASK); + + if (check_pblendw (&x, &dst.s[16], &src3.s[0])) + abort (); + + if (check_pblendw (&y, &src3.s[0], &dst.s[16])) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pcmpeqq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pcmpeqq.c new file mode 100644 index 000000000..8611b8248 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pcmpeqq.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 64 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 2]; + long long ll[NUM]; + } dst, src1, src2; + int i, sign=1; + long long is_eq; + + for (i = 0; i < NUM; i++) + { + src1.ll[i] = i * i * sign; + src2.ll[i] = (i + 20) * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 2) + dst.x [i / 2] = _mm_cmpeq_epi64(src1.x [i / 2], src2.x [i / 2]); + + for (i = 0; i < NUM; i++) + { + is_eq = src1.ll[i] == src2.ll[i] ? 0xffffffffffffffffLL : 0LL; + if (is_eq != dst.ll[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pextrb.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pextrb.c new file mode 100644 index 000000000..bef4d2d16 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pextrb.c @@ -0,0 +1,87 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H +#include <smmintrin.h> + +#define msk0 0 +#define msk1 1 +#define msk2 2 +#define msk3 3 +#define msk4 4 +#define msk5 5 +#define msk6 6 +#define msk7 7 +#define msk8 8 +#define msk9 9 +#define msk10 10 +#define msk11 11 +#define msk12 12 +#define msk13 13 +#define msk14 14 +#define msk15 15 + +static void +TEST (void) +{ + union + { + __m128i x; + int i[4]; + char c[16]; + } val1; + int res[16], masks[16]; + int i; + + val1.i[0] = 0x04030201; + val1.i[1] = 0x08070605; + val1.i[2] = 0x0C0B0A09; + val1.i[3] = 0x100F0E0D; + + res[0] = _mm_extract_epi8 (val1.x, msk0); + res[1] = _mm_extract_epi8 (val1.x, msk1); + res[2] = _mm_extract_epi8 (val1.x, msk2); + res[3] = _mm_extract_epi8 (val1.x, msk3); + res[4] = _mm_extract_epi8 (val1.x, msk4); + res[5] = _mm_extract_epi8 (val1.x, msk5); + res[6] = _mm_extract_epi8 (val1.x, msk6); + res[7] = _mm_extract_epi8 (val1.x, msk7); + res[8] = _mm_extract_epi8 (val1.x, msk8); + res[9] = _mm_extract_epi8 (val1.x, msk9); + res[10] = _mm_extract_epi8 (val1.x, msk10); + res[11] = _mm_extract_epi8 (val1.x, msk11); + res[12] = _mm_extract_epi8 (val1.x, msk12); + res[13] = _mm_extract_epi8 (val1.x, msk13); + res[14] = _mm_extract_epi8 (val1.x, msk14); + res[15] = _mm_extract_epi8 (val1.x, msk15); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + masks[4] = msk4; + masks[5] = msk5; + masks[6] = msk6; + masks[7] = msk7; + masks[8] = msk8; + masks[9] = msk9; + masks[10] = msk10; + masks[11] = msk11; + masks[12] = msk12; + masks[13] = msk13; + masks[14] = msk14; + masks[15] = msk15; + + for (i = 0; i < 16; i++) + if (res[i] != val1.c [masks[i]]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pextrd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pextrd.c new file mode 100644 index 000000000..3091e5a05 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pextrd.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H +#include <smmintrin.h> + + +#define msk0 0 +#define msk1 1 +#define msk2 2 +#define msk3 3 + +static void +TEST (void) +{ + union + { + __m128i x; + int i[4]; + } val1; + int res[4], masks[4]; + int i; + + val1.i[0] = 0x04030201; + val1.i[1] = 0x08070605; + val1.i[2] = 0x0C0B0A09; + val1.i[3] = 0x100F0E0D; + + res[0] = _mm_extract_epi32 (val1.x, msk0); + res[1] = _mm_extract_epi32 (val1.x, msk1); + res[2] = _mm_extract_epi32 (val1.x, msk2); + res[3] = _mm_extract_epi32 (val1.x, msk3); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + + for (i = 0; i < 4; i++) + if (res[i] != val1.i [masks[i]]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c new file mode 100644 index 000000000..112dd37fd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c @@ -0,0 +1,45 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define msk0 0 +#define msk1 1 + +static void +__attribute__((noinline)) +TEST (void) +{ + union + { + __m128i x; + long long ll[2]; + } val1; + long long res[2]; + int masks[2]; + int i; + + val1.ll[0] = 0x0807060504030201LL; + val1.ll[1] = 0x100F0E0D0C0B0A09LL; + + res[0] = _mm_extract_epi64 (val1.x, msk0); + res[1] = _mm_extract_epi64 (val1.x, msk1); + + masks[0] = msk0; + masks[1] = msk1; + + for (i = 0; i < 2; i++) + if (res[i] != val1.ll [masks[i]]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pextrw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pextrw.c new file mode 100644 index 000000000..2a0f03c07 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pextrw.c @@ -0,0 +1,64 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define msk0 0 +#define msk1 1 +#define msk2 2 +#define msk3 3 +#define msk4 4 +#define msk5 5 +#define msk6 6 +#define msk7 7 + +static void +TEST (void) +{ + union + { + __m128i x; + int i[4]; + short s[8]; + } val1; + int res[8], masks[8]; + int i; + + val1.i[0] = 0x04030201; + val1.i[1] = 0x08070605; + val1.i[2] = 0x0C0B0A09; + val1.i[3] = 0x100F0E0D; + + res[0] = _mm_extract_epi16 (val1.x, msk0); + res[1] = _mm_extract_epi16 (val1.x, msk1); + res[2] = _mm_extract_epi16 (val1.x, msk2); + res[3] = _mm_extract_epi16 (val1.x, msk3); + res[4] = _mm_extract_epi16 (val1.x, msk4); + res[5] = _mm_extract_epi16 (val1.x, msk5); + res[6] = _mm_extract_epi16 (val1.x, msk6); + res[7] = _mm_extract_epi16 (val1.x, msk7); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + masks[4] = msk4; + masks[5] = msk5; + masks[6] = msk6; + masks[7] = msk7; + + for (i = 0; i < 8; i++) + if (res[i] != val1.s [masks[i]]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-2.c new file mode 100644 index 000000000..c9f9c1cdf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-2.c @@ -0,0 +1,78 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O3 -msse4.1 -mno-avx2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +extern void abort (void); + +#define N 1024 +short a[N], c, e; +unsigned short b[N], d, f; + +__attribute__((noinline)) short +vecsmax (void) +{ + int i; + short r = -32768; + for (i = 0; i < N; ++i) + if (r < a[i]) r = a[i]; + return r; +} + +__attribute__((noinline)) unsigned short +vecumax (void) +{ + int i; + unsigned short r = 0; + for (i = 0; i < N; ++i) + if (r < b[i]) r = b[i]; + return r; +} + +__attribute__((noinline)) short +vecsmin (void) +{ + int i; + short r = 32767; + for (i = 0; i < N; ++i) + if (r > a[i]) r = a[i]; + return r; +} + +__attribute__((noinline)) unsigned short +vecumin (void) +{ + int i; + unsigned short r = 65535; + for (i = 0; i < N; ++i) + if (r > b[i]) r = b[i]; + return r; +} + +static void +TEST (void) +{ + int i; + for (i = 0; i < N; ++i) + { + a[i] = i - N / 2; + b[i] = i + 32768 - N / 2; + } + a[N / 3] = N; + a[2 * N / 3] = -N; + b[N / 5] = 32768 + N; + b[4 * N / 5] = 32768 - N; + if (vecsmax () != N || vecsmin () != -N) + abort (); + if (vecumax () != 32768 + N || vecumin () != 32768 - N) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-3.c new file mode 100644 index 000000000..95c5f059d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse4.1 -mno-avx2" } */ + +#include "sse4_1-phminposuw-2.c" + +/* { dg-final { scan-assembler "phminposuw\[^\n\r\]*xmm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw.c new file mode 100644 index 000000000..ab4683401 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw.c @@ -0,0 +1,57 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 64 + +static void +TEST (void) +{ + union + { + __m128i x[NUM/8]; + unsigned short s[NUM]; + } src; + unsigned short minVal[NUM/8]; + int minInd[NUM/8]; + unsigned short minValScalar, minIndScalar; + int i, j, res; + + for (i = 0; i < NUM; i++) + src.s[i] = i * i / (i + i / 3.14 + 1.0); + + for (i = 0, j = 0; i < NUM; i += 8, j++) + { + res = _mm_cvtsi128_si32 (_mm_minpos_epu16 (src.x [i/8])); + minVal[j] = res & 0xffff; + minInd[j] = (res >> 16) & 0x3; + } + + for (i = 0; i < NUM; i += 8) + { + minValScalar = src.s[i]; + minIndScalar = 0; + + for (j = i + 1; j < i + 8; j++) + if (minValScalar > src.s[j]) + { + minValScalar = src.s[j]; + minIndScalar = j - i; + } + + if (minValScalar != minVal[i/8] && minIndScalar != minInd[i/8]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pinsrb.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pinsrb.c new file mode 100644 index 000000000..18427360f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pinsrb.c @@ -0,0 +1,110 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +#define msk0 0x00 +#define msk1 0x01 +#define msk2 0x02 +#define msk3 0x03 +#define msk4 0x04 +#define msk5 0x05 +#define msk6 0x06 +#define msk7 0x07 +#define msk8 0x08 +#define msk9 0x09 +#define mskA 0x0A +#define mskB 0x0B +#define mskC 0x0C +#define mskD 0x0D +#define mskE 0x0E +#define mskF 0x0F + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + unsigned char c[16]; + } res [16], val, tmp; + int masks[16]; + unsigned char ins[4] = { 3, 4, 5, 6 }; + int i; + + val.i[0] = 0x35251505; + val.i[1] = 0x75655545; + val.i[2] = 0xB5A59585; + val.i[3] = 0xF5E5D5C5; + + /* Check pinsrb imm8, r32, xmm. */ + res[0].x = _mm_insert_epi8 (val.x, ins[0], msk0); + res[1].x = _mm_insert_epi8 (val.x, ins[0], msk1); + res[2].x = _mm_insert_epi8 (val.x, ins[0], msk2); + res[3].x = _mm_insert_epi8 (val.x, ins[0], msk3); + res[4].x = _mm_insert_epi8 (val.x, ins[0], msk4); + res[5].x = _mm_insert_epi8 (val.x, ins[0], msk5); + res[6].x = _mm_insert_epi8 (val.x, ins[0], msk6); + res[7].x = _mm_insert_epi8 (val.x, ins[0], msk7); + res[8].x = _mm_insert_epi8 (val.x, ins[0], msk8); + res[9].x = _mm_insert_epi8 (val.x, ins[0], msk9); + res[10].x = _mm_insert_epi8 (val.x, ins[0], mskA); + res[11].x = _mm_insert_epi8 (val.x, ins[0], mskB); + res[12].x = _mm_insert_epi8 (val.x, ins[0], mskC); + res[13].x = _mm_insert_epi8 (val.x, ins[0], mskD); + res[14].x = _mm_insert_epi8 (val.x, ins[0], mskE); + res[15].x = _mm_insert_epi8 (val.x, ins[0], mskF); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + masks[4] = msk4; + masks[5] = msk5; + masks[6] = msk6; + masks[7] = msk7; + masks[8] = msk8; + masks[9] = msk9; + masks[10] = mskA; + masks[11] = mskB; + masks[12] = mskC; + masks[13] = mskD; + masks[14] = mskE; + masks[15] = mskF; + + for (i = 0; i < 16; i++) + { + tmp.x = val.x; + tmp.c[masks[i]] = ins[0]; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } + + /* Check pinsrb imm8, m8, xmm. */ + for (i = 0; i < 16; i++) + { + res[i].x = _mm_insert_epi8 (val.x, ins[i % 4], msk0); + masks[i] = msk0; + } + + for (i = 0; i < 16; i++) + { + tmp.x = val.x; + tmp.c[masks[i]] = ins[i % 4]; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pinsrd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pinsrd.c new file mode 100644 index 000000000..7a5d5fbc9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pinsrd.c @@ -0,0 +1,73 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +#define msk0 0x00 +#define msk1 0x01 +#define msk2 0x02 +#define msk3 0x03 + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + } res [4], val, tmp; + static unsigned int ins[4] = { 3, 4, 5, 6 }; + int masks[4]; + int i; + + val.i[0] = 55; + val.i[1] = 55; + val.i[2] = 55; + val.i[3] = 55; + + /* Check pinsrd imm8, r32, xmm. */ + res[0].x = _mm_insert_epi32 (val.x, ins[0], msk0); + res[1].x = _mm_insert_epi32 (val.x, ins[0], msk1); + res[2].x = _mm_insert_epi32 (val.x, ins[0], msk2); + res[3].x = _mm_insert_epi32 (val.x, ins[0], msk3); + + masks[0] = msk0; + masks[1] = msk1; + masks[2] = msk2; + masks[3] = msk3; + + for (i = 0; i < 4; i++) + { + tmp.x = val.x; + tmp.i[masks[i]] = ins[0]; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } + + /* Check pinsrd imm8, m32, xmm. */ + for (i = 0; i < 4; i++) + { + res[i].x = _mm_insert_epi32 (val.x, ins[i], msk0); + masks[i] = msk0; + } + + for (i = 0; i < 4; i++) + { + tmp.x = val.x; + tmp.i[masks[i]] = ins[i]; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c new file mode 100644 index 000000000..1ed0987bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c @@ -0,0 +1,67 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> +#include <string.h> + +#define msk0 0x00 +#define msk1 0x01 + +static void +__attribute__((noinline)) +TEST (void) +{ + union + { + __m128i x; + unsigned long long ll[2]; + } res [4], val, tmp; + int masks[4]; + static unsigned long long ins[2] = + { 0xAABBAABBAABBAABBLL, 0xCCDDCCDDCCDDCCDDLL }; + int i; + + val.ll[0] = 0x0807060504030201LL; + val.ll[1] = 0x100F0E0D0C0B0A09LL; + + /* Check pinsrq imm8, r64, xmm. */ + res[0].x = _mm_insert_epi64 (val.x, ins[0], msk0); + res[1].x = _mm_insert_epi64 (val.x, ins[0], msk1); + + masks[0] = msk0; + masks[1] = msk1; + + for (i = 0; i < 2; i++) + { + tmp.x = val.x; + tmp.ll[masks[i]] = ins[0]; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } + + /* Check pinsrq imm8, m64, xmm. */ + for (i = 0; i < 2; i++) + { + res[i].x = _mm_insert_epi64 (val.x, ins[i], msk0); + masks[i] = msk0; + } + + for (i = 0; i < 2; i++) + { + tmp.x = val.x; + tmp.ll[masks[i]] = ins[i]; + if (memcmp (&tmp, &res[i], sizeof (tmp))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsb.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsb.c new file mode 100644 index 000000000..ab445eefd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsb.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 1024 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 16]; + char i[NUM]; + } dst, src1, src2; + int i, sign = 1; + char max; + + for (i = 0; i < NUM; i++) + { + src1.i[i] = i * i * sign; + src2.i[i] = (i + 20) * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 16) + dst.x[i / 16] = _mm_max_epi8 (src1.x[i / 16], src2.x[i / 16]); + + for (i = 0; i < NUM; i++) + { + max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i]; + if (max != dst.i[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsd.c new file mode 100644 index 000000000..37c77aef5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsd.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 64 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 4]; + int i[NUM]; + } dst, src1, src2; + int i, sign = 1; + int max; + + for (i = 0; i < NUM; i++) + { + src1.i[i] = i * i * sign; + src2.i[i] = (i + 20) * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 4) + dst.x[i / 4] = _mm_max_epi32 (src1.x[i / 4], src2.x[i / 4]); + + for (i = 0; i < NUM; i++) + { + max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i]; + if (max != dst.i[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmaxud.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmaxud.c new file mode 100644 index 000000000..693c078fe --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmaxud.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 64 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 4]; + unsigned int i[NUM]; + } dst, src1, src2; + int i; + unsigned int max; + + for (i = 0; i < NUM; i++) + { + src1.i[i] = i * i; + src2.i[i] = i + 20; + if ((i % 4)) + src2.i[i] |= 0x80000000; + } + + for (i = 0; i < NUM; i += 4) + dst.x[i / 4] = _mm_max_epu32 (src1.x[i / 4], src2.x[i / 4]); + + for (i = 0; i < NUM; i++) + { + max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i]; + if (max != dst.i[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmaxuw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmaxuw.c new file mode 100644 index 000000000..7b5cfcd8f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmaxuw.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 64 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 8]; + unsigned short i[NUM]; + } dst, src1, src2; + int i; + unsigned short max; + + for (i = 0; i < NUM; i++) + { + src1.i[i] = i * i; + src2.i[i] = i + 20; + if ((i % 8)) + src2.i[i] |= 0x8000; + } + + for (i = 0; i < NUM; i += 8) + dst.x[i / 8] = _mm_max_epu16 (src1.x[i / 8], src2.x[i / 8]); + + for (i = 0; i < NUM; i++) + { + max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i]; + if (max != dst.i[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pminsb.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pminsb.c new file mode 100644 index 000000000..6f32d8b83 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pminsb.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 1024 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 16]; + char i[NUM]; + } dst, src1, src2; + int i, sign = 1; + char min; + + for (i = 0; i < NUM; i++) + { + src1.i[i] = i * i * sign; + src2.i[i] = (i + 20) * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 16) + dst.x[i / 16] = _mm_min_epi8 (src1.x[i / 16], src2.x[i / 16]); + + for (i = 0; i < NUM; i++) + { + min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i]; + if (min != dst.i[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pminsd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pminsd.c new file mode 100644 index 000000000..a3de148a0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pminsd.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 64 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 4]; + int i[NUM]; + } dst, src1, src2; + int i, sign = 1; + int min; + + for (i = 0; i < NUM; i++) + { + src1.i[i] = i * i * sign; + src2.i[i] = (i + 20) * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 4) + dst.x[i / 4] = _mm_min_epi32 (src1.x[i / 4], src2.x[i / 4]); + + for (i = 0; i < NUM; i++) + { + min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i]; + if (min != dst.i[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pminud.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pminud.c new file mode 100644 index 000000000..9daffc070 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pminud.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 64 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 4]; + unsigned int i[NUM]; + } dst, src1, src2; + int i; + unsigned int min; + + for (i = 0; i < NUM; i++) + { + src1.i[i] = i * i; + src2.i[i] = i + 20; + if ((i % 4)) + src2.i[i] |= 0x80000000; + } + + for (i = 0; i < NUM; i += 4) + dst.x[i / 4] = _mm_min_epu32 (src1.x[i / 4], src2.x[i / 4]); + + for (i = 0; i < NUM; i++) + { + min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i]; + if (min != dst.i[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pminuw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pminuw.c new file mode 100644 index 000000000..6ed5d9e2e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pminuw.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 64 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 8]; + unsigned short i[NUM]; + } dst, src1, src2; + int i; + unsigned short min; + + for (i = 0; i < NUM; i++) + { + src1.i[i] = i * i; + src2.i[i] = i + 20; + if ((i % 8)) + src2.i[i] |= 0x8000; + } + + for (i = 0; i < NUM; i += 8) + dst.x[i / 8] = _mm_min_epu16 (src1.x[i / 8], src2.x[i / 8]); + + for (i = 0; i < NUM; i++) + { + min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i]; + if (min != dst.i[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbd.c new file mode 100644 index 000000000..00ce3ef77 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbd.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 128 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 4]; + int i[NUM]; + char c[NUM * 4]; + } dst, src; + int i, sign = 1; + + for (i = 0; i < NUM; i++) + { + src.c[(i % 4) + (i / 4) * 16] = i * i * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 4) + dst.x [i / 4] = _mm_cvtepi8_epi32 (src.x [i / 4]); + + for (i = 0; i < NUM; i++) + if (src.c[(i % 4) + (i / 4) * 16] != dst.i[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbq.c new file mode 100644 index 000000000..0df6a61c7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbq.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 128 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 2]; + long long ll[NUM]; + char c[NUM * 8]; + } dst, src; + int i, sign = 1; + + for (i = 0; i < NUM; i++) + { + src.c[(i % 2) + (i / 2) * 16] = i * i * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 2) + dst.x [i / 2] = _mm_cvtepi8_epi64 (src.x [i / 2]); + + for (i = 0; i < NUM; i++) + if (src.c[(i % 2) + (i / 2) * 16] != dst.ll[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbw.c new file mode 100644 index 000000000..36accff4c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbw.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 128 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 8]; + short s[NUM]; + char c[NUM * 2]; + } dst, src; + int i, sign = 1; + + for (i = 0; i < NUM; i++) + { + src.c[(i % 8) + (i / 8) * 16] = i * i * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 8) + dst.x [i / 8] = _mm_cvtepi8_epi16 (src.x [i / 8]); + + for (i = 0; i < NUM; i++) + if (src.c[(i % 8) + (i / 8) * 16] != dst.s[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxdq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxdq.c new file mode 100644 index 000000000..e46ba1961 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxdq.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 128 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 2]; + long long ll[NUM]; + int i[NUM * 2]; + } dst, src; + int i, sign = 1; + + for (i = 0; i < NUM; i++) + { + src.i[(i % 2) + (i / 2) * 4] = i * i * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 2) + dst.x [i / 2] = _mm_cvtepi32_epi64 (src.x [i / 2]); + + for (i = 0; i < NUM; i++) + if (src.i[(i % 2) + (i / 2) * 4] != dst.ll[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwd.c new file mode 100644 index 000000000..61d9d3c2e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwd.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 128 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 4]; + int i[NUM]; + short s[NUM * 2]; + } dst, src; + int i, sign = 1; + + for (i = 0; i < NUM; i++) + { + src.s[(i % 4) + (i / 4) * 8] = i * i * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 4) + dst.x [i / 4] = _mm_cvtepi16_epi32 (src.x [i / 4]); + + for (i = 0; i < NUM; i++) + if (src.s[(i % 4) + (i / 4) * 8] != dst.i[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwq.c new file mode 100644 index 000000000..160d6467d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwq.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 128 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 2]; + long long ll[NUM]; + short s[NUM * 4]; + } dst, src; + int i, sign = 1; + + for (i = 0; i < NUM; i++) + { + src.s[(i % 2) + (i / 2) * 8] = i * i * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 2) + dst.x [i / 2] = _mm_cvtepi16_epi64 (src.x [i / 2]); + + for (i = 0; i < NUM; i++) + if (src.s[(i % 2) + (i / 2) * 8] != dst.ll[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbd.c new file mode 100644 index 000000000..6ebd6cf4e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbd.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 128 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 4]; + unsigned int i[NUM]; + unsigned char c[NUM * 4]; + } dst, src; + int i; + + for (i = 0; i < NUM; i++) + { + src.c[(i % 4) + (i / 4) * 16] = i * i; + if ((i % 4)) + src.c[(i % 4) + (i / 4) * 16] |= 0x80; + } + + for (i = 0; i < NUM; i += 4) + dst.x [i / 4] = _mm_cvtepu8_epi32 (src.x [i / 4]); + + for (i = 0; i < NUM; i++) + if (src.c[(i % 4) + (i / 4) * 16] != dst.i[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbq.c new file mode 100644 index 000000000..8b2f18a22 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbq.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 128 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 2]; + unsigned long long ll[NUM]; + unsigned char c[NUM * 8]; + } dst, src; + int i; + + for (i = 0; i < NUM; i++) + { + src.c[(i % 2) + (i / 2) * 16] = i * i; + if ((i % 2)) + src.c[(i % 2) + (i / 2) * 16] |= 0x80; + } + + for (i = 0; i < NUM; i += 2) + dst.x [i / 2] = _mm_cvtepu8_epi64 (src.x [i / 2]); + + for (i = 0; i < NUM; i++) + if (src.c[(i % 2) + (i / 2) * 16] != dst.ll[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbw.c new file mode 100644 index 000000000..8e1452bf7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbw.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 128 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 8]; + unsigned short s[NUM]; + unsigned char c[NUM * 2]; + } dst, src; + int i; + + for (i = 0; i < NUM; i++) + { + src.c[(i % 8) + (i / 8) * 16] = i * i; + if ((i % 4)) + src.c[(i % 8) + (i / 8) * 16] |= 0x80; + } + + for (i = 0; i < NUM; i += 8) + dst.x [i / 8] = _mm_cvtepu8_epi16 (src.x [i / 8]); + + for (i = 0; i < NUM; i++) + if (src.c[(i % 8) + (i / 8) * 16] != dst.s[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxdq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxdq.c new file mode 100644 index 000000000..cb2a4383e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxdq.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 128 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 2]; + unsigned long long ll[NUM]; + unsigned int i[NUM * 2]; + } dst, src; + int i; + + for (i = 0; i < NUM; i++) + { + src.i[(i % 2) + (i / 2) * 4] = i * i; + if ((i % 2)) + src.i[(i % 2) + (i / 2) * 4] |= 0x80000000; + } + + for (i = 0; i < NUM; i += 2) + dst.x [i / 2] = _mm_cvtepu32_epi64 (src.x [i / 2]); + + for (i = 0; i < NUM; i++) + if (src.i[(i % 2) + (i / 2) * 4] != dst.ll[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwd.c new file mode 100644 index 000000000..b525f4c6a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwd.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 128 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 4]; + unsigned int i[NUM]; + unsigned short s[NUM * 2]; + } dst, src; + int i; + + for (i = 0; i < NUM; i++) + { + src.s[(i % 4) + (i / 4) * 8] = i * i; + if ((i % 4)) + src.s[(i % 4) + (i / 4) * 8] |= 0x8000; + } + + for (i = 0; i < NUM; i += 4) + dst.x [i / 4] = _mm_cvtepu16_epi32 (src.x [i / 4]); + + for (i = 0; i < NUM; i++) + if (src.s[(i % 4) + (i / 4) * 8] != dst.i[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwq.c new file mode 100644 index 000000000..98f552aac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwq.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 128 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 2]; + unsigned long long ll[NUM]; + unsigned short s[NUM * 4]; + } dst, src; + int i; + + for (i = 0; i < NUM; i++) + { + src.s[(i % 2) + (i / 2) * 8] = i * i; + if ((i % 2)) + src.s[(i % 2) + (i / 2) * 8] |= 0x8000; + } + + for (i = 0; i < NUM; i += 2) + dst.x [i / 2] = _mm_cvtepu16_epi64 (src.x [i / 2]); + + for (i = 0; i < NUM; i++) + if (src.s[(i % 2) + (i / 2) * 8] != dst.ll[i]) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmuldq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmuldq.c new file mode 100644 index 000000000..fc3830a45 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmuldq.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 64 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 2]; + long long ll[NUM]; + } dst; + union + { + __m128i x[NUM / 2]; + int i[NUM * 2]; + } src1, src2; + int i, sign = 1; + long long value; + + for (i = 0; i < NUM * 2; i += 2) + { + src1.i[i] = i * i * sign; + src2.i[i] = (i + 20) * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 2) + dst.x[i / 2] = _mm_mul_epi32 (src1.x[i / 2], src2.x[i / 2]); + + for (i = 0; i < NUM; i++) + { + value = (long long) src1.i[i * 2] * (long long) src2.i[i * 2]; + if (value != dst.ll[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmulld.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmulld.c new file mode 100644 index 000000000..9fb77d0ac --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-pmulld.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define NUM 64 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 4]; + int i[NUM]; + } dst, src1, src2; + int i, sign = 1; + int value; + + for (i = 0; i < NUM; i++) + { + src1.i[i] = i * i * sign; + src2.i[i] = (i + 20) * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 4) + dst.x[i / 4] = _mm_mullo_epi32 (src1.x[i / 4], src2.x[i / 4]); + + for (i = 0; i < NUM; i++) + { + value = src1.i[i] * src2.i[i]; + if (value != dst.i[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ptest-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ptest-1.c new file mode 100644 index 000000000..8b57a2111 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ptest-1.c @@ -0,0 +1,117 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +static int +make_ptestz (__m128i m, __m128i v) +{ + union + { + __m128i x; + unsigned char c[16]; + } val, mask; + int i, z; + + mask.x = m; + val.x = v; + + z = 1; + for (i = 0; i < 16; i++) + if ((mask.c[i] & val.c[i])) + { + z = 0; + break; + } + return z; +} + +static int +make_ptestc (__m128i m, __m128i v) +{ + union + { + __m128i x; + unsigned char c[16]; + } val, mask; + int i, c; + + mask.x = m; + val.x = v; + + c = 1; + for (i = 0; i < 16; i++) + if ((val.c[i] & ~mask.c[i])) + { + c = 0; + break; + } + return c; +} + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + } val[4]; + int i, j, l; + int res[32]; + + val[0].i[0] = 0x11111111; + val[0].i[1] = 0x00000000; + val[0].i[2] = 0x00000000; + val[0].i[3] = 0x11111111; + + val[1].i[0] = 0x00000000; + val[1].i[1] = 0x11111111; + val[1].i[2] = 0x11111111; + val[1].i[3] = 0x00000000; + + val[2].i[0] = 0; + val[2].i[1] = 0; + val[2].i[2] = 0; + val[2].i[3] = 0; + + val[3].i[0] = 0xffffffff; + val[3].i[1] = 0xffffffff; + val[3].i[2] = 0xffffffff; + val[3].i[3] = 0xffffffff; + + l = 0; + for(i = 0; i < 4; i++) + for(j = 0; j < 4; j++) + { + res[l++] = _mm_testz_si128 (val[j].x, val[i].x); + res[l++] = _mm_testc_si128 (val[j].x, val[i].x); + } + + l = 0; + for(i = 0; i < 4; i++) + for(j = 0; j < 4; j++) + { + if (res[l++] != make_ptestz (val[j].x, val[i].x)) + abort (); + if (res[l++] != make_ptestc (val[j].x, val[i].x)) + abort (); + } + + if (res[2] != _mm_testz_si128 (val[1].x, val[0].x)) + abort (); + + if (res[3] != _mm_testc_si128 (val[1].x, val[0].x)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ptest-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ptest-2.c new file mode 100644 index 000000000..2e6df9538 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ptest-2.c @@ -0,0 +1,96 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +static int +make_ptestnzc (__m128i m, __m128i v) +{ + union + { + __m128i x; + unsigned char c[16]; + } val, mask; + int i, z, c; + + mask.x = m; + val.x = v; + + z = c = 1; + for (i = 0; i < 16; i++) + { + if ((mask.c[i] & val.c[i])) + z = 0; + if ((~mask.c[i] & val.c[i])) + c = 0; + } + + return (z == 0 && c == 0) ? 1 : 0; +} + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + } val[4]; + int i, j, l; + int res[32]; + + val[0].i[0] = 0x11111111; + val[0].i[1] = 0x00000000; + val[0].i[2] = 0x00000000; + val[0].i[3] = 0x11111111; + + val[1].i[0] = 0x00000000; + val[1].i[1] = 0x11111111; + val[1].i[2] = 0x11111111; + val[1].i[3] = 0x00000000; + + val[2].i[0] = 0; + val[2].i[1] = 0; + val[2].i[2] = 0; + val[2].i[3] = 0; + + val[3].i[0] = 0xffffffff; + val[3].i[1] = 0xffffffff; + val[3].i[2] = 0xffffffff; + val[3].i[3] = 0xffffffff; + + l = 0; + for(i = 0; i < 4; i++) + for(j = 0; j < 4; j++) + { + res[l++] = _mm_testnzc_si128 (val[j].x, val[i].x); + res[l++] = _mm_testnzc_si128 (val[j].x, val[i].x); + } + + l = 0; + for(i = 0; i < 4; i++) + for(j = 0; j < 4; j++) + { + if (res[l++] != make_ptestnzc (val[j].x, val[i].x)) + abort (); + if (res[l++] != make_ptestnzc (val[j].x, val[i].x)) + abort (); + } + + if (res[2] != _mm_testnzc_si128 (val[1].x, val[0].x)) + abort (); + + if (res[3] != _mm_testnzc_si128 (val[1].x, val[0].x)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ptest-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ptest-3.c new file mode 100644 index 000000000..bf2df320e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-ptest-3.c @@ -0,0 +1,85 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +static void +TEST (void) +{ + union + { + __m128i x; + unsigned int i[4]; + } val[4]; + int correct_zeros[4]; + int correct_ones[4]; + int correct_mixed[4]; + int zeros[4]; + int ones[4]; + int mixed[4]; + int i; + __m128i v; + + val[0].i[0] = 0x11111111; + val[0].i[1] = 0x00000000; + val[0].i[2] = 0x00000000; + val[0].i[3] = 0x11111111; + correct_zeros[0] = 0; + correct_ones[0] = 0; + correct_mixed[0] = 1; + + val[1].i[0] = 0x00000000; + val[1].i[1] = 0x11111111; + val[1].i[2] = 0x11111111; + val[1].i[3] = 0x00000000; + correct_zeros[1] = 0; + correct_ones[1] = 0; + correct_mixed[1] = 1; + + val[2].i[0] = 0; + val[2].i[1] = 0; + val[2].i[2] = 0; + val[2].i[3] = 0; + correct_zeros[2] = 1; + correct_ones[2] = 0; + correct_mixed[2] = 0; + + val[3].i[0] = 0xffffffff; + val[3].i[1] = 0xffffffff; + val[3].i[2] = 0xffffffff; + val[3].i[3] = 0xffffffff; + correct_zeros[3] = 0; + correct_ones[3] = 1; + correct_mixed[3] = 0; + + for (i=0; i < 4; i++) + zeros[i] = _mm_test_all_zeros (val[i].x, val[i].x); + + for( i=0; i < 4; i++ ) + ones[i] = _mm_test_all_ones (val[i].x); + + v = _mm_cmpeq_epi32 (val[0].x, val[0].x); + for( i=0; i < 4; i++ ) + mixed[i] = _mm_test_mix_ones_zeros (val[i].x, v); + + for( i=0; i < 4; i++ ) + { + if (zeros[i] != correct_zeros[i]) + abort (); + if (ones[i] != correct_ones[i]) + abort (); + if (mixed[i] != correct_mixed[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-rint-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-rint-sfix-vec.c new file mode 100644 index 000000000..d9c2fbf2d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-rint-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double rint (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) rint (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) rint (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-rint-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-rint-vec.c new file mode 100644 index 000000000..f20359a1a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-rint-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double rint (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = rint (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != rint (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-rintf-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-rintf-sfix-vec.c new file mode 100644 index 000000000..1d25f7669 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-rintf-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float rintf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) rintf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) rintf (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-rintf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-rintf-vec.c new file mode 100644 index 000000000..716cad1e3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-rintf-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float rintf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = rintf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != rintf (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-round-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-round-sfix-vec.c new file mode 100644 index 000000000..9abbe55b7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-round-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double round (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) round (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) round (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-round-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-round-vec.c new file mode 100644 index 000000000..bb912cef9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-round-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double round (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = round (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != round (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-round.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-round.h new file mode 100644 index 000000000..0210ac130 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-round.h @@ -0,0 +1,95 @@ +#include <smmintrin.h> +#include <math.h> + +#define NUM 64 + +static void +init_round (FP_T *src) +{ + int i, sign = 1; + FP_T f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1)* f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI *sign); + sign = -sign; + } +} + +static FP_T +do_round (FP_T f, int type) +{ + short saved_cw, new_cw, clr_mask; + FP_T ret; + + if ((type & 4)) + { + type = 0; + clr_mask = 0xFFFF; + } + else + { + type = 0x003F | ((type & 3) << 10); + clr_mask = ~0x0C3F; + } + + __asm__ ("fld" ASM_SUFFIX " %0" : : "m" (*&f)); + + __asm__ ("fstcw %0" : "=m" (*&saved_cw)); + new_cw = saved_cw & clr_mask; + new_cw |= type; + __asm__ ("fldcw %0" : : "m" (*&new_cw)); + + __asm__ ("frndint\n" + "fstp" ASM_SUFFIX " %0\n" : "=m" (*&ret)); + __asm__ ("fldcw %0" : : "m" (*&saved_cw)); + return ret; +} + +static void +sse4_1_test (void) +{ + int i; + FP_T f; + union + { + VEC_T x[NUM / LOOP_INCREMENT]; + FP_T f[NUM]; + } dst, src; + + init_round (src.f); + + for (i = 0; i < NUM / LOOP_INCREMENT; i++) + dst.x[i] = ROUND_INTRIN (src.x[i], ROUND_MODE); + + for (i = 0; i < NUM; i += CHECK_LOOP_INCREMENT) + { + f = do_round (src.f[i], CHECK_ROUND_MODE); + if (f != dst.f[i]) + abort (); + } + + if (_MM_FROUND_TO_NEAREST_INT != 0x00 + || _MM_FROUND_TO_NEG_INF != 0x01 + || _MM_FROUND_TO_POS_INF != 0x02 + || _MM_FROUND_TO_ZERO != 0x03 + || _MM_FROUND_CUR_DIRECTION != 0x04 + || _MM_FROUND_RAISE_EXC != 0x00 + || _MM_FROUND_NO_EXC != 0x08 + || _MM_FROUND_NINT != 0x00 + || _MM_FROUND_FLOOR != 0x01 + || _MM_FROUND_CEIL != 0x02 + || _MM_FROUND_TRUNC != 0x03 + || _MM_FROUND_RINT != 0x04 + || _MM_FROUND_NEARBYINT != 0x0C) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundf-sfix-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundf-sfix-vec.c new file mode 100644 index 000000000..5384e5c62 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundf-sfix-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float roundf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + int r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = (int) roundf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != (int) roundf (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundf-vec.c new file mode 100644 index 000000000..d254aa66b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundf-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float roundf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = roundf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != roundf (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-1.c new file mode 100644 index 000000000..8baee3390 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +#define iRoundMode 0x2 + +static void +TEST (void) +{ + union128d u, s; + double e[2] = {0.0}; + int i; + + s.x = _mm_set_pd (1.1234, -2.3478); + u.x = _mm_round_pd (s.x, iRoundMode); + + for (i = 0; i < 2; i++) + { + __m128d tmp = _mm_load_sd (&s.a[i]); + tmp = _mm_round_sd (tmp, tmp, iRoundMode); + _mm_store_sd (&e[i], tmp); + } + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-2.c new file mode 100644 index 000000000..86b78ed75 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-2.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +static void +TEST (void) +{ + union128d u, s; + double e[2] = {0.0}; + int i; + + s.x = _mm_set_pd (1.1234, -2.3478); + u.x = _mm_floor_pd (s.x); + + for (i = 0; i < 2; i++) + { + __m128d tmp = _mm_load_sd (&s.a[i]); + tmp = _mm_floor_sd (tmp, tmp); + _mm_store_sd (&e[i], tmp); + } + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-3.c new file mode 100644 index 000000000..6e6a05c59 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-3.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <smmintrin.h> + +static void +TEST (void) +{ + union128d u, s; + double e[2] = {0.0}; + int i; + + s.x = _mm_set_pd (1.1234, -2.3478); + u.x = _mm_ceil_pd (s.x); + + for (i = 0; i < 2; i++) + { + __m128d tmp = _mm_load_sd (&s.a[i]); + tmp = _mm_ceil_sd (tmp, tmp); + _mm_store_sd (&e[i], tmp); + } + + if (check_union128d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundps-1.c new file mode 100644 index 000000000..71bc51be2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundps-1.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#include "sse4_1-check.h" + +#define VEC_T __m128 +#define FP_T float +#define ASM_SUFFIX "s" + +#define ROUND_INTRIN(x, mode) _mm_ceil_ps(x) +#define ROUND_MODE _MM_FROUND_CEIL +#define CHECK_ROUND_MODE 0x02 + +#define LOOP_INCREMENT 4 +#define CHECK_LOOP_INCREMENT 1 + +#include "sse4_1-round.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundps-2.c new file mode 100644 index 000000000..672e92067 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundps-2.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#include "sse4_1-check.h" + +#define VEC_T __m128 +#define FP_T float +#define ASM_SUFFIX "s" + +#define ROUND_INTRIN _mm_round_ps +#define ROUND_MODE _MM_FROUND_NINT +#define CHECK_ROUND_MODE 0x00 + +#define LOOP_INCREMENT 4 +#define CHECK_LOOP_INCREMENT 1 + +#include "sse4_1-round.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundps-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundps-3.c new file mode 100644 index 000000000..4bfc1cacc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundps-3.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#include "sse4_1-check.h" + +#define VEC_T __m128 +#define FP_T float +#define ASM_SUFFIX "s" + +#define ROUND_INTRIN(x, mode) _mm_floor_ps(x) +#define ROUND_MODE _MM_FROUND_FLOOR +#define CHECK_ROUND_MODE 0x01 + +#define LOOP_INCREMENT 4 +#define CHECK_LOOP_INCREMENT 1 + +#include "sse4_1-round.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-1.c new file mode 100644 index 000000000..ae8881cf0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-1.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#include "sse4_1-check.h" + +#define VEC_T __m128d +#define FP_T double +#define ASM_SUFFIX "l" + +#define ROUND_INTRIN(x, mode) _mm_ceil_sd(x, x) +#define ROUND_MODE _MM_FROUND_CEIL +#define CHECK_ROUND_MODE 0x02 + +#define LOOP_INCREMENT 2 +#define CHECK_LOOP_INCREMENT 2 + +#include "sse4_1-round.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-2.c new file mode 100644 index 000000000..70679bb07 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-2.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#include "sse4_1-check.h" + +#define VEC_T __m128d +#define FP_T double +#define ASM_SUFFIX "l" + +#define ROUND_INTRIN(x, mode) _mm_round_sd(x, x, mode) +#define ROUND_MODE _MM_FROUND_NINT +#define CHECK_ROUND_MODE 0x00 + +#define LOOP_INCREMENT 2 +#define CHECK_LOOP_INCREMENT 2 + +#include "sse4_1-round.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-3.c new file mode 100644 index 000000000..81a3f7606 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-3.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#include "sse4_1-check.h" + +#define VEC_T __m128d +#define FP_T double +#define ASM_SUFFIX "l" + +#define ROUND_INTRIN(x, mode) _mm_floor_sd(x, x) +#define ROUND_MODE _MM_FROUND_FLOOR +#define CHECK_ROUND_MODE 0x01 + +#define LOOP_INCREMENT 2 +#define CHECK_LOOP_INCREMENT 2 + +#include "sse4_1-round.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-4.c new file mode 100644 index 000000000..124f82502 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-4.c @@ -0,0 +1,92 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#include "sse4_1-check.h" + +#include <smmintrin.h> +#include <math.h> +#include <string.h> + +#define NUM 64 + +static void +init_round (double *src) +{ + int i, sign = 1; + double d = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1)* d * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + d = d * src[i]; + } + else if (i == (NUM / 2)) + d = rand (); + else if ((i % 6) == 0) + d = 1 / (d * (i + 1) * src[i] * M_PI *sign); + sign = -sign; + } +} + +static double +do_round (double f, int type) +{ + short saved_cw, new_cw, clr_mask; + double ret; + + if ((type & 4)) + { + type = 0; + clr_mask = 0xFFFF; + } + else + { + type = 0x003F | ((type & 3) << 10); + clr_mask = ~0x0C3F; + } + + __asm__ ("fldl %0" : : "m" (*&f)); + + __asm__ ("fstcw %0" : "=m" (*&saved_cw)); + new_cw = saved_cw & clr_mask; + new_cw |= type; + __asm__ ("fldcw %0" : : "m" (*&new_cw)); + + __asm__ ("frndint\n" + "fstpl %0\n" : "=m" (*&ret)); + __asm__ ("fldcw %0" : : "m" (*&saved_cw)); + return ret; +} + +static void +sse4_1_test (void) +{ + int i; + double f; + union + { + __m128d x[NUM / 2]; + double d[NUM]; + } dst, src; + + init_round (src.d); + memset (&dst, 0, NUM * sizeof(double)); + + for (i = 0; i < NUM / 2 ; i++) + dst.x[i] = _mm_round_sd (dst.x[i], src.x[i], _MM_FROUND_TRUNC); + + for (i = 0; i < NUM; i += 2) + { + if (dst.d[i + 1] != 0.0) + abort (); + + f = do_round (src.d[i], 0x03); + if (f != dst.d[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c new file mode 100644 index 000000000..96dd8a6a7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#include "sse4_1-check.h" + +#define VEC_T __m128 +#define FP_T float +#define ASM_SUFFIX "s" + +#define ROUND_INTRIN(x, mode) _mm_ceil_ss(x, x) +#define ROUND_MODE _MM_FROUND_CEIL +#define CHECK_ROUND_MODE 0x02 + +#define LOOP_INCREMENT 4 +#define CHECK_LOOP_INCREMENT 4 + +#include "sse4_1-round.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c new file mode 100644 index 000000000..f052c029f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#include "sse4_1-check.h" + +#define VEC_T __m128 +#define FP_T float +#define ASM_SUFFIX "s" + +#define ROUND_INTRIN(x, mode) _mm_round_ss(x, x, mode) +#define ROUND_MODE _MM_FROUND_NINT +#define CHECK_ROUND_MODE 0x00 + +#define LOOP_INCREMENT 4 +#define CHECK_LOOP_INCREMENT 4 + +#include "sse4_1-round.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c new file mode 100644 index 000000000..0a696b1cf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#include "sse4_1-check.h" + +#define VEC_T __m128 +#define FP_T float +#define ASM_SUFFIX "s" + +#define ROUND_INTRIN(x, mode) _mm_floor_ss(x, x) +#define ROUND_MODE _MM_FROUND_FLOOR +#define CHECK_ROUND_MODE 0x01 + +#define LOOP_INCREMENT 4 +#define CHECK_LOOP_INCREMENT 4 + +#include "sse4_1-round.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundss-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundss-4.c new file mode 100644 index 000000000..71042d1b7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-roundss-4.c @@ -0,0 +1,107 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#include "sse4_1-check.h" + +#include <smmintrin.h> +#include <math.h> +#include <string.h> + +#define NUM 64 + +static void +init_round (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1)* f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI *sign); + sign = -sign; + } +} + +static float +do_round (float f, int type) +{ + short saved_cw, new_cw, clr_mask; + float ret; + + if ((type & 4)) + { + type = 0; + clr_mask = 0xFFFF; + } + else + { + type = 0x003F | ((type & 3) << 10); + clr_mask = ~0x0C3F; + } + + __asm__ ("flds %0" : : "m" (*&f)); + + __asm__ ("fstcw %0" : "=m" (*&saved_cw)); + new_cw = saved_cw & clr_mask; + new_cw |= type; + __asm__ ("fldcw %0" : : "m" (*&new_cw)); + + __asm__ ("frndint\n" + "fstps %0\n" : "=m" (*&ret)); + __asm__ ("fldcw %0" : : "m" (*&saved_cw)); + return ret; +} + +static void +sse4_1_test (void) +{ + int i, j; + float f; + union + { + __m128 x[NUM / 4]; + float f[NUM]; + } dst, src; + + init_round (src.f); + memset (&dst, 0, NUM * sizeof(float)); + + for (i = 0; i < NUM / 4 ; i++) + dst.x[i] = _mm_round_ss (dst.x[i], src.x[i], _MM_FROUND_RINT); + + for (i = 0; i < NUM; i += 4) + { + for (j = 0; j < 3; j++) + if (dst.f[i + j + 1] != 0.0) + abort (); + + f = do_round (src.f[i], 0x04); + if (f != dst.f[i]) + abort (); + } + + for (i = 0; i < NUM / 4 ; i++) + dst.x[i] = _mm_round_ss (dst.x[i], src.x[i], _MM_FROUND_NEARBYINT); + + for (i = 0; i < NUM; i += 4) + { + for (j = 0; j < 3; j++) + if (dst.f[i + j + 1] != 0.0) + abort (); + + f = do_round (src.f[i], 0x0c); + if (f != dst.f[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c new file mode 100644 index 000000000..989e4f708 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <emmintrin.h> + +static void +__attribute__((noinline)) +test (unsigned int *v) +{ + union + { + __m128i x; + unsigned int i[4]; + } u; + unsigned int i; + + u.x = _mm_set_epi32 (v[3], v[2], v[1], v[0]); + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]); +#endif + abort (); + } +} + +static void +sse4_1_test (void) +{ + unsigned int v[4] + = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c new file mode 100644 index 000000000..8679f5286 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <emmintrin.h> + +static void +__attribute__((noinline)) +test (unsigned long long *v) +{ + union + { + __m128i x; + unsigned long long i[2]; + } u; + unsigned int i; + + u.x = _mm_set_epi64x (v[1], v[0]); + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (v[i] != u.i[i]) + { +#ifdef DEBUG + printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]); +#endif + abort (); + } +} + +static void +sse4_1_test (void) +{ + unsigned long long v[2] + = { 0x7B5B546573745665LL, 0x63746F725D53475DLL }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-ps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-ps-1.c new file mode 100644 index 000000000..fe77d94ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-ps-1.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#ifdef DEBUG +#include <stdio.h> +#endif + +#include <xmmintrin.h> + +static void +__attribute__((noinline)) +test (float *v) +{ + union + { + __m128 x; + float f[4]; + } u; + unsigned int i; + + u.x = _mm_set_ps (v[3], v[2], v[1], v[0]); + + for (i = 0; i < sizeof (v) / sizeof (v[0]); i++) + if (v[i] != u.f[i]) + { +#ifdef DEBUG + printf ("%i: %f != %f\n", i, v[i], u.f[i]); +#endif + abort (); + } +} + +static void +sse4_1_test (void) +{ + float v[4] = { -3, 2, 1, 9 }; + test (v); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1.c new file mode 100644 index 000000000..23c090330 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "set-v16qi-1.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c new file mode 100644 index 000000000..b8612962d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -mtune=core2 -msse4.1" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "set-v16qi-1.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2.c new file mode 100644 index 000000000..524587082 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "set-v16qi-2.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c new file mode 100644 index 000000000..21f1692cd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -mtune=core2 -msse4.1" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "set-v16qi-2.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3.c new file mode 100644 index 000000000..99f563ab1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "set-v16qi-3.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c new file mode 100644 index 000000000..1065a843a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -mtune=core2 -msse4.1" } */ + +#define CHECK_H "sse4_1-check.h" +#define TEST sse4_1_test + +#include "set-v16qi-3.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-trunc-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-trunc-vec.c new file mode 100644 index 000000000..9cbcd9b39 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-trunc-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern double trunc (double); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (double *src) +{ + int i, sign = 1; + double f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + double a[NUM]; + double r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = trunc (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != trunc (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-truncf-vec.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-truncf-vec.c new file mode 100644 index 000000000..815b50814 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_1-truncf-vec.c @@ -0,0 +1,62 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-skip-if "no M_PI" { vxworks_kernel } } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_1-check.h" +#endif + +#ifndef TEST +#define TEST sse4_1_test +#endif + +#include CHECK_H + +#include <math.h> + +extern float truncf (float); + +#define NUM 64 + +static void +__attribute__((__target__("fpmath=sse"))) +init_src (float *src) +{ + int i, sign = 1; + float f = rand (); + + for (i = 0; i < NUM; i++) + { + src[i] = (i + 1) * f * M_PI * sign; + if (i < (NUM / 2)) + { + if ((i % 6) == 0) + f = f * src[i]; + } + else if (i == (NUM / 2)) + f = rand (); + else if ((i % 6) == 0) + f = 1 / (f * (i + 1) * src[i] * M_PI * sign); + sign = -sign; + } +} + +static void +__attribute__((__target__("fpmath=387"))) +TEST (void) +{ + float a[NUM]; + float r[NUM]; + int i; + + init_src (a); + + for (i = 0; i < NUM; i++) + r[i] = truncf (a[i]); + + /* check results: */ + for (i = 0; i < NUM; i++) + if (r[i] != truncf (a[i])) + abort(); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-check.h new file mode 100644 index 000000000..d10e6c7d7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-check.h @@ -0,0 +1,28 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void sse4_2_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + sse4_2_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run SSE4.2 test only if host has SSE4.2 support. */ + if (ecx & bit_SSE4_2) + do_test (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32.h new file mode 100644 index 000000000..c0bcd16cc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32.h @@ -0,0 +1,163 @@ +#include "sse4_2-check.h" + +#include <nmmintrin.h> +#include <string.h> + +#define POLYNOMIAL 0x11EDC6F41LL + +#define MAX_BUF 16 + +static void +shift_mem_by1 (unsigned char* buf, int len) +{ + int i; + + for (i = len - 1; i >= 0; i--) + { + buf[i] = buf[i] << 1; + if (i > 0 && (buf[i-1] & 0x80)) + buf[i] |= 1; + } +} + +static void +do_div (unsigned char* buf, unsigned char* div) +{ + int i; + for (i = 0; i < 5; i++) + buf[i] ^= div[i]; +} + +static unsigned int +calc_rem (unsigned char* buf, int len) +{ + union + { + unsigned long long ll; + unsigned char c[8]; + } divisor; + union + { + unsigned int i; + unsigned char c[4]; + } ret; + unsigned char *div_buf; + unsigned char divident[MAX_BUF]; + int disp = len / 8; + int i; + + divisor.ll = POLYNOMIAL << 7LL; + + memcpy (divident, buf, disp); + + div_buf = divident + disp - 5; + + for (i = 0; i < len - 32; i++) + { + if ((div_buf[4] & 0x80)) + do_div (div_buf, divisor.c); + shift_mem_by1 (divident, disp); + } + + memcpy (ret.c, div_buf + 1, sizeof (ret)); + return ret.i; +} + +static void +reverse_bits (unsigned char *src, int len) +{ + unsigned char buf[MAX_BUF]; + unsigned char *tmp = buf + len - 1; + unsigned char ch; + int i, j; + + for (i = 0; i < len; i++) + { + ch = 0; + for (j = 0; j < 8; j++) + if ((src[i] & (1 << j))) + ch |= 1 << (7 - j); + *tmp-- = ch; + } + + for (i = 0; i < len; i++) + src[i] = buf[i]; +} + +static void +shift_mem ( unsigned char *src, unsigned char *dst, int len, int shft) +{ + int disp = shft / 8; + int i; + + memset (dst, 0, len + disp); + for (i = 0; i < len; i++) + dst[i + disp] = src[i]; +} + +static void +xor_mem (unsigned char *src, unsigned char *dst, int len) +{ + int disp = len / 8; + int i; + + for (i = 0; i < disp; i++) + dst[i] ^= src[i]; +} + +static DST_T +compute_crc32 (DST_T crc, SRC_T inp) +{ + unsigned char crcbuf[sizeof (DST_T)]; + unsigned char inbuf[sizeof (SRC_T)]; + unsigned char tmp1[MAX_BUF], tmp2[MAX_BUF]; + int crc_sh, xor_sz; + union + { + unsigned int i; + unsigned char c[4]; + } ret; + + crc_sh = sizeof (SRC_T) * 8; + xor_sz = 32 + crc_sh; + memcpy (crcbuf, &crc, sizeof (DST_T)); + memcpy (inbuf, &inp, sizeof (SRC_T)); + + reverse_bits (crcbuf, 4); + reverse_bits (inbuf, sizeof (SRC_T)); + + shift_mem (inbuf, tmp1, sizeof (SRC_T), 32); + shift_mem (crcbuf, tmp2, 4, crc_sh); + + xor_mem (tmp1, tmp2, xor_sz); + + ret.i = calc_rem (tmp2, xor_sz); + + reverse_bits (ret.c, 4); + + return (DST_T)ret.i; +} + +#define NUM 1024 + +static void +sse4_2_test (void) +{ + DST_T dst[NUM]; + SRC_T src[NUM]; + int i; + + for (i = 0; i < NUM; i++) + { + dst[i] = rand (); + if (sizeof (DST_T) > 4) + dst[i] |= (DST_T)rand () << (DST_T)(sizeof (DST_T) * 4); + src[i] = rand (); + if (sizeof (SRC_T) > 4) + src[i] |= (SRC_T)rand () << (SRC_T)(sizeof (DST_T) * 4); + } + + for (i = 0; i < NUM; i++) + if (CRC32 (dst[i], src[i]) != compute_crc32 (dst[i], src[i])) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32b.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32b.c new file mode 100644 index 000000000..05a609cd1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32b.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#define CRC32 _mm_crc32_u8 +#define DST_T unsigned int +#define SRC_T unsigned char + +#include "sse4_2-crc32.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32l.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32l.c new file mode 100644 index 000000000..00cdf6ad3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32l.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#define CRC32 _mm_crc32_u32 +#define DST_T unsigned int +#define SRC_T unsigned int + +#include "sse4_2-crc32.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c new file mode 100644 index 000000000..f1f75d916 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c @@ -0,0 +1,9 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#define CRC32 _mm_crc32_u64 +#define DST_T unsigned long long +#define SRC_T unsigned long long + +#include "sse4_2-crc32.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32w.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32w.c new file mode 100644 index 000000000..03991e553 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-crc32w.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#define CRC32 _mm_crc32_u16 +#define DST_T unsigned int +#define SRC_T unsigned short + +#include "sse4_2-crc32.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-1.c new file mode 100644 index 000000000..5b7f3ad77 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-1.c @@ -0,0 +1,83 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_2-check.h" +#endif + +#ifndef TEST +#define TEST sse4_2_test +#endif + +#include CHECK_H + +#include "sse4_2-pcmpstr.h" + +#define NUM 1024 + +#define IMM_VAL0 \ + (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY) +#define IMM_VAL1 \ + (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \ + | _SIDD_MOST_SIGNIFICANT) +#define IMM_VAL2 \ + (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY) +#define IMM_VAL3 \ + (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \ + | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_LEAST_SIGNIFICANT) + + +static void +TEST (void) +{ + union + { + __m128i x[NUM]; + char c[NUM *16]; + } src1, src2; + int res, correct, l1, l2; + int i; + + for (i = 0; i < NUM *16; i++) + { + src1.c[i] = rand (); + src2.c[i] = rand (); + } + + for (i = 0; i < NUM; i++) + { + l1 = rand () % 18; + l2 = rand () % 18; + + switch ((rand () % 4)) + { + case 0: + res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL0, + NULL); + break; + + case 1: + res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL1, + NULL); + break; + + case 2: + res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL2, + NULL); + break; + + default: + res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL3, + NULL); + break; + } + + if (correct != res) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-2.c new file mode 100644 index 000000000..800084ff6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-2.c @@ -0,0 +1,119 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_2-check.h" +#endif + +#ifndef TEST +#define TEST sse4_2_test +#endif + +#include CHECK_H + +#include "sse4_2-pcmpstr.h" + +#define NUM 1024 + +#define IMM_VAL0 \ + (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY) +#define IMM_VAL1 \ + (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \ + | _SIDD_MOST_SIGNIFICANT) +#define IMM_VAL2 \ + (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY) +#define IMM_VAL3 \ + (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \ + | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_LEAST_SIGNIFICANT) + + +static void +TEST (void) +{ + union + { + __m128i x[NUM]; + char c[NUM *16]; + } src1, src2; + int res, correct, correct_flags, l1, l2; + int flags, cf, zf, sf, of, af; + int i; + + for (i = 0; i < NUM *16; i++) + { + src1.c[i] = rand (); + src2.c[i] = rand (); + } + + for (i = 0; i < NUM; i++) + { + l1 = rand () % 18; + l2 = rand () % 18; + + switch ((rand () % 4)) + { + case 0: + res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL0, + &correct_flags); + break; + + case 1: + res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL1, + &correct_flags); + break; + + case 2: + res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL2, + &correct_flags); + break; + + default: + res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL3, + &correct_flags); + break; + } + + if (correct != res) + abort (); + + flags = 0; + if (cf) + flags |= CFLAG; + if (zf) + flags |= ZFLAG; + if (sf) + flags |= SFLAG; + if (of) + flags |= OFLAG; + + if (flags != correct_flags + || (af && (cf || zf)) + || (!af && !(cf || zf))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-1.c new file mode 100644 index 000000000..f02bb7e69 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-1.c @@ -0,0 +1,84 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_2-check.h" +#endif + +#ifndef TEST +#define TEST sse4_2_test +#endif + +#include CHECK_H + +#include "sse4_2-pcmpstr.h" + +#define NUM 1024 + +#define IMM_VAL0 \ + (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY) +#define IMM_VAL1 \ + (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \ + | _SIDD_BIT_MASK) +#define IMM_VAL2 \ + (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY) +#define IMM_VAL3 \ + (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \ + | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_UNIT_MASK) + + +static void +TEST (void) +{ + union + { + __m128i x[NUM]; + char c[NUM *16]; + } src1, src2; + __m128i res, correct; + int l1, l2; + int i; + + for (i = 0; i < NUM *16; i++) + { + src1.c[i] = rand (); + src2.c[i] = rand (); + } + + for (i = 0; i < NUM; i++) + { + l1 = rand () % 18; + l2 = rand () % 18; + + switch((rand() % 4)) + { + case 0: + res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL0, + NULL); + break; + + case 1: + res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL1, + NULL); + break; + + case 2: + res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL2, + NULL); + break; + + default: + res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL3, + NULL); + break; + } + + if (memcmp (&correct, &res, sizeof (res))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-2.c new file mode 100644 index 000000000..845471f0b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-2.c @@ -0,0 +1,119 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_2-check.h" +#endif + +#ifndef TEST +#define TEST sse4_2_test +#endif + +#include CHECK_H + +#include "sse4_2-pcmpstr.h" + +#define NUM 1024 + +#define IMM_VAL0 \ + (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY) +#define IMM_VAL1 \ + (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \ + | _SIDD_BIT_MASK) +#define IMM_VAL2 \ + (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_NEGATIVE_POLARITY) +#define IMM_VAL3 \ + (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \ + | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_UNIT_MASK) + +static void +TEST (void) +{ + union + { + __m128i x[NUM]; + char c[NUM *16]; + } src1, src2; + __m128i res, correct; + int correct_flags, l1, l2; + int flags, cf, zf, sf, of, af; + int i; + + for (i = 0; i < NUM *16; i++) + { + src1.c[i] = rand (); + src2.c[i] = rand (); + } + + for (i = 0; i < NUM; i++) + { + l1 = rand () % 18; + l2 = rand () % 18; + + switch ((rand () % 4)) + { + case 0: + res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL0); + correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL0, + &correct_flags); + break; + + case 1: + res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL1); + correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL1, + &correct_flags); + break; + + case 2: + res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL2); + correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL2, + &correct_flags); + break; + + default: + res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL3); + correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL3, + &correct_flags); + break; + } + + if (memcmp (&correct, &res, sizeof (res))) + abort (); + + flags = 0; + if (cf) + flags |= CFLAG; + if (zf) + flags |= ZFLAG; + if (sf) + flags |= SFLAG; + if (of) + flags |= OFLAG; + + if (flags != correct_flags + || (af && (cf || zf)) + || (!af && !(cf || zf))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpgtq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpgtq.c new file mode 100644 index 000000000..e2ef66f2a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpgtq.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_2-check.h" +#endif + +#ifndef TEST +#define TEST sse4_2_test +#endif + +#include CHECK_H + +#include <nmmintrin.h> + +#define NUM 64 + +static void +TEST (void) +{ + union + { + __m128i x[NUM / 2]; + long long ll[NUM]; + } dst, src1, src2; + int i, sign = 1; + long long is_eq; + + for (i = 0; i < NUM; i++) + { + src1.ll[i] = i * i * sign; + src2.ll[i] = (i + 20) * sign; + sign = -sign; + } + + for (i = 0; i < NUM; i += 2) + dst.x[i / 2] = _mm_cmpgt_epi64 (src1.x[i / 2], src2.x[i / 2]); + + for (i = 0; i < NUM; i++) + { + is_eq = src1.ll[i] > src2.ll[i] ? 0xFFFFFFFFFFFFFFFFLL : 0LL; + if (is_eq != dst.ll[i]) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-1.c new file mode 100644 index 000000000..b74df024d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-1.c @@ -0,0 +1,76 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_2-check.h" +#endif + +#ifndef TEST +#define TEST sse4_2_test +#endif + +#include CHECK_H + +#include "sse4_2-pcmpstr.h" + +#define NUM 1024 + +#define IMM_VAL0 \ + (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY) +#define IMM_VAL1 \ + (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \ + | _SIDD_MOST_SIGNIFICANT) +#define IMM_VAL2 \ + (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY) +#define IMM_VAL3 \ + (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \ + | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_MOST_SIGNIFICANT) + + +static void +TEST (void) +{ + union + { + __m128i x[NUM]; + char c[NUM *16]; + } src1, src2; + int res, correct; + int i; + + for (i = 0; i < NUM *16; i++) + { + src1.c[i] = rand (); + src2.c[i] = rand (); + } + + for (i = 0; i < NUM; i++) + { + switch ((rand () % 4)) + { + case 0: + res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL0); + correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL0, NULL); + break; + + case 1: + res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL1); + correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL1, NULL); + break; + + case 2: + res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL2); + correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL2, NULL); + break; + + default: + res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL3); + correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL3, NULL); + break; + } + + if (correct != res) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-2.c new file mode 100644 index 000000000..5aea655ed --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-2.c @@ -0,0 +1,116 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_2-check.h" +#endif + +#ifndef TEST +#define TEST sse4_2_test +#endif + +#include CHECK_H + +#include "sse4_2-pcmpstr.h" + +#define NUM 1024 + +#define IMM_VAL0 \ + (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY) +#define IMM_VAL1 \ + (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \ + | _SIDD_MOST_SIGNIFICANT) +#define IMM_VAL2 \ + (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY) +#define IMM_VAL3 \ + (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \ + | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_MOST_SIGNIFICANT) + + +static void +TEST (void) +{ + union + { + __m128i x[NUM]; + char c[NUM *16]; + } src1, src2; + int res, correct, correct_flags; + int flags, cf, zf, sf, of, af; + int i; + + for (i = 0; i < NUM *16; i++) + { + src1.c[i] = rand (); + src2.c[i] = rand (); + } + + for (i = 0; i < NUM; i++) + { + switch ((rand () % 4)) + { + case 0: + res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL0); + cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL0); + zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL0); + sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL0); + of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL0); + af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL0); + correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL0, + &correct_flags); + break; + + case 1: + res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL1); + cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL1); + zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL1); + sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL1); + of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL1); + af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL1); + correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL1, + &correct_flags); + break; + + case 2: + res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL2); + cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL2); + zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL2); + sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL2); + of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL2); + af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL2); + correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL2, + &correct_flags); + break; + + default: + res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL3); + cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL3); + zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL3); + sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL3); + of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL3); + af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL3); + correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL3, + &correct_flags); + break; + } + + if (correct != res) + abort (); + + flags = 0; + if (cf) + flags |= CFLAG; + if (zf) + flags |= ZFLAG; + if (sf) + flags |= SFLAG; + if (of) + flags |= OFLAG; + + if (flags != correct_flags + || (af && (cf || zf)) + || (!af && !(cf || zf))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-1.c new file mode 100644 index 000000000..b8ec890cb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-1.c @@ -0,0 +1,76 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_2-check.h" +#endif + +#ifndef TEST +#define TEST sse4_2_test +#endif + +#include CHECK_H + +#include "sse4_2-pcmpstr.h" + +#define NUM 1024 + +#define IMM_VAL0 \ + (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY) +#define IMM_VAL1 \ + (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \ + | _SIDD_BIT_MASK) +#define IMM_VAL2 \ + (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY) +#define IMM_VAL3 \ + (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \ + | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_UNIT_MASK) + + +static void +TEST (void) +{ + union + { + __m128i x[NUM]; + char c[NUM *16]; + } src1, src2; + __m128i res, correct; + int i; + + for (i = 0; i < NUM *16; i++) + { + src1.c[i] = rand (); + src2.c[i] = rand (); + } + + for (i = 0; i < NUM; i++) + { + switch((rand() % 4)) + { + case 0: + res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL0); + correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL0, NULL); + break; + + case 1: + res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL1); + correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL1, NULL); + break; + + case 2: + res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL2); + correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL2, NULL); + break; + + default: + res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL3); + correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL3, NULL); + break; + } + + if (memcmp (&correct, &res, sizeof (res))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-2.c new file mode 100644 index 000000000..c6896ee61 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-2.c @@ -0,0 +1,116 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#ifndef CHECK_H +#define CHECK_H "sse4_2-check.h" +#endif + +#ifndef TEST +#define TEST sse4_2_test +#endif + +#include CHECK_H + +#include "sse4_2-pcmpstr.h" + +#define NUM 1024 + +#define IMM_VAL0 \ + (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY) +#define IMM_VAL1 \ + (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \ + | _SIDD_BIT_MASK) +#define IMM_VAL2 \ + (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY) +#define IMM_VAL3 \ + (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \ + | _SIDD_POSITIVE_POLARITY | _SIDD_UNIT_MASK) + +static void +TEST (void) +{ + union + { + __m128i x[NUM]; + char c[NUM *16]; + } src1, src2; + __m128i res, correct; + int correct_flags; + int flags, cf, zf, sf, of, af; + int i; + + for (i = 0; i < NUM *16; i++) + { + src1.c[i] = rand (); + src2.c[i] = rand (); + } + + for (i = 0; i < NUM; i++) + { + switch ((rand () % 4)) + { + case 0: + res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL0); + cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL0); + zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL0); + sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL0); + of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL0); + af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL0); + correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL0, + &correct_flags); + break; + + case 1: + res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL1); + cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL1); + zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL1); + sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL1); + of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL1); + af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL1); + correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL1, + &correct_flags); + break; + + case 2: + res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL2); + cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL2); + zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL2); + sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL2); + of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL2); + af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL2); + correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL2, + &correct_flags); + break; + + default: + res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL3); + cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL3); + zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL3); + sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL3); + of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL3); + af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL3); + correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL3, + &correct_flags); + break; + } + + if (memcmp (&correct, &res, sizeof (res))) + abort (); + + flags = 0; + if (cf) + flags |= CFLAG; + if (zf) + flags |= ZFLAG; + if (sf) + flags |= SFLAG; + if (of) + flags |= OFLAG; + + if (flags != correct_flags + || (af && (cf || zf)) + || (!af && !(cf || zf))) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpstr.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpstr.h new file mode 100644 index 000000000..999b5c8ed --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-pcmpstr.h @@ -0,0 +1,447 @@ +#include <nmmintrin.h> +#include <string.h> + +#define CFLAG 0x00000001 +#define ZFLAG 0x00000002 +#define SFLAG 0x00000004 +#define OFLAG 0x00000008 +#define AFLAG 0x00000010 +#define PFLAG 0x00000020 + +#define PCMPSTR_EQ(X, Y, RES) \ + { \ + int __size = (sizeof (*X) ^ 3) * 8; \ + int __i, __j; \ + for (__i = 0; __i < __size; __i++) \ + for (__j = 0; __j < __size; __j++) \ + RES[__j][__i] = (X[__i] == Y[__j]); \ + } + +#define PCMPSTR_RNG(X, Y, RES) \ + { \ + int __size = (sizeof (*X) ^ 3) * 8; \ + int __i, __j; \ + for (__j = 0; __j < __size; __j++) \ + for (__i = 0; __i < __size - 1; __i += 2) \ + { \ + RES[__j][__i] = (Y[__j] >= X[__i]); \ + RES[__j][__i+1] = (Y[__j] <= X[__i + 1]); \ + } \ + } + +static void +override_invalid (unsigned char res[16][16], int la, int lb, + const int mode, int dim) +{ + int i, j; + + for (j = 0; j < dim; j++) + for (i = 0; i < dim; i++) + if (i < la && j >= lb) + res[j][i] = 0; + else if (i >= la) + switch ((mode & 0x0C)) + { + case _SIDD_CMP_EQUAL_ANY: + case _SIDD_CMP_RANGES: + res[j][i] = 0; + break; + case _SIDD_CMP_EQUAL_EACH: + res[j][i] = (j >= lb) ? 1: 0; + break; + case _SIDD_CMP_EQUAL_ORDERED: + res[j][i] = 1; + break; + } +} + +static void +calc_matrix (__m128i a, int la, __m128i b, int lb, const int mode, + unsigned char res[16][16]) +{ + union + { + __m128i x; + signed char sc[16]; + unsigned char uc[16]; + signed short ss[8]; + unsigned short us[8]; + } d, s; + + d.x = a; + s.x = b; + + switch ((mode & 3)) + { + case _SIDD_UBYTE_OPS: + if ((mode & 0x0C) == _SIDD_CMP_RANGES) + { + PCMPSTR_RNG (d.uc, s.uc, res); + } + else + { + PCMPSTR_EQ (d.uc, s.uc, res); + } + break; + case _SIDD_UWORD_OPS: + if ((mode & 0x0C) == _SIDD_CMP_RANGES) + { + PCMPSTR_RNG (d.us, s.us, res); + } + else + { + PCMPSTR_EQ (d.us, s.us, res); + } + break; + case _SIDD_SBYTE_OPS: + if ((mode & 0x0C) == _SIDD_CMP_RANGES) + { + PCMPSTR_RNG (d.sc, s.sc, res); + } + else + { + PCMPSTR_EQ (d.sc, s.sc, res); + } + break; + case _SIDD_SWORD_OPS: + if ((mode & 0x0C) == _SIDD_CMP_RANGES) + { + PCMPSTR_RNG (d.ss, s.ss, res); + } + else + { + PCMPSTR_EQ (d.ss, s.ss, res); + } + break; + } + + override_invalid (res, la, lb, mode, (mode & 1) == 0 ? 16 : 8); +} + +static int +calc_res (__m128i a, int la, __m128i b, int lb, const int mode) +{ + unsigned char mtx[16][16]; + int i, j, k, dim, res = 0; + + memset (mtx, 0, sizeof (mtx)); + + dim = (mode & 1) == 0 ? 16 : 8; + + if (la < 0) + la = -la; + + if (lb < 0) + lb = -lb; + + if (la > dim) + la = dim; + + if (lb > dim) + lb = dim; + + calc_matrix (a, la, b, lb, mode, mtx); + + switch ((mode & 0x0C)) + { + case _SIDD_CMP_EQUAL_ANY: + for (i = 0; i < dim; i++) + for (j = 0; j < dim; j++) + if (mtx[i][j]) + res |= (1 << i); + break; + + case _SIDD_CMP_RANGES: + for (i = 0; i < dim; i += 2) + for(j = 0; j < dim; j++) + if (mtx[j][i] && mtx[j][i+1]) + res |= (1 << j); + break; + + case _SIDD_CMP_EQUAL_EACH: + for(i = 0; i < dim; i++) + if (mtx[i][i]) + res |= (1 << i); + break; + + case _SIDD_CMP_EQUAL_ORDERED: + for(i = 0; i < dim; i++) + { + unsigned char val = 1; + + for (j = 0, k = i; j < dim - i && k < dim; j++, k++) + val &= mtx[k][j]; + + if (val) + res |= (1 << i); + else + res &= ~(1 << i); + } + break; + } + + switch ((mode & 0x30)) + { + case _SIDD_POSITIVE_POLARITY: + case _SIDD_MASKED_POSITIVE_POLARITY: + break; + + case _SIDD_NEGATIVE_POLARITY: + res ^= -1; + break; + + case _SIDD_MASKED_NEGATIVE_POLARITY: + for (i = 0; i < lb; i++) + if (res & (1 << i)) + res &= ~(1 << i); + else + res |= (1 << i); + break; + } + + return res & ((dim == 8) ? 0xFF : 0xFFFF); +} + +static int +cmp_flags (__m128i a, int la, __m128i b, int lb, + int mode, int res2, int is_implicit) +{ + int i; + int flags = 0; + int is_bytes_mode = (mode & 1) == 0; + union + { + __m128i x; + unsigned char uc[16]; + unsigned short us[8]; + } d, s; + + d.x = a; + s.x = b; + + /* CF: reset if (RES2 == 0), set otherwise. */ + if (res2 != 0) + flags |= CFLAG; + + if (is_implicit) + { + /* ZF: set if any byte/word of src xmm operand is null, reset + otherwise. + SF: set if any byte/word of dst xmm operand is null, reset + otherwise. */ + + if (is_bytes_mode) + { + for (i = 0; i < 16; i++) + { + if (s.uc[i] == 0) + flags |= ZFLAG; + if (d.uc[i] == 0) + flags |= SFLAG; + } + } + else + { + for (i = 0; i < 8; i++) + { + if (s.us[i] == 0) + flags |= ZFLAG; + if (d.us[i] == 0) + flags |= SFLAG; + } + } + } + else + { + /* ZF: set if abs value of EDX/RDX < 16 (8), reset otherwise. + SF: set if abs value of EAX/RAX < 16 (8), reset otherwise. */ + int max_ind = is_bytes_mode ? 16 : 8; + + if (la < 0) + la = -la; + if (lb < 0) + lb = -lb; + + if (lb < max_ind) + flags |= ZFLAG; + if (la < max_ind) + flags |= SFLAG; + } + + /* OF: equal to RES2[0]. */ + if ((res2 & 0x1)) + flags |= OFLAG; + + /* AF: Reset. + PF: Reset. */ + return flags; +} + +static int +cmp_indexed (__m128i a, int la, __m128i b, int lb, + const int mode, int *res2) +{ + int i, ndx; + int dim = (mode & 1) == 0 ? 16 : 8; + int r2; + + r2 = calc_res (a, la, b, lb, mode); + + ndx = dim; + if ((mode & 0x40)) + { + for (i = dim - 1; i >= 0; i--) + if (r2 & (1 << i)) + { + ndx = i; + break; + } + } + else + { + for (i = 0; i < dim; i++) + if ((r2 & (1 << i))) + { + ndx = i; + break; + } + } + + *res2 = r2; + return ndx; +} + +static __m128i +cmp_masked (__m128i a, int la, __m128i b, int lb, + const int mode, int *res2) +{ + union + { + __m128i x; + char c[16]; + short s[8]; + } ret; + int i; + int dim = (mode & 1) == 0 ? 16 : 8; + union + { + int i; + char c[4]; + short s[2]; + } r2; + + r2.i = calc_res (a, la, b, lb, mode); + + memset (&ret, 0, sizeof (ret)); + + if (mode & 0x40) + { + for (i = 0; i < dim; i++) + if (dim == 8) + ret.s [i] = (r2.i & (1 << i)) ? -1 : 0; + else + ret.c [i] = (r2.i & (1 << i)) ? -1 : 0; + } + else + { + if (dim == 16) + ret.s[0] = r2.s[0]; + else + ret.c[0] = r2.c[0]; + } + + *res2 = r2.i; + + return ret.x; +} + +static int +calc_str_len (__m128i a, const int mode) +{ + union + { + __m128i x; + char c[16]; + short s[8]; + } s; + int i; + int dim = (mode & 1) == 0 ? 16 : 8; + + s.x = a; + + if ((mode & 1)) + { + for (i = 0; i < dim; i++) + if (s.s[i] == 0) + break; + } + else + { + for (i = 0; i < dim; i++) + if (s.c[i] == 0) + break; + } + + return i; +} + +static inline int +cmp_ei (__m128i *a, int la, __m128i *b, int lb, + const int mode, int *flags) +{ + int res2; + int index = cmp_indexed (*a, la, *b, lb, mode, &res2); + + if (flags != NULL) + *flags = cmp_flags (*a, la, *b, lb, mode, res2, 0); + + return index; +} + +static inline int +cmp_ii (__m128i *a, __m128i *b, const int mode, int *flags) +{ + int la, lb; + int res2; + int index; + + la = calc_str_len (*a, mode); + lb = calc_str_len (*b, mode); + + index = cmp_indexed (*a, la, *b, lb, mode, &res2); + + if (flags != NULL) + *flags = cmp_flags (*a, la, *b, lb, mode, res2, 1); + + return index; +} + +static inline __m128i +cmp_em (__m128i *a, int la, __m128i *b, int lb, + const int mode, int *flags ) +{ + int res2; + __m128i mask = cmp_masked (*a, la, *b, lb, mode, &res2); + + if (flags != NULL) + *flags = cmp_flags (*a, la, *b, lb, mode, res2, 0); + + return mask; +} + +static inline __m128i +cmp_im (__m128i *a, __m128i *b, const int mode, int *flags) +{ + int la, lb; + int res2; + __m128i mask; + + la = calc_str_len (*a, mode); + lb = calc_str_len (*b, mode); + + mask = cmp_masked (*a, la, *b, lb, mode, &res2); + if (flags != NULL) + *flags = cmp_flags (*a, la, *b, lb, mode, res2, 1); + + return mask; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-popcnt.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-popcnt.h new file mode 100644 index 000000000..ce06ba1b8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-popcnt.h @@ -0,0 +1,41 @@ +#include "sse4_2-check.h" + +#include <nmmintrin.h> + +#define NUM 1024 + +static int +compute_popcnt (TYPE v) +{ + int ret; + int i; + + ret = 0; + for (i = 0; i < sizeof(v) * 8; i++) + if ((v & ((TYPE)1 << (TYPE) i))) + ret++; + + return ret; +} + +static void +sse4_2_test (void) +{ + int i; + TYPE vals[NUM]; + TYPE res; + + for (i = 0; i < NUM; i++) + { + vals[i] = rand (); + if (sizeof (TYPE) > 4) + vals[i] |= (TYPE)rand() << (TYPE)(sizeof (TYPE) * 4); + } + + for (i=0; i < NUM; i++) + { + res = POPCNT (vals[i]); + if (res != compute_popcnt (vals[i])) + abort (); + } +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-popcntl.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-popcntl.c new file mode 100644 index 000000000..30da548d9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-popcntl.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#define TYPE unsigned int +#define POPCNT _mm_popcnt_u32 + +#include "sse4_2-popcnt.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c new file mode 100644 index 000000000..47cdf3562 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c @@ -0,0 +1,8 @@ +/* { dg-do run { target { ! { ia32 } } } } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.2" } */ + +#define TYPE unsigned long long +#define POPCNT _mm_popcnt_u64 + +#include "sse4_2-popcnt.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-check.h new file mode 100644 index 000000000..d43b4b222 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-check.h @@ -0,0 +1,28 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void sse4a_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + sse4a_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run SSE4a test only if host has SSE4a support. */ + if (ecx & bit_SSE4a) + do_test (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-extract.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-extract.c new file mode 100644 index 000000000..5fb190e44 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-extract.c @@ -0,0 +1,84 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4a } */ +/* { dg-options "-O2 -msse4a" } */ + +#include "sse4a-check.h" + +#include <ammintrin.h> + +typedef union +{ + long long i[2]; + __m128i vec; +} LI; + +static long long +sse4a_test_extrq (long long in) +{ + __m128i v1, v2; + long long index_length, pad; + LI v_out; + index_length = 0x0000000000000810LL; + pad = 0x0; + v1 = _mm_set_epi64x (pad, in); + v2 = _mm_set_epi64x (pad, index_length); + v_out.vec = _mm_extract_si64 (v1, v2); + return (v_out.i[0]); +} + +static long long +sse4a_test_extrqi (long long in) +{ + __m128i v1; + long long pad =0x0; + LI v_out; + v1 = _mm_set_epi64x (pad, in); + v_out.vec = _mm_extracti_si64 (v1, (unsigned int) 0x10,(unsigned int) 0x08); + return (v_out.i[0]); +} + +static chk (long long i1, long long i2) +{ + int n_fails =0; + if (i1 != i2) + n_fails +=1; + return n_fails; +} + +long long vals_in[5] = + { + 0x1234567887654321LL, + 0x1456782093002490LL, + 0x2340909123990390LL, + 0x9595959599595999LL, + 0x9099038798000029LL + }; + +long long vals_out[5] = + { + 0x0000000000006543LL, + 0x0000000000000024LL, + 0x0000000000009903LL, + 0x0000000000005959LL, + 0x0000000000000000LL + }; + +static void +sse4a_test (void) +{ + int i; + int fail = 0; + long long out; + + for (i = 0; i < 5; i += 1) + { + out = sse4a_test_extrq (vals_in[i]); + fail += chk(out, vals_out[i]); + + out = sse4a_test_extrqi (vals_in[i]); + fail += chk(out, vals_out[i]); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-insert.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-insert.c new file mode 100644 index 000000000..c1bd1006d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-insert.c @@ -0,0 +1,94 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4a } */ +/* { dg-options "-O2 -msse4a" } */ + +#include "sse4a-check.h" + +#include <ammintrin.h> + +typedef union +{ + long long i[2]; + __m128i vec; +} LI; + +static long long +sse4a_test_insert (long long in1, long long in2) +{ + __m128i v1,v2; + long long index_length, pad; + LI v_out; + index_length = 0x0000000000000810LL; + pad = 0x0; + v1 = _mm_set_epi64x (pad, in1); + v2 = _mm_set_epi64x (index_length, in2); + v_out.vec = _mm_insert_si64 (v1, v2); + return (v_out.i[0]); +} + +static long long +sse4a_test_inserti (long long in1, long long in2) +{ + __m128i v1,v2; + long long pad = 0x0; + LI v_out; + v1 = _mm_set_epi64x (pad, in1); + v2 = _mm_set_epi64x (pad, in2); + v_out.vec = _mm_inserti_si64 (v1, v2, (unsigned int) 0x10, (unsigned int) 0x08); + return (v_out.i[0]); +} + +static chk (long long i1, long long i2) +{ + int n_fails =0; + if (i1 != i2) + n_fails +=1; + return n_fails; +} + +long long vals_in1[5] = + { + 0x1234567887654321LL, + 0x1456782093002490LL, + 0x2340909123990390LL, + 0x9595959599595999LL, + 0x9099038798000029LL + }; + +long long vals_in2[5] = + { + 0x9ABCDEF00FEDCBA9LL, + 0x234567097289672ALL, + 0x45476453097BD342LL, + 0x23569012AE586FF0LL, + 0x432567ABCDEF765DLL + }; + +long long vals_out[5] = + { + 0x1234567887CBA921LL, + 0x1456782093672A90LL, + 0x2340909123D34290LL, + 0x95959595996FF099LL, + 0x9099038798765D29LL + }; + +static void +sse4a_test (void) +{ + int i; + int fail = 0; + long long out; + + for (i = 0; i < 5; i += 1) + { + out = sse4a_test_insert (vals_in1[i], vals_in2[i]); + fail += chk(out, vals_out[i]); + + out = sse4a_test_inserti (vals_in1[i], vals_in2[i]); + fail += chk(out, vals_out[i]); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-montsd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-montsd.c new file mode 100644 index 000000000..1cc067db6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-montsd.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4a } */ +/* { dg-options "-O2 -msse4a" } */ + +#include "sse4a-check.h" + +#include <ammintrin.h> + +static void +sse4a_test_movntsd (double *out, double *in) +{ + __m128d in_v2df = _mm_load_sd (in); + _mm_stream_sd (out, in_v2df); +} + +static int +chk_sd (double *v1, double *v2) +{ + int n_fails = 0; + if (v1[0] != v2[0]) + n_fails += 1; + return n_fails; +} + +double vals[10] = + { + 100.0, 200.0, 300.0, 400.0, 5.0, + -1.0, .345, -21.5, 9.32, 8.41 + }; + +static void +sse4a_test (void) +{ + int i; + int fail = 0; + double *out; + + out = (double *) malloc (sizeof (double)); + for (i = 0; i < 10; i += 1) + { + sse4a_test_movntsd (out, &vals[i]); + + fail += chk_sd (out, &vals[i]); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-montss.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-montss.c new file mode 100644 index 000000000..41e80e83d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sse4a-montss.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4a } */ +/* { dg-options "-O2 -msse4a" } */ + +#include "sse4a-check.h" + +#include <ammintrin.h> + +static void +sse4a_test_movntss (float *out, float *in) +{ + __m128 in_v4sf = _mm_load_ss (in); + _mm_stream_ss (out, in_v4sf); +} + +static int +chk_ss (float *v1, float *v2) +{ + int n_fails = 0; + if (v1[0] != v2[0]) + n_fails += 1; + return n_fails; +} + +float vals[10] = + { + 100.0, 200.0, 300.0, 400.0, 5.0, + -1.0, .345, -21.5, 9.32, 8.41 + }; + +static void +sse4a_test (void) +{ + int i; + int fail = 0; + float *out; + + out = (float *) malloc (sizeof (float)); + for (i = 0; i < 10; i += 1) + { + sse4a_test_movntss (out, &vals[i]); + + fail += chk_ss (out, &vals[i]); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefn-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefn-1.c new file mode 100644 index 000000000..4c72fa4d1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefn-1.c @@ -0,0 +1,31 @@ +/* Test argument passing with SSE and local functions + Written by Paolo Bonzini, 25 January 2005 */ + +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-final { scan-assembler "movss" } } */ +/* { dg-final { scan-assembler "mulss" } } */ +/* { dg-final { scan-assembler-not "movsd" } } */ +/* { dg-final { scan-assembler-not "mulsd" } } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */ +/* { dg-options "-O2 -march=i386 -msse -mno-sse2 -mfpmath=sse -fno-inline" } */ + +static float xs (void) +{ + return 3.14159265; +} + +float ys (float a) +{ + return xs () * a; +} + +static double xd (void) +{ + return 3.1415926535; +} + +double yd (double a) +{ + return xd () * a; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefn-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefn-2.c new file mode 100644 index 000000000..2549855cf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefn-2.c @@ -0,0 +1,31 @@ +/* Test argument passing with SSE2 and local functions + Written by Paolo Bonzini, 25 January 2005 */ + +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-final { scan-assembler "movss" } } */ +/* { dg-final { scan-assembler "mulss" } } */ +/* { dg-final { scan-assembler "movsd" } } */ +/* { dg-final { scan-assembler "mulsd" } } */ +/* { dg-options "-O2 -msse2 -mfpmath=sse -fno-inline" } */ + +static float xs (void) +{ + return 3.14159265; +} + +float ys (float a) +{ + return xs () * a; +} + +static double xd (void) +{ + return 3.1415926535; +} + +double yd (double a) +{ + return xd () * a; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefn-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefn-3.c new file mode 100644 index 000000000..b96b21179 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefn-3.c @@ -0,0 +1,39 @@ +/* Execution test for argument passing with SSE and local functions + Written by Paolo Bonzini, 25 January 2005 */ + +/* { dg-do run } */ +/* { dg-options "-O2 -msse -mfpmath=sse" } */ +/* { dg-require-effective-target sse } */ + +#include "sse-check.h" + +#include <assert.h> + +static float xs (void) +{ + return 3.14159265; +} + +float ys (float a) +{ + return xs () * a; +} + +static double xd (void) +{ + return 3.1415926535; +} + +double yd (double a) +{ + return xd () * a; +} + +static void +sse_test (void) +{ + assert (ys (1) == xs ()); + assert (ys (2) == xs () * 2); + assert (yd (1) == xd ()); + assert (yd (2) == xd () * 2); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefn-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefn-4.c new file mode 100644 index 000000000..2d7407eae --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefn-4.c @@ -0,0 +1,39 @@ +/* Execution test for argument passing with SSE2 and local functions + Written by Paolo Bonzini, 25 January 2005 */ + +/* { dg-do run } */ +/* { dg-options "-O2 -msse2 -mfpmath=sse" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include <assert.h> + +static float xs (void) +{ + return 3.14159265; +} + +float ys (float a) +{ + return xs () * a; +} + +static double xd (void) +{ + return 3.1415926535; +} + +double yd (double a) +{ + return xd () * a; +} + +static void +sse2_test (void) +{ + assert (ys (1) == xs ()); + assert (ys (2) == xs () * 2); + assert (yd (1) == xd ()); + assert (yd (2) == xd () * 2); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefp-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefp-1.c new file mode 100644 index 000000000..621e362f4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefp-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -march=k8 -mfpmath=sse" } */ +/* { dg-final { scan-assembler "maxsd" } } */ +/* { dg-final { scan-assembler "minsd" } } */ +double x; +t() +{ + x=x>5?x:5; +} + +double x; +q() +{ + x=x<5?x:5; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefp-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefp-2.c new file mode 100644 index 000000000..a6caee398 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssefp-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -march=k8 -mfpmath=sse" } */ +/* { dg-final { scan-assembler "maxsd" } } */ +/* { dg-final { scan-assembler "minsd" } } */ +double x; +q() +{ + x=x<5?5:x; +} + +double x; +q1() +{ + x=x>5?5:x; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-1.c new file mode 100644 index 000000000..63bad7e47 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse" } */ +/* { dg-require-effective-target ia32 } */ + +float essef(float) __attribute__((sseregparm)); +double essed(double) __attribute__((sseregparm)); +float __attribute__((sseregparm, noinline)) ssef(float f) { return f; } +double __attribute__((sseregparm, noinline)) ssed(double d) { return d; } +extern double d; +extern float f; +void test(void) +{ + f = essef(f); + d = essed(d); + f = ssef(f); + d = ssed(d); +} + +/* { dg-final { scan-assembler-not "fldl" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-2.c new file mode 100644 index 000000000..b5e521a11 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-sse" } */ +/* { dg-require-effective-target ia32 } */ + +float essef(float) __attribute__((sseregparm)); +double essed(double) __attribute__((sseregparm)); +float __attribute__((sseregparm, noinline)) ssef(float f) { return f; } /* { dg-error "SSE" } */ +double __attribute__((sseregparm, noinline)) ssed(double d) { return d; } /* { dg-error "SSE" } */ +extern double d; +extern float f; +void test(void) +{ + f = essef(f); + d = essed(d); + f = ssef(f); + d = ssed(d); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-3.c new file mode 100644 index 000000000..5c16f4354 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -O2" } */ +/* { dg-require-effective-target ia32 } */ + +/* Make sure we know that mysinfp returns in %xmm0. */ + +double __attribute__((sseregparm)) mysin(double x); +double __attribute__((sseregparm)) (*mysinfp)(double) = mysin; +double bar(double x) +{ + return 1.0+mysinfp(x); +} + +/* { dg-final { scan-assembler "fldl" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-4.c new file mode 100644 index 000000000..47d66e3ab --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -O2" } */ +/* { dg-require-effective-target ia32 } */ + +/* Make sure we know that mysinfp returns in %xmm0. */ + +double __attribute__((sseregparm)) mysin(double x); +double __attribute__((sseregparm)) (*mysinfp)(double) = mysin; +double bar(double x) +{ + return mysinfp(x); +} + +/* { dg-final { scan-assembler "fldl" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-5.c new file mode 100644 index 000000000..d0f4757b5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-5.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -O2" } */ +/* { dg-require-effective-target ia32 } */ + +/* Make sure we know that mysinfp returns in %xmm0. */ + +double __attribute__((sseregparm)) mysin(void); +double __attribute__((sseregparm)) (*mysinfp)(void) = mysin; +double bar(double x) +{ + return mysinfp(); +} + +/* { dg-final { scan-assembler "fldl" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-6.c new file mode 100644 index 000000000..a4a836386 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-6.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -O2" } */ +/* { dg-require-effective-target ia32 } */ + +/* Make sure we know that mysinfp returns in %xmm0. */ + +double __attribute__((sseregparm)) mysin(double x); +double bar(double x) +{ + return mysin(x); +} + +/* { dg-final { scan-assembler "fldl" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-7.c new file mode 100644 index 000000000..54b2573cf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-7.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -O2" } */ +/* { dg-require-effective-target ia32 } */ + +/* Make sure we know that mysinfp returns in %xmm0. */ + +double __attribute__((sseregparm)) mysin(void); +double bar(double x) +{ + return mysin(); +} + +/* { dg-final { scan-assembler "fldl" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-8.c new file mode 100644 index 000000000..a7068dfe0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sseregparm-8.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-sse" } */ +/* { dg-require-effective-target ia32 } */ + +float essef(float) __attribute__((sseregparm)); +double essed(double) __attribute__((sseregparm)); +float __attribute__((sseregparm)) ssef(float f); +double __attribute__((sseregparm)) ssed(double d); +extern double d; +extern float f; +void test(void) +{ + f = essef(f); /* { dg-error "SSE" } */ + d = essed(d); /* { dg-error "SSE" } */ + f = ssef(f); /* { dg-error "SSE" } */ + d = ssed(d); /* { dg-error "SSE" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-1.c new file mode 100644 index 000000000..ef89059b8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* This test checks for absolute memory operands. */ +/* { dg-require-effective-target nonpic } */ +/* { dg-options "-O2 -msse2 -march=k8" } */ +/* { dg-final { scan-assembler "andpd\[^\\n\]*magic" } } */ +/* { dg-final { scan-assembler "andnpd\[^\\n\]*magic" } } */ +/* { dg-final { scan-assembler "xorpd\[^\\n\]*magic" } } */ +/* { dg-final { scan-assembler "orpd\[^\\n\]*magic" } } */ +/* { dg-final { scan-assembler-not "movdqa" } } */ +/* { dg-final { scan-assembler "movapd\[^\\n\]*magic" } } */ + +/* Verify that we generate proper instruction with memory operand. */ + +#include <xmmintrin.h> + +static __m128d magic_a, magic_b; + +__m128d +t1(void) +{ +return _mm_and_pd (magic_a,magic_b); +} +__m128d +t2(void) +{ +return _mm_andnot_pd (magic_a,magic_b); +} +__m128d +t3(void) +{ +return _mm_or_pd (magic_a,magic_b); +} +__m128d +t4(void) +{ +return _mm_xor_pd (magic_a,magic_b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-2.c new file mode 100644 index 000000000..b68a63923 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-2.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -march=k8" } */ +/* { dg-final { scan-assembler "andpd" } } */ +/* { dg-final { scan-assembler "andnpd" } } */ +/* { dg-final { scan-assembler "xorpd" } } */ +/* { dg-final { scan-assembler "orpd" } } */ +/* { dg-final { scan-assembler-not "movdqa" } } */ + +/* Verify that we generate proper instruction without memory operand. */ + +#include <xmmintrin.h> +__m128d +t1(__m128d a, __m128d b) +{ +a=_mm_sqrt_pd(a); +b=_mm_sqrt_pd(b); +return _mm_and_pd (a,b); +} +__m128d +t2(__m128d a, __m128d b) +{ +a=_mm_sqrt_pd(a); +b=_mm_sqrt_pd(b); +return _mm_andnot_pd (a,b); +} +__m128d +t3(__m128d a, __m128d b) +{ +a=_mm_sqrt_pd(a); +b=_mm_sqrt_pd(b); +return _mm_or_pd (a,b); +} +__m128d +t4(__m128d a, __m128d b) +{ +a=_mm_sqrt_pd(a); +b=_mm_sqrt_pd(b); +return _mm_xor_pd (a,b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-3.c new file mode 100644 index 000000000..d6887d5cd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-3.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* This test checks for absolute memory operands. */ +/* { dg-require-effective-target nonpic } */ +/* { dg-options "-O2 -msse2 -march=k8" } */ +/* { dg-final { scan-assembler "andps\[^\\n\]*magic" } } */ +/* { dg-final { scan-assembler "andnps\[^\\n\]*magic" } } */ +/* { dg-final { scan-assembler "xorps\[^\\n\]*magic" } } */ +/* { dg-final { scan-assembler "orps\[^\\n\]*magic" } } */ +/* { dg-final { scan-assembler-not "movdqa" } } */ +/* { dg-final { scan-assembler "movaps\[^\\n\]*magic" } } */ + +/* Verify that we generate proper instruction with memory operand. */ + +#include <xmmintrin.h> + +static __m128 magic_a, magic_b; +__m128 +t1(void) +{ +return _mm_and_ps (magic_a,magic_b); +} +__m128 +t2(void) +{ +return _mm_andnot_ps (magic_a,magic_b); +} +__m128 +t3(void) +{ +return _mm_or_ps (magic_a,magic_b); +} +__m128 +t4(void) +{ +return _mm_xor_ps (magic_a,magic_b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-4.c new file mode 100644 index 000000000..9994b07f2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-4.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -march=k8" } */ +/* { dg-final { scan-assembler "andps" } } */ +/* { dg-final { scan-assembler "andnps" } } */ +/* { dg-final { scan-assembler "xorps" } } */ +/* { dg-final { scan-assembler "orps" } } */ + +/* Verify that we generate proper instruction without memory operand. */ + +#include <xmmintrin.h> +__m128 +t1(__m128 a, __m128 b) +{ +a=_mm_sqrt_ps(a); +b=_mm_sqrt_ps(b); +return _mm_and_ps (a,b); +} +__m128 +t2(__m128 a, __m128 b) +{ +a=_mm_sqrt_ps(a); +b=_mm_sqrt_ps(b); +return _mm_andnot_ps (a,b); +} +__m128 +t3(__m128 a, __m128 b) +{ +a=_mm_sqrt_ps(a); +b=_mm_sqrt_ps(b); +return _mm_or_ps (a,b); +} +__m128 +t4(__m128 a, __m128 b) +{ +a=_mm_sqrt_ps(a); +b=_mm_sqrt_ps(b); +return _mm_xor_ps (a,b); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-5.c new file mode 100644 index 000000000..75133e9fa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssetype-5.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* This test checks for absolute memory operands. */ +/* { dg-require-effective-target nonpic } */ +/* { dg-options "-O2 -msse2 -march=k8" } */ +/* { dg-final { scan-assembler "pand\[^\\n\]*magic" } } */ +/* { dg-final { scan-assembler "pandn\[^\\n\]*magic" } } */ +/* { dg-final { scan-assembler "pxor\[^\\n\]*magic" } } */ +/* { dg-final { scan-assembler "por\[^\\n\]*magic" } } */ +/* { dg-final { scan-assembler "movdqa" } } */ +/* { dg-final { scan-assembler-not "movaps\[^\\n\]*magic" } } */ + +/* Verify that we generate proper instruction with memory operand. */ + +#include <xmmintrin.h> +static __m128i magic_a, magic_b; +__m128i +t1(void) +{ +return _mm_and_si128 (magic_a,magic_b); +} +__m128i +t2(void) +{ +return _mm_andnot_si128 (magic_a,magic_b); +} +__m128i +t3(void) +{ +return _mm_or_si128 (magic_a,magic_b); +} +__m128i +t4(void) +{ +return _mm_xor_si128 (magic_a,magic_b); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-check.h new file mode 100644 index 000000000..3ca79333c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-check.h @@ -0,0 +1,28 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "cpuid.h" + +static void ssse3_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + ssse3_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run SSSE3 test only if host has SSSE3 support. */ + if (ecx & bit_SSSE3) + do_test (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c new file mode 100644 index 000000000..7caa1b6c3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c @@ -0,0 +1,80 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H + +#include "ssse3-vals.h" +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_pabsb (int *i1, int *r) +{ + __m64 t1 = *(__m64 *) i1; + *(__m64 *) r = _mm_abs_pi8 (t1); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_pabsb128 (int *i1, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + *(__m128i *) r = _mm_abs_epi8 (t1); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int *i1, int *r) +{ + char *b1 = (char *) i1; + char *bout = (char *) r; + int i; + + for (i = 0; i < 16; i++) + if (b1[i] < 0) + bout[i] = -b1[i]; + else + bout[i] = b1[i]; +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 4) + { + /* Manually compute the result */ + compute_correct_result(&vals[i + 0], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_pabsb (&vals[i + 0], &r[0]); + ssse3_test_pabsb (&vals[i + 2], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_pabsb128 (&vals[i + 0], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c new file mode 100644 index 000000000..3a73cf011 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c @@ -0,0 +1,79 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H + +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_pabsd (int *i1, int *r) +{ + __m64 t1 = *(__m64 *) i1; + *(__m64 *) r = _mm_abs_pi32 (t1); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_pabsd128 (int *i1, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + *(__m128i *) r = _mm_abs_epi32 (t1); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int *i1, int *r) +{ + int i; + + for (i = 0; i < 4; i++) + if (i1[i] < 0) + r[i] = -i1[i]; + else + r[i] = i1[i]; +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 4) + { + /* Manually compute the result */ + compute_correct_result(&vals[i + 0], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_pabsd (&vals[i + 0], &r[0]); + ssse3_test_pabsd (&vals[i + 2], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_pabsd128 (&vals[i + 0], r); + fail += chk_128(ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c new file mode 100644 index 000000000..67e4721b8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c @@ -0,0 +1,81 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H + +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_pabsw (int *i1, int *r) +{ + __m64 t1 = *(__m64 *) i1; + *(__m64 *) r = _mm_abs_pi16 (t1); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_pabsw128 (int *i1, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + *(__m128i *) r = _mm_abs_epi16 (t1); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int *i1, int *r) +{ + short *s1 = (short *) i1; + short *sout = (short *) r; + int i; + + for (i = 0; i < 8; i++) + if (s1[i] < 0) + sout[i] = -s1[i]; + else + sout[i] = s1[i]; +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 4) + { + /* Manually compute the result */ + compute_correct_result (&vals[i + 0], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_pabsw (&vals[i + 0], &r[0]); + ssse3_test_pabsw (&vals[i + 2], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_pabsw128 (&vals[i + 0], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-palignr.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-palignr.c new file mode 100644 index 000000000..dbee9bee4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-palignr.c @@ -0,0 +1,279 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H + +#include "ssse3-vals.h" + +#include <tmmintrin.h> +#include <string.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_palignr (int *i1, int *i2, unsigned int imm, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + + switch (imm) + { + case 0: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 0); + break; + case 1: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 1); + break; + case 2: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 2); + break; + case 3: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 3); + break; + case 4: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 4); + break; + case 5: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 5); + break; + case 6: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 6); + break; + case 7: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 7); + break; + case 8: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 8); + break; + case 9: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 9); + break; + case 10: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 10); + break; + case 11: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 11); + break; + case 12: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 12); + break; + case 13: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 13); + break; + case 14: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 14); + break; + case 15: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 15); + break; + default: + *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 16); + break; + } + + _mm_empty(); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_palignr128 (int *i1, int *i2, unsigned int imm, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + + switch (imm) + { + case 0: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 0); + break; + case 1: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 1); + break; + case 2: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 2); + break; + case 3: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 3); + break; + case 4: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 4); + break; + case 5: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 5); + break; + case 6: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 6); + break; + case 7: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 7); + break; + case 8: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 8); + break; + case 9: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 9); + break; + case 10: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 10); + break; + case 11: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 11); + break; + case 12: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 12); + break; + case 13: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 13); + break; + case 14: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 14); + break; + case 15: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 15); + break; + case 16: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 16); + break; + case 17: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 17); + break; + case 18: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 18); + break; + case 19: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 19); + break; + case 20: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 20); + break; + case 21: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 21); + break; + case 22: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 22); + break; + case 23: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 23); + break; + case 24: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 24); + break; + case 25: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 25); + break; + case 26: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 26); + break; + case 27: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 27); + break; + case 28: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 28); + break; + case 29: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 29); + break; + case 30: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 30); + break; + case 31: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 31); + break; + default: + *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 32); + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result_128 (int *i1, int *i2, unsigned int imm, int *r) +{ + char buf [32]; + char *bout = (char *) r; + int i; + + memcpy (&buf[0], i2, 16); + memcpy (&buf[16], i1, 16); + + for (i = 0; i < 16; i++) + if (imm >= 32 || imm + i >= 32) + bout[i] = 0; + else + bout[i] = buf[imm + i]; +} + +#ifndef __AVX__ +static void +compute_correct_result_64 (int *i1, int *i2, unsigned int imm, int *r) +{ + char buf [16]; + char *bout = (char *)r; + int i; + + /* Handle the first half */ + memcpy (&buf[0], i2, 8); + memcpy (&buf[8], i1, 8); + + for (i = 0; i < 8; i++) + if (imm >= 16 || imm + i >= 16) + bout[i] = 0; + else + bout[i] = buf[imm + i]; + + /* Handle the second half */ + memcpy (&buf[0], &i2[2], 8); + memcpy (&buf[8], &i1[2], 8); + + for (i = 0; i < 8; i++) + if (imm >= 16 || imm + i >= 16) + bout[i + 8] = 0; + else + bout[i + 8] = buf[imm + i]; +} +#endif + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + unsigned int imm; + int fail = 0; + + for (i = 0; i < 256; i += 8) + for (imm = 0; imm < 100; imm++) + { +#ifndef __AVX__ + /* Manually compute the result */ + compute_correct_result_64 (&vals[i + 0], &vals[i + 4], imm, ck); + + /* Run the 64-bit tests */ + ssse3_test_palignr (&vals[i + 0], &vals[i + 4], imm, &r[0]); + ssse3_test_palignr (&vals[i + 2], &vals[i + 6], imm, &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Recompute the results for 128-bits */ + compute_correct_result_128 (&vals[i + 0], &vals[i + 4], imm, ck); + + /* Run the 128-bit tests */ + ssse3_test_palignr128 (&vals[i + 0], &vals[i + 4], imm, r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phaddd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phaddd.c new file mode 100644 index 000000000..bef781686 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phaddd.c @@ -0,0 +1,81 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H + +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_phaddd (int *i1, int *i2, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + *(__m64 *) r = _mm_hadd_pi32 (t1, t2); + _mm_empty(); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_phaddd128 (int *i1, int *i2, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + *(__m128i *) r = _mm_hadd_epi32 (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result(int *i1, int *i2, int *r) +{ + int i; + + for (i = 0; i < 2; i++) + r[i] = i1[2 * i] + i1[2 * i + 1]; + for (i = 0; i < 2; i++) + r[i + 2] = i2[2 * i] + i2[2 * i + 1]; +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + + for (i = 0; i < 256; i += 8) + { + /* Manually compute the result */ + compute_correct_result (&vals[i + 0], &vals[i + 4], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_phaddd (&vals[i + 0], &vals[i + 2], &r[0]); + ssse3_test_phaddd (&vals[i + 4], &vals[i + 6], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_phaddd128 (&vals[i + 0], &vals[i + 4], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phaddsw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phaddsw.c new file mode 100644 index 000000000..ff31fe5a5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phaddsw.c @@ -0,0 +1,95 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H + +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_phaddsw (int *i1, int *i2, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + *(__m64 *) r = _mm_hadds_pi16 (t1, t2); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_phaddsw128 (int *i1, int *i2, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + *(__m128i *) r = _mm_hadds_epi16 (t1, t2); +} + +static short +signed_saturate_to_word (int x) +{ + if (x > (int) 0x7fff) + return 0x7fff; + + if (x < (int) 0xffff8000) + return 0x8000; + + return (short) x; +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int *i1, int *i2, int *r) +{ + short *s1 = (short *) i1; + short *s2 = (short *) i2; + short *sout = (short *) r; + int i; + + for (i = 0; i < 4; i++) + sout[i] = signed_saturate_to_word(s1[2 * i] + s1[2 * i + 1]); + for (i = 0; i < 4; i++) + sout[i + 4] = signed_saturate_to_word(s2[2 * i] + s2[2 * i + 1]); +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 8) + { + /* Manually compute the result */ + compute_correct_result (&vals[i + 0], &vals[i + 4], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_phaddsw (&vals[i + 0], &vals[i + 2], &r[0]); + ssse3_test_phaddsw (&vals[i + 4], &vals[i + 6], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_phaddsw128 (&vals[i + 0], &vals[i + 4], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phaddw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phaddw.c new file mode 100644 index 000000000..05c0afd4f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phaddw.c @@ -0,0 +1,84 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H + +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_phaddw (int *i1, int *i2, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + *(__m64 *) r = _mm_hadd_pi16 (t1, t2); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_phaddw128 (int *i1, int *i2, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + *(__m128i *) r = _mm_hadd_epi16 (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result(int *i1, int *i2, int *r) +{ + short *s1 = (short *) i1; + short *s2 = (short *) i2; + short *sout = (short *) r; + int i; + + for (i = 0; i < 4; i++) + sout[i] = s1[2 * i] + s1[2 * i + 1]; + + for (i = 0; i < 4; i++) + sout[i + 4] = s2[2 * i] + s2[2 * i + 1]; +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 8) + { + /* Manually compute the result */ + compute_correct_result (&vals[i + 0], &vals[i + 4], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_phaddw (&vals[i + 0], &vals[i + 2], &r[0]); + ssse3_test_phaddw (&vals[i + 4], &vals[i + 6], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_phaddw128 (&vals[i + 0], &vals[i + 4], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phsubd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phsubd.c new file mode 100644 index 000000000..5884e5c12 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phsubd.c @@ -0,0 +1,80 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H + +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_phsubd (int *i1, int *i2, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + *(__m64 *) r = _mm_hsub_pi32(t1, t2); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_phsubd128 (int *i1, int *i2, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + *(__m128i *) r = _mm_hsub_epi32 (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int *i1, int *i2, int *r) +{ + int i; + + for (i = 0; i < 2; i++) + r[i] = i1[2 * i] - i1[2 * i + 1]; + for (i = 0; i < 2; i++) + r[i + 2] = i2[2 * i] - i2[2 * i + 1]; +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 8) + { + /* Manually compute the result */ + compute_correct_result (&vals[i + 0], &vals[i + 4], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_phsubd (&vals[i + 0], &vals[i + 2], &r[0]); + ssse3_test_phsubd (&vals[i + 4], &vals[i + 6], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_phsubd128 (&vals[i + 0], &vals[i + 4], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phsubsw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phsubsw.c new file mode 100644 index 000000000..371c8d112 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phsubsw.c @@ -0,0 +1,98 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H + +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_phsubsw (int *i1, int *i2, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + + *(__m64 *) r = _mm_hsubs_pi16 (t1, t2); + + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_phsubsw128 (int *i1, int *i2, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + *(__m128i *) r = _mm_hsubs_epi16 (t1, t2); +} + +static short +signed_saturate_to_word (int x) +{ + if (x > (int )0x7fff) + return 0x7fff; + + if (x < (int) 0xffff8000) + return 0x8000; + + return (short)x; +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int *i1, int *i2, int *r) +{ + short *s1 = (short *) i1; + short *s2 = (short *) i2; + short *sout = (short *) r; + int i; + + for (i = 0; i < 4; i++) + sout[i] = signed_saturate_to_word (s1[2 * i] - s1[2 * i + 1]); + + for (i = 0; i < 4; i++) + sout[i + 4] = signed_saturate_to_word (s2[2 * i] - s2[2 * i + 1]); +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 8) + { + /* Manually compute the result */ + compute_correct_result (&vals[i + 0], &vals[i + 4], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_phsubsw (&vals[i + 0], &vals[i + 2], &r[0]); + ssse3_test_phsubsw (&vals[i + 4], &vals[i + 6], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_phsubsw128 (&vals[i + 0], &vals[i + 4], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phsubw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phsubw.c new file mode 100644 index 000000000..f3dbf9c98 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-phsubw.c @@ -0,0 +1,83 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_phsubw (int *i1, int *i2, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + *(__m64 *) r = _mm_hsub_pi16 (t1, t2); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_phsubw128 (int *i1, int *i2, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + + *(__m128i *) r = _mm_hsub_epi16 (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int *i1, int *i2, int *r) +{ + short *s1 = (short *) i1; + short *s2 = (short *) i2; + short *sout = (short *) r; + int i; + + for (i = 0; i < 4; i++) + sout[i] = s1[2 * i] - s1[2 * i + 1]; + for (i = 0; i < 4; i++) + sout[i + 4] = s2[2 * i] - s2[2 * i + 1]; +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 8) + { + /* Manually compute the result */ + compute_correct_result (&vals[i + 0], &vals[i + 4], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_phsubw (&vals[i + 0], &vals[i + 2], &r[0]); + ssse3_test_phsubw (&vals[i + 4], &vals[i + 6], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_phsubw128 (&vals[i + 0], &vals[i + 4], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pmaddubsw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pmaddubsw.c new file mode 100644 index 000000000..00bfc844f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pmaddubsw.c @@ -0,0 +1,98 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H + +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_pmaddubsw (int *i1, int *i2, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + *(__m64 *) r = _mm_maddubs_pi16 (t1, t2); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_pmaddubsw128 (int *i1, int *i2, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + *(__m128i *) r = _mm_maddubs_epi16 (t1, t2); +} + +static short +signed_saturate_to_word(int x) +{ + if (x > (int) 0x7fff) + return 0x7fff; + + if (x < (int) 0xffff8000) + return 0x8000; + + return (short) x; +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int *i1, int *i2, int *r) +{ + unsigned char *ub1 = (unsigned char *) i1; + char *sb2 = (char *) i2; + short *sout = (short *) r; + int t0; + int i; + + for (i = 0; i < 8; i++) + { + t0 = ((int) ub1[2 * i] * (int) sb2[2 * i] + + (int) ub1[2 * i + 1] * (int) sb2[2 * i + 1]); + sout[i] = signed_saturate_to_word (t0); + } +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 8) + { + /* Manually compute the result */ + compute_correct_result (&vals[i + 0], &vals[i + 4], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_pmaddubsw (&vals[i + 0], &vals[i + 4], &r[0]); + ssse3_test_pmaddubsw (&vals[i + 2], &vals[i + 6], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_pmaddubsw128 (&vals[i + 0], &vals[i + 4], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pmulhrsw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pmulhrsw.c new file mode 100644 index 000000000..24570b3bd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pmulhrsw.c @@ -0,0 +1,85 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H + +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_pmulhrsw (int *i1, int *i2, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + *(__m64 *) r = _mm_mulhrs_pi16 (t1, t2); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_pmulhrsw128 (int *i1, int *i2, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + *(__m128i *) r = _mm_mulhrs_epi16 (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int *i1, int *i2, int *r) +{ + short *s1 = (short *) i1; + short *s2 = (short *) i2; + short *sout = (short *) r; + int t0; + int i; + + for (i = 0; i < 8; i++) + { + t0 = (((int) s1[i] * (int) s2[i]) >> 14) + 1; + sout[i] = (short) (t0 >> 1); + } +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 8) + { + /* Manually compute the result */ + compute_correct_result (&vals[i + 0], &vals[i + 4], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_pmulhrsw (&vals[i + 0], &vals[i + 4], &r[0]); + ssse3_test_pmulhrsw (&vals[i + 2], &vals[i + 6], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_pmulhrsw128 (&vals[i + 0], &vals[i + 4], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pshufb.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pshufb.c new file mode 100644 index 000000000..b995456b6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-pshufb.c @@ -0,0 +1,114 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H + +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_pshufb (int *i1, int *i2, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + *(__m64 *)r = _mm_shuffle_pi8 (t1, t2); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_pshufb128 (int *i1, int *i2, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + *(__m128i *)r = _mm_shuffle_epi8 (t1, t2); +} + +#ifndef __AVX__ +/* Routine to manually compute the results */ +static void +compute_correct_result_64 (int *i1, int *i2, int *r) +{ + char *b1 = (char *) i1; + char *b2 = (char *) i2; + char *bout = (char *) r; + int i; + char select; + + for (i = 0; i < 16; i++) + { + select = b2[i]; + if (select & 0x80) + bout[i] = 0; + else if (i < 8) + bout[i] = b1[select & 0x7]; + else + bout[i] = b1[8 + (select & 0x7)]; + } +} +#endif + +static void +compute_correct_result_128 (int *i1, int *i2, int *r) +{ + char *b1 = (char *) i1; + char *b2 = (char *) i2; + char *bout = (char *) r; + int i; + char select; + + for (i = 0; i < 16; i++) + { + select = b2[i]; + if (select & 0x80) + bout[i] = 0; + else + bout[i] = b1[select & 0xf]; + } +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 8) + { +#ifndef __AVX__ + /* Manually compute the result */ + compute_correct_result_64 (&vals[i + 0], &vals[i + 4], ck); + + /* Run the 64-bit tests */ + ssse3_test_pshufb (&vals[i + 0], &vals[i + 4], &r[0]); + ssse3_test_pshufb (&vals[i + 2], &vals[i + 6], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Recompute the result for 128-bits */ + compute_correct_result_128 (&vals[i + 0], &vals[i + 4], ck); + + /* Run the 128-bit tests */ + ssse3_test_pshufb128 (&vals[i + 0], &vals[i + 4], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-psignb.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-psignb.c new file mode 100644 index 000000000..7462929aa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-psignb.c @@ -0,0 +1,85 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_psignb (int *i1, int *i2, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + *(__m64 *) r = _mm_sign_pi8 (t1, t2); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_psignb128 (int *i1, int *i2, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + *(__m128i *) r = _mm_sign_epi8 (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int *i1, int *i2, int *r) +{ + char *b1 = (char *) i1; + char *b2 = (char *) i2; + char *bout = (char *) r; + int i; + + for (i = 0; i < 16; i++) + if (b2[i] < 0) + bout[i] = -b1[i]; + else if (b2[i] == 0) + bout[i] = 0; + else + bout[i] = b1[i]; +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 8) + { + /* Manually compute the result */ + compute_correct_result (&vals[i + 0], &vals[i + 4], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_psignb (&vals[i + 0], &vals[i + 4], &r[0]); + ssse3_test_psignb (&vals[i + 2], &vals[i + 6], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_psignb128 (&vals[i + 0], &vals[i + 4], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-psignd.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-psignd.c new file mode 100644 index 000000000..eca0489f8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-psignd.c @@ -0,0 +1,82 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_psignd (int *i1, int *i2, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + *(__m64 *) r = _mm_sign_pi32 (t1, t2); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_psignd128 (int *i1, int *i2, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + *(__m128i *)r = _mm_sign_epi32 (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int *i1, int *i2, int *r) +{ + int i; + + for (i = 0; i < 4; i++) + if (i2[i] < 0) + r[i] = -i1[i]; + else if (i2[i] == 0) + r[i] = 0; + else + r[i] = i1[i]; +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 8) + { + /* Manually compute the result */ + compute_correct_result (&vals[i + 0], &vals[i + 4], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_psignd (&vals[i + 0], &vals[i + 4], &r[0]); + ssse3_test_psignd (&vals[i + 2], &vals[i + 6], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_psignd128 (&vals[i + 0], &vals[i + 4], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-psignw.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-psignw.c new file mode 100644 index 000000000..00a506fd8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-psignw.c @@ -0,0 +1,85 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */ + +#ifndef CHECK_H +#define CHECK_H "ssse3-check.h" +#endif + +#ifndef TEST +#define TEST ssse3_test +#endif + +#include CHECK_H +#include "ssse3-vals.h" + +#include <tmmintrin.h> + +#ifndef __AVX__ +/* Test the 64-bit form */ +static void +ssse3_test_psignw (int *i1, int *i2, int *r) +{ + __m64 t1 = *(__m64 *) i1; + __m64 t2 = *(__m64 *) i2; + *(__m64 *) r = _mm_sign_pi16 (t1, t2); + _mm_empty (); +} +#endif + +/* Test the 128-bit form */ +static void +ssse3_test_psignw128 (int *i1, int *i2, int *r) +{ + /* Assumes incoming pointers are 16-byte aligned */ + __m128i t1 = *(__m128i *) i1; + __m128i t2 = *(__m128i *) i2; + *(__m128i *) r = _mm_sign_epi16 (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int *i1, int *i2, int *r) +{ + short *s1 = (short *) i1; + short *s2 = (short *) i2; + short *sout = (short *) r; + int i; + + for (i = 0; i < 8; i++) + if (s2[i] < 0) + sout[i] = -s1[i]; + else if (s2[i] == 0) + sout[i] = 0; + else + sout[i] = s1[i]; +} + +static void +TEST (void) +{ + int i; + int r [4] __attribute__ ((aligned(16))); + int ck [4]; + int fail = 0; + + for (i = 0; i < 256; i += 8) + { + /* Manually compute the result */ + compute_correct_result (&vals[i + 0], &vals[i + 4], ck); + +#ifndef __AVX__ + /* Run the 64-bit tests */ + ssse3_test_psignw (&vals[i + 0], &vals[i + 4], &r[0]); + ssse3_test_psignw (&vals[i + 2], &vals[i + 6], &r[2]); + fail += chk_128 (ck, r); +#endif + + /* Run the 128-bit tests */ + ssse3_test_psignw128 (&vals[i + 0], &vals[i + 4], r); + fail += chk_128 (ck, r); + } + + if (fail != 0) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-vals.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-vals.h new file mode 100644 index 000000000..048ca911c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/ssse3-vals.h @@ -0,0 +1,60 @@ +/* Routine to check correctness of the results */ +static int +chk_128 (int *v1, int *v2) +{ + int i; + int n_fails = 0; + + for (i = 0; i < 4; i++) + if (v1[i] != v2[i]) + n_fails += 1; + + return n_fails; +} + +static int vals [256] __attribute__ ((aligned(16))) = +{ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x5be800ee, 0x4f2d7b15, + 0x409d9291, 0xdd95f27f, 0x423986e3, 0x21a4d2cd, 0xa7056d84, 0x4f4e5a3b, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x73ef0244, 0xcd836329, 0x847f634f, 0xa7e3abcf, 0xb4c14764, 0x1ef42c06, + 0x504f29ac, 0x4ae7ca73, 0xaddde3c9, 0xf63ded2e, 0xa5d3553d, 0xa52ae05f, + 0x6fd3c83a, 0x7dc2b300, 0x76b05de7, 0xea8ebae5, 0x549568dd, 0x172f0358, + 0x917eadf0, 0x796fb0a7, 0xb39381af, 0xd0591d61, 0x731d2f17, 0xbc4b6f5d, + 0x8ec664c2, 0x3c199c19, 0x9c81db12, 0x6d85913b, 0x486107a9, 0xab6f4b26, + 0x5630d37c, 0x20836e85, 0x40d4e746, 0xdfbaba36, 0xbeacaa69, 0xb3c84083, + 0x8a688eb4, 0x08cde481, 0x66e7a190, 0x74ee1639, 0xb3942a19, 0xe0c40471, + 0x9b789489, 0x9751207a, 0x543a1524, 0x41da7ad6, 0x614bb563, 0xf86f57b1, + 0x69e62199, 0x2150cb12, 0x9ed74062, 0x429471f4, 0xad28502b, 0xf2e2d4d5, + 0x45b6ce09, 0xaaa5e649, 0xb46da484, 0x0a637515, 0xae7a3212, 0x5afc784c, + 0x776cfbbe, 0x9c542bb2, 0x64193aa8, 0x16e8a655, 0x4e3d2f92, 0xe05d7b72, + 0x89854ebc, 0x8c318814, 0xb81e76e0, 0x3f2625f5, 0x61b44852, 0x5209d7ad, + 0x842fe317, 0xd3cfcca1, 0x8d287cc7, 0x80f0c9a8, 0x4215f4e5, 0x563993d6, + 0x5d627433, 0xc4449e35, 0x5b4fe009, 0x3ef92286, 0xacbc8927, 0x549ab870, + 0x9ac5b959, 0xed8f1c91, 0x7ecf02cd, 0x989c0e8b, 0xa31d6918, 0x1dc2bcc1, + 0x99d3f3cc, 0x6857acc8, 0x45d7324a, 0xaebdf2e6, 0x7af2f2ae, 0x09716f73, + 0x7816e694, 0xc65493c0, 0x9f7e87bc, 0xaa96cd40, 0xbfb5bfc6, 0x01a2cce7, + 0x5f1d8c46, 0x45303efb, 0xb24607c3, 0xef2009a7, 0xba873753, 0xbefb14bc, + 0x74e53cd3, 0x70124708, 0x6eb4bdbd, 0xf3ba5e43, 0x4c94085f, 0x0c03e7e0, + 0x9a084931, 0x62735424, 0xaeee77c5, 0xdb34f90f, 0x6860cbdd, 0xaf77cf9f, + 0x95b28158, 0x23bd70d7, 0x9fbc3d88, 0x742e659e, 0x53bcfb48, 0xb8a63f6c, + 0x4dcf3373, 0x2b168627, 0x4fe20745, 0xd0af5e94, 0x22514e6a, 0xb8ef25c2, + 0x89ec781a, 0x13d9002b, 0x6d724500, 0x7fdbf63f, 0xb0e9ced5, 0xf919e0f3, + 0x00fef203, 0x8905d47a, 0x434e7517, 0x4aef8e2c, 0x689f51e8, 0xe513b7c3, + 0x72bbc5d2, 0x3a222f74, 0x05c3a0f9, 0xd5489d82, 0xb41fbe83, 0xec5d305f, + 0x5ea02b0b, 0xb176065b, 0xa8eb404e, 0x80349117, 0x210fd49e, 0x43898d0e, + 0x6c151b9c, 0x8742df18, 0x7b64de73, 0x1dbf52b2, 0x55c9cb19, 0xeb841f10, + 0x10b8ae76, 0x0764ecb6, 0xb7479018, 0x2672cb3f, 0x7ac9ac90, 0x4be5332c, + 0x8f1a0615, 0x4efb7a77, 0x16551a85, 0xdb2c3d66, 0x49179c07, 0x5dc4657e, + 0x5e76907e, 0xd7486a9c, 0x445204a4, 0x65cdc426, 0x33f86ded, 0xcba95dda, + 0x83351f16, 0xfedefad9, 0x639b620f, 0x86896a64, 0xba4099ba, 0x965f4a21, + 0x1247154f, 0x25604c42, 0x5862d692, 0xb1e9149e, 0x612516a5, 0x02c49bf8, + 0x631212bf, 0x9f69f54e, 0x168b63b0, 0x310a25ba, 0xa42a59cd, 0x084f0af9, + 0x44a06cec, 0x5c0cda40, 0xb932d721, 0x7c42bb0d, 0x213cd3f0, 0xedc7f5a4, + 0x7fb85859, 0x6b3da5ea, 0x61cd591e, 0xe8e9aa08, 0x4361fc34, 0x53d40d2a, + 0x0511ad1b, 0xf996b44c, 0xb5ead756, 0xc022138d, 0x6172adf1, 0xa4a0a3b4, + 0x8c2977b8, 0xa8e482ed, 0x04fcdd6b, 0x3f7b85d4, 0x4fca1e46, 0xa392ddca, + 0x569fc791, 0x346a706c, 0x543bf3eb, 0x895b3cde, 0x2146bb80, 0x26b3c168, + 0x929998db, 0x1ea472c9, 0x7207b36b, 0x6a8f10d4 +}; diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stack-prot-kernel.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stack-prot-kernel.c new file mode 100644 index 000000000..4a93e333c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stack-prot-kernel.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target nonpic } */ +/* { dg-options "-O2 -fstack-protector-all -mcmodel=kernel" } */ + +void test1 (int x) +{ + char p[40]; + int i; + for (i=0; i<40; i++) + p[i] = x; +} + +/* { dg-final { scan-assembler-not "%fs" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stack-realign.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stack-realign.c new file mode 100644 index 000000000..a45441845 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stack-realign.c @@ -0,0 +1,17 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-mstackrealign -O2" } */ + +extern void abort (void); + +__attribute__((noinline)) static void foo (int i1, int i2, int i3) +{ + if (i3 != 3) + abort (); +} + +int main (int argc, char **argv) +{ + foo (1, 2, 3); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stack-usage-realign.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stack-usage-realign.c new file mode 100644 index 000000000..c899606d6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stack-usage-realign.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-skip-if "no stack realignment" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-fstack-usage -msse2 -mforce-drap" } */ + +typedef int __attribute__((vector_size(16))) vec; + +vec foo (vec v) +{ + return v; +} + +int main (void) +{ + vec V; + V = foo (V); + return 0; +} + +/* { dg-final { scan-stack-usage "main\t48\tdynamic,bounded" } } */ +/* { dg-final { cleanup-stack-usage } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c new file mode 100644 index 000000000..dfe3968f5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-mpreferred-stack-boundary=2" } */ + +/* This case is to detect a compile time regression introduced in stack + branch development. */ +f(){asm("%0"::"r"(1.5F));}g(){asm("%0"::"r"(1.5));} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c new file mode 100644 index 000000000..161d2292d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c @@ -0,0 +1,15 @@ +/* PR target/39137 */ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -mpreferred-stack-boundary=2" } */ +/* Make sure dynamic stack realignment isn't performed just because there + are long long variables. */ +/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-8,\[^\\n\]*sp" } } */ + +void fn (void *); + +void f1 (void) +{ + unsigned long long a; + fn (&a); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c new file mode 100644 index 000000000..6ea83f98f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c @@ -0,0 +1,33 @@ +/* { dg-do compile { target { ! *-*-darwin* } } } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-O2 -mpreferred-stack-boundary=2" } */ +/* { dg-final { scan-assembler-times "and\[lq\]?\[^\\n\]*-8,\[^\\n\]*sp" 2 } } */ +/* { dg-final { scan-assembler-times "and\[lq\]?\[^\\n\]*-16,\[^\\n\]*sp" 2 } } */ + +void fn (void *); + +void f2 (void) +{ + unsigned long long a __attribute__((aligned (8))); + fn (&a); +} + +void f3 (void) +{ + typedef unsigned long long L __attribute__((aligned (8))); + L a; + fn (&a); +} + +void f4 (void) +{ + unsigned long long a __attribute__((aligned (16))); + fn (&a); +} + +void f5 (void) +{ + typedef unsigned long long L __attribute__((aligned (16))); + L a; + fn (&a); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/pr39146.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/pr39146.c new file mode 100644 index 000000000..9ae5f0345 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/pr39146.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ +/* { dg-options "-O2 -mavx" } */ + +typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__)); + + +__m256i +bar (__m256i x) +{ + return x; +} + +/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-32,\[^\\n\]*sp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-1.c new file mode 100644 index 000000000..c9fcc1213 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-mpreferred-stack-boundary=2" } */ + +/* This compile only test is to detect an assertion failure in stack branch + development. */ + +double +foo (void) +{ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-2.c new file mode 100644 index 000000000..d393913ae --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-mpreferred-stack-boundary=2" } */ + +/* This compile only test is to detect an assertion failure in stack branch + development. */ +void baz (void); + +double foo (void) +{ + baz (); + return; +} + +double bar (void) +{ + baz (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-3.c new file mode 100644 index 000000000..e32547e01 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! { ia32 && dfp } } { "*" } { "" } } */ +/* { dg-options "-msse -std=gnu99 -mpreferred-stack-boundary=2" } */ +/* { dg-require-effective-target sse } */ + +/* This compile only test is to detect an assertion failure in stack branch + development. */ +_Decimal128 test (void) +{ + return 1234123412341234.123412341234dl; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-4.c new file mode 100644 index 000000000..a1e35dcc2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mpreferred-stack-boundary=4" } */ +/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-64,\[^\\n\]*sp" } } */ + +/* This compile only test is to detect an assertion failure in stack branch + development. */ +typedef int aligned __attribute__((aligned(64))); + +aligned +foo (void) { } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-5.c new file mode 100644 index 000000000..208bc0d8a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-5.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mpreferred-stack-boundary=4" } */ +/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-64,\[^\\n\]*sp" } } */ + +/* This compile only test is to detect an assertion failure in stack branch + development. */ +struct bar +{ + int x; +} __attribute__((aligned(64))); + + +struct bar +foo (void) { } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-6.c new file mode 100644 index 000000000..b1aa1eac8 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/return-6.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mpreferred-stack-boundary=4" } */ +/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-64,\[^\\n\]*sp" } } */ + +/* This compile only test is to detect an assertion failure in stack branch + development. */ +struct bar +{ + int x __attribute__((aligned(64))); +}; + + +struct bar +foo (void) { } diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/stackalign.exp b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/stackalign.exp new file mode 100644 index 000000000..db7a49427 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/stackalign/stackalign.exp @@ -0,0 +1,46 @@ +# Copyright (C) 2008-2013 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# Exit immediately if this isn't a x86 target. +if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then { + return +} + +load_lib gcc-dg.exp + +# Only run on targets which support automatic stack alignment. +if { ![check_effective_target_automatic_stack_alignment] } then { + return +} + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS "-w" +} + +# Initialize `dg'. +dg-init + +set additional_flags "-mstackrealign" + +dg-runtest [lsort [glob $srcdir/$subdir/*.c]] $additional_flags $DEFAULT_CFLAGS + +set additional_flags "-mno-stackrealign" + +dg-runtest [lsort [glob $srcdir/$subdir/*.c]] $additional_flags $DEFAULT_CFLAGS + +dg-finish diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/strinline.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/strinline.c new file mode 100644 index 000000000..2fe671416 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/strinline.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-O2 -fPIC" } */ +typedef unsigned int size_t; + char * +__mempcpy_by2 (char *__dest, __const char *__src, size_t __srclen) +{ + register char *__tmp = __dest; + register unsigned long int __d0, __d1; + __asm__ __volatile__ + ("shrl $1,%3\n\t" + "jz 2f\n" + "1:\n\t" + "movl (%2),%0\n\t" + "leal 4(%2),%2\n\t" + "movl %0,(%1)\n\t" + "leal 4(%1),%1\n\t" + "decl %3\n\t" + "jnz 1b\n" + "2:\n\t" + "movw (%2),%w0\n\t" + "movw %w0,(%1)" + : "=&q" (__d0), "=r" (__tmp), "=&r" (__src), "=&r" (__d1), + "=m" ( *(struct { __extension__ char __x[__srclen]; } *)__dest) + : "1" (__tmp), "2" (__src), "3" (__srclen / 2), + "m" ( *(struct { __extension__ char __x[__srclen]; } *)__src) + : "cc"); + return __tmp + 2; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sw-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sw-1.c new file mode 100644 index 000000000..d07ac9cf5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/sw-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=generic -fshrink-wrap -fdump-rtl-pro_and_epilogue" } */ +/* { dg-skip-if "No shrink-wrapping preformed" { x86_64-*-mingw* } { "*" } { "" } } */ + +#include <string.h> + +int c; +int x[2000]; +__attribute__((regparm(1))) void foo (int a, int b) + { + int t[200]; + if (a == 0 || c == 0) + return; + memcpy (t, x + b, sizeof t); + c = t[a]; + } + +/* { dg-final { scan-rtl-dump "Performing shrink-wrapping" "pro_and_epilogue" } } */ +/* { dg-final { cleanup-rtl-dump "pro_and_epilogue" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/tailcall-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/tailcall-1.c new file mode 100644 index 000000000..9aae9d45e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/tailcall-1.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-require-effective-target nonpic } */ +/* { dg-options "-O2" } */ + +typedef unsigned int Cardinal; +typedef char *String; +typedef struct _WidgetRec *Widget; + +typedef union _XEvent { + int type; + long pad[24]; +} XEvent; + + +extern int SendMousePosition (Widget w, XEvent* event); + + +void +HandleIgnore(Widget w, + XEvent * event, + String * params , + Cardinal *param_count ) +{ + + (void) SendMousePosition(w, event); +} + +/* { dg-final { scan-assembler "jmp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/tbm-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/tbm-1.c new file mode 100644 index 000000000..2c16d74db --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/tbm-1.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtbm" } */ +/* { dg-final { scan-assembler "bextr\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "blcfill\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "blci\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "blcic\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "blcmsk\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "blcs\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "blsfill\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "blsic\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "t1mskc\[^\\n]*(%|)eax" } } */ +/* { dg-final { scan-assembler "tzmsk\[^\\n]*(%|)eax" } } */ + +#include <x86intrin.h> + +unsigned int +func_bextri32 (unsigned int X) +{ + return __bextri_u32 (X, 0x101); +} + +unsigned int +func_blcfill32 (unsigned int X) +{ + return __blcfill_u32 (X); +} + +unsigned int +func_blci32 (unsigned int X) +{ + return __blci_u32 (X); +} + +unsigned int +func_blcic32 (unsigned int X) +{ + return __blcic_u32 (X); +} + +unsigned int +func_blcmsk32 (unsigned int X) +{ + return __blcmsk_u32 (X); +} + +unsigned int +func_blcs32 (unsigned int X) +{ + return __blcs_u32 (X); +} + +unsigned int +func_blsfill32 (unsigned int X) +{ + return __blsfill_u32 (X); +} + +unsigned int +func_blsic32 (unsigned int X) +{ + return __blsic_u32 (X); +} + +unsigned int +func_t1mskc32 (unsigned int X) +{ + return __t1mskc_u32 (X); +} + +unsigned int +func_tzmsk32 (unsigned int X) +{ + return __tzmsk_u32 (X); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/tbm-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/tbm-2.c new file mode 100644 index 000000000..fa3870a5e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/tbm-2.c @@ -0,0 +1,74 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mtbm" } */ +/* { dg-final { scan-assembler "bextr\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "blcfill\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "blci\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "blcic\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "blcmsk\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "blcs\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "blsfill\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "blsic\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "t1mskc\[^\\n]*(%|)rax" } } */ +/* { dg-final { scan-assembler "tzmsk\[^\\n]*(%|)rax" } } */ + +#include <x86intrin.h> + +unsigned long long +func_bextri64 (unsigned long long X) +{ + return __bextri_u64 (X, 0x101); +} + +unsigned long long +func_blcfill64 (unsigned long long X) +{ + return __blcfill_u64 (X); +} + +unsigned long long +func_blci64 (unsigned long long X) +{ + return __blci_u64 (X); +} + +unsigned long long +func_blcic64 (unsigned long long X) +{ + return __blcic_u64 (X); +} + +unsigned long long +func_blcmsk64 (unsigned long long X) +{ + return __blcmsk_u64 (X); +} + +unsigned long long +func_blcs64 (unsigned long long X) +{ + return __blcs_u64 (X); +} + +unsigned long long +func_blsfill64 (unsigned long long X) +{ + return __blsfill_u64 (X); +} + +unsigned long long +func_blsic64 (unsigned long long X) +{ + return __blsic_u64 (X); +} + +unsigned long long +func_t1mskc64 (unsigned long long X) +{ + return __t1mskc_u64 (X); +} + +unsigned long long +func_tzmsk64 (unsigned long long X) +{ + return __tzmsk_u64 (X); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-1.c new file mode 100644 index 000000000..57276192e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-1.c @@ -0,0 +1,94 @@ +/* PR target/49411 */ +/* { dg-do compile } */ +/* { dg-options "-O0 -mf16c -maes -mpclmul" } */ + +#include <x86intrin.h> + +__m128i i1, i2, i3, i4; +__m128 a1, a2, a3, a4; +__m128d d1, d2, d3, d4; +__m256i l1, l2, l3, l4; +__m256 b1, b2, b3, b4; +__m256d e1, e2, e3, e4; +__m64 m1, m2, m3, m4; +int k1, k2, k3, k4; +float f1, f2, f3, f4; + +void +test8bit (void) +{ + i1 = _mm_cmpistrm (i2, i3, 256); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistri (i2, i3, 256); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistra (i2, i3, 256); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistrc (i2, i3, 256); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistro (i2, i3, 256); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistrs (i2, i3, 256); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistrz (i2, i3, 256); /* { dg-error "the third argument must be an 8-bit immediate" } */ + i1 = _mm_cmpestrm (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestri (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestra (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestrc (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestro (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestrs (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestrz (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + b1 = _mm256_blend_ps (b2, b3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + k1 = _cvtss_sh (f1, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm256_cvtps_ph (b2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + b1 = _mm256_dp_ps (b2, b3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + e1 = _mm256_permute2f128_pd (e2, e3, 256);/* { dg-error "the last argument must be an 8-bit immediate" } */ + b1 = _mm256_permute2f128_ps (b2, b3, 256);/* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_permute2f128_si256 (l2, l3, 256);/* { dg-error "the last argument must be an 8-bit immediate" } */ + b1 = _mm256_permute_ps (b2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_aeskeygenassist_si128 (i2, 256);/* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_blend_epi16 (i2, i3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_clmulepi64_si128 (i2, i3, 256);/* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_cvtps_ph (a1, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + d1 = _mm_dp_pd (d2, d3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + a1 = _mm_dp_ps (a2, a3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + a1 = _mm_insert_ps (a2, a3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_mpsadbw_epu8 (i2, i3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + a1 = _mm_permute_ps (a2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_slli_si128 (i2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_srli_si128 (i2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ +} + +void +test5bit (void) +{ + d1 = _mm_cmp_sd (d2, d3, 32); /* { dg-error "the last argument must be a 5-bit immediate" } */ + a1 = _mm_cmp_ss (a2, a3, 32); /* { dg-error "the last argument must be a 5-bit immediate" } */ + d1 = _mm_cmp_pd (d2, d3, 32); /* { dg-error "the last argument must be a 5-bit immediate" } */ + a1 = _mm_cmp_ps (a2, a3, 32); /* { dg-error "the last argument must be a 5-bit immediate" } */ + e1 = _mm256_cmp_pd (e2, e3, 32); /* { dg-error "the last argument must be a 5-bit immediate" } */ + b1 = _mm256_cmp_ps (b2, b3, 32); /* { dg-error "the last argument must be a 5-bit immediate" } */ +} + +void +test4bit (void) +{ + d1 = _mm_round_pd (d2, 16); /* { dg-error "the last argument must be a 4-bit immediate" } */ + d1 = _mm_round_sd (d2, d3, 16); /* { dg-error "the last argument must be a 4-bit immediate" } */ + a1 = _mm_round_ps (a2, 16); /* { dg-error "the last argument must be a 4-bit immediate" } */ + a1 = _mm_round_ss (a2, a2, 16); /* { dg-error "the last argument must be a 4-bit immediate" } */ + a1 = _mm_blend_ps (a2, a3, 16); /* { dg-error "the last argument must be a 4-bit immediate" } */ + e1 = _mm256_blend_pd (e2, e3, 16); /* { dg-error "the last argument must be a 4-bit immediate" } */ + e1 = _mm256_round_pd (e2, 16); /* { dg-error "the last argument must be a 4-bit immediate" } */ + b1 = _mm256_round_ps (b2, 16); /* { dg-error "the last argument must be a 4-bit immediate" } */ +} + +void +test2bit (void) +{ + d1 = _mm_blend_pd (d2, d3, 4); /* { dg-error "the last argument must be a 2-bit immediate" } */ +} + +void +test1bit (void) +{ + d1 = _mm256_extractf128_pd (e2, 2); /* { dg-error "the last argument must be a 1-bit immediate" } */ + a1 = _mm256_extractf128_ps (b2, 2); /* { dg-error "the last argument must be a 1-bit immediate" } */ + i1 = _mm256_extractf128_si256 (l2, 2); /* { dg-error "the last argument must be a 1-bit immediate" } */ + e1 = _mm256_insertf128_pd (e2, d1, 2); /* { dg-error "the last argument must be a 1-bit immediate" } */ + b1 = _mm256_insertf128_ps (b2, a1, 2); /* { dg-error "the last argument must be a 1-bit immediate" } */ + l1 = _mm256_insertf128_si256 (l2, i1, 2);/* { dg-error "the last argument must be a 1-bit immediate" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-2.c new file mode 100644 index 000000000..3d5080920 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-2.c @@ -0,0 +1,94 @@ +/* PR target/49411 */ +/* { dg-do compile } */ +/* { dg-options "-O0 -mf16c -maes -mpclmul" } */ + +#include <x86intrin.h> + +__m128i i1, i2, i3, i4; +__m128 a1, a2, a3, a4; +__m128d d1, d2, d3, d4; +__m256i l1, l2, l3, l4; +__m256 b1, b2, b3, b4; +__m256d e1, e2, e3, e4; +__m64 m1, m2, m3, m4; +int k1, k2, k3, k4; +float f1, f2, f3, f4; + +void +test8bit (void) +{ + i1 = _mm_cmpistrm (i2, i3, -10); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistri (i2, i3, -10); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistra (i2, i3, -10); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistrc (i2, i3, -10); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistro (i2, i3, -10); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistrs (i2, i3, -10); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistrz (i2, i3, -10); /* { dg-error "the third argument must be an 8-bit immediate" } */ + i1 = _mm_cmpestrm (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestri (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestra (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestrc (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestro (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestrs (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestrz (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */ + b1 = _mm256_blend_ps (b2, b3, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + k1 = _cvtss_sh (f1, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm256_cvtps_ph (b2, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + b1 = _mm256_dp_ps (b2, b3, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + e1 = _mm256_permute2f128_pd (e2, e3, -10);/* { dg-error "the last argument must be an 8-bit immediate" } */ + b1 = _mm256_permute2f128_ps (b2, b3, -10);/* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_permute2f128_si256 (l2, l3, -10);/* { dg-error "the last argument must be an 8-bit immediate" } */ + b1 = _mm256_permute_ps (b2, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_aeskeygenassist_si128 (i2, -10);/* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_blend_epi16 (i2, i3, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_clmulepi64_si128 (i2, i3, -10);/* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_cvtps_ph (a1, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + d1 = _mm_dp_pd (d2, d3, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + a1 = _mm_dp_ps (a2, a3, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + a1 = _mm_insert_ps (a2, a3, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_mpsadbw_epu8 (i2, i3, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + a1 = _mm_permute_ps (a2, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_slli_si128 (i2, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_srli_si128 (i2, -10); /* { dg-error "the last argument must be an 8-bit immediate" } */ +} + +void +test5bit (void) +{ + d1 = _mm_cmp_sd (d2, d3, -7); /* { dg-error "the last argument must be a 5-bit immediate" } */ + a1 = _mm_cmp_ss (a2, a3, -7); /* { dg-error "the last argument must be a 5-bit immediate" } */ + d1 = _mm_cmp_pd (d2, d3, -7); /* { dg-error "the last argument must be a 5-bit immediate" } */ + a1 = _mm_cmp_ps (a2, a3, -7); /* { dg-error "the last argument must be a 5-bit immediate" } */ + e1 = _mm256_cmp_pd (e2, e3, -7); /* { dg-error "the last argument must be a 5-bit immediate" } */ + b1 = _mm256_cmp_ps (b2, b3, -7); /* { dg-error "the last argument must be a 5-bit immediate" } */ +} + +void +test4bit (void) +{ + d1 = _mm_round_pd (d2, -7); /* { dg-error "the last argument must be a 4-bit immediate" } */ + d1 = _mm_round_sd (d2, d3, -7); /* { dg-error "the last argument must be a 4-bit immediate" } */ + a1 = _mm_round_ps (a2, -7); /* { dg-error "the last argument must be a 4-bit immediate" } */ + a1 = _mm_round_ss (a2, a2, -7); /* { dg-error "the last argument must be a 4-bit immediate" } */ + a1 = _mm_blend_ps (a2, a3, -7); /* { dg-error "the last argument must be a 4-bit immediate" } */ + e1 = _mm256_blend_pd (e2, e3, -7); /* { dg-error "the last argument must be a 4-bit immediate" } */ + e1 = _mm256_round_pd (e2, -7); /* { dg-error "the last argument must be a 4-bit immediate" } */ + b1 = _mm256_round_ps (b2, -7); /* { dg-error "the last argument must be a 4-bit immediate" } */ +} + +void +test2bit (void) +{ + d1 = _mm_blend_pd (d2, d3, -1); /* { dg-error "the last argument must be a 2-bit immediate" } */ +} + +void +test1bit (void) +{ + d1 = _mm256_extractf128_pd (e2, -1); /* { dg-error "the last argument must be a 1-bit immediate" } */ + a1 = _mm256_extractf128_ps (b2, -1); /* { dg-error "the last argument must be a 1-bit immediate" } */ + i1 = _mm256_extractf128_si256 (l2, -1); /* { dg-error "the last argument must be a 1-bit immediate" } */ + e1 = _mm256_insertf128_pd (e2, d1, -1); /* { dg-error "the last argument must be a 1-bit immediate" } */ + b1 = _mm256_insertf128_ps (b2, a1, -1); /* { dg-error "the last argument must be a 1-bit immediate" } */ + l1 = _mm256_insertf128_si256 (l2, i1, -1);/* { dg-error "the last argument must be a 1-bit immediate" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-3.c new file mode 100644 index 000000000..3e4fea7fe --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-3.c @@ -0,0 +1,94 @@ +/* PR target/49411 */ +/* { dg-do compile } */ +/* { dg-options "-O0 -mf16c -maes -mpclmul" } */ + +#include <x86intrin.h> + +__m128i i1, i2, i3, i4; +__m128 a1, a2, a3, a4; +__m128d d1, d2, d3, d4; +__m256i l1, l2, l3, l4; +__m256 b1, b2, b3, b4; +__m256d e1, e2, e3, e4; +__m64 m1, m2, m3, m4; +int k1, k2, k3, k4; +float f1, f2, f3, f4; + +void +test8bit (void) +{ + i1 = _mm_cmpistrm (i2, i3, k4); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistri (i2, i3, k4); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistra (i2, i3, k4); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistrc (i2, i3, k4); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistro (i2, i3, k4); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistrs (i2, i3, k4); /* { dg-error "the third argument must be an 8-bit immediate" } */ + k1 = _mm_cmpistrz (i2, i3, k4); /* { dg-error "the third argument must be an 8-bit immediate" } */ + i1 = _mm_cmpestrm (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestri (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestra (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestrc (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestro (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestrs (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */ + k1 = _mm_cmpestrz (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */ + b1 = _mm256_blend_ps (b2, b3, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + k1 = _cvtss_sh (f1, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm256_cvtps_ph (b2, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + b1 = _mm256_dp_ps (b2, b3, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + e1 = _mm256_permute2f128_pd (e2, e3, k4);/* { dg-error "the last argument must be an 8-bit immediate" } */ + b1 = _mm256_permute2f128_ps (b2, b3, k4);/* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_permute2f128_si256 (l2, l3, k4);/* { dg-error "the last argument must be an 8-bit immediate" } */ + b1 = _mm256_permute_ps (b2, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_aeskeygenassist_si128 (i2, k4);/* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_blend_epi16 (i2, i3, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_clmulepi64_si128 (i2, i3, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_cvtps_ph (a1, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + d1 = _mm_dp_pd (d2, d3, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + a1 = _mm_dp_ps (a2, a3, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + a1 = _mm_insert_ps (a2, a3, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_mpsadbw_epu8 (i2, i3, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + a1 = _mm_permute_ps (a2, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_slli_si128 (i2, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_srli_si128 (i2, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ +} + +void +test5bit (void) +{ + d1 = _mm_cmp_sd (d2, d3, k4); /* { dg-error "the last argument must be a 5-bit immediate" } */ + a1 = _mm_cmp_ss (a2, a3, k4); /* { dg-error "the last argument must be a 5-bit immediate" } */ + d1 = _mm_cmp_pd (d2, d3, k4); /* { dg-error "the last argument must be a 5-bit immediate" } */ + a1 = _mm_cmp_ps (a2, a3, k4); /* { dg-error "the last argument must be a 5-bit immediate" } */ + e1 = _mm256_cmp_pd (e2, e3, k4); /* { dg-error "the last argument must be a 5-bit immediate" } */ + b1 = _mm256_cmp_ps (b2, b3, k4); /* { dg-error "the last argument must be a 5-bit immediate" } */ +} + +void +test4bit (void) +{ + d1 = _mm_round_pd (d2, k4); /* { dg-error "the last argument must be a 4-bit immediate" } */ + d1 = _mm_round_sd (d2, d3, k4); /* { dg-error "the last argument must be a 4-bit immediate" } */ + a1 = _mm_round_ps (a2, k4); /* { dg-error "the last argument must be a 4-bit immediate" } */ + a1 = _mm_round_ss (a2, a2, k4); /* { dg-error "the last argument must be a 4-bit immediate" } */ + a1 = _mm_blend_ps (a2, a3, k4); /* { dg-error "the last argument must be a 4-bit immediate" } */ + e1 = _mm256_blend_pd (e2, e3, k4); /* { dg-error "the last argument must be a 4-bit immediate" } */ + e1 = _mm256_round_pd (e2, k4); /* { dg-error "the last argument must be a 4-bit immediate" } */ + b1 = _mm256_round_ps (b2, k4); /* { dg-error "the last argument must be a 4-bit immediate" } */ +} + +void +test2bit (void) +{ + d1 = _mm_blend_pd (d2, d3, k4); /* { dg-error "the last argument must be a 2-bit immediate" } */ +} + +void +test1bit (void) +{ + d1 = _mm256_extractf128_pd (e2, k4); /* { dg-error "the last argument must be a 1-bit immediate" } */ + a1 = _mm256_extractf128_ps (b2, k4); /* { dg-error "the last argument must be a 1-bit immediate" } */ + i1 = _mm256_extractf128_si256 (l2, k4); /* { dg-error "the last argument must be a 1-bit immediate" } */ + e1 = _mm256_insertf128_pd (e2, d1, k4); /* { dg-error "the last argument must be a 1-bit immediate" } */ + b1 = _mm256_insertf128_ps (b2, a1, k4); /* { dg-error "the last argument must be a 1-bit immediate" } */ + l1 = _mm256_insertf128_si256 (l2, i1, k4);/* { dg-error "the last argument must be a 1-bit immediate" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-4.c new file mode 100644 index 000000000..2eaf41338 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-4.c @@ -0,0 +1,97 @@ +/* PR target/49411 */ +/* { dg-do assemble } */ +/* { dg-options "-O0 -mf16c -maes -mpclmul" } */ +/* { dg-require-effective-target f16c } */ +/* { dg-require-effective-target vaes } */ +/* { dg-require-effective-target vpclmul } */ + +#include <x86intrin.h> + +__m128i i1, i2, i3, i4; +__m128 a1, a2, a3, a4; +__m128d d1, d2, d3, d4; +__m256i l1, l2, l3, l4; +__m256 b1, b2, b3, b4; +__m256d e1, e2, e3, e4; +__m64 m1, m2, m3, m4; +int k1, k2, k3, k4; +float f1, f2, f3, f4; + +void +test8bit (void) +{ + i1 = _mm_cmpistrm (i2, i3, 255); + k1 = _mm_cmpistri (i2, i3, 255); + k1 = _mm_cmpistra (i2, i3, 255); + k1 = _mm_cmpistrc (i2, i3, 255); + k1 = _mm_cmpistro (i2, i3, 255); + k1 = _mm_cmpistrs (i2, i3, 255); + k1 = _mm_cmpistrz (i2, i3, 255); + i1 = _mm_cmpestrm (i2, k2, i3, k3, 255); + k1 = _mm_cmpestri (i2, k2, i3, k3, 255); + k1 = _mm_cmpestra (i2, k2, i3, k3, 255); + k1 = _mm_cmpestrc (i2, k2, i3, k3, 255); + k1 = _mm_cmpestro (i2, k2, i3, k3, 255); + k1 = _mm_cmpestrs (i2, k2, i3, k3, 255); + k1 = _mm_cmpestrz (i2, k2, i3, k3, 255); + b1 = _mm256_blend_ps (b2, b3, 255); + k1 = _cvtss_sh (f1, 255); + i1 = _mm256_cvtps_ph (b2, 255); + b1 = _mm256_dp_ps (b2, b3, 255); + e1 = _mm256_permute2f128_pd (e2, e3, 255); + b1 = _mm256_permute2f128_ps (b2, b3, 255); + l1 = _mm256_permute2f128_si256 (l2, l3, 255); + b1 = _mm256_permute_ps (b2, 255); + i1 = _mm_aeskeygenassist_si128 (i2, 255); + i1 = _mm_blend_epi16 (i2, i3, 255); + i1 = _mm_clmulepi64_si128 (i2, i3, 255); + i1 = _mm_cvtps_ph (a1, 255); + d1 = _mm_dp_pd (d2, d3, 255); + a1 = _mm_dp_ps (a2, a3, 255); + a1 = _mm_insert_ps (a2, a3, 255); + i1 = _mm_mpsadbw_epu8 (i2, i3, 255); + a1 = _mm_permute_ps (a2, 255); + i1 = _mm_slli_si128 (i2, 255); + i1 = _mm_srli_si128 (i2, 255); +} + +void +test5bit (void) +{ + d1 = _mm_cmp_sd (d2, d3, 31); + a1 = _mm_cmp_ss (a2, a3, 31); + d1 = _mm_cmp_pd (d2, d3, 31); + a1 = _mm_cmp_ps (a2, a3, 31); + e1 = _mm256_cmp_pd (e2, e3, 31); + b1 = _mm256_cmp_ps (b2, b3, 31); +} + +void +test4bit (void) +{ + d1 = _mm_round_pd (d2, 15); + d1 = _mm_round_sd (d2, d3, 15); + a1 = _mm_round_ps (a2, 15); + a1 = _mm_round_ss (a2, a2, 15); + a1 = _mm_blend_ps (a2, a3, 15); + e1 = _mm256_blend_pd (e2, e3, 15); + e1 = _mm256_round_pd (e2, 15); + b1 = _mm256_round_ps (b2, 15); +} + +void +test2bit (void) +{ + d1 = _mm_blend_pd (d2, d3, 3); +} + +void +test1bit (void) +{ + d1 = _mm256_extractf128_pd (e2, 1); + a1 = _mm256_extractf128_ps (b2, 1); + i1 = _mm256_extractf128_si256 (l2, 1); + e1 = _mm256_insertf128_pd (e2, d1, 1); + b1 = _mm256_insertf128_ps (b2, a1, 1); + l1 = _mm256_insertf128_si256 (l2, i1, 1); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-5.c new file mode 100644 index 000000000..67c152834 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-5.c @@ -0,0 +1,8 @@ +/* PR target/49411 */ +/* { dg-do assemble } */ +/* { dg-options "-O2 -mf16c -maes -mpclmul" } */ +/* { dg-require-effective-target f16c } */ +/* { dg-require-effective-target vaes } */ +/* { dg-require-effective-target vpclmul } */ + +#include "testimm-4.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-6.c new file mode 100644 index 000000000..087a6ffa5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-6.c @@ -0,0 +1,41 @@ +/* PR target/49411 */ +/* { dg-do compile } */ +/* { dg-options "-O0 -mxop" } */ + +#include <x86intrin.h> + +__m128i i1, i2, i3, i4; +__m128 a1, a2, a3, a4; +__m128d d1, d2, d3, d4; +__m256i l1, l2, l3, l4; +__m256 b1, b2, b3, b4; +__m256d e1, e2, e3, e4; +__m64 m1, m2, m3, m4; +int k1, k2, k3, k4; +float f1, f2, f3, f4; + +void +test2bit (void) +{ + d1 = _mm_permute2_pd (d2, d3, i1, 17); /* { dg-error "the last argument must be a 2-bit immediate" } */ + e1 = _mm256_permute2_pd (e2, e3, l1, 17); /* { dg-error "the last argument must be a 2-bit immediate" } */ + a1 = _mm_permute2_ps (a2, a3, i1, 17); /* { dg-error "the last argument must be a 2-bit immediate" } */ + b1 = _mm256_permute2_ps (b2, b3, l1, 17); /* { dg-error "the last argument must be a 2-bit immediate" } */ + d1 = _mm_permute2_pd (d2, d3, i1, k4); /* { dg-error "the last argument must be a 2-bit immediate" } */ + e1 = _mm256_permute2_pd (e2, e3, l1, k4); /* { dg-error "the last argument must be a 2-bit immediate" } */ + a1 = _mm_permute2_ps (a2, a3, i1, k4); /* { dg-error "the last argument must be a 2-bit immediate" } */ + b1 = _mm256_permute2_ps (b2, b3, l1, k4); /* { dg-error "the last argument must be a 2-bit immediate" } */ +} + +void +test2args (void) +{ + i1 = _mm_extracti_si64 (i2, 256, 0); /* { dg-error "the next to last argument must be an 8-bit immediate" } */ + i1 = _mm_extracti_si64 (i2, 0, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_inserti_si64 (i2, i3, 256, 0); /* { dg-error "the next to last argument must be an 8-bit immediate" } */ + i2 = _mm_inserti_si64 (i2, i3, 0, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_extracti_si64 (i2, k4, 0); /* { dg-error "the next to last argument must be an 8-bit immediate" } */ + i1 = _mm_extracti_si64 (i2, 0, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_inserti_si64 (i2, i3, k4, 0); /* { dg-error "the next to last argument must be an 8-bit immediate" } */ + i2 = _mm_inserti_si64 (i2, i3, 0, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-7.c new file mode 100644 index 000000000..9b16fc7f0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-7.c @@ -0,0 +1,46 @@ +/* PR target/49411 */ +/* { dg-do assemble } */ +/* { dg-options "-O0 -mxop" } */ +/* { dg-require-effective-target xop } */ + +#include <x86intrin.h> + +__m128i i1, i2, i3, i4; +__m128 a1, a2, a3, a4; +__m128d d1, d2, d3, d4; +__m256i l1, l2, l3, l4; +__m256 b1, b2, b3, b4; +__m256d e1, e2, e3, e4; +__m64 m1, m2, m3, m4; +int k1, k2, k3, k4; +float f1, f2, f3, f4; + +void +test2bit (void) +{ + d1 = _mm_permute2_pd (d2, d3, i1, 3); + e1 = _mm256_permute2_pd (e2, e3, l1, 3); + a1 = _mm_permute2_ps (a2, a3, i1, 3); + b1 = _mm256_permute2_ps (b2, b3, l1, 3); + d1 = _mm_permute2_pd (d2, d3, i1, 0); + e1 = _mm256_permute2_pd (e2, e3, l1, 0); + a1 = _mm_permute2_ps (a2, a3, i1, 0); + b1 = _mm256_permute2_ps (b2, b3, l1, 0); +} + +void +test2args (void) +{ + i1 = _mm_extracti_si64 (i2, 255, 0); + i1 = _mm_extracti_si64 (i2, 0, 255); + i1 = _mm_inserti_si64 (i2, i3, 255, 0); + i2 = _mm_inserti_si64 (i2, i3, 0, 255); + i1 = _mm_extracti_si64 (i2, 255, 255); + i1 = _mm_extracti_si64 (i2, 255, 255); + i1 = _mm_inserti_si64 (i2, i3, 255, 255); + i2 = _mm_inserti_si64 (i2, i3, 255, 255); + i1 = _mm_extracti_si64 (i2, 0, 0); + i1 = _mm_extracti_si64 (i2, 0, 0); + i1 = _mm_inserti_si64 (i2, i3, 0, 0); + i2 = _mm_inserti_si64 (i2, i3, 0, 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-8.c new file mode 100644 index 000000000..5169763fe --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-8.c @@ -0,0 +1,6 @@ +/* PR target/49411 */ +/* { dg-do assemble } */ +/* { dg-options "-O2 -mxop" } */ +/* { dg-require-effective-target xop } */ + +#include "testimm-7.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-9.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-9.c new file mode 100644 index 000000000..a9b4fe9e3 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/testimm-9.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -mavx2" } */ + +#include <x86intrin.h> + +__m128i i1, i2, i3, i4; +__m256i l1, l2, l3, l4; +__m256d e1, e2, e3, e4; + +void +test8bit (void) +{ + l1 = _mm256_mpsadbw_epu8 (l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_alignr_epi8 (l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + i1 = _mm_blend_epi32 (i1, i1, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_blend_epi32 (l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_blend_epi16(l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_permute2x128_si256 (l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + e1 = _mm256_permute4x64_pd (e2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_permute4x64_epi64 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_shuffle_epi32 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_shufflehi_epi16 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_shufflelo_epi16 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_slli_si256 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ + l1 = _mm256_srli_si256 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */ +} + +void +test1bit (void) +{ + i1 = _mm256_extracti128_si256 (l1, 2); /* { dg-error "the last argument must be an 1-bit immediate" } */ + l1 = _mm256_inserti128_si256 (l1, i2, 2); /* { dg-error "the last argument must be an 1-bit immediate" } */ +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-1.c new file mode 100644 index 000000000..eebd84362 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-1.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +extern void abort (void); + +void +__attribute__((noinline)) +test (unsigned int x, unsigned int y, unsigned int q, unsigned int r) +{ + if ((x / y) != q || (x % y) != r) + abort (); +} + +int +main () +{ + test (7, 6, 1, 1); + test (255, 254, 1, 1); + test (256, 254, 1, 2); + test (256, 256, 1, 0); + test (254, 256, 0, 254); + test (254, 255, 0, 254); + test (254, 1, 254, 0); + test (255, 2, 127, 1); + test (1, 256, 0, 1); + test (0x80000000, 0x7fffffff, 1, 1); + test (0x7fffffff, 0x80000000, 0, 0x7fffffff); + test (0x80000000, 0x80000003, 0, 0x80000000); + test (0xfffffffd, 0xfffffffe, 0, 0xfffffffd); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-2.c new file mode 100644 index 000000000..2bba8f3c9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +unsigned int +foo (unsigned int x, unsigned int y) +{ + return x / y; +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-times "divl" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-3.c new file mode 100644 index 000000000..f2ac4e5da --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +unsigned int +foo (unsigned int x, unsigned int y) +{ + return x % y; +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-times "divl" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-4.c new file mode 100644 index 000000000..14dd87c17 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +extern void abort (void); + +void +test (unsigned int x, unsigned int y, unsigned int q, unsigned int r) +{ + if ((x / y) != q || (x % y) != r) + abort (); +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-times "divl" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-4a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-4a.c new file mode 100644 index 000000000..f1ff38909 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-4a.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -m8bit-idiv" } */ + +extern void abort (void); + +void +test (unsigned int x, unsigned int y, unsigned int q, unsigned int r) +{ + if ((x / y) != q || (x % y) != r) + abort (); +} + +/* { dg-final { scan-assembler-not "divb" } } */ +/* { dg-final { scan-assembler-times "divl" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-5.c new file mode 100644 index 000000000..7c31a0a9c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-5.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +extern void foo (unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int); + +void +bar (unsigned int x, unsigned int y) +{ + foo (0, 0, 0, 0, x / y, x % y); +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-times "divl" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-6.c new file mode 100644 index 000000000..d77417178 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-6.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +extern void abort (void); + +void +__attribute__((noinline)) +test (unsigned long long x, unsigned long long y, + unsigned long long q, unsigned long long r) +{ + if ((x / y) != q || (x % y) != r) + abort (); +} + +int +main () +{ + test (7, 6, 1, 1); + test (255, 254, 1, 1); + test (256, 254, 1, 2); + test (256, 256, 1, 0); + test (254, 256, 0, 254); + test (254, 255, 0, 254); + test (254, 1, 254, 0); + test (255, 2, 127, 1); + test (1, 256, 0, 1); + test (0x80000000, 0x7fffffff, 1, 1); + test (0x7fffffff, 0x80000000, 0, 0x7fffffff); + test (0x80000000, 0x80000003, 0, 0x80000000); + test (0xfffffffd, 0xfffffffe, 0, 0xfffffffd); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-7.c new file mode 100644 index 000000000..4a68a75f2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-7.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +extern void abort (void); + +void +test (unsigned long long x, unsigned long long y, + unsigned long long q, unsigned long long r) +{ + if ((x / y) != q || (x % y) != r) + abort (); +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-times "divq" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-8.c new file mode 100644 index 000000000..bef496490 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/udivmod-8.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -m8bit-idiv" } */ + +extern void foo (unsigned long long, unsigned long long, + unsigned long long, unsigned long long, + unsigned long long, unsigned long long); + +void +bar (unsigned long long x, unsigned long long y) +{ + foo (0, 0, 0, 0, x / y, x % y); +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-times "divq" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/umod-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/umod-1.c new file mode 100644 index 000000000..54edf139d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/umod-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=atom" } */ + +unsigned char +foo (unsigned char x, unsigned char y) +{ + return x % y; +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-not "divw" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/umod-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/umod-2.c new file mode 100644 index 000000000..6fe738468 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/umod-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=atom" } */ + +extern unsigned char z; + +unsigned char +foo (unsigned char x, unsigned char y) +{ + z = x/y; + return x % y; +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-not "divw" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/umod-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/umod-3.c new file mode 100644 index 000000000..7123bc9f2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/umod-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=atom" } */ + +extern void abort (void); +extern void exit (int); + +unsigned char cx = 7; + +int +main () +{ + unsigned char cy; + + cy = cx / 6; if (cy != 1) abort (); + cy = cx % 6; if (cy != 1) abort (); + + exit(0); +} + +/* { dg-final { scan-assembler-times "divb" 1 } } */ +/* { dg-final { scan-assembler-not "divw" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/unordcmp-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/unordcmp-1.c new file mode 100644 index 000000000..49d4b8e07 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/unordcmp-1.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-final { scan-assembler "cmpunordss" } } */ +/* { dg-final { scan-assembler "cmpunordps" } } */ +/* { dg-final { scan-assembler "cmpunordsd" } } */ +/* { dg-final { scan-assembler "cmpunordpd" } } */ +/* { dg-final { scan-assembler-not "cmpordss" } } */ +/* { dg-final { scan-assembler-not "cmpordps" } } */ +/* { dg-final { scan-assembler-not "cmpordsd" } } */ +/* { dg-final { scan-assembler-not "cmpordpd" } } */ + +#include <emmintrin.h> + +__m128 +f1 (__m128 x, __m128 y) +{ + return _mm_cmpunord_ss (x, y); +} + +__m128 +f2 (__m128 x, __m128 y) +{ + return _mm_cmpunord_ps (x, y); +} + +__m128d +f3 (__m128d x, __m128d y) +{ + return _mm_cmpunord_sd (x, y); +} + +__m128d +f4 (__m128d x, __m128d y) +{ + return _mm_cmpunord_pd (x, y); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/unroll-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/unroll-1.c new file mode 100644 index 000000000..cc8132e20 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/unroll-1.c @@ -0,0 +1,18 @@ +/* PR optimization/8599 */ +/* { dg-do run } */ +/* { dg-require-effective-target ia32 } */ +/* { dg-options "-mtune=k6 -O2 -funroll-loops" } */ + +extern void exit (int); + +void *array[4]; + +int main () +{ + int i; + + for (i = 0; i < 4; i++) + array[i] = 0; + + exit (0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-1.c new file mode 100644 index 000000000..a2db4b9f7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-1.c @@ -0,0 +1,34 @@ +/* PR middle-end/36858 */ +/* { dg-do run } */ +/* { dg-options "-w" { target { ! { ia32 } } } } */ +/* { dg-options "-w" { target { llp64 } } } */ +/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" { target { ia32 } } } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" +#include <stdarg.h> +#include <emmintrin.h> + +int +__attribute__((noinline)) +test (int a, ...) +{ + return a; +} + +__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 }; + +int +__attribute__((noinline)) +foo (void) +{ + return test (1, n1); +} + +static void +__attribute__((noinline)) +sse2_test (void) +{ + if (foo () != 1) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-10.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-10.c new file mode 100644 index 000000000..053649877 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-10.c @@ -0,0 +1,112 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-mavx" } */ + +#include <stdarg.h> +#include <assert.h> + +#include "avx-check.h" + +struct m256d +{ + __m256d v; +}; + +__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 }; +struct m256d n2 = { { -93.83, 893.318, 3994.3, -39484.0 } }; +__m128i n3 = { 893, -3180 } ; +int n4 = 324; +double n5 = 103.3; +__m128i n6 = { -123, 2 }; +__m128d n7 = { -91.387, -8193.518 }; +struct m256d n8 = { { -123.3, 2.3, 3.4, -10.03 } }; +__m128 n9 = { -123.3, 2.3, 3.4, -10.03 }; +__m128i n10 = { 1233, -100 }; +int n11 = 407; +double n12 = 304.9; +__m128i n13 = { 233, -110 }; +__m256i n14 = { -1233, 23, 34, -1003 }; +__m128i n15 = { -393, -180 }; +__m128d n16 = { 73.0, 63.18 }; +__m256 n17 = { -183.3, -22.3, 13.9, -119.3, 483.1, 122.3, -33.4, -9.37 }; +__m128 n18 = { -183.3, 22.3, 13.4, -19.03 }; + +__m128 e1; +struct m256d e2; +__m128i e3; +int e4; +double e5; +__m128i e6; +__m128d e7; +struct m256d e8; +__m128 e9; +__m128i e10; +int e11; +double e12; +__m128i e13; +__m256i e14; +__m128i e15; +__m128d e16; +__m256 e17; +__m128 e18; + +static void +__attribute__((noinline)) +foo (va_list va_arglist) +{ + e4 = va_arg (va_arglist, int); + e5 = va_arg (va_arglist, double); + e6 = va_arg (va_arglist, __m128i); + e7 = va_arg (va_arglist, __m128d); + e8 = va_arg (va_arglist, struct m256d); + e9 = va_arg (va_arglist, __m128); + e10 = va_arg (va_arglist, __m128i); + e11 = va_arg (va_arglist, int); + e12 = va_arg (va_arglist, double); + e13 = va_arg (va_arglist, __m128i); + e14 = va_arg (va_arglist, __m256i); + e15 = va_arg (va_arglist, __m128i); + e16 = va_arg (va_arglist, __m128d); + e17 = va_arg (va_arglist, __m256); + e18 = va_arg (va_arglist, __m128); + va_end (va_arglist); +} + +static void +__attribute__((noinline)) +test (__m128 a1, struct m256d a2, __m128i a3, ...) +{ + va_list va_arglist; + + e1 = a1; + e2 = a2; + e3 = a3; + va_start (va_arglist, a3); + foo (va_arglist); + va_end (va_arglist); +} + +static void +avx_test (void) +{ + test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, + n13, n14, n15, n16, n17, n18); + assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0); + assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0); + assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0); + assert (n4 == e4); + assert (n5 == e5); + assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0); + assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0); + assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0); + assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0); + assert (__builtin_memcmp (&e10, &n10, sizeof (e10)) == 0); + assert (n11 == e11); + assert (n12 == e12); + assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0); + assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0); + assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0); + assert (__builtin_memcmp (&e16, &n16, sizeof (e16)) == 0); + assert (__builtin_memcmp (&e17, &n17, sizeof (e17)) == 0); + assert (__builtin_memcmp (&e18, &n18, sizeof (e18)) == 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-2.c new file mode 100644 index 000000000..bd5ad5446 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-2.c @@ -0,0 +1,42 @@ +/* PR middle-end/36859 */ +/* { dg-do run } */ +/* { dg-options "-w" { target { ! { ia32 } } } } */ +/* { dg-options "-w" { target { llp64 } } } */ +/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" { target { ia32 } } } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" +#include <stdarg.h> +#include <emmintrin.h> + +__m128 +__attribute__((noinline)) +test (int a, ...) +{ + __m128 x; + va_list va_arglist; + + va_start (va_arglist, a); + x = va_arg (va_arglist, __m128); + va_end (va_arglist); + return x; +} + +__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 }; + +int +__attribute__((noinline)) +foo (void) +{ + __m128 x = test (1, n1); + if (__builtin_memcmp (&x, &n1, sizeof (x)) != 0) + abort (); + return 0; +} + +static void +__attribute__((noinline)) +sse2_test (void) +{ + foo (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-3.c new file mode 100644 index 000000000..3bfc3f14c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-3.c @@ -0,0 +1,86 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include <stdarg.h> +#include <assert.h> + +#include "sse2-check.h" + +__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 }; +__m128d n2 = { -93.83, 893.318 }; +__m128i n3 = { 893, -3180 } ; +int n4 = 324; +double n5 = 103.3; +__m128i n6 = { -123, 2 }; +__m128d n7 = { -91.387, -8193.518 }; +__m128 n8 = { -123.3, 2.3, 3.4, -10.03 }; +__m128i n9 = { 1233, -100 }; +int n10 = 407; +double n11 = 304.9; +__m128i n12 = { 233, -110 }; +__m128i n13 = { -393, -180 }; +__m128d n14 = { 73.0, 63.18 }; +__m128 n15 = { -183.3, 22.3, 13.4, -19.03 }; + +__m128 e1; +__m128d e2; +__m128i e3; +int e4; +double e5; +__m128i e6; +__m128d e7; +__m128 e8; +__m128i e9; +int e10; +double e11; +__m128i e12; +__m128i e13; +__m128d e14; +__m128 e15; + +static void +__attribute__((noinline)) +test (__m128 a1, __m128d a2, __m128i a3, ...) +{ + va_list va_arglist; + + e1 = a1; + e2 = a2; + e3 = a3; + va_start (va_arglist, a3); + e4 = va_arg (va_arglist, int); + e5 = va_arg (va_arglist, double); + e6 = va_arg (va_arglist, __m128i); + e7 = va_arg (va_arglist, __m128d); + e8 = va_arg (va_arglist, __m128); + e9 = va_arg (va_arglist, __m128i); + e10 = va_arg (va_arglist, int); + e11 = va_arg (va_arglist, double); + e12 = va_arg (va_arglist, __m128i); + e13 = va_arg (va_arglist, __m128i); + e14 = va_arg (va_arglist, __m128d); + e15 = va_arg (va_arglist, __m128); + va_end (va_arglist); +} + +static void +sse2_test (void) +{ + test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15); + assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0); + assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0); + assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0); + assert (n4 == e4); + assert (n5 == e5); + assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0); + assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0); + assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0); + assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0); + assert (n10 == e10); + assert (n11 == e11); + assert (__builtin_memcmp (&e12, &n12, sizeof (e12)) == 0); + assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0); + assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0); + assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-4.c new file mode 100644 index 000000000..8034dcadb --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-4.c @@ -0,0 +1,93 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include <stdarg.h> +#include <assert.h> + +#include "sse2-check.h" + +__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 }; +__m128d n2 = { -93.83, 893.318 }; +__m128i n3 = { 893, -3180 } ; +int n4 = 324; +double n5 = 103.3; +__m128i n6 = { -123, 2 }; +__m128d n7 = { -91.387, -8193.518 }; +__m128 n8 = { -123.3, 2.3, 3.4, -10.03 }; +__m128i n9 = { 1233, -100 }; +int n10 = 407; +double n11 = 304.9; +__m128i n12 = { 233, -110 }; +__m128i n13 = { -393, -180 }; +__m128d n14 = { 73.0, 63.18 }; +__m128 n15 = { -183.3, 22.3, 13.4, -19.03 }; + +__m128 e1; +__m128d e2; +__m128i e3; +int e4; +double e5; +__m128i e6; +__m128d e7; +__m128 e8; +__m128i e9; +int e10; +double e11; +__m128i e12; +__m128i e13; +__m128d e14; +__m128 e15; + +static void +__attribute__((noinline)) +foo (va_list va_arglist) +{ + e4 = va_arg (va_arglist, int); + e5 = va_arg (va_arglist, double); + e6 = va_arg (va_arglist, __m128i); + e7 = va_arg (va_arglist, __m128d); + e8 = va_arg (va_arglist, __m128); + e9 = va_arg (va_arglist, __m128i); + e10 = va_arg (va_arglist, int); + e11 = va_arg (va_arglist, double); + e12 = va_arg (va_arglist, __m128i); + e13 = va_arg (va_arglist, __m128i); + e14 = va_arg (va_arglist, __m128d); + e15 = va_arg (va_arglist, __m128); +} + +static void +__attribute__((noinline)) +test (__m128 a1, __m128d a2, __m128i a3, ...) +{ + va_list va_arglist; + + e1 = a1; + e2 = a2; + e3 = a3; + va_start (va_arglist, a3); + foo (va_arglist); + va_end (va_arglist); +} + +static void +sse2_test (void) +{ + test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15); + assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0); + assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0); + assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0); + assert (n4 == e4); + assert (n5 == e5); + assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0); + assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0); + assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0); + assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0); + assert (n10 == e10); + assert (n11 == e11); + assert (__builtin_memcmp (&e12, &n12, sizeof (e12)) == 0); + assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0); + assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0); + assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-5.c new file mode 100644 index 000000000..03ff60cd7 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-5.c @@ -0,0 +1,99 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-mavx" } */ + +#include <stdarg.h> +#include <assert.h> + +#include "avx-check.h" + +__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 }; +__m256d n2 = { -93.83, 893.318, 3994.3, -39484.0 }; +__m128i n3 = { 893, -3180 } ; +int n4 = 324; +double n5 = 103.3; +__m128i n6 = { -123, 2 }; +__m128d n7 = { -91.387, -8193.518 }; +__m256d n8 = { -123.3, 2.3, 3.4, -10.03 }; +__m128 n9 = { -123.3, 2.3, 3.4, -10.03 }; +__m128i n10 = { 1233, -100 }; +int n11 = 407; +double n12 = 304.9; +__m128i n13 = { 233, -110 }; +__m256i n14 = { -1233, 23, 34, -1003 }; +__m128i n15 = { -393, -180 }; +__m128d n16 = { 73.0, 63.18 }; +__m256 n17 = { -183.3, -22.3, 13.9, -119.3, 483.1, 122.3, -33.4, -9.37 }; +__m128 n18 = { -183.3, 22.3, 13.4, -19.03 }; + +__m128 e1; +__m256d e2; +__m128i e3; +int e4; +double e5; +__m128i e6; +__m128d e7; +__m256d e8; +__m128 e9; +__m128i e10; +int e11; +double e12; +__m128i e13; +__m256i e14; +__m128i e15; +__m128d e16; +__m256 e17; +__m128 e18; + +static void +__attribute__((noinline)) +test (__m128 a1, __m256d a2, __m128i a3, ...) +{ + va_list va_arglist; + + e1 = a1; + e2 = a2; + e3 = a3; + va_start (va_arglist, a3); + e4 = va_arg (va_arglist, int); + e5 = va_arg (va_arglist, double); + e6 = va_arg (va_arglist, __m128i); + e7 = va_arg (va_arglist, __m128d); + e8 = va_arg (va_arglist, __m256d); + e9 = va_arg (va_arglist, __m128); + e10 = va_arg (va_arglist, __m128i); + e11 = va_arg (va_arglist, int); + e12 = va_arg (va_arglist, double); + e13 = va_arg (va_arglist, __m128i); + e14 = va_arg (va_arglist, __m256i); + e15 = va_arg (va_arglist, __m128i); + e16 = va_arg (va_arglist, __m128d); + e17 = va_arg (va_arglist, __m256); + e18 = va_arg (va_arglist, __m128); + va_end (va_arglist); +} + +static void +avx_test (void) +{ + test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, + n13, n14, n15, n16, n17, n18); + assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0); + assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0); + assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0); + assert (n4 == e4); + assert (n5 == e5); + assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0); + assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0); + assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0); + assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0); + assert (__builtin_memcmp (&e10, &n10, sizeof (e10)) == 0); + assert (n11 == e11); + assert (n12 == e12); + assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0); + assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0); + assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0); + assert (__builtin_memcmp (&e16, &n16, sizeof (e16)) == 0); + assert (__builtin_memcmp (&e17, &n17, sizeof (e17)) == 0); + assert (__builtin_memcmp (&e18, &n18, sizeof (e18)) == 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-6.c new file mode 100644 index 000000000..5c645c41d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-6.c @@ -0,0 +1,107 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-mavx" } */ + +#include <stdarg.h> +#include <assert.h> + +#include "avx-check.h" + +__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 }; +__m256d n2 = { -93.83, 893.318, 3994.3, -39484.0 }; +__m128i n3 = { 893, -3180 } ; +int n4 = 324; +double n5 = 103.3; +__m128i n6 = { -123, 2 }; +__m128d n7 = { -91.387, -8193.518 }; +__m256d n8 = { -123.3, 2.3, 3.4, -10.03 }; +__m128 n9 = { -123.3, 2.3, 3.4, -10.03 }; +__m128i n10 = { 1233, -100 }; +int n11 = 407; +double n12 = 304.9; +__m128i n13 = { 233, -110 }; +__m256i n14 = { -1233, 23, 34, -1003 }; +__m128i n15 = { -393, -180 }; +__m128d n16 = { 73.0, 63.18 }; +__m256 n17 = { -183.3, -22.3, 13.9, -119.3, 483.1, 122.3, -33.4, -9.37 }; +__m128 n18 = { -183.3, 22.3, 13.4, -19.03 }; + +__m128 e1; +__m256d e2; +__m128i e3; +int e4; +double e5; +__m128i e6; +__m128d e7; +__m256d e8; +__m128 e9; +__m128i e10; +int e11; +double e12; +__m128i e13; +__m256i e14; +__m128i e15; +__m128d e16; +__m256 e17; +__m128 e18; + +static void +__attribute__((noinline)) +foo (va_list va_arglist) +{ + e4 = va_arg (va_arglist, int); + e5 = va_arg (va_arglist, double); + e6 = va_arg (va_arglist, __m128i); + e7 = va_arg (va_arglist, __m128d); + e8 = va_arg (va_arglist, __m256d); + e9 = va_arg (va_arglist, __m128); + e10 = va_arg (va_arglist, __m128i); + e11 = va_arg (va_arglist, int); + e12 = va_arg (va_arglist, double); + e13 = va_arg (va_arglist, __m128i); + e14 = va_arg (va_arglist, __m256i); + e15 = va_arg (va_arglist, __m128i); + e16 = va_arg (va_arglist, __m128d); + e17 = va_arg (va_arglist, __m256); + e18 = va_arg (va_arglist, __m128); + va_end (va_arglist); +} + +static void +__attribute__((noinline)) +test (__m128 a1, __m256d a2, __m128i a3, ...) +{ + va_list va_arglist; + + e1 = a1; + e2 = a2; + e3 = a3; + va_start (va_arglist, a3); + foo (va_arglist); + va_end (va_arglist); +} + +static void +avx_test (void) +{ + test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, + n13, n14, n15, n16, n17, n18); + assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0); + assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0); + assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0); + assert (n4 == e4); + assert (n5 == e5); + assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0); + assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0); + assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0); + assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0); + assert (__builtin_memcmp (&e10, &n10, sizeof (e10)) == 0); + assert (n11 == e11); + assert (n12 == e12); + assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0); + assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0); + assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0); + assert (__builtin_memcmp (&e16, &n16, sizeof (e16)) == 0); + assert (__builtin_memcmp (&e17, &n17, sizeof (e17)) == 0); + assert (__builtin_memcmp (&e18, &n18, sizeof (e18)) == 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-7.c new file mode 100644 index 000000000..0f10d6784 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-7.c @@ -0,0 +1,91 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include <stdarg.h> +#include <assert.h> + +#include "sse2-check.h" + +struct m128 +{ + __m128 v; +}; + +struct m128 n1 = { { -283.3, -23.3, 213.4, 1119.03 } }; +__m128d n2 = { -93.83, 893.318 }; +__m128i n3 = { 893, -3180 } ; +int n4 = 324; +double n5 = 103.3; +__m128i n6 = { -123, 2 }; +__m128d n7 = { -91.387, -8193.518 }; +struct m128 n8 = { { -123.3, 2.3, 3.4, -10.03 } }; +__m128i n9 = { 1233, -100 }; +int n10 = 407; +double n11 = 304.9; +__m128i n12 = { 233, -110 }; +__m128i n13 = { -393, -180 }; +__m128d n14 = { 73.0, 63.18 }; +struct m128 n15 = { { -183.3, 22.3, 13.4, -19.03 } }; + +struct m128 e1; +__m128d e2; +__m128i e3; +int e4; +double e5; +__m128i e6; +__m128d e7; +struct m128 e8; +__m128i e9; +int e10; +double e11; +__m128i e12; +__m128i e13; +__m128d e14; +struct m128 e15; + +static void +__attribute__((noinline)) +test (struct m128 a1, __m128d a2, __m128i a3, ...) +{ + va_list va_arglist; + + e1 = a1; + e2 = a2; + e3 = a3; + va_start (va_arglist, a3); + e4 = va_arg (va_arglist, int); + e5 = va_arg (va_arglist, double); + e6 = va_arg (va_arglist, __m128i); + e7 = va_arg (va_arglist, __m128d); + e8 = va_arg (va_arglist, struct m128); + e9 = va_arg (va_arglist, __m128i); + e10 = va_arg (va_arglist, int); + e11 = va_arg (va_arglist, double); + e12 = va_arg (va_arglist, __m128i); + e13 = va_arg (va_arglist, __m128i); + e14 = va_arg (va_arglist, __m128d); + e15 = va_arg (va_arglist, struct m128); + va_end (va_arglist); +} + +static void +sse2_test (void) +{ + test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15); + assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0); + assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0); + assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0); + assert (n4 == e4); + assert (n5 == e5); + assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0); + assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0); + assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0); + assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0); + assert (n10 == e10); + assert (n11 == e11); + assert (__builtin_memcmp (&e12, &n12, sizeof (e12)) == 0); + assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0); + assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0); + assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-8.c new file mode 100644 index 000000000..5c5a0b4a1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-8.c @@ -0,0 +1,98 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include <stdarg.h> +#include <assert.h> + +#include "sse2-check.h" + +struct m128 +{ + __m128 v; +}; + +struct m128 n1 = { { -283.3, -23.3, 213.4, 1119.03 } }; +__m128d n2 = { -93.83, 893.318 }; +__m128i n3 = { 893, -3180 } ; +int n4 = 324; +double n5 = 103.3; +__m128i n6 = { -123, 2 }; +__m128d n7 = { -91.387, -8193.518 }; +struct m128 n8 = { { -123.3, 2.3, 3.4, -10.03 } }; +__m128i n9 = { 1233, -100 }; +int n10 = 407; +double n11 = 304.9; +__m128i n12 = { 233, -110 }; +__m128i n13 = { -393, -180 }; +__m128d n14 = { 73.0, 63.18 }; +struct m128 n15 = { { -183.3, 22.3, 13.4, -19.03 } }; + +struct m128 e1; +__m128d e2; +__m128i e3; +int e4; +double e5; +__m128i e6; +__m128d e7; +struct m128 e8; +__m128i e9; +int e10; +double e11; +__m128i e12; +__m128i e13; +__m128d e14; +struct m128 e15; + +static void +__attribute__((noinline)) +foo (va_list va_arglist) +{ + e4 = va_arg (va_arglist, int); + e5 = va_arg (va_arglist, double); + e6 = va_arg (va_arglist, __m128i); + e7 = va_arg (va_arglist, __m128d); + e8 = va_arg (va_arglist, struct m128); + e9 = va_arg (va_arglist, __m128i); + e10 = va_arg (va_arglist, int); + e11 = va_arg (va_arglist, double); + e12 = va_arg (va_arglist, __m128i); + e13 = va_arg (va_arglist, __m128i); + e14 = va_arg (va_arglist, __m128d); + e15 = va_arg (va_arglist, struct m128); +} + +static void +__attribute__((noinline)) +test (struct m128 a1, __m128d a2, __m128i a3, ...) +{ + va_list va_arglist; + + e1 = a1; + e2 = a2; + e3 = a3; + va_start (va_arglist, a3); + foo (va_arglist); + va_end (va_arglist); +} + +static void +sse2_test (void) +{ + test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15); + assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0); + assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0); + assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0); + assert (n4 == e4); + assert (n5 == e5); + assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0); + assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0); + assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0); + assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0); + assert (n10 == e10); + assert (n11 == e11); + assert (__builtin_memcmp (&e12, &n12, sizeof (e12)) == 0); + assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0); + assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0); + assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-9.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-9.c new file mode 100644 index 000000000..581abb178 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vararg-9.c @@ -0,0 +1,104 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx } */ +/* { dg-options "-mavx" } */ + +#include <stdarg.h> +#include <assert.h> + +#include "avx-check.h" + +struct m256d +{ + __m256d v; +}; + +__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 }; +struct m256d n2 = { { -93.83, 893.318, 3994.3, -39484.0 } }; +__m128i n3 = { 893, -3180 } ; +int n4 = 324; +double n5 = 103.3; +__m128i n6 = { -123, 2 }; +__m128d n7 = { -91.387, -8193.518 }; +struct m256d n8 = { { -123.3, 2.3, 3.4, -10.03 } }; +__m128 n9 = { -123.3, 2.3, 3.4, -10.03 }; +__m128i n10 = { 1233, -100 }; +int n11 = 407; +double n12 = 304.9; +__m128i n13 = { 233, -110 }; +__m256i n14 = { -1233, 23, 34, -1003 }; +__m128i n15 = { -393, -180 }; +__m128d n16 = { 73.0, 63.18 }; +__m256 n17 = { -183.3, -22.3, 13.9, -119.3, 483.1, 122.3, -33.4, -9.37 }; +__m128 n18 = { -183.3, 22.3, 13.4, -19.03 }; + +__m128 e1; +struct m256d e2; +__m128i e3; +int e4; +double e5; +__m128i e6; +__m128d e7; +struct m256d e8; +__m128 e9; +__m128i e10; +int e11; +double e12; +__m128i e13; +__m256i e14; +__m128i e15; +__m128d e16; +__m256 e17; +__m128 e18; + +static void +__attribute__((noinline)) +test (__m128 a1, struct m256d a2, __m128i a3, ...) +{ + va_list va_arglist; + + e1 = a1; + e2 = a2; + e3 = a3; + va_start (va_arglist, a3); + e4 = va_arg (va_arglist, int); + e5 = va_arg (va_arglist, double); + e6 = va_arg (va_arglist, __m128i); + e7 = va_arg (va_arglist, __m128d); + e8 = va_arg (va_arglist, struct m256d); + e9 = va_arg (va_arglist, __m128); + e10 = va_arg (va_arglist, __m128i); + e11 = va_arg (va_arglist, int); + e12 = va_arg (va_arglist, double); + e13 = va_arg (va_arglist, __m128i); + e14 = va_arg (va_arglist, __m256i); + e15 = va_arg (va_arglist, __m128i); + e16 = va_arg (va_arglist, __m128d); + e17 = va_arg (va_arglist, __m256); + e18 = va_arg (va_arglist, __m128); + va_end (va_arglist); +} + +static void +avx_test (void) +{ + test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, + n13, n14, n15, n16, n17, n18); + assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0); + assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0); + assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0); + assert (n4 == e4); + assert (n5 == e5); + assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0); + assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0); + assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0); + assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0); + assert (__builtin_memcmp (&e10, &n10, sizeof (e10)) == 0); + assert (n11 == e11); + assert (n12 == e12); + assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0); + assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0); + assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0); + assert (__builtin_memcmp (&e16, &n16, sizeof (e16)) == 0); + assert (__builtin_memcmp (&e17, &n17, sizeof (e17)) == 0); + assert (__builtin_memcmp (&e18, &n18, sizeof (e18)) == 0); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtph2ps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtph2ps-1.c new file mode 100644 index 000000000..3b46671f0 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtph2ps-1.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-require-effective-target f16c } */ +/* { dg-options "-O2 -mf16c" } */ + +#include "f16c-check.h" + +static void +f16c_test (void) +{ + union128i_w val; + union128 res; + float exp[4]; + + exp[0] = 1; + exp[1] = -2; + exp[2] = -1; + exp[3] = 2; + + val.a[0] = 0x3c00; + val.a[1] = 0xc000; + val.a[2] = 0xbc00; + val.a[3] = 0x4000; + + res.x = _mm_cvtph_ps (val.x); + + if (check_union128 (res, exp)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtph2ps-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtph2ps-2.c new file mode 100644 index 000000000..1523deaa1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtph2ps-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-require-effective-target f16c } */ +/* { dg-options "-O2 -mf16c" } */ + +#include "f16c-check.h" + +static void +f16c_test (void) +{ + union256 res; + union128i_w val; + float exp[8]; + + exp[0] = 1; + exp[1] = 2; + exp[2] = 4; + exp[3] = 8; + exp[4] = -1; + exp[5] = -2; + exp[6] = -4; + exp[7] = -8; + + val.a[0] = 0x3c00; + val.a[1] = 0x4000; + val.a[2] = 0x4400; + val.a[3] = 0x4800; + val.a[4] = 0xbc00; + val.a[5] = 0xc000; + val.a[6] = 0xc400; + val.a[7] = 0xc800; + + res.x = _mm256_cvtph_ps (val.x); + + if (check_union256 (res, exp)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtph2ps-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtph2ps-3.c new file mode 100644 index 000000000..49b61f678 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtph2ps-3.c @@ -0,0 +1,18 @@ +/* { dg-do run } */ +/* { dg-require-effective-target f16c } */ +/* { dg-options "-O2 -mf16c" } */ + +#include "f16c-check.h" + +static void +f16c_test (void) +{ + unsigned short val = 0xc000; + float exp = -2; + float res; + + res = _cvtsh_ss (val); + + if (res != exp) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtps2ph-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtps2ph-1.c new file mode 100644 index 000000000..c114c98ad --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtps2ph-1.c @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-require-effective-target f16c } */ +/* { dg-options "-O2 -mf16c" } */ + +#include "f16c-check.h" + +static void +f16c_test (void) +{ + union128 val; + union128i_w res; + short exp[8]; + + val.a[0] = 1; + val.a[1] = -2; + val.a[2] = -1; + val.a[3] = 2; + + exp[0] = 0x3c00; + exp[1] = 0xc000; + exp[2] = 0xbc00; + exp[3] = 0x4000; + exp[4] = 0; + exp[5] = 0; + exp[6] = 0; + exp[7] = 0; + + res.x = _mm_cvtps_ph (val.x, 0); + + if (check_union128i_w (res, exp)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtps2ph-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtps2ph-2.c new file mode 100644 index 000000000..57436ae86 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtps2ph-2.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-require-effective-target f16c } */ +/* { dg-options "-O2 -mf16c" } */ + +#include "f16c-check.h" + +static void +f16c_test (void) +{ + union256 val; + union128i_w res; + short exp[8]; + + val.a[0] = 1; + val.a[1] = 2; + val.a[2] = 4; + val.a[3] = 8; + val.a[4] = -1; + val.a[5] = -2; + val.a[6] = -4; + val.a[7] = -8; + + exp[0] = 0x3c00; + exp[1] = 0x4000; + exp[2] = 0x4400; + exp[3] = 0x4800; + exp[4] = 0xbc00; + exp[5] = 0xc000; + exp[6] = 0xc400; + exp[7] = 0xc800; + + res.x = _mm256_cvtps_ph (val.x, 0); + + if (check_union128i_w (res, exp)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtps2ph-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtps2ph-3.c new file mode 100644 index 000000000..3b7cb5c5c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vcvtps2ph-3.c @@ -0,0 +1,18 @@ +/* { dg-do run } */ +/* { dg-require-effective-target f16c } */ +/* { dg-options "-O2 -mf16c" } */ + +#include "f16c-check.h" + +static void +f16c_test (void) +{ + float val = -2; + unsigned short exp = 0xc000; + unsigned short res; + + res = _cvtss_sh (val, 0); + + if (res != exp) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-1.c new file mode 100644 index 000000000..17e295985 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8 -msse2 -mno-sse4" } */ + +#define vector __attribute__((vector_size(16))) + +float a; +vector float f1(void) { return (vector float){ a, 0.0, 0.0, 0.0}; } +vector float f2(void) { return (vector float){ 0.0, a, 0.0, 0.0}; } +vector float f3(void) { return (vector float){ 0.0, 0.0, a, 0.0}; } +vector float f4(void) { return (vector float){ 0.0, 0.0, 0.0, a}; } +/* { dg-final { scan-assembler-not "movaps" } } */ +/* { dg-final { scan-assembler-not "xor" } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-2.c new file mode 100644 index 000000000..d7b910062 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8 -msse2 -mno-sse4" } */ + +#define vector __attribute__((vector_size(16))) + +int a; +vector int f1(void) { return (vector int){ a, 0, 0, 0}; } +vector int f2(void) { return (vector int){ 0, a, 0, 0}; } +vector int f3(void) { return (vector int){ 0, 0, a, 0}; } +vector int f4(void) { return (vector int){ 0, 0, 0, a}; } +/* { dg-final { scan-assembler-not "movaps" } } */ +/* { dg-final { scan-assembler-not "xor" } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-3.c new file mode 100644 index 000000000..062fb1ed1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +#define vector __attribute__((vector_size(16))) + +char a; +vector char f(void) { return (vector char){ a, a, a, a, a, a, a, a, + a, a, a, a, a, a, a, a }; } +/* { dg-final { scan-assembler-not "sall" } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-4.c new file mode 100644 index 000000000..2dfa29c49 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +#define vector __attribute__((vector_size(16))) + +short a; +vector short f(void) { return (vector short){ a, a, a, a, a, a, a, a }; } +/* { dg-final { scan-assembler-not "sall" } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-5.c new file mode 100644 index 000000000..dcf8b9206 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-5.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +#define vector __attribute__((vector_size(16))) + +float a, b; +vector float f1(void) { return (vector float){ 0.0, 0.0, a, a}; } +vector float f2(void) { return (vector float){ a, a, 0.0, 0.0}; } +vector float f3(void) { return (vector float){ 0.0, a, 0.0, a}; } +vector float f4(void) { return (vector float){ a, 0.0, a, 0.0}; } + +vector float f5(void) { return (vector float){ 1.0, 1.0, a, a}; } +vector float f6(void) { return (vector float){ a, a, 1.0, 1.0}; } +vector float f7(void) { return (vector float){ 1.0, a, 1.0, a}; } +vector float f8(void) { return (vector float){ a, 1.0, a, 1.0}; } + +vector float fa(void) { return (vector float){ 1.0, 1.0, 0.0, 0.0}; } +vector float fb(void) { return (vector float){ 1.0, 0.0, 1.0, 0.0}; } +vector float fc(void) { return (vector float){ 0.0, 1.0, 0.0, 1.0}; } + +vector float fA(void) { return (vector float){ a, a, b, b}; } +vector float fB(void) { return (vector float){ a, b, a, b}; } +vector float fC(void) { return (vector float){ a, a, a, a}; } + +/* { dg-final { scan-assembler-not "%mm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-6.c new file mode 100644 index 000000000..6817922d2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vecinit-6.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +#define vector __attribute__((vector_size(16))) + +int a, b; +vector int f1(void) { return (vector int){ 0, 0, a, a}; } +vector int f2(void) { return (vector int){ a, a, 0, 0}; } +vector int f3(void) { return (vector int){ 0, a, 0, a}; } +vector int f4(void) { return (vector int){ a, 0, a, 0}; } + +vector int f5(void) { return (vector int){ 1, 1, a, a}; } +vector int f6(void) { return (vector int){ a, a, 1, 1}; } +vector int f7(void) { return (vector int){ 1, a, 1, a}; } +vector int f8(void) { return (vector int){ a, 1, a, 1}; } + +vector int fa(void) { return (vector int){ 1, 1, 0, 0}; } +vector int fb(void) { return (vector int){ 1, 0, 1, 0}; } +vector int fc(void) { return (vector int){ 0, 1, 0, 1}; } + +vector int fA(void) { return (vector int){ a, a, b, b}; } +vector int fB(void) { return (vector int){ a, b, a, b}; } +vector int fC(void) { return (vector int){ a, a, a, a}; } + +/* { dg-final { scan-assembler-not "%mm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-args.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-args.c new file mode 100644 index 000000000..fc458896e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-args.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-w -Wno-psabi" } */ + +/* SSE1 and SSE2 modes. */ +typedef unsigned char V16QImode __attribute__((vector_size(16))); +typedef unsigned short V8HImode __attribute__((vector_size(16))); +typedef unsigned int V4SImode __attribute__((vector_size(16))); +typedef unsigned long long V2DImode __attribute__((vector_size(16))); +typedef float V4SFmode __attribute__((vector_size(16))); +typedef double V2DFmode __attribute__((vector_size(16))); + +/* MMX and 3DNOW modes. */ +typedef unsigned char V8QImode __attribute__((vector_size(8))); +typedef unsigned short V4HImode __attribute__((vector_size(8))); +typedef unsigned int V2SImode __attribute__((vector_size(8))); +typedef float V2SFmode __attribute__((vector_size(8))); + +/* Test argument loading and unloading of each. */ +#define TEST(TYPE) \ +extern TYPE data_##TYPE; \ +void r_##TYPE (TYPE x) { data_##TYPE = x; } \ +void s_##TYPE (void) { r_##TYPE (data_##TYPE); } + +TEST(V16QImode) +TEST(V8HImode) +TEST(V4SImode) +TEST(V2DImode) +TEST(V4SFmode) +TEST(V2DFmode) +TEST(V8QImode) +TEST(V4HImode) +TEST(V2SImode) +TEST(V2SFmode) diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-double-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-double-1.c new file mode 100644 index 000000000..d96d6399c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-double-1.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=core2" } } */ +/* { dg-options "-O2 -ftree-vectorize -mfpmath=sse -march=core2 -fdump-tree-vect-stats" } */ + +extern void abort (void); + +#ifndef STATIC +#define STATIC +#endif + +#define N 16 + +double cb[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45}; +double ca[N]; + +STATIC void +__attribute__ ((noinline)) +sse2_test (void) +{ + int i; + + for (i = 0; i < N; i++) + { + ca[i] = cb[i]; + } + + /* check results: */ + for (i = 0; i < N; i++) + { + if (ca[i] != cb[i]) + abort (); + } +} + +/* { dg-final { scan-tree-dump-times "Vectorized loops: 1" 1 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-double-1a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-double-1a.c new file mode 100644 index 000000000..a62c93903 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-double-1a.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -ftree-vectorize -mfpmath=sse -msse2 -mtune=core2" } */ + +#define STATIC static + +#include "vect-double-1.c" +#include "sse2-check.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-double-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-double-2.c new file mode 100644 index 000000000..a76dcb46c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-double-2.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -mfpmath=sse -msse2 -mtune=atom -fdump-tree-vect-stats" } */ + +extern void abort (void); + +#ifndef STATIC +#define STATIC +#endif + +#define N 16 + +double cb[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45}; +double ca[N]; + +STATIC void +__attribute__ ((noinline)) +sse2_test (void) +{ + int i; + + for (i = 0; i < N; i++) + { + ca[i] = cb[i]; + } + + /* check results: */ + for (i = 0; i < N; i++) + { + if (ca[i] != cb[i]) + abort (); + } +} + +/* { dg-final { scan-tree-dump-not "vectorized 1 loops" "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-double-2a.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-double-2a.c new file mode 100644 index 000000000..94f806275 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-double-2a.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse2 } */ +/* { dg-options "-O2 -ftree-vectorize -mfpmath=sse -msse2 -mtune=atom" } */ + +#define STATIC static + +#include "vect-double-2.c" +#include "sse2-check.h" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-rebuild.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-rebuild.c new file mode 100644 index 000000000..570967f6b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-rebuild.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mavx -fno-tree-forwprop" } */ + +typedef double v2df __attribute__ ((__vector_size__ (16))); +typedef double v4df __attribute__ ((__vector_size__ (32))); + +v2df f1 (v2df x) +{ + v2df xx = { x[0], x[1] }; + return xx; +} + +v4df f2 (v4df x) +{ + v4df xx = { x[0], x[1], x[2], x[3] }; + return xx; +} + +v2df g (v2df x) +{ + v2df xx = { x[1], x[0] }; + return xx; +} + +v2df h (v4df x) +{ + v2df xx = { x[2], x[3] }; + return xx; +} + +/* { dg-final { scan-assembler-not "unpck" } } */ +/* { dg-final { scan-assembler-times "\tv?permilpd\[ \t\]" 1 } } */ +/* { dg-final { scan-assembler-times "\tv?extractf128\[ \t\]" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-sizes-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-sizes-1.c new file mode 100644 index 000000000..3c18f3bd6 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect-sizes-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -ffast-math -mavx -mtune=generic" } */ + +double a[1024]; + +void dependence_distance_4 (void) +{ + int i; + for (i = 0; i < 1020; ++i) + a[i + 4] = a[i] + a[i + 4]; +} + +/* { dg-final { scan-assembler "vmovapd\[ \\t\]+\[^\n\]*%ymm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect8-ret.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect8-ret.c new file mode 100644 index 000000000..513369d0f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vect8-ret.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-mmmx" { target i?86-*-solaris2.9 *-*-vxworks* } } */ +/* { dg-options "-mmmx -mvect8-ret-in-mem" } */ + +#include <mmintrin.h> + +__m64 +vecret (__m64 vect) +{ + return vect; +} + +/* { dg-final { scan-assembler-times "movq" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize1.c new file mode 100644 index 000000000..f673e44c9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize1.c @@ -0,0 +1,20 @@ +/* PR middle-end/28915 */ +/* { dg-options "-msse -O2 -ftree-vectorize -fdump-tree-vect" } */ +/* { dg-require-effective-target sse } */ + +extern char lanip[3][40]; +typedef struct +{ + char *t[8]; +}tx_typ; + +int set_names (void) +{ + static tx_typ tt1; + int ln; + for (ln = 0; ln < 8; ln++) + tt1.t[ln] = lanip[1]; +} + +/* { dg-final { scan-tree-dump "vect_cst" "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize2.c new file mode 100644 index 000000000..427e2d401 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize2.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2 -mfpmath=sse -mtune=generic" } */ + +double a[256]; +int b[256]; +unsigned short c[256]; + +extern long lrint (double); + +void foo(void) +{ + int i; + + for (i=0; i<256; ++i) + b[i] = lrint (a[i]); +} + +void bar(void) +{ + int i; + + for (i=0; i<256; ++i) + { + b[i] = lrint (a[i]); + c[i] += c[i]; + } +} + +/* { dg-final { scan-assembler "cvtpd2dq" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize3.c new file mode 100644 index 000000000..2947acbaf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize3.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2 -mfpmath=sse" } */ + +float a[256]; +int b[256]; +unsigned short c[256]; + +extern long lrintf (float); + +void foo(void) +{ + int i; + + for (i=0; i<256; ++i) + b[i] = lrintf (a[i]); +} + +void bar(void) +{ + int i; + + for (i=0; i<256; ++i) + { + b[i] = lrintf (a[i]); + c[i] += c[i]; + } +} + +/* { dg-final { scan-assembler "cvtps2dq" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize4-avx.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize4-avx.c new file mode 100644 index 000000000..33e991893 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize4-avx.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx -mtune=generic" } */ + + +extern double sqrt (double __x); +calc_freq (int *dest) +{ + float tmp_out[257]; + int i; + for (i = 0; i < 256; i++) + dest[i] = sqrt (tmp_out[i]); +} + +/* { dg-final { scan-assembler "vsqrtpd\[ \\t\]+\[^\n\]*%ymm" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize4.c new file mode 100644 index 000000000..557d0a26e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize4.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2 -mtune=generic --param ggc-min-expand=0 --param ggc-min-heapsize=0" } */ +/* This test, tests two thing, we vectorize square root and also we don't crash due to a GC issue. */ + + +extern double sqrt (double __x); +calc_freq (int *dest) +{ + float tmp_out[257]; + int i; + for (i = 0; i < 256; i++) + dest[i] = sqrt (tmp_out[i]); +} + +/* { dg-final { scan-assembler "sqrtpd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize5.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize5.c new file mode 100644 index 000000000..2065e5d15 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize5.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -ftree-vectorize -mveclibabi=acml -ffast-math -mtune=generic" } */ + +double x[256]; + +extern double sin(double); + +void foo(void) +{ + int i; + + for (i=0; i<256; ++i) + x[i] = sin(x[i]); +} + +/* { dg-final { scan-assembler "__vrd2_sin" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize6.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize6.c new file mode 100644 index 000000000..d299a1551 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize6.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -ftree-vectorize -mveclibabi=svml -ffast-math -mtune=generic" } */ + +double x[256]; + +extern double sin(double); + +void foo(void) +{ + int i; + + for (i=0; i<256; ++i) + x[i] = sin(x[i]); +} + +/* { dg-final { scan-assembler "vmldSin2" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize7.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize7.c new file mode 100644 index 000000000..10b7ba278 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize7.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -msse2" } */ + +unsigned int a[256]; +float b[256]; + +void foo(void) +{ + int i; + + for (i=0; i<256; ++i) + b[i] = a[i]; +} + +/* { dg-final { scan-assembler "cvtdq2ps" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize8.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize8.c new file mode 100644 index 000000000..a194bb088 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vectorize8.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -msse2 -mtune=generic" } */ + +unsigned int a[256]; +double b[256]; + +void foo(void) +{ + int i; + + for (i=0; i<256; ++i) + b[i] = a[i]; +} + +/* { dg-final { scan-assembler "cvtdq2pd" } } */ + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/volatile-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/volatile-1.c new file mode 100644 index 000000000..714314cee --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/volatile-1.c @@ -0,0 +1,14 @@ +/* PR optimization/11381 */ +/* Originator: <tobias@ringstrom.mine.nu> */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +/* Verify that the comparison is not optimized away. */ + +void foo(volatile unsigned int *vaddr) +{ + while (*vaddr != *vaddr) + ; +} + +/* { dg-final { scan-assembler "cmp" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/volatile-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/volatile-2.c new file mode 100644 index 000000000..f4e6fb124 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/volatile-2.c @@ -0,0 +1,93 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target nonpic } */ +/* { dg-options "-O2" } */ + +/* Check volatiles are written, read or not re-read consistently */ + + +/* simple assignments */ + +extern int volatile obj_0; +void test_0 (int data) +{ + /* should not reread obj */ + /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_0(\\(%rip\\))?" } } */ + /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_0(\\(%rip\\))?," } } */ + obj_0 = data; +} + +extern int volatile obj_1; +int test_1 (int data) +{ + /* should not reread obj */ + /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_1(\\(%rip\\))?" } } */ + /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_1(\\(%rip\\))?," } } */ + return obj_1 = data; +} + +extern int volatile obj_2; +int test_2 (void) +{ + /* should not reread obj */ + /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_2(\\(%rip\\))?" } } */ + /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_2(\\(%rip\\))?," } } */ + return obj_2 = 0; +} + + +/* Assignments in compound exprs */ + +extern int volatile obj_3; +int test_3 (int data) +{ + /* should not reread obj */ + /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_3(\\(%rip\\))?" } } */ + /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_3(\\(%rip\\))?," } } */ + return (obj_3 = data, 0); +} + +extern int volatile obj_4; +int test_4 (void) +{ + /* should not reread obj */ + /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_4(\\(%rip\\))?" } } */ + /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_4(\\(%rip\\))?," } } */ + return (obj_4 = 0, 0); +} +extern int volatile obj_5; +int test_5 (void) +{ + /* should reread obj */ + /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_5(\\(%rip\\))?" } } */ + /* { dg-final { scan-assembler "movl\[ \t\]_?obj_5(\\(%rip\\))?," } } */ + return (obj_5 = 0, obj_5); +} + +/* Assignments in conditional exprs */ + +extern int volatile obj_6; +void test_6 (int data, int cond) +{ + /* should not reread obj */ + /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_6(\\(%rip\\))?" } } */ + /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_6(\\(%rip\\))?," } } */ + cond ? obj_6 = data : 0; +} + +extern int volatile obj_7; +int test_7 (int data, int cond) +{ + /* should not reread obj */ + /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_7(\\(%rip\\))?" } } */ + /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_7(\\(%rip\\))?," } } */ + return cond ? obj_7 = data : 0; +} + +extern int volatile obj_8; +int test_8 (int cond) +{ + /* should not reread obj */ + /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_8(\\(%rip\\))?" } } */ + /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_8(\\(%rip\\))?," } } */ + return cond ? obj_8 = 0 : 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c new file mode 100644 index 000000000..f11a8aff5 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fstrict-volatile-bitfields" } */ + +typedef struct { + char a:1; + char b:7; + int c; +} BitStruct; + +volatile BitStruct bits; + +int foo () +{ + return bits.b; +} + +/* { dg-final { scan-assembler "mov(b|zbl).*bits" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c new file mode 100644 index 000000000..302625a19 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-strict-volatile-bitfields" } */ + +typedef struct { + char a:1; + char b:7; + int c; +} BitStruct; + +volatile BitStruct bits; + +int foo () +{ + return bits.b; +} + +/* { dg-final { scan-assembler "movl.*bits" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-2-2.inc b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-2-2.inc new file mode 100644 index 000000000..ef66f6808 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-2-2.inc @@ -0,0 +1,27 @@ +/* This file auto-generated with ./vperm.pl 2 2. */ + +void check0(void) +{ + TEST (0, 0) + TEST (1, 0) + TEST (2, 0) + TEST (3, 0) + TEST (0, 1) + TEST (1, 1) + TEST (2, 1) + TEST (3, 1) + TEST (0, 2) + TEST (1, 2) + TEST (2, 2) + TEST (3, 2) + TEST (0, 3) + TEST (1, 3) + TEST (2, 3) + TEST (3, 3) +} + +void check(void) +{ + check0 (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-4-1.inc b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-4-1.inc new file mode 100644 index 000000000..c04f1856f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-4-1.inc @@ -0,0 +1,272 @@ +/* This file auto-generated with ./vperm.pl 4 1. */ + +void check0(void) +{ + TEST (0, 0, 0, 0) + TEST (1, 0, 0, 0) + TEST (2, 0, 0, 0) + TEST (3, 0, 0, 0) + TEST (0, 1, 0, 0) + TEST (1, 1, 0, 0) + TEST (2, 1, 0, 0) + TEST (3, 1, 0, 0) + TEST (0, 2, 0, 0) + TEST (1, 2, 0, 0) + TEST (2, 2, 0, 0) + TEST (3, 2, 0, 0) + TEST (0, 3, 0, 0) + TEST (1, 3, 0, 0) + TEST (2, 3, 0, 0) + TEST (3, 3, 0, 0) + TEST (0, 0, 1, 0) + TEST (1, 0, 1, 0) + TEST (2, 0, 1, 0) + TEST (3, 0, 1, 0) + TEST (0, 1, 1, 0) + TEST (1, 1, 1, 0) + TEST (2, 1, 1, 0) + TEST (3, 1, 1, 0) + TEST (0, 2, 1, 0) + TEST (1, 2, 1, 0) + TEST (2, 2, 1, 0) + TEST (3, 2, 1, 0) + TEST (0, 3, 1, 0) + TEST (1, 3, 1, 0) + TEST (2, 3, 1, 0) + TEST (3, 3, 1, 0) + TEST (0, 0, 2, 0) + TEST (1, 0, 2, 0) + TEST (2, 0, 2, 0) + TEST (3, 0, 2, 0) + TEST (0, 1, 2, 0) + TEST (1, 1, 2, 0) + TEST (2, 1, 2, 0) + TEST (3, 1, 2, 0) + TEST (0, 2, 2, 0) + TEST (1, 2, 2, 0) + TEST (2, 2, 2, 0) + TEST (3, 2, 2, 0) + TEST (0, 3, 2, 0) + TEST (1, 3, 2, 0) + TEST (2, 3, 2, 0) + TEST (3, 3, 2, 0) + TEST (0, 0, 3, 0) + TEST (1, 0, 3, 0) + TEST (2, 0, 3, 0) + TEST (3, 0, 3, 0) + TEST (0, 1, 3, 0) + TEST (1, 1, 3, 0) + TEST (2, 1, 3, 0) + TEST (3, 1, 3, 0) + TEST (0, 2, 3, 0) + TEST (1, 2, 3, 0) + TEST (2, 2, 3, 0) + TEST (3, 2, 3, 0) + TEST (0, 3, 3, 0) + TEST (1, 3, 3, 0) + TEST (2, 3, 3, 0) + TEST (3, 3, 3, 0) + TEST (0, 0, 0, 1) + TEST (1, 0, 0, 1) + TEST (2, 0, 0, 1) + TEST (3, 0, 0, 1) + TEST (0, 1, 0, 1) + TEST (1, 1, 0, 1) + TEST (2, 1, 0, 1) + TEST (3, 1, 0, 1) + TEST (0, 2, 0, 1) + TEST (1, 2, 0, 1) + TEST (2, 2, 0, 1) + TEST (3, 2, 0, 1) + TEST (0, 3, 0, 1) + TEST (1, 3, 0, 1) + TEST (2, 3, 0, 1) + TEST (3, 3, 0, 1) + TEST (0, 0, 1, 1) + TEST (1, 0, 1, 1) + TEST (2, 0, 1, 1) + TEST (3, 0, 1, 1) + TEST (0, 1, 1, 1) + TEST (1, 1, 1, 1) + TEST (2, 1, 1, 1) + TEST (3, 1, 1, 1) + TEST (0, 2, 1, 1) + TEST (1, 2, 1, 1) + TEST (2, 2, 1, 1) + TEST (3, 2, 1, 1) + TEST (0, 3, 1, 1) + TEST (1, 3, 1, 1) + TEST (2, 3, 1, 1) + TEST (3, 3, 1, 1) + TEST (0, 0, 2, 1) + TEST (1, 0, 2, 1) + TEST (2, 0, 2, 1) + TEST (3, 0, 2, 1) + TEST (0, 1, 2, 1) + TEST (1, 1, 2, 1) + TEST (2, 1, 2, 1) + TEST (3, 1, 2, 1) + TEST (0, 2, 2, 1) + TEST (1, 2, 2, 1) + TEST (2, 2, 2, 1) + TEST (3, 2, 2, 1) + TEST (0, 3, 2, 1) + TEST (1, 3, 2, 1) + TEST (2, 3, 2, 1) + TEST (3, 3, 2, 1) + TEST (0, 0, 3, 1) + TEST (1, 0, 3, 1) + TEST (2, 0, 3, 1) + TEST (3, 0, 3, 1) + TEST (0, 1, 3, 1) + TEST (1, 1, 3, 1) + TEST (2, 1, 3, 1) + TEST (3, 1, 3, 1) + TEST (0, 2, 3, 1) + TEST (1, 2, 3, 1) + TEST (2, 2, 3, 1) + TEST (3, 2, 3, 1) + TEST (0, 3, 3, 1) + TEST (1, 3, 3, 1) + TEST (2, 3, 3, 1) + TEST (3, 3, 3, 1) +} + +void check1(void) +{ + TEST (0, 0, 0, 2) + TEST (1, 0, 0, 2) + TEST (2, 0, 0, 2) + TEST (3, 0, 0, 2) + TEST (0, 1, 0, 2) + TEST (1, 1, 0, 2) + TEST (2, 1, 0, 2) + TEST (3, 1, 0, 2) + TEST (0, 2, 0, 2) + TEST (1, 2, 0, 2) + TEST (2, 2, 0, 2) + TEST (3, 2, 0, 2) + TEST (0, 3, 0, 2) + TEST (1, 3, 0, 2) + TEST (2, 3, 0, 2) + TEST (3, 3, 0, 2) + TEST (0, 0, 1, 2) + TEST (1, 0, 1, 2) + TEST (2, 0, 1, 2) + TEST (3, 0, 1, 2) + TEST (0, 1, 1, 2) + TEST (1, 1, 1, 2) + TEST (2, 1, 1, 2) + TEST (3, 1, 1, 2) + TEST (0, 2, 1, 2) + TEST (1, 2, 1, 2) + TEST (2, 2, 1, 2) + TEST (3, 2, 1, 2) + TEST (0, 3, 1, 2) + TEST (1, 3, 1, 2) + TEST (2, 3, 1, 2) + TEST (3, 3, 1, 2) + TEST (0, 0, 2, 2) + TEST (1, 0, 2, 2) + TEST (2, 0, 2, 2) + TEST (3, 0, 2, 2) + TEST (0, 1, 2, 2) + TEST (1, 1, 2, 2) + TEST (2, 1, 2, 2) + TEST (3, 1, 2, 2) + TEST (0, 2, 2, 2) + TEST (1, 2, 2, 2) + TEST (2, 2, 2, 2) + TEST (3, 2, 2, 2) + TEST (0, 3, 2, 2) + TEST (1, 3, 2, 2) + TEST (2, 3, 2, 2) + TEST (3, 3, 2, 2) + TEST (0, 0, 3, 2) + TEST (1, 0, 3, 2) + TEST (2, 0, 3, 2) + TEST (3, 0, 3, 2) + TEST (0, 1, 3, 2) + TEST (1, 1, 3, 2) + TEST (2, 1, 3, 2) + TEST (3, 1, 3, 2) + TEST (0, 2, 3, 2) + TEST (1, 2, 3, 2) + TEST (2, 2, 3, 2) + TEST (3, 2, 3, 2) + TEST (0, 3, 3, 2) + TEST (1, 3, 3, 2) + TEST (2, 3, 3, 2) + TEST (3, 3, 3, 2) + TEST (0, 0, 0, 3) + TEST (1, 0, 0, 3) + TEST (2, 0, 0, 3) + TEST (3, 0, 0, 3) + TEST (0, 1, 0, 3) + TEST (1, 1, 0, 3) + TEST (2, 1, 0, 3) + TEST (3, 1, 0, 3) + TEST (0, 2, 0, 3) + TEST (1, 2, 0, 3) + TEST (2, 2, 0, 3) + TEST (3, 2, 0, 3) + TEST (0, 3, 0, 3) + TEST (1, 3, 0, 3) + TEST (2, 3, 0, 3) + TEST (3, 3, 0, 3) + TEST (0, 0, 1, 3) + TEST (1, 0, 1, 3) + TEST (2, 0, 1, 3) + TEST (3, 0, 1, 3) + TEST (0, 1, 1, 3) + TEST (1, 1, 1, 3) + TEST (2, 1, 1, 3) + TEST (3, 1, 1, 3) + TEST (0, 2, 1, 3) + TEST (1, 2, 1, 3) + TEST (2, 2, 1, 3) + TEST (3, 2, 1, 3) + TEST (0, 3, 1, 3) + TEST (1, 3, 1, 3) + TEST (2, 3, 1, 3) + TEST (3, 3, 1, 3) + TEST (0, 0, 2, 3) + TEST (1, 0, 2, 3) + TEST (2, 0, 2, 3) + TEST (3, 0, 2, 3) + TEST (0, 1, 2, 3) + TEST (1, 1, 2, 3) + TEST (2, 1, 2, 3) + TEST (3, 1, 2, 3) + TEST (0, 2, 2, 3) + TEST (1, 2, 2, 3) + TEST (2, 2, 2, 3) + TEST (3, 2, 2, 3) + TEST (0, 3, 2, 3) + TEST (1, 3, 2, 3) + TEST (2, 3, 2, 3) + TEST (3, 3, 2, 3) + TEST (0, 0, 3, 3) + TEST (1, 0, 3, 3) + TEST (2, 0, 3, 3) + TEST (3, 0, 3, 3) + TEST (0, 1, 3, 3) + TEST (1, 1, 3, 3) + TEST (2, 1, 3, 3) + TEST (3, 1, 3, 3) + TEST (0, 2, 3, 3) + TEST (1, 2, 3, 3) + TEST (2, 2, 3, 3) + TEST (3, 2, 3, 3) + TEST (0, 3, 3, 3) + TEST (1, 3, 3, 3) + TEST (2, 3, 3, 3) + TEST (3, 3, 3, 3) +} + +void check(void) +{ + check0 (); + check1 (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-4-2.inc b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-4-2.inc new file mode 100644 index 000000000..2f7baa0ed --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-4-2.inc @@ -0,0 +1,4262 @@ +/* This file auto-generated with ./vperm.pl 4 2. */ + +void check0(void) +{ + TEST (0, 0, 0, 0) + TEST (1, 0, 0, 0) + TEST (2, 0, 0, 0) + TEST (3, 0, 0, 0) + TEST (4, 0, 0, 0) + TEST (5, 0, 0, 0) + TEST (6, 0, 0, 0) + TEST (7, 0, 0, 0) + TEST (0, 1, 0, 0) + TEST (1, 1, 0, 0) + TEST (2, 1, 0, 0) + TEST (3, 1, 0, 0) + TEST (4, 1, 0, 0) + TEST (5, 1, 0, 0) + TEST (6, 1, 0, 0) + TEST (7, 1, 0, 0) + TEST (0, 2, 0, 0) + TEST (1, 2, 0, 0) + TEST (2, 2, 0, 0) + TEST (3, 2, 0, 0) + TEST (4, 2, 0, 0) + TEST (5, 2, 0, 0) + TEST (6, 2, 0, 0) + TEST (7, 2, 0, 0) + TEST (0, 3, 0, 0) + TEST (1, 3, 0, 0) + TEST (2, 3, 0, 0) + TEST (3, 3, 0, 0) + TEST (4, 3, 0, 0) + TEST (5, 3, 0, 0) + TEST (6, 3, 0, 0) + TEST (7, 3, 0, 0) + TEST (0, 4, 0, 0) + TEST (1, 4, 0, 0) + TEST (2, 4, 0, 0) + TEST (3, 4, 0, 0) + TEST (4, 4, 0, 0) + TEST (5, 4, 0, 0) + TEST (6, 4, 0, 0) + TEST (7, 4, 0, 0) + TEST (0, 5, 0, 0) + TEST (1, 5, 0, 0) + TEST (2, 5, 0, 0) + TEST (3, 5, 0, 0) + TEST (4, 5, 0, 0) + TEST (5, 5, 0, 0) + TEST (6, 5, 0, 0) + TEST (7, 5, 0, 0) + TEST (0, 6, 0, 0) + TEST (1, 6, 0, 0) + TEST (2, 6, 0, 0) + TEST (3, 6, 0, 0) + TEST (4, 6, 0, 0) + TEST (5, 6, 0, 0) + TEST (6, 6, 0, 0) + TEST (7, 6, 0, 0) + TEST (0, 7, 0, 0) + TEST (1, 7, 0, 0) + TEST (2, 7, 0, 0) + TEST (3, 7, 0, 0) + TEST (4, 7, 0, 0) + TEST (5, 7, 0, 0) + TEST (6, 7, 0, 0) + TEST (7, 7, 0, 0) + TEST (0, 0, 1, 0) + TEST (1, 0, 1, 0) + TEST (2, 0, 1, 0) + TEST (3, 0, 1, 0) + TEST (4, 0, 1, 0) + TEST (5, 0, 1, 0) + TEST (6, 0, 1, 0) + TEST (7, 0, 1, 0) + TEST (0, 1, 1, 0) + TEST (1, 1, 1, 0) + TEST (2, 1, 1, 0) + TEST (3, 1, 1, 0) + TEST (4, 1, 1, 0) + TEST (5, 1, 1, 0) + TEST (6, 1, 1, 0) + TEST (7, 1, 1, 0) + TEST (0, 2, 1, 0) + TEST (1, 2, 1, 0) + TEST (2, 2, 1, 0) + TEST (3, 2, 1, 0) + TEST (4, 2, 1, 0) + TEST (5, 2, 1, 0) + TEST (6, 2, 1, 0) + TEST (7, 2, 1, 0) + TEST (0, 3, 1, 0) + TEST (1, 3, 1, 0) + TEST (2, 3, 1, 0) + TEST (3, 3, 1, 0) + TEST (4, 3, 1, 0) + TEST (5, 3, 1, 0) + TEST (6, 3, 1, 0) + TEST (7, 3, 1, 0) + TEST (0, 4, 1, 0) + TEST (1, 4, 1, 0) + TEST (2, 4, 1, 0) + TEST (3, 4, 1, 0) + TEST (4, 4, 1, 0) + TEST (5, 4, 1, 0) + TEST (6, 4, 1, 0) + TEST (7, 4, 1, 0) + TEST (0, 5, 1, 0) + TEST (1, 5, 1, 0) + TEST (2, 5, 1, 0) + TEST (3, 5, 1, 0) + TEST (4, 5, 1, 0) + TEST (5, 5, 1, 0) + TEST (6, 5, 1, 0) + TEST (7, 5, 1, 0) + TEST (0, 6, 1, 0) + TEST (1, 6, 1, 0) + TEST (2, 6, 1, 0) + TEST (3, 6, 1, 0) + TEST (4, 6, 1, 0) + TEST (5, 6, 1, 0) + TEST (6, 6, 1, 0) + TEST (7, 6, 1, 0) + TEST (0, 7, 1, 0) + TEST (1, 7, 1, 0) + TEST (2, 7, 1, 0) + TEST (3, 7, 1, 0) + TEST (4, 7, 1, 0) + TEST (5, 7, 1, 0) + TEST (6, 7, 1, 0) + TEST (7, 7, 1, 0) +} + +void check1(void) +{ + TEST (0, 0, 2, 0) + TEST (1, 0, 2, 0) + TEST (2, 0, 2, 0) + TEST (3, 0, 2, 0) + TEST (4, 0, 2, 0) + TEST (5, 0, 2, 0) + TEST (6, 0, 2, 0) + TEST (7, 0, 2, 0) + TEST (0, 1, 2, 0) + TEST (1, 1, 2, 0) + TEST (2, 1, 2, 0) + TEST (3, 1, 2, 0) + TEST (4, 1, 2, 0) + TEST (5, 1, 2, 0) + TEST (6, 1, 2, 0) + TEST (7, 1, 2, 0) + TEST (0, 2, 2, 0) + TEST (1, 2, 2, 0) + TEST (2, 2, 2, 0) + TEST (3, 2, 2, 0) + TEST (4, 2, 2, 0) + TEST (5, 2, 2, 0) + TEST (6, 2, 2, 0) + TEST (7, 2, 2, 0) + TEST (0, 3, 2, 0) + TEST (1, 3, 2, 0) + TEST (2, 3, 2, 0) + TEST (3, 3, 2, 0) + TEST (4, 3, 2, 0) + TEST (5, 3, 2, 0) + TEST (6, 3, 2, 0) + TEST (7, 3, 2, 0) + TEST (0, 4, 2, 0) + TEST (1, 4, 2, 0) + TEST (2, 4, 2, 0) + TEST (3, 4, 2, 0) + TEST (4, 4, 2, 0) + TEST (5, 4, 2, 0) + TEST (6, 4, 2, 0) + TEST (7, 4, 2, 0) + TEST (0, 5, 2, 0) + TEST (1, 5, 2, 0) + TEST (2, 5, 2, 0) + TEST (3, 5, 2, 0) + TEST (4, 5, 2, 0) + TEST (5, 5, 2, 0) + TEST (6, 5, 2, 0) + TEST (7, 5, 2, 0) + TEST (0, 6, 2, 0) + TEST (1, 6, 2, 0) + TEST (2, 6, 2, 0) + TEST (3, 6, 2, 0) + TEST (4, 6, 2, 0) + TEST (5, 6, 2, 0) + TEST (6, 6, 2, 0) + TEST (7, 6, 2, 0) + TEST (0, 7, 2, 0) + TEST (1, 7, 2, 0) + TEST (2, 7, 2, 0) + TEST (3, 7, 2, 0) + TEST (4, 7, 2, 0) + TEST (5, 7, 2, 0) + TEST (6, 7, 2, 0) + TEST (7, 7, 2, 0) + TEST (0, 0, 3, 0) + TEST (1, 0, 3, 0) + TEST (2, 0, 3, 0) + TEST (3, 0, 3, 0) + TEST (4, 0, 3, 0) + TEST (5, 0, 3, 0) + TEST (6, 0, 3, 0) + TEST (7, 0, 3, 0) + TEST (0, 1, 3, 0) + TEST (1, 1, 3, 0) + TEST (2, 1, 3, 0) + TEST (3, 1, 3, 0) + TEST (4, 1, 3, 0) + TEST (5, 1, 3, 0) + TEST (6, 1, 3, 0) + TEST (7, 1, 3, 0) + TEST (0, 2, 3, 0) + TEST (1, 2, 3, 0) + TEST (2, 2, 3, 0) + TEST (3, 2, 3, 0) + TEST (4, 2, 3, 0) + TEST (5, 2, 3, 0) + TEST (6, 2, 3, 0) + TEST (7, 2, 3, 0) + TEST (0, 3, 3, 0) + TEST (1, 3, 3, 0) + TEST (2, 3, 3, 0) + TEST (3, 3, 3, 0) + TEST (4, 3, 3, 0) + TEST (5, 3, 3, 0) + TEST (6, 3, 3, 0) + TEST (7, 3, 3, 0) + TEST (0, 4, 3, 0) + TEST (1, 4, 3, 0) + TEST (2, 4, 3, 0) + TEST (3, 4, 3, 0) + TEST (4, 4, 3, 0) + TEST (5, 4, 3, 0) + TEST (6, 4, 3, 0) + TEST (7, 4, 3, 0) + TEST (0, 5, 3, 0) + TEST (1, 5, 3, 0) + TEST (2, 5, 3, 0) + TEST (3, 5, 3, 0) + TEST (4, 5, 3, 0) + TEST (5, 5, 3, 0) + TEST (6, 5, 3, 0) + TEST (7, 5, 3, 0) + TEST (0, 6, 3, 0) + TEST (1, 6, 3, 0) + TEST (2, 6, 3, 0) + TEST (3, 6, 3, 0) + TEST (4, 6, 3, 0) + TEST (5, 6, 3, 0) + TEST (6, 6, 3, 0) + TEST (7, 6, 3, 0) + TEST (0, 7, 3, 0) + TEST (1, 7, 3, 0) + TEST (2, 7, 3, 0) + TEST (3, 7, 3, 0) + TEST (4, 7, 3, 0) + TEST (5, 7, 3, 0) + TEST (6, 7, 3, 0) + TEST (7, 7, 3, 0) +} + +void check2(void) +{ + TEST (0, 0, 4, 0) + TEST (1, 0, 4, 0) + TEST (2, 0, 4, 0) + TEST (3, 0, 4, 0) + TEST (4, 0, 4, 0) + TEST (5, 0, 4, 0) + TEST (6, 0, 4, 0) + TEST (7, 0, 4, 0) + TEST (0, 1, 4, 0) + TEST (1, 1, 4, 0) + TEST (2, 1, 4, 0) + TEST (3, 1, 4, 0) + TEST (4, 1, 4, 0) + TEST (5, 1, 4, 0) + TEST (6, 1, 4, 0) + TEST (7, 1, 4, 0) + TEST (0, 2, 4, 0) + TEST (1, 2, 4, 0) + TEST (2, 2, 4, 0) + TEST (3, 2, 4, 0) + TEST (4, 2, 4, 0) + TEST (5, 2, 4, 0) + TEST (6, 2, 4, 0) + TEST (7, 2, 4, 0) + TEST (0, 3, 4, 0) + TEST (1, 3, 4, 0) + TEST (2, 3, 4, 0) + TEST (3, 3, 4, 0) + TEST (4, 3, 4, 0) + TEST (5, 3, 4, 0) + TEST (6, 3, 4, 0) + TEST (7, 3, 4, 0) + TEST (0, 4, 4, 0) + TEST (1, 4, 4, 0) + TEST (2, 4, 4, 0) + TEST (3, 4, 4, 0) + TEST (4, 4, 4, 0) + TEST (5, 4, 4, 0) + TEST (6, 4, 4, 0) + TEST (7, 4, 4, 0) + TEST (0, 5, 4, 0) + TEST (1, 5, 4, 0) + TEST (2, 5, 4, 0) + TEST (3, 5, 4, 0) + TEST (4, 5, 4, 0) + TEST (5, 5, 4, 0) + TEST (6, 5, 4, 0) + TEST (7, 5, 4, 0) + TEST (0, 6, 4, 0) + TEST (1, 6, 4, 0) + TEST (2, 6, 4, 0) + TEST (3, 6, 4, 0) + TEST (4, 6, 4, 0) + TEST (5, 6, 4, 0) + TEST (6, 6, 4, 0) + TEST (7, 6, 4, 0) + TEST (0, 7, 4, 0) + TEST (1, 7, 4, 0) + TEST (2, 7, 4, 0) + TEST (3, 7, 4, 0) + TEST (4, 7, 4, 0) + TEST (5, 7, 4, 0) + TEST (6, 7, 4, 0) + TEST (7, 7, 4, 0) + TEST (0, 0, 5, 0) + TEST (1, 0, 5, 0) + TEST (2, 0, 5, 0) + TEST (3, 0, 5, 0) + TEST (4, 0, 5, 0) + TEST (5, 0, 5, 0) + TEST (6, 0, 5, 0) + TEST (7, 0, 5, 0) + TEST (0, 1, 5, 0) + TEST (1, 1, 5, 0) + TEST (2, 1, 5, 0) + TEST (3, 1, 5, 0) + TEST (4, 1, 5, 0) + TEST (5, 1, 5, 0) + TEST (6, 1, 5, 0) + TEST (7, 1, 5, 0) + TEST (0, 2, 5, 0) + TEST (1, 2, 5, 0) + TEST (2, 2, 5, 0) + TEST (3, 2, 5, 0) + TEST (4, 2, 5, 0) + TEST (5, 2, 5, 0) + TEST (6, 2, 5, 0) + TEST (7, 2, 5, 0) + TEST (0, 3, 5, 0) + TEST (1, 3, 5, 0) + TEST (2, 3, 5, 0) + TEST (3, 3, 5, 0) + TEST (4, 3, 5, 0) + TEST (5, 3, 5, 0) + TEST (6, 3, 5, 0) + TEST (7, 3, 5, 0) + TEST (0, 4, 5, 0) + TEST (1, 4, 5, 0) + TEST (2, 4, 5, 0) + TEST (3, 4, 5, 0) + TEST (4, 4, 5, 0) + TEST (5, 4, 5, 0) + TEST (6, 4, 5, 0) + TEST (7, 4, 5, 0) + TEST (0, 5, 5, 0) + TEST (1, 5, 5, 0) + TEST (2, 5, 5, 0) + TEST (3, 5, 5, 0) + TEST (4, 5, 5, 0) + TEST (5, 5, 5, 0) + TEST (6, 5, 5, 0) + TEST (7, 5, 5, 0) + TEST (0, 6, 5, 0) + TEST (1, 6, 5, 0) + TEST (2, 6, 5, 0) + TEST (3, 6, 5, 0) + TEST (4, 6, 5, 0) + TEST (5, 6, 5, 0) + TEST (6, 6, 5, 0) + TEST (7, 6, 5, 0) + TEST (0, 7, 5, 0) + TEST (1, 7, 5, 0) + TEST (2, 7, 5, 0) + TEST (3, 7, 5, 0) + TEST (4, 7, 5, 0) + TEST (5, 7, 5, 0) + TEST (6, 7, 5, 0) + TEST (7, 7, 5, 0) +} + +void check3(void) +{ + TEST (0, 0, 6, 0) + TEST (1, 0, 6, 0) + TEST (2, 0, 6, 0) + TEST (3, 0, 6, 0) + TEST (4, 0, 6, 0) + TEST (5, 0, 6, 0) + TEST (6, 0, 6, 0) + TEST (7, 0, 6, 0) + TEST (0, 1, 6, 0) + TEST (1, 1, 6, 0) + TEST (2, 1, 6, 0) + TEST (3, 1, 6, 0) + TEST (4, 1, 6, 0) + TEST (5, 1, 6, 0) + TEST (6, 1, 6, 0) + TEST (7, 1, 6, 0) + TEST (0, 2, 6, 0) + TEST (1, 2, 6, 0) + TEST (2, 2, 6, 0) + TEST (3, 2, 6, 0) + TEST (4, 2, 6, 0) + TEST (5, 2, 6, 0) + TEST (6, 2, 6, 0) + TEST (7, 2, 6, 0) + TEST (0, 3, 6, 0) + TEST (1, 3, 6, 0) + TEST (2, 3, 6, 0) + TEST (3, 3, 6, 0) + TEST (4, 3, 6, 0) + TEST (5, 3, 6, 0) + TEST (6, 3, 6, 0) + TEST (7, 3, 6, 0) + TEST (0, 4, 6, 0) + TEST (1, 4, 6, 0) + TEST (2, 4, 6, 0) + TEST (3, 4, 6, 0) + TEST (4, 4, 6, 0) + TEST (5, 4, 6, 0) + TEST (6, 4, 6, 0) + TEST (7, 4, 6, 0) + TEST (0, 5, 6, 0) + TEST (1, 5, 6, 0) + TEST (2, 5, 6, 0) + TEST (3, 5, 6, 0) + TEST (4, 5, 6, 0) + TEST (5, 5, 6, 0) + TEST (6, 5, 6, 0) + TEST (7, 5, 6, 0) + TEST (0, 6, 6, 0) + TEST (1, 6, 6, 0) + TEST (2, 6, 6, 0) + TEST (3, 6, 6, 0) + TEST (4, 6, 6, 0) + TEST (5, 6, 6, 0) + TEST (6, 6, 6, 0) + TEST (7, 6, 6, 0) + TEST (0, 7, 6, 0) + TEST (1, 7, 6, 0) + TEST (2, 7, 6, 0) + TEST (3, 7, 6, 0) + TEST (4, 7, 6, 0) + TEST (5, 7, 6, 0) + TEST (6, 7, 6, 0) + TEST (7, 7, 6, 0) + TEST (0, 0, 7, 0) + TEST (1, 0, 7, 0) + TEST (2, 0, 7, 0) + TEST (3, 0, 7, 0) + TEST (4, 0, 7, 0) + TEST (5, 0, 7, 0) + TEST (6, 0, 7, 0) + TEST (7, 0, 7, 0) + TEST (0, 1, 7, 0) + TEST (1, 1, 7, 0) + TEST (2, 1, 7, 0) + TEST (3, 1, 7, 0) + TEST (4, 1, 7, 0) + TEST (5, 1, 7, 0) + TEST (6, 1, 7, 0) + TEST (7, 1, 7, 0) + TEST (0, 2, 7, 0) + TEST (1, 2, 7, 0) + TEST (2, 2, 7, 0) + TEST (3, 2, 7, 0) + TEST (4, 2, 7, 0) + TEST (5, 2, 7, 0) + TEST (6, 2, 7, 0) + TEST (7, 2, 7, 0) + TEST (0, 3, 7, 0) + TEST (1, 3, 7, 0) + TEST (2, 3, 7, 0) + TEST (3, 3, 7, 0) + TEST (4, 3, 7, 0) + TEST (5, 3, 7, 0) + TEST (6, 3, 7, 0) + TEST (7, 3, 7, 0) + TEST (0, 4, 7, 0) + TEST (1, 4, 7, 0) + TEST (2, 4, 7, 0) + TEST (3, 4, 7, 0) + TEST (4, 4, 7, 0) + TEST (5, 4, 7, 0) + TEST (6, 4, 7, 0) + TEST (7, 4, 7, 0) + TEST (0, 5, 7, 0) + TEST (1, 5, 7, 0) + TEST (2, 5, 7, 0) + TEST (3, 5, 7, 0) + TEST (4, 5, 7, 0) + TEST (5, 5, 7, 0) + TEST (6, 5, 7, 0) + TEST (7, 5, 7, 0) + TEST (0, 6, 7, 0) + TEST (1, 6, 7, 0) + TEST (2, 6, 7, 0) + TEST (3, 6, 7, 0) + TEST (4, 6, 7, 0) + TEST (5, 6, 7, 0) + TEST (6, 6, 7, 0) + TEST (7, 6, 7, 0) + TEST (0, 7, 7, 0) + TEST (1, 7, 7, 0) + TEST (2, 7, 7, 0) + TEST (3, 7, 7, 0) + TEST (4, 7, 7, 0) + TEST (5, 7, 7, 0) + TEST (6, 7, 7, 0) + TEST (7, 7, 7, 0) +} + +void check4(void) +{ + TEST (0, 0, 0, 1) + TEST (1, 0, 0, 1) + TEST (2, 0, 0, 1) + TEST (3, 0, 0, 1) + TEST (4, 0, 0, 1) + TEST (5, 0, 0, 1) + TEST (6, 0, 0, 1) + TEST (7, 0, 0, 1) + TEST (0, 1, 0, 1) + TEST (1, 1, 0, 1) + TEST (2, 1, 0, 1) + TEST (3, 1, 0, 1) + TEST (4, 1, 0, 1) + TEST (5, 1, 0, 1) + TEST (6, 1, 0, 1) + TEST (7, 1, 0, 1) + TEST (0, 2, 0, 1) + TEST (1, 2, 0, 1) + TEST (2, 2, 0, 1) + TEST (3, 2, 0, 1) + TEST (4, 2, 0, 1) + TEST (5, 2, 0, 1) + TEST (6, 2, 0, 1) + TEST (7, 2, 0, 1) + TEST (0, 3, 0, 1) + TEST (1, 3, 0, 1) + TEST (2, 3, 0, 1) + TEST (3, 3, 0, 1) + TEST (4, 3, 0, 1) + TEST (5, 3, 0, 1) + TEST (6, 3, 0, 1) + TEST (7, 3, 0, 1) + TEST (0, 4, 0, 1) + TEST (1, 4, 0, 1) + TEST (2, 4, 0, 1) + TEST (3, 4, 0, 1) + TEST (4, 4, 0, 1) + TEST (5, 4, 0, 1) + TEST (6, 4, 0, 1) + TEST (7, 4, 0, 1) + TEST (0, 5, 0, 1) + TEST (1, 5, 0, 1) + TEST (2, 5, 0, 1) + TEST (3, 5, 0, 1) + TEST (4, 5, 0, 1) + TEST (5, 5, 0, 1) + TEST (6, 5, 0, 1) + TEST (7, 5, 0, 1) + TEST (0, 6, 0, 1) + TEST (1, 6, 0, 1) + TEST (2, 6, 0, 1) + TEST (3, 6, 0, 1) + TEST (4, 6, 0, 1) + TEST (5, 6, 0, 1) + TEST (6, 6, 0, 1) + TEST (7, 6, 0, 1) + TEST (0, 7, 0, 1) + TEST (1, 7, 0, 1) + TEST (2, 7, 0, 1) + TEST (3, 7, 0, 1) + TEST (4, 7, 0, 1) + TEST (5, 7, 0, 1) + TEST (6, 7, 0, 1) + TEST (7, 7, 0, 1) + TEST (0, 0, 1, 1) + TEST (1, 0, 1, 1) + TEST (2, 0, 1, 1) + TEST (3, 0, 1, 1) + TEST (4, 0, 1, 1) + TEST (5, 0, 1, 1) + TEST (6, 0, 1, 1) + TEST (7, 0, 1, 1) + TEST (0, 1, 1, 1) + TEST (1, 1, 1, 1) + TEST (2, 1, 1, 1) + TEST (3, 1, 1, 1) + TEST (4, 1, 1, 1) + TEST (5, 1, 1, 1) + TEST (6, 1, 1, 1) + TEST (7, 1, 1, 1) + TEST (0, 2, 1, 1) + TEST (1, 2, 1, 1) + TEST (2, 2, 1, 1) + TEST (3, 2, 1, 1) + TEST (4, 2, 1, 1) + TEST (5, 2, 1, 1) + TEST (6, 2, 1, 1) + TEST (7, 2, 1, 1) + TEST (0, 3, 1, 1) + TEST (1, 3, 1, 1) + TEST (2, 3, 1, 1) + TEST (3, 3, 1, 1) + TEST (4, 3, 1, 1) + TEST (5, 3, 1, 1) + TEST (6, 3, 1, 1) + TEST (7, 3, 1, 1) + TEST (0, 4, 1, 1) + TEST (1, 4, 1, 1) + TEST (2, 4, 1, 1) + TEST (3, 4, 1, 1) + TEST (4, 4, 1, 1) + TEST (5, 4, 1, 1) + TEST (6, 4, 1, 1) + TEST (7, 4, 1, 1) + TEST (0, 5, 1, 1) + TEST (1, 5, 1, 1) + TEST (2, 5, 1, 1) + TEST (3, 5, 1, 1) + TEST (4, 5, 1, 1) + TEST (5, 5, 1, 1) + TEST (6, 5, 1, 1) + TEST (7, 5, 1, 1) + TEST (0, 6, 1, 1) + TEST (1, 6, 1, 1) + TEST (2, 6, 1, 1) + TEST (3, 6, 1, 1) + TEST (4, 6, 1, 1) + TEST (5, 6, 1, 1) + TEST (6, 6, 1, 1) + TEST (7, 6, 1, 1) + TEST (0, 7, 1, 1) + TEST (1, 7, 1, 1) + TEST (2, 7, 1, 1) + TEST (3, 7, 1, 1) + TEST (4, 7, 1, 1) + TEST (5, 7, 1, 1) + TEST (6, 7, 1, 1) + TEST (7, 7, 1, 1) +} + +void check5(void) +{ + TEST (0, 0, 2, 1) + TEST (1, 0, 2, 1) + TEST (2, 0, 2, 1) + TEST (3, 0, 2, 1) + TEST (4, 0, 2, 1) + TEST (5, 0, 2, 1) + TEST (6, 0, 2, 1) + TEST (7, 0, 2, 1) + TEST (0, 1, 2, 1) + TEST (1, 1, 2, 1) + TEST (2, 1, 2, 1) + TEST (3, 1, 2, 1) + TEST (4, 1, 2, 1) + TEST (5, 1, 2, 1) + TEST (6, 1, 2, 1) + TEST (7, 1, 2, 1) + TEST (0, 2, 2, 1) + TEST (1, 2, 2, 1) + TEST (2, 2, 2, 1) + TEST (3, 2, 2, 1) + TEST (4, 2, 2, 1) + TEST (5, 2, 2, 1) + TEST (6, 2, 2, 1) + TEST (7, 2, 2, 1) + TEST (0, 3, 2, 1) + TEST (1, 3, 2, 1) + TEST (2, 3, 2, 1) + TEST (3, 3, 2, 1) + TEST (4, 3, 2, 1) + TEST (5, 3, 2, 1) + TEST (6, 3, 2, 1) + TEST (7, 3, 2, 1) + TEST (0, 4, 2, 1) + TEST (1, 4, 2, 1) + TEST (2, 4, 2, 1) + TEST (3, 4, 2, 1) + TEST (4, 4, 2, 1) + TEST (5, 4, 2, 1) + TEST (6, 4, 2, 1) + TEST (7, 4, 2, 1) + TEST (0, 5, 2, 1) + TEST (1, 5, 2, 1) + TEST (2, 5, 2, 1) + TEST (3, 5, 2, 1) + TEST (4, 5, 2, 1) + TEST (5, 5, 2, 1) + TEST (6, 5, 2, 1) + TEST (7, 5, 2, 1) + TEST (0, 6, 2, 1) + TEST (1, 6, 2, 1) + TEST (2, 6, 2, 1) + TEST (3, 6, 2, 1) + TEST (4, 6, 2, 1) + TEST (5, 6, 2, 1) + TEST (6, 6, 2, 1) + TEST (7, 6, 2, 1) + TEST (0, 7, 2, 1) + TEST (1, 7, 2, 1) + TEST (2, 7, 2, 1) + TEST (3, 7, 2, 1) + TEST (4, 7, 2, 1) + TEST (5, 7, 2, 1) + TEST (6, 7, 2, 1) + TEST (7, 7, 2, 1) + TEST (0, 0, 3, 1) + TEST (1, 0, 3, 1) + TEST (2, 0, 3, 1) + TEST (3, 0, 3, 1) + TEST (4, 0, 3, 1) + TEST (5, 0, 3, 1) + TEST (6, 0, 3, 1) + TEST (7, 0, 3, 1) + TEST (0, 1, 3, 1) + TEST (1, 1, 3, 1) + TEST (2, 1, 3, 1) + TEST (3, 1, 3, 1) + TEST (4, 1, 3, 1) + TEST (5, 1, 3, 1) + TEST (6, 1, 3, 1) + TEST (7, 1, 3, 1) + TEST (0, 2, 3, 1) + TEST (1, 2, 3, 1) + TEST (2, 2, 3, 1) + TEST (3, 2, 3, 1) + TEST (4, 2, 3, 1) + TEST (5, 2, 3, 1) + TEST (6, 2, 3, 1) + TEST (7, 2, 3, 1) + TEST (0, 3, 3, 1) + TEST (1, 3, 3, 1) + TEST (2, 3, 3, 1) + TEST (3, 3, 3, 1) + TEST (4, 3, 3, 1) + TEST (5, 3, 3, 1) + TEST (6, 3, 3, 1) + TEST (7, 3, 3, 1) + TEST (0, 4, 3, 1) + TEST (1, 4, 3, 1) + TEST (2, 4, 3, 1) + TEST (3, 4, 3, 1) + TEST (4, 4, 3, 1) + TEST (5, 4, 3, 1) + TEST (6, 4, 3, 1) + TEST (7, 4, 3, 1) + TEST (0, 5, 3, 1) + TEST (1, 5, 3, 1) + TEST (2, 5, 3, 1) + TEST (3, 5, 3, 1) + TEST (4, 5, 3, 1) + TEST (5, 5, 3, 1) + TEST (6, 5, 3, 1) + TEST (7, 5, 3, 1) + TEST (0, 6, 3, 1) + TEST (1, 6, 3, 1) + TEST (2, 6, 3, 1) + TEST (3, 6, 3, 1) + TEST (4, 6, 3, 1) + TEST (5, 6, 3, 1) + TEST (6, 6, 3, 1) + TEST (7, 6, 3, 1) + TEST (0, 7, 3, 1) + TEST (1, 7, 3, 1) + TEST (2, 7, 3, 1) + TEST (3, 7, 3, 1) + TEST (4, 7, 3, 1) + TEST (5, 7, 3, 1) + TEST (6, 7, 3, 1) + TEST (7, 7, 3, 1) +} + +void check6(void) +{ + TEST (0, 0, 4, 1) + TEST (1, 0, 4, 1) + TEST (2, 0, 4, 1) + TEST (3, 0, 4, 1) + TEST (4, 0, 4, 1) + TEST (5, 0, 4, 1) + TEST (6, 0, 4, 1) + TEST (7, 0, 4, 1) + TEST (0, 1, 4, 1) + TEST (1, 1, 4, 1) + TEST (2, 1, 4, 1) + TEST (3, 1, 4, 1) + TEST (4, 1, 4, 1) + TEST (5, 1, 4, 1) + TEST (6, 1, 4, 1) + TEST (7, 1, 4, 1) + TEST (0, 2, 4, 1) + TEST (1, 2, 4, 1) + TEST (2, 2, 4, 1) + TEST (3, 2, 4, 1) + TEST (4, 2, 4, 1) + TEST (5, 2, 4, 1) + TEST (6, 2, 4, 1) + TEST (7, 2, 4, 1) + TEST (0, 3, 4, 1) + TEST (1, 3, 4, 1) + TEST (2, 3, 4, 1) + TEST (3, 3, 4, 1) + TEST (4, 3, 4, 1) + TEST (5, 3, 4, 1) + TEST (6, 3, 4, 1) + TEST (7, 3, 4, 1) + TEST (0, 4, 4, 1) + TEST (1, 4, 4, 1) + TEST (2, 4, 4, 1) + TEST (3, 4, 4, 1) + TEST (4, 4, 4, 1) + TEST (5, 4, 4, 1) + TEST (6, 4, 4, 1) + TEST (7, 4, 4, 1) + TEST (0, 5, 4, 1) + TEST (1, 5, 4, 1) + TEST (2, 5, 4, 1) + TEST (3, 5, 4, 1) + TEST (4, 5, 4, 1) + TEST (5, 5, 4, 1) + TEST (6, 5, 4, 1) + TEST (7, 5, 4, 1) + TEST (0, 6, 4, 1) + TEST (1, 6, 4, 1) + TEST (2, 6, 4, 1) + TEST (3, 6, 4, 1) + TEST (4, 6, 4, 1) + TEST (5, 6, 4, 1) + TEST (6, 6, 4, 1) + TEST (7, 6, 4, 1) + TEST (0, 7, 4, 1) + TEST (1, 7, 4, 1) + TEST (2, 7, 4, 1) + TEST (3, 7, 4, 1) + TEST (4, 7, 4, 1) + TEST (5, 7, 4, 1) + TEST (6, 7, 4, 1) + TEST (7, 7, 4, 1) + TEST (0, 0, 5, 1) + TEST (1, 0, 5, 1) + TEST (2, 0, 5, 1) + TEST (3, 0, 5, 1) + TEST (4, 0, 5, 1) + TEST (5, 0, 5, 1) + TEST (6, 0, 5, 1) + TEST (7, 0, 5, 1) + TEST (0, 1, 5, 1) + TEST (1, 1, 5, 1) + TEST (2, 1, 5, 1) + TEST (3, 1, 5, 1) + TEST (4, 1, 5, 1) + TEST (5, 1, 5, 1) + TEST (6, 1, 5, 1) + TEST (7, 1, 5, 1) + TEST (0, 2, 5, 1) + TEST (1, 2, 5, 1) + TEST (2, 2, 5, 1) + TEST (3, 2, 5, 1) + TEST (4, 2, 5, 1) + TEST (5, 2, 5, 1) + TEST (6, 2, 5, 1) + TEST (7, 2, 5, 1) + TEST (0, 3, 5, 1) + TEST (1, 3, 5, 1) + TEST (2, 3, 5, 1) + TEST (3, 3, 5, 1) + TEST (4, 3, 5, 1) + TEST (5, 3, 5, 1) + TEST (6, 3, 5, 1) + TEST (7, 3, 5, 1) + TEST (0, 4, 5, 1) + TEST (1, 4, 5, 1) + TEST (2, 4, 5, 1) + TEST (3, 4, 5, 1) + TEST (4, 4, 5, 1) + TEST (5, 4, 5, 1) + TEST (6, 4, 5, 1) + TEST (7, 4, 5, 1) + TEST (0, 5, 5, 1) + TEST (1, 5, 5, 1) + TEST (2, 5, 5, 1) + TEST (3, 5, 5, 1) + TEST (4, 5, 5, 1) + TEST (5, 5, 5, 1) + TEST (6, 5, 5, 1) + TEST (7, 5, 5, 1) + TEST (0, 6, 5, 1) + TEST (1, 6, 5, 1) + TEST (2, 6, 5, 1) + TEST (3, 6, 5, 1) + TEST (4, 6, 5, 1) + TEST (5, 6, 5, 1) + TEST (6, 6, 5, 1) + TEST (7, 6, 5, 1) + TEST (0, 7, 5, 1) + TEST (1, 7, 5, 1) + TEST (2, 7, 5, 1) + TEST (3, 7, 5, 1) + TEST (4, 7, 5, 1) + TEST (5, 7, 5, 1) + TEST (6, 7, 5, 1) + TEST (7, 7, 5, 1) +} + +void check7(void) +{ + TEST (0, 0, 6, 1) + TEST (1, 0, 6, 1) + TEST (2, 0, 6, 1) + TEST (3, 0, 6, 1) + TEST (4, 0, 6, 1) + TEST (5, 0, 6, 1) + TEST (6, 0, 6, 1) + TEST (7, 0, 6, 1) + TEST (0, 1, 6, 1) + TEST (1, 1, 6, 1) + TEST (2, 1, 6, 1) + TEST (3, 1, 6, 1) + TEST (4, 1, 6, 1) + TEST (5, 1, 6, 1) + TEST (6, 1, 6, 1) + TEST (7, 1, 6, 1) + TEST (0, 2, 6, 1) + TEST (1, 2, 6, 1) + TEST (2, 2, 6, 1) + TEST (3, 2, 6, 1) + TEST (4, 2, 6, 1) + TEST (5, 2, 6, 1) + TEST (6, 2, 6, 1) + TEST (7, 2, 6, 1) + TEST (0, 3, 6, 1) + TEST (1, 3, 6, 1) + TEST (2, 3, 6, 1) + TEST (3, 3, 6, 1) + TEST (4, 3, 6, 1) + TEST (5, 3, 6, 1) + TEST (6, 3, 6, 1) + TEST (7, 3, 6, 1) + TEST (0, 4, 6, 1) + TEST (1, 4, 6, 1) + TEST (2, 4, 6, 1) + TEST (3, 4, 6, 1) + TEST (4, 4, 6, 1) + TEST (5, 4, 6, 1) + TEST (6, 4, 6, 1) + TEST (7, 4, 6, 1) + TEST (0, 5, 6, 1) + TEST (1, 5, 6, 1) + TEST (2, 5, 6, 1) + TEST (3, 5, 6, 1) + TEST (4, 5, 6, 1) + TEST (5, 5, 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TEST (4, 3, 6, 2) + TEST (5, 3, 6, 2) + TEST (6, 3, 6, 2) + TEST (7, 3, 6, 2) + TEST (0, 4, 6, 2) + TEST (1, 4, 6, 2) + TEST (2, 4, 6, 2) + TEST (3, 4, 6, 2) + TEST (4, 4, 6, 2) + TEST (5, 4, 6, 2) + TEST (6, 4, 6, 2) + TEST (7, 4, 6, 2) + TEST (0, 5, 6, 2) + TEST (1, 5, 6, 2) + TEST (2, 5, 6, 2) + TEST (3, 5, 6, 2) + TEST (4, 5, 6, 2) + TEST (5, 5, 6, 2) + TEST (6, 5, 6, 2) + TEST (7, 5, 6, 2) + TEST (0, 6, 6, 2) + TEST (1, 6, 6, 2) + TEST (2, 6, 6, 2) + TEST (3, 6, 6, 2) + TEST (4, 6, 6, 2) + TEST (5, 6, 6, 2) + TEST (6, 6, 6, 2) + TEST (7, 6, 6, 2) + TEST (0, 7, 6, 2) + TEST (1, 7, 6, 2) + TEST (2, 7, 6, 2) + TEST (3, 7, 6, 2) + TEST (4, 7, 6, 2) + TEST (5, 7, 6, 2) + TEST (6, 7, 6, 2) + TEST (7, 7, 6, 2) + TEST (0, 0, 7, 2) + TEST (1, 0, 7, 2) + TEST (2, 0, 7, 2) + TEST (3, 0, 7, 2) + TEST (4, 0, 7, 2) + TEST (5, 0, 7, 2) + TEST (6, 0, 7, 2) + TEST (7, 0, 7, 2) + TEST (0, 1, 7, 2) + TEST (1, 1, 7, 2) + TEST (2, 1, 7, 2) + TEST (3, 1, 7, 2) + TEST (4, 1, 7, 2) + TEST (5, 1, 7, 2) + TEST (6, 1, 7, 2) + TEST (7, 1, 7, 2) + TEST (0, 2, 7, 2) + TEST (1, 2, 7, 2) + TEST (2, 2, 7, 2) + TEST (3, 2, 7, 2) + TEST (4, 2, 7, 2) + TEST (5, 2, 7, 2) + TEST (6, 2, 7, 2) + TEST (7, 2, 7, 2) + TEST (0, 3, 7, 2) + TEST (1, 3, 7, 2) + TEST (2, 3, 7, 2) + TEST (3, 3, 7, 2) + TEST (4, 3, 7, 2) + TEST (5, 3, 7, 2) + TEST (6, 3, 7, 2) + TEST (7, 3, 7, 2) + TEST (0, 4, 7, 2) + TEST (1, 4, 7, 2) + TEST (2, 4, 7, 2) + TEST (3, 4, 7, 2) + TEST (4, 4, 7, 2) + TEST (5, 4, 7, 2) + TEST (6, 4, 7, 2) + TEST (7, 4, 7, 2) + TEST (0, 5, 7, 2) + TEST (1, 5, 7, 2) + TEST (2, 5, 7, 2) + TEST (3, 5, 7, 2) + TEST (4, 5, 7, 2) + TEST (5, 5, 7, 2) + TEST (6, 5, 7, 2) + TEST (7, 5, 7, 2) + TEST (0, 6, 7, 2) + TEST (1, 6, 7, 2) + TEST (2, 6, 7, 2) + TEST (3, 6, 7, 2) + TEST (4, 6, 7, 2) + TEST (5, 6, 7, 2) + TEST (6, 6, 7, 2) + TEST (7, 6, 7, 2) + TEST (0, 7, 7, 2) + TEST (1, 7, 7, 2) + TEST (2, 7, 7, 2) + TEST (3, 7, 7, 2) + TEST (4, 7, 7, 2) + TEST (5, 7, 7, 2) + TEST (6, 7, 7, 2) + TEST (7, 7, 7, 2) +} + +void check12(void) +{ + TEST (0, 0, 0, 3) + TEST (1, 0, 0, 3) + TEST (2, 0, 0, 3) + TEST (3, 0, 0, 3) + TEST (4, 0, 0, 3) + TEST (5, 0, 0, 3) + TEST (6, 0, 0, 3) + TEST (7, 0, 0, 3) + TEST (0, 1, 0, 3) + TEST (1, 1, 0, 3) + TEST (2, 1, 0, 3) + TEST (3, 1, 0, 3) + TEST (4, 1, 0, 3) + TEST (5, 1, 0, 3) + TEST (6, 1, 0, 3) + TEST (7, 1, 0, 3) + TEST (0, 2, 0, 3) + TEST (1, 2, 0, 3) + TEST (2, 2, 0, 3) + TEST (3, 2, 0, 3) + TEST (4, 2, 0, 3) + TEST (5, 2, 0, 3) + TEST (6, 2, 0, 3) + TEST (7, 2, 0, 3) + TEST (0, 3, 0, 3) + TEST (1, 3, 0, 3) + TEST (2, 3, 0, 3) + TEST (3, 3, 0, 3) + TEST (4, 3, 0, 3) + TEST (5, 3, 0, 3) + TEST (6, 3, 0, 3) + TEST (7, 3, 0, 3) + TEST (0, 4, 0, 3) + TEST (1, 4, 0, 3) + TEST (2, 4, 0, 3) + TEST (3, 4, 0, 3) + TEST (4, 4, 0, 3) + TEST (5, 4, 0, 3) + TEST (6, 4, 0, 3) + TEST (7, 4, 0, 3) + TEST (0, 5, 0, 3) + TEST (1, 5, 0, 3) + TEST (2, 5, 0, 3) + TEST (3, 5, 0, 3) + TEST (4, 5, 0, 3) + TEST (5, 5, 0, 3) + TEST (6, 5, 0, 3) + TEST (7, 5, 0, 3) + TEST (0, 6, 0, 3) + TEST (1, 6, 0, 3) + TEST (2, 6, 0, 3) + TEST (3, 6, 0, 3) + TEST (4, 6, 0, 3) + TEST (5, 6, 0, 3) + TEST (6, 6, 0, 3) + TEST (7, 6, 0, 3) + TEST (0, 7, 0, 3) + TEST (1, 7, 0, 3) + TEST (2, 7, 0, 3) + TEST (3, 7, 0, 3) + TEST (4, 7, 0, 3) + TEST (5, 7, 0, 3) + TEST (6, 7, 0, 3) + TEST (7, 7, 0, 3) + TEST (0, 0, 1, 3) + TEST (1, 0, 1, 3) + TEST (2, 0, 1, 3) + TEST (3, 0, 1, 3) + TEST (4, 0, 1, 3) + TEST (5, 0, 1, 3) + TEST (6, 0, 1, 3) + TEST (7, 0, 1, 3) + TEST (0, 1, 1, 3) + TEST (1, 1, 1, 3) + TEST (2, 1, 1, 3) + TEST (3, 1, 1, 3) + TEST (4, 1, 1, 3) + TEST (5, 1, 1, 3) + TEST (6, 1, 1, 3) + TEST (7, 1, 1, 3) + TEST (0, 2, 1, 3) + TEST (1, 2, 1, 3) + TEST (2, 2, 1, 3) + TEST (3, 2, 1, 3) + TEST (4, 2, 1, 3) + TEST (5, 2, 1, 3) + TEST (6, 2, 1, 3) + TEST (7, 2, 1, 3) + TEST (0, 3, 1, 3) + TEST (1, 3, 1, 3) + TEST (2, 3, 1, 3) + TEST (3, 3, 1, 3) + TEST (4, 3, 1, 3) + TEST (5, 3, 1, 3) + TEST (6, 3, 1, 3) + TEST (7, 3, 1, 3) + TEST (0, 4, 1, 3) + TEST (1, 4, 1, 3) + TEST (2, 4, 1, 3) + TEST (3, 4, 1, 3) + TEST (4, 4, 1, 3) + TEST (5, 4, 1, 3) + TEST (6, 4, 1, 3) + TEST (7, 4, 1, 3) + TEST (0, 5, 1, 3) + TEST (1, 5, 1, 3) + TEST (2, 5, 1, 3) + TEST (3, 5, 1, 3) + TEST (4, 5, 1, 3) + TEST (5, 5, 1, 3) + TEST (6, 5, 1, 3) + TEST (7, 5, 1, 3) + TEST (0, 6, 1, 3) + TEST (1, 6, 1, 3) + TEST (2, 6, 1, 3) + TEST (3, 6, 1, 3) + TEST (4, 6, 1, 3) + TEST (5, 6, 1, 3) + TEST (6, 6, 1, 3) + TEST (7, 6, 1, 3) + TEST (0, 7, 1, 3) + TEST (1, 7, 1, 3) + TEST (2, 7, 1, 3) + TEST (3, 7, 1, 3) + TEST (4, 7, 1, 3) + TEST (5, 7, 1, 3) + TEST (6, 7, 1, 3) + TEST (7, 7, 1, 3) +} + +void check13(void) +{ + TEST (0, 0, 2, 3) + TEST (1, 0, 2, 3) + TEST (2, 0, 2, 3) + TEST (3, 0, 2, 3) + TEST (4, 0, 2, 3) + TEST (5, 0, 2, 3) + TEST (6, 0, 2, 3) + TEST (7, 0, 2, 3) + TEST (0, 1, 2, 3) + TEST (1, 1, 2, 3) + TEST (2, 1, 2, 3) + TEST (3, 1, 2, 3) + TEST (4, 1, 2, 3) + TEST (5, 1, 2, 3) + TEST (6, 1, 2, 3) + TEST (7, 1, 2, 3) + TEST (0, 2, 2, 3) + TEST (1, 2, 2, 3) + TEST (2, 2, 2, 3) + TEST (3, 2, 2, 3) + TEST (4, 2, 2, 3) + TEST (5, 2, 2, 3) + TEST (6, 2, 2, 3) + TEST (7, 2, 2, 3) + TEST (0, 3, 2, 3) + TEST (1, 3, 2, 3) + TEST (2, 3, 2, 3) + TEST (3, 3, 2, 3) + TEST (4, 3, 2, 3) + TEST (5, 3, 2, 3) + TEST (6, 3, 2, 3) + TEST (7, 3, 2, 3) + TEST (0, 4, 2, 3) + TEST (1, 4, 2, 3) + TEST (2, 4, 2, 3) + TEST (3, 4, 2, 3) + TEST (4, 4, 2, 3) + TEST (5, 4, 2, 3) + TEST (6, 4, 2, 3) + TEST (7, 4, 2, 3) + TEST (0, 5, 2, 3) + TEST (1, 5, 2, 3) + TEST (2, 5, 2, 3) + TEST (3, 5, 2, 3) + TEST (4, 5, 2, 3) + TEST (5, 5, 2, 3) + TEST (6, 5, 2, 3) + TEST (7, 5, 2, 3) + TEST (0, 6, 2, 3) + TEST (1, 6, 2, 3) + TEST (2, 6, 2, 3) + TEST (3, 6, 2, 3) + TEST (4, 6, 2, 3) + TEST (5, 6, 2, 3) + TEST (6, 6, 2, 3) + TEST (7, 6, 2, 3) + TEST (0, 7, 2, 3) + TEST (1, 7, 2, 3) + TEST (2, 7, 2, 3) + TEST (3, 7, 2, 3) + TEST (4, 7, 2, 3) + TEST (5, 7, 2, 3) + TEST (6, 7, 2, 3) + TEST (7, 7, 2, 3) + TEST (0, 0, 3, 3) + TEST (1, 0, 3, 3) + TEST (2, 0, 3, 3) + TEST (3, 0, 3, 3) + TEST (4, 0, 3, 3) + TEST (5, 0, 3, 3) + TEST (6, 0, 3, 3) + TEST (7, 0, 3, 3) + TEST (0, 1, 3, 3) + TEST (1, 1, 3, 3) + TEST (2, 1, 3, 3) + TEST (3, 1, 3, 3) + TEST (4, 1, 3, 3) + TEST (5, 1, 3, 3) + TEST (6, 1, 3, 3) + TEST (7, 1, 3, 3) + TEST (0, 2, 3, 3) + TEST (1, 2, 3, 3) + TEST (2, 2, 3, 3) + TEST (3, 2, 3, 3) + TEST (4, 2, 3, 3) + TEST (5, 2, 3, 3) + TEST (6, 2, 3, 3) + TEST (7, 2, 3, 3) + TEST (0, 3, 3, 3) + TEST (1, 3, 3, 3) + TEST (2, 3, 3, 3) + TEST (3, 3, 3, 3) + TEST (4, 3, 3, 3) + TEST (5, 3, 3, 3) + TEST (6, 3, 3, 3) + TEST (7, 3, 3, 3) + TEST (0, 4, 3, 3) + TEST (1, 4, 3, 3) + TEST (2, 4, 3, 3) + TEST (3, 4, 3, 3) + TEST (4, 4, 3, 3) + TEST (5, 4, 3, 3) + TEST (6, 4, 3, 3) + TEST (7, 4, 3, 3) + TEST (0, 5, 3, 3) + TEST (1, 5, 3, 3) + TEST (2, 5, 3, 3) + TEST (3, 5, 3, 3) + TEST (4, 5, 3, 3) + TEST (5, 5, 3, 3) + TEST (6, 5, 3, 3) + TEST (7, 5, 3, 3) + TEST (0, 6, 3, 3) + TEST (1, 6, 3, 3) + TEST (2, 6, 3, 3) + TEST (3, 6, 3, 3) + TEST (4, 6, 3, 3) + TEST (5, 6, 3, 3) + TEST (6, 6, 3, 3) + TEST (7, 6, 3, 3) + TEST (0, 7, 3, 3) + TEST (1, 7, 3, 3) + TEST (2, 7, 3, 3) + TEST (3, 7, 3, 3) + TEST (4, 7, 3, 3) + TEST (5, 7, 3, 3) + TEST (6, 7, 3, 3) + TEST (7, 7, 3, 3) +} + +void check14(void) +{ + TEST (0, 0, 4, 3) + TEST (1, 0, 4, 3) + TEST (2, 0, 4, 3) + TEST (3, 0, 4, 3) + TEST (4, 0, 4, 3) + TEST (5, 0, 4, 3) + TEST (6, 0, 4, 3) + TEST (7, 0, 4, 3) + TEST (0, 1, 4, 3) + TEST (1, 1, 4, 3) + TEST (2, 1, 4, 3) + TEST (3, 1, 4, 3) + TEST (4, 1, 4, 3) + TEST (5, 1, 4, 3) + TEST (6, 1, 4, 3) + TEST (7, 1, 4, 3) + TEST (0, 2, 4, 3) + TEST (1, 2, 4, 3) + TEST (2, 2, 4, 3) + TEST (3, 2, 4, 3) + TEST (4, 2, 4, 3) + TEST (5, 2, 4, 3) + TEST (6, 2, 4, 3) + TEST (7, 2, 4, 3) + TEST (0, 3, 4, 3) + TEST (1, 3, 4, 3) + TEST (2, 3, 4, 3) + TEST (3, 3, 4, 3) + TEST (4, 3, 4, 3) + TEST (5, 3, 4, 3) + TEST (6, 3, 4, 3) + TEST (7, 3, 4, 3) + TEST (0, 4, 4, 3) + TEST (1, 4, 4, 3) + TEST (2, 4, 4, 3) + TEST (3, 4, 4, 3) + TEST (4, 4, 4, 3) + TEST (5, 4, 4, 3) + TEST (6, 4, 4, 3) + TEST (7, 4, 4, 3) + TEST (0, 5, 4, 3) + TEST (1, 5, 4, 3) + TEST (2, 5, 4, 3) + TEST (3, 5, 4, 3) + TEST (4, 5, 4, 3) + TEST (5, 5, 4, 3) + TEST (6, 5, 4, 3) + TEST (7, 5, 4, 3) + TEST (0, 6, 4, 3) + TEST (1, 6, 4, 3) + TEST (2, 6, 4, 3) + TEST (3, 6, 4, 3) + TEST (4, 6, 4, 3) + TEST (5, 6, 4, 3) + TEST (6, 6, 4, 3) + TEST (7, 6, 4, 3) + TEST (0, 7, 4, 3) + TEST (1, 7, 4, 3) + TEST (2, 7, 4, 3) + TEST (3, 7, 4, 3) + TEST (4, 7, 4, 3) + TEST (5, 7, 4, 3) + TEST (6, 7, 4, 3) + TEST (7, 7, 4, 3) + TEST (0, 0, 5, 3) + TEST (1, 0, 5, 3) + TEST (2, 0, 5, 3) + TEST (3, 0, 5, 3) + TEST (4, 0, 5, 3) + TEST (5, 0, 5, 3) + TEST (6, 0, 5, 3) + TEST (7, 0, 5, 3) + TEST (0, 1, 5, 3) + TEST (1, 1, 5, 3) + TEST (2, 1, 5, 3) + TEST (3, 1, 5, 3) + TEST (4, 1, 5, 3) + TEST (5, 1, 5, 3) + TEST (6, 1, 5, 3) + TEST (7, 1, 5, 3) + TEST (0, 2, 5, 3) + TEST (1, 2, 5, 3) + TEST (2, 2, 5, 3) + TEST (3, 2, 5, 3) + TEST (4, 2, 5, 3) + TEST (5, 2, 5, 3) + TEST (6, 2, 5, 3) + TEST (7, 2, 5, 3) + TEST (0, 3, 5, 3) + TEST (1, 3, 5, 3) + TEST (2, 3, 5, 3) + TEST (3, 3, 5, 3) + TEST (4, 3, 5, 3) + TEST (5, 3, 5, 3) + TEST (6, 3, 5, 3) + TEST (7, 3, 5, 3) + TEST (0, 4, 5, 3) + TEST (1, 4, 5, 3) + TEST (2, 4, 5, 3) + TEST (3, 4, 5, 3) + TEST (4, 4, 5, 3) + TEST (5, 4, 5, 3) + TEST (6, 4, 5, 3) + TEST (7, 4, 5, 3) + TEST (0, 5, 5, 3) + TEST (1, 5, 5, 3) + TEST (2, 5, 5, 3) + TEST (3, 5, 5, 3) + TEST (4, 5, 5, 3) + TEST (5, 5, 5, 3) + TEST (6, 5, 5, 3) + TEST (7, 5, 5, 3) + TEST (0, 6, 5, 3) + TEST (1, 6, 5, 3) + TEST (2, 6, 5, 3) + TEST (3, 6, 5, 3) + TEST (4, 6, 5, 3) + TEST (5, 6, 5, 3) + TEST (6, 6, 5, 3) + TEST (7, 6, 5, 3) + TEST (0, 7, 5, 3) + TEST (1, 7, 5, 3) + TEST (2, 7, 5, 3) + TEST (3, 7, 5, 3) + TEST (4, 7, 5, 3) + TEST (5, 7, 5, 3) + TEST (6, 7, 5, 3) + TEST (7, 7, 5, 3) +} + +void check15(void) +{ + TEST (0, 0, 6, 3) + TEST (1, 0, 6, 3) + TEST (2, 0, 6, 3) + TEST (3, 0, 6, 3) + TEST (4, 0, 6, 3) + TEST (5, 0, 6, 3) + TEST (6, 0, 6, 3) + TEST (7, 0, 6, 3) + TEST (0, 1, 6, 3) + TEST (1, 1, 6, 3) + TEST (2, 1, 6, 3) + TEST (3, 1, 6, 3) + TEST (4, 1, 6, 3) + TEST (5, 1, 6, 3) + TEST (6, 1, 6, 3) + TEST (7, 1, 6, 3) + TEST (0, 2, 6, 3) + TEST (1, 2, 6, 3) + TEST (2, 2, 6, 3) + TEST (3, 2, 6, 3) + TEST (4, 2, 6, 3) + TEST (5, 2, 6, 3) + TEST (6, 2, 6, 3) + TEST (7, 2, 6, 3) + TEST (0, 3, 6, 3) + TEST (1, 3, 6, 3) + TEST (2, 3, 6, 3) + TEST (3, 3, 6, 3) + TEST (4, 3, 6, 3) + TEST (5, 3, 6, 3) + TEST (6, 3, 6, 3) + TEST (7, 3, 6, 3) + TEST (0, 4, 6, 3) + TEST (1, 4, 6, 3) + TEST (2, 4, 6, 3) + TEST (3, 4, 6, 3) + TEST (4, 4, 6, 3) + TEST (5, 4, 6, 3) + TEST (6, 4, 6, 3) + TEST (7, 4, 6, 3) + TEST (0, 5, 6, 3) + TEST (1, 5, 6, 3) + TEST (2, 5, 6, 3) + TEST (3, 5, 6, 3) + TEST (4, 5, 6, 3) + TEST (5, 5, 6, 3) + TEST (6, 5, 6, 3) + TEST (7, 5, 6, 3) + TEST (0, 6, 6, 3) + TEST (1, 6, 6, 3) + TEST (2, 6, 6, 3) + TEST (3, 6, 6, 3) + TEST (4, 6, 6, 3) + TEST (5, 6, 6, 3) + TEST (6, 6, 6, 3) + TEST (7, 6, 6, 3) + TEST (0, 7, 6, 3) + TEST (1, 7, 6, 3) + TEST (2, 7, 6, 3) + TEST (3, 7, 6, 3) + TEST (4, 7, 6, 3) + TEST (5, 7, 6, 3) + TEST (6, 7, 6, 3) + TEST (7, 7, 6, 3) + TEST (0, 0, 7, 3) + TEST (1, 0, 7, 3) + TEST (2, 0, 7, 3) + TEST (3, 0, 7, 3) + TEST (4, 0, 7, 3) + TEST (5, 0, 7, 3) + TEST (6, 0, 7, 3) + TEST (7, 0, 7, 3) + TEST (0, 1, 7, 3) + TEST (1, 1, 7, 3) + TEST (2, 1, 7, 3) + TEST (3, 1, 7, 3) + TEST (4, 1, 7, 3) + TEST (5, 1, 7, 3) + TEST (6, 1, 7, 3) + TEST (7, 1, 7, 3) + TEST (0, 2, 7, 3) + TEST (1, 2, 7, 3) + TEST (2, 2, 7, 3) + TEST (3, 2, 7, 3) + TEST (4, 2, 7, 3) + TEST (5, 2, 7, 3) + TEST (6, 2, 7, 3) + TEST (7, 2, 7, 3) + TEST (0, 3, 7, 3) + TEST (1, 3, 7, 3) + TEST (2, 3, 7, 3) + TEST (3, 3, 7, 3) + TEST (4, 3, 7, 3) + TEST (5, 3, 7, 3) + TEST (6, 3, 7, 3) + TEST (7, 3, 7, 3) + TEST (0, 4, 7, 3) + TEST (1, 4, 7, 3) + TEST (2, 4, 7, 3) + TEST (3, 4, 7, 3) + TEST (4, 4, 7, 3) + TEST (5, 4, 7, 3) + TEST (6, 4, 7, 3) + TEST (7, 4, 7, 3) + TEST (0, 5, 7, 3) + TEST (1, 5, 7, 3) + TEST (2, 5, 7, 3) + TEST (3, 5, 7, 3) + TEST (4, 5, 7, 3) + TEST (5, 5, 7, 3) + TEST (6, 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TEST (7, 3, 0, 4) + TEST (0, 4, 0, 4) + TEST (1, 4, 0, 4) + TEST (2, 4, 0, 4) + TEST (3, 4, 0, 4) + TEST (4, 4, 0, 4) + TEST (5, 4, 0, 4) + TEST (6, 4, 0, 4) + TEST (7, 4, 0, 4) + TEST (0, 5, 0, 4) + TEST (1, 5, 0, 4) + TEST (2, 5, 0, 4) + TEST (3, 5, 0, 4) + TEST (4, 5, 0, 4) + TEST (5, 5, 0, 4) + TEST (6, 5, 0, 4) + TEST (7, 5, 0, 4) + TEST (0, 6, 0, 4) + TEST (1, 6, 0, 4) + TEST (2, 6, 0, 4) + TEST (3, 6, 0, 4) + TEST (4, 6, 0, 4) + TEST (5, 6, 0, 4) + TEST (6, 6, 0, 4) + TEST (7, 6, 0, 4) + TEST (0, 7, 0, 4) + TEST (1, 7, 0, 4) + TEST (2, 7, 0, 4) + TEST (3, 7, 0, 4) + TEST (4, 7, 0, 4) + TEST (5, 7, 0, 4) + TEST (6, 7, 0, 4) + TEST (7, 7, 0, 4) + TEST (0, 0, 1, 4) + TEST (1, 0, 1, 4) + TEST (2, 0, 1, 4) + TEST (3, 0, 1, 4) + TEST (4, 0, 1, 4) + TEST (5, 0, 1, 4) + TEST (6, 0, 1, 4) + TEST (7, 0, 1, 4) + TEST (0, 1, 1, 4) + TEST (1, 1, 1, 4) + TEST (2, 1, 1, 4) + TEST (3, 1, 1, 4) + TEST (4, 1, 1, 4) + TEST (5, 1, 1, 4) + TEST (6, 1, 1, 4) + TEST (7, 1, 1, 4) + TEST (0, 2, 1, 4) + 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7) + TEST (3, 4, 3, 7) + TEST (4, 4, 3, 7) + TEST (5, 4, 3, 7) + TEST (6, 4, 3, 7) + TEST (7, 4, 3, 7) + TEST (0, 5, 3, 7) + TEST (1, 5, 3, 7) + TEST (2, 5, 3, 7) + TEST (3, 5, 3, 7) + TEST (4, 5, 3, 7) + TEST (5, 5, 3, 7) + TEST (6, 5, 3, 7) + TEST (7, 5, 3, 7) + TEST (0, 6, 3, 7) + TEST (1, 6, 3, 7) + TEST (2, 6, 3, 7) + TEST (3, 6, 3, 7) + TEST (4, 6, 3, 7) + TEST (5, 6, 3, 7) + TEST (6, 6, 3, 7) + TEST (7, 6, 3, 7) + TEST (0, 7, 3, 7) + TEST (1, 7, 3, 7) + TEST (2, 7, 3, 7) + TEST (3, 7, 3, 7) + TEST (4, 7, 3, 7) + TEST (5, 7, 3, 7) + TEST (6, 7, 3, 7) + TEST (7, 7, 3, 7) +} + +void check30(void) +{ + TEST (0, 0, 4, 7) + TEST (1, 0, 4, 7) + TEST (2, 0, 4, 7) + TEST (3, 0, 4, 7) + TEST (4, 0, 4, 7) + TEST (5, 0, 4, 7) + TEST (6, 0, 4, 7) + TEST (7, 0, 4, 7) + TEST (0, 1, 4, 7) + TEST (1, 1, 4, 7) + TEST (2, 1, 4, 7) + TEST (3, 1, 4, 7) + TEST (4, 1, 4, 7) + TEST (5, 1, 4, 7) + TEST (6, 1, 4, 7) + TEST (7, 1, 4, 7) + TEST (0, 2, 4, 7) + TEST (1, 2, 4, 7) + TEST (2, 2, 4, 7) + TEST (3, 2, 4, 7) + TEST (4, 2, 4, 7) + TEST (5, 2, 4, 7) + TEST (6, 2, 4, 7) + TEST (7, 2, 4, 7) + TEST (0, 3, 4, 7) + TEST (1, 3, 4, 7) + TEST (2, 3, 4, 7) + TEST (3, 3, 4, 7) + TEST (4, 3, 4, 7) + TEST (5, 3, 4, 7) + TEST (6, 3, 4, 7) + TEST (7, 3, 4, 7) + TEST (0, 4, 4, 7) + TEST (1, 4, 4, 7) + TEST (2, 4, 4, 7) + TEST (3, 4, 4, 7) + TEST (4, 4, 4, 7) + TEST (5, 4, 4, 7) + TEST (6, 4, 4, 7) + TEST (7, 4, 4, 7) + TEST (0, 5, 4, 7) + TEST (1, 5, 4, 7) + TEST (2, 5, 4, 7) + TEST (3, 5, 4, 7) + TEST (4, 5, 4, 7) + TEST (5, 5, 4, 7) + TEST (6, 5, 4, 7) + TEST (7, 5, 4, 7) + TEST (0, 6, 4, 7) + TEST (1, 6, 4, 7) + TEST (2, 6, 4, 7) + TEST (3, 6, 4, 7) + TEST (4, 6, 4, 7) + TEST (5, 6, 4, 7) + TEST (6, 6, 4, 7) + TEST (7, 6, 4, 7) + TEST (0, 7, 4, 7) + TEST (1, 7, 4, 7) + TEST (2, 7, 4, 7) + TEST (3, 7, 4, 7) + TEST (4, 7, 4, 7) + TEST (5, 7, 4, 7) + TEST (6, 7, 4, 7) + TEST (7, 7, 4, 7) + TEST (0, 0, 5, 7) + TEST (1, 0, 5, 7) + TEST (2, 0, 5, 7) + TEST (3, 0, 5, 7) + TEST (4, 0, 5, 7) + TEST (5, 0, 5, 7) + TEST (6, 0, 5, 7) + TEST (7, 0, 5, 7) + TEST (0, 1, 5, 7) + TEST (1, 1, 5, 7) + TEST (2, 1, 5, 7) + TEST (3, 1, 5, 7) + TEST (4, 1, 5, 7) + TEST (5, 1, 5, 7) + TEST (6, 1, 5, 7) + TEST (7, 1, 5, 7) + TEST (0, 2, 5, 7) + TEST (1, 2, 5, 7) + TEST (2, 2, 5, 7) + TEST (3, 2, 5, 7) + TEST (4, 2, 5, 7) + TEST (5, 2, 5, 7) + TEST (6, 2, 5, 7) + TEST (7, 2, 5, 7) + TEST (0, 3, 5, 7) + TEST (1, 3, 5, 7) + TEST (2, 3, 5, 7) + TEST (3, 3, 5, 7) + TEST (4, 3, 5, 7) + TEST (5, 3, 5, 7) + TEST (6, 3, 5, 7) + TEST (7, 3, 5, 7) + TEST (0, 4, 5, 7) + TEST (1, 4, 5, 7) + TEST (2, 4, 5, 7) + TEST (3, 4, 5, 7) + TEST (4, 4, 5, 7) + TEST (5, 4, 5, 7) + TEST (6, 4, 5, 7) + TEST (7, 4, 5, 7) + TEST (0, 5, 5, 7) + TEST (1, 5, 5, 7) + TEST (2, 5, 5, 7) + TEST (3, 5, 5, 7) + TEST (4, 5, 5, 7) + TEST (5, 5, 5, 7) + TEST (6, 5, 5, 7) + TEST (7, 5, 5, 7) + TEST (0, 6, 5, 7) + TEST (1, 6, 5, 7) + TEST (2, 6, 5, 7) + TEST (3, 6, 5, 7) + TEST (4, 6, 5, 7) + TEST (5, 6, 5, 7) + TEST (6, 6, 5, 7) + TEST (7, 6, 5, 7) + TEST (0, 7, 5, 7) + TEST (1, 7, 5, 7) + TEST (2, 7, 5, 7) + TEST (3, 7, 5, 7) + TEST (4, 7, 5, 7) + TEST (5, 7, 5, 7) + TEST (6, 7, 5, 7) + TEST (7, 7, 5, 7) +} + +void check31(void) +{ + TEST (0, 0, 6, 7) + TEST (1, 0, 6, 7) + TEST (2, 0, 6, 7) + TEST (3, 0, 6, 7) + TEST (4, 0, 6, 7) + TEST (5, 0, 6, 7) + TEST (6, 0, 6, 7) + TEST (7, 0, 6, 7) + TEST (0, 1, 6, 7) + TEST (1, 1, 6, 7) + TEST (2, 1, 6, 7) + TEST (3, 1, 6, 7) + TEST (4, 1, 6, 7) + TEST (5, 1, 6, 7) + TEST (6, 1, 6, 7) + TEST (7, 1, 6, 7) + TEST (0, 2, 6, 7) + TEST (1, 2, 6, 7) + TEST (2, 2, 6, 7) + TEST (3, 2, 6, 7) + TEST (4, 2, 6, 7) + TEST (5, 2, 6, 7) + TEST (6, 2, 6, 7) + TEST (7, 2, 6, 7) + TEST (0, 3, 6, 7) + TEST (1, 3, 6, 7) + TEST (2, 3, 6, 7) + TEST (3, 3, 6, 7) + TEST (4, 3, 6, 7) + TEST (5, 3, 6, 7) + TEST (6, 3, 6, 7) + TEST (7, 3, 6, 7) + TEST (0, 4, 6, 7) + TEST (1, 4, 6, 7) + TEST (2, 4, 6, 7) + TEST (3, 4, 6, 7) + TEST (4, 4, 6, 7) + TEST (5, 4, 6, 7) + TEST (6, 4, 6, 7) + TEST (7, 4, 6, 7) + TEST (0, 5, 6, 7) + TEST (1, 5, 6, 7) + TEST (2, 5, 6, 7) + TEST (3, 5, 6, 7) + TEST (4, 5, 6, 7) + TEST (5, 5, 6, 7) + TEST (6, 5, 6, 7) + TEST (7, 5, 6, 7) + TEST (0, 6, 6, 7) + TEST (1, 6, 6, 7) + TEST (2, 6, 6, 7) + TEST (3, 6, 6, 7) + TEST (4, 6, 6, 7) + TEST (5, 6, 6, 7) + TEST (6, 6, 6, 7) + TEST (7, 6, 6, 7) + TEST (0, 7, 6, 7) + TEST (1, 7, 6, 7) + TEST (2, 7, 6, 7) + TEST (3, 7, 6, 7) + TEST (4, 7, 6, 7) + TEST (5, 7, 6, 7) + TEST (6, 7, 6, 7) + TEST (7, 7, 6, 7) + TEST (0, 0, 7, 7) + TEST (1, 0, 7, 7) + TEST (2, 0, 7, 7) + TEST (3, 0, 7, 7) + TEST (4, 0, 7, 7) + TEST (5, 0, 7, 7) + TEST (6, 0, 7, 7) + TEST (7, 0, 7, 7) + TEST (0, 1, 7, 7) + TEST (1, 1, 7, 7) + TEST (2, 1, 7, 7) + TEST (3, 1, 7, 7) + TEST (4, 1, 7, 7) + TEST (5, 1, 7, 7) + TEST (6, 1, 7, 7) + TEST (7, 1, 7, 7) + TEST (0, 2, 7, 7) + TEST (1, 2, 7, 7) + TEST (2, 2, 7, 7) + TEST (3, 2, 7, 7) + TEST (4, 2, 7, 7) + TEST (5, 2, 7, 7) + TEST (6, 2, 7, 7) + TEST (7, 2, 7, 7) + TEST (0, 3, 7, 7) + TEST (1, 3, 7, 7) + TEST (2, 3, 7, 7) + TEST (3, 3, 7, 7) + TEST (4, 3, 7, 7) + TEST (5, 3, 7, 7) + TEST (6, 3, 7, 7) + TEST (7, 3, 7, 7) + TEST (0, 4, 7, 7) + TEST (1, 4, 7, 7) + TEST (2, 4, 7, 7) + TEST (3, 4, 7, 7) + TEST (4, 4, 7, 7) + TEST (5, 4, 7, 7) + TEST (6, 4, 7, 7) + TEST (7, 4, 7, 7) + TEST (0, 5, 7, 7) + TEST (1, 5, 7, 7) + TEST (2, 5, 7, 7) + TEST (3, 5, 7, 7) + TEST (4, 5, 7, 7) + TEST (5, 5, 7, 7) + TEST (6, 5, 7, 7) + TEST (7, 5, 7, 7) + TEST (0, 6, 7, 7) + TEST (1, 6, 7, 7) + TEST (2, 6, 7, 7) + TEST (3, 6, 7, 7) + TEST (4, 6, 7, 7) + TEST (5, 6, 7, 7) + TEST (6, 6, 7, 7) + TEST (7, 6, 7, 7) + TEST (0, 7, 7, 7) + TEST (1, 7, 7, 7) + TEST (2, 7, 7, 7) + TEST (3, 7, 7, 7) + TEST (4, 7, 7, 7) + TEST (5, 7, 7, 7) + TEST (6, 7, 7, 7) + TEST (7, 7, 7, 7) +} + +void check(void) +{ + check0 (); + check1 (); + check2 (); + check3 (); + check4 (); + check5 (); + check6 (); + check7 (); + check8 (); + check9 (); + check10 (); + check11 (); + check12 (); + check13 (); + check14 (); + check15 (); + check16 (); + check17 (); + check18 (); + check19 (); + check20 (); + check21 (); + check22 (); + check23 (); + check24 (); + check25 (); + check26 (); + check27 (); + check28 (); + check29 (); + check30 (); + check31 (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v2df.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v2df.c new file mode 100644 index 000000000..5aefc05f4 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v2df.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "isa-check.h" +#include "sse-os-support.h" + +typedef double S; +typedef double V __attribute__((vector_size(16))); +typedef long long IV __attribute__((vector_size(16))); +typedef union { S s[2]; V v; } U; + +static U i[2], b, c; + +extern int memcmp (const void *, const void *, __SIZE_TYPE__); +#define assert(T) ((T) || (__builtin_trap (), 0)) + +#define TEST(E0, E1) \ + b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1}); \ + c.s[0] = i[0].s[E0]; \ + c.s[1] = i[0].s[E1]; \ + __asm__("" : : : "memory"); \ + assert (memcmp (&b, &c, sizeof(c)) == 0); + +#include "vperm-2-2.inc" + +int main() +{ + check_isa (); + + if (!sse_os_support ()) + exit (0); + + i[0].s[0] = 0; + i[0].s[1] = 1; + i[0].s[2] = 2; + i[0].s[3] = 3; + + check(); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v2di.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v2di.c new file mode 100644 index 000000000..282cce6e9 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v2di.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "isa-check.h" +#include "sse-os-support.h" + +typedef long long S; +typedef long long V __attribute__((vector_size(16))); +typedef long long IV __attribute__((vector_size(16))); +typedef union { S s[2]; V v; } U; + +static U i[2], b, c; + +extern int memcmp (const void *, const void *, __SIZE_TYPE__); +#define assert(T) ((T) || (__builtin_trap (), 0)) + +#define TEST(E0, E1) \ + b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1}); \ + c.s[0] = i[0].s[E0]; \ + c.s[1] = i[0].s[E1]; \ + __asm__("" : : : "memory"); \ + assert (memcmp (&b, &c, sizeof(c)) == 0); + +#include "vperm-2-2.inc" + +int main() +{ + check_isa (); + + if (!sse_os_support ()) + exit (0); + + i[0].s[0] = 0; + i[0].s[1] = 1; + i[0].s[2] = 2; + i[0].s[3] = 3; + + check(); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c new file mode 100644 index 000000000..f16c34bc2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O -msse" } */ +/* { dg-require-effective-target sse } */ + +#include "isa-check.h" +#include "sse-os-support.h" + +typedef float S; +typedef float V __attribute__((vector_size(16))); +typedef int IV __attribute__((vector_size(16))); +typedef union { S s[4]; V v; } U; + +static U i[2], b, c; + +extern int memcmp (const void *, const void *, __SIZE_TYPE__); +#define assert(T) ((T) || (__builtin_trap (), 0)) + +#define TEST(E0, E1, E2, E3) \ + b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \ + c.s[0] = i[0].s[E0]; \ + c.s[1] = i[0].s[E1]; \ + c.s[2] = i[0].s[E2]; \ + c.s[3] = i[0].s[E3]; \ + __asm__("" : : : "memory"); \ + assert (memcmp (&b, &c, sizeof(c)) == 0); + +#include "vperm-4-1.inc" + +int main() +{ + check_isa (); + + if (!sse_os_support ()) + exit (0); + + i[0].s[0] = 0; + i[0].s[1] = 1; + i[0].s[2] = 2; + i[0].s[3] = 3; + i[0].s[4] = 4; + i[0].s[5] = 5; + i[0].s[6] = 6; + i[0].s[7] = 7; + + check(); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c new file mode 100644 index 000000000..12a462370 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O -mssse3" } */ + +#include "isa-check.h" + +typedef float S; +typedef float V __attribute__((vector_size(16))); +typedef int IV __attribute__((vector_size(16))); +typedef union { S s[4]; V v; } U; + +static U i[2], b, c; + +extern int memcmp (const void *, const void *, __SIZE_TYPE__); +#define assert(T) ((T) || (__builtin_trap (), 0)) + +#define TEST(E0, E1, E2, E3) \ + b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \ + c.s[0] = i[0].s[E0]; \ + c.s[1] = i[0].s[E1]; \ + c.s[2] = i[0].s[E2]; \ + c.s[3] = i[0].s[E3]; \ + __asm__("" : : : "memory"); \ + assert (memcmp (&b, &c, sizeof(c)) == 0); + +#include "vperm-4-2.inc" + +int main() +{ + check_isa (); + + i[0].s[0] = 0; + i[0].s[1] = 1; + i[0].s[2] = 2; + i[0].s[3] = 3; + i[0].s[4] = 4; + i[0].s[5] = 5; + i[0].s[6] = 6; + i[0].s[7] = 7; + + check(); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c new file mode 100644 index 000000000..4667f9556 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O -msse2" } */ +/* { dg-require-effective-target sse2 } */ + +#include "isa-check.h" +#include "sse-os-support.h" + +typedef int S; +typedef int V __attribute__((vector_size(16))); +typedef int IV __attribute__((vector_size(16))); +typedef union { S s[4]; V v; } U; + +static U i[2], b, c; + +extern int memcmp (const void *, const void *, __SIZE_TYPE__); +#define assert(T) ((T) || (__builtin_trap (), 0)) + +#define TEST(E0, E1, E2, E3) \ + b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \ + c.s[0] = i[0].s[E0]; \ + c.s[1] = i[0].s[E1]; \ + c.s[2] = i[0].s[E2]; \ + c.s[3] = i[0].s[E3]; \ + __asm__("" : : : "memory"); \ + assert (memcmp (&b, &c, sizeof(c)) == 0); + +#include "vperm-4-1.inc" + +int main() +{ + check_isa (); + + if (!sse_os_support ()) + exit (0); + + i[0].s[0] = 0; + i[0].s[1] = 1; + i[0].s[2] = 2; + i[0].s[3] = 3; + i[0].s[4] = 4; + i[0].s[5] = 5; + i[0].s[6] = 6; + i[0].s[7] = 7; + + check(); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4si-2-sse4.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4si-2-sse4.c new file mode 100644 index 000000000..1f35b825c --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4si-2-sse4.c @@ -0,0 +1,4 @@ +/* { dg-do run } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O -msse4" } */ +#include "vperm-v4si-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c new file mode 100644 index 000000000..930434555 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O -mssse3" } */ + +#include "isa-check.h" + +typedef int S; +typedef int V __attribute__((vector_size(16))); +typedef int IV __attribute__((vector_size(16))); +typedef union { S s[4]; V v; } U; + +static U i[2], b, c; + +extern int memcmp (const void *, const void *, __SIZE_TYPE__); +#define assert(T) ((T) || (__builtin_trap (), 0)) + +#define TEST(E0, E1, E2, E3) \ + b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \ + c.s[0] = i[0].s[E0]; \ + c.s[1] = i[0].s[E1]; \ + c.s[2] = i[0].s[E2]; \ + c.s[3] = i[0].s[E3]; \ + __asm__("" : : : "memory"); \ + assert (memcmp (&b, &c, sizeof(c)) == 0); + +#include "vperm-4-2.inc" + +int main() +{ + check_isa (); + + i[0].s[0] = 0; + i[0].s[1] = 1; + i[0].s[2] = 2; + i[0].s[3] = 3; + i[0].s[4] = 4; + i[0].s[5] = 5; + i[0].s[6] = 6; + i[0].s[7] = 7; + + check(); + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4si-2x.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4si-2x.c new file mode 100644 index 000000000..48d1424b2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm-v4si-2x.c @@ -0,0 +1,4 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O -mxop" } */ +#include "vperm-v4si-2.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm.pl b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm.pl new file mode 100755 index 000000000..80fae9daa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/vperm.pl @@ -0,0 +1,41 @@ +#!/usr/bin/perl + +$nelt = int($ARGV[0]); +$leng = int($ARGV[1]); + +print "/* This file auto-generated with ./vperm.pl $nelt $leng. */\n\n"; + +for ($i = 0; $i < $nelt; ++$i) { $perm[$i] = 0; } +$ncheck = 0; + +for ($i = 0; $i < ($leng * $nelt) ** $nelt; ++$i) +{ + if ($i % 128 == 0) + { + print "}\n\n" if $ncheck > 0; + print "void check$ncheck(void)\n{\n"; + ++$ncheck; + } + + print " TEST ("; + for ($j = 0; $j < $nelt; ++$j) + { + print $perm[$j]; + print ", " if $j < $nelt - 1; + } + print ")\n"; + + INCR: for ($j = 0; $j < $nelt; ++$j) + { + last INCR if ++$perm[$j] < $leng * $nelt; + $perm[$j] = 0; + } +} +print "}\n\n"; + +print "void check(void)\n{\n"; +for ($i = 0; $i < $ncheck; ++$i) +{ + print " check$i ();\n"; +} +print "}\n\n"; diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/warn-vect-op-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/warn-vect-op-1.c new file mode 100644 index 000000000..6fecf9262 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/warn-vect-op-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-mno-sse -Wvector-operation-performance" } */ +#define vector(elcount, type) \ +__attribute__((vector_size((elcount)*sizeof(type)))) type + +int main (int argc, char *argv[]) +{ + vector (4, int) v0 = {argc, 1, 15, 38}; + vector (4, int) v1 = {-4, argc, 2, 11}; + vector (4, int) res[] = + { + v0 + v1, /* { dg-warning "expanded piecewise" } */ + v0 - v1, /* { dg-warning "expanded piecewise" } */ + v0 > v1, /* { dg-warning "expanded piecewise" } */ + v0 & v1, /* { dg-warning "expanded in parallel" } */ + __builtin_shuffle (v0, v1), /* { dg-warning "expanded piecewise" } */ + __builtin_shuffle (v0, v1, v1) /* { dg-warning "expanded piecewise" } */ + }; + + return res[argc][argc]; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/warn-vect-op-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/warn-vect-op-2.c new file mode 100644 index 000000000..6e6311924 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/warn-vect-op-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-mno-sse -Wvector-operation-performance" } */ +#define vector(elcount, type) \ +__attribute__((vector_size((elcount)*sizeof(type)))) type + +int main (int argc, char *argv[]) +{ + vector (16, signed char) v0 = {argc, 1, 15, 38, 12, -1, argc, 2, + argc, 1, 15, 38, 12, -1, argc, 2}; + vector (16, signed char) v1 = {-4, argc, 2, 11, 1, 17, -8, argc, + argc, 1, 15, 38, 12, -1, argc, 2}; + vector (16, signed char) res[] = + { + v0 + v1, /* { dg-warning "expanded in parallel" } */ + v0 - v1, /* { dg-warning "expanded in parallel" } */ + v0 > v1, /* { dg-warning "expanded piecewise" } */ + v0 & v1, /* { dg-warning "expanded in parallel" } */ + __builtin_shuffle (v0, v1), /* { dg-warning "expanded piecewise" } */ + __builtin_shuffle (v0, v1, v1) /* { dg-warning "expanded piecewise" } */ + }; + + return res[argc][argc]; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/warn-vect-op-3.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/warn-vect-op-3.c new file mode 100644 index 000000000..bdbd8b520 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/warn-vect-op-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-mno-sse -Wvector-operation-performance" } */ +#define vector(elcount, type) \ +__attribute__((vector_size((elcount)*sizeof(type)))) type + +int main (int argc, char *argv[]) +{ + vector (8, short) v0 = {argc, 1, 15, 38, 12, -1, argc, 2}; + vector (8, short) v1 = {-4, argc, 2, 11, 1, 17, -8, argc}; + vector (8, short) res[] = + { + v0 + v1, /* { dg-warning "expanded in parallel" } */ + v0 - v1, /* { dg-warning "expanded in parallel" } */ + v0 > v1, /* { dg-warning "expanded piecewise" } */ + v0 & v1, /* { dg-warning "expanded in parallel" } */ + __builtin_shuffle (v0, v1), /* { dg-warning "expanded piecewise" } */ + __builtin_shuffle (v0, v1, v1) /* { dg-warning "expanded piecewise" } */ + }; + + return res[argc][argc]; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wmul-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wmul-1.c new file mode 100644 index 000000000..4ef8385ef --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wmul-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target ia32 } */ + +long long mac(const int *a, const int *b, long long sqr, long long *sum) +{ + int i; + long long dotp = *sum; + + for (i = 0; i < 150; i++) { + dotp += (long long)b[i] * a[i]; + sqr += (long long)b[i] * b[i]; + } + + *sum = dotp; + return sqr; +} + +/* { dg-final { scan-assembler-times "imull" 2 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wmul-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wmul-2.c new file mode 100644 index 000000000..0a8265445 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wmul-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target ia32 } */ + +void vec_mpy(int y[], const int x[], int scaler) +{ + int i; + + for (i = 0; i < 150; i++) + y[i] += (((long long)scaler * x[i]) >> 31); +} + +/* { dg-final { scan-assembler-times "imull" 1 } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wrfsbase-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wrfsbase-1.c new file mode 100644 index 000000000..dc1503817 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wrfsbase-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "wrfsbase\[ \t]+(%|)(edi|ecx)" } } */ + +#include <immintrin.h> + +void +write_fs_base32 (unsigned int base) +{ + _writefsbase_u32 (base); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wrfsbase-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wrfsbase-2.c new file mode 100644 index 000000000..fc4a7b5ff --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wrfsbase-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "wrfsbase\[ \t]+(%|)(rdi|rcx)" } } */ + +#include <immintrin.h> + +void +write_fs_base64 (unsigned long long base) +{ + _writefsbase_u64 (base); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wrgsbase-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wrgsbase-1.c new file mode 100644 index 000000000..5474288be --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wrgsbase-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "wrgsbase\[ \t]+(%|)(edi|ecx)" } } */ + +#include <immintrin.h> + +void +write_gs_base32 (unsigned int base) +{ + _writegsbase_u32 (base); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wrgsbase-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wrgsbase-2.c new file mode 100644 index 000000000..cf9475084 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/wrgsbase-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mfsgsbase" } */ +/* { dg-final { scan-assembler "wrgsbase\[ \t]+(%|)(rdi|rcx)" } } */ + +#include <immintrin.h> + +void +write_gs_base64 (unsigned long long base) +{ + _writegsbase_u64 (base); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xchg-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xchg-1.c new file mode 100644 index 000000000..e81fe49cd --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xchg-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=k8" } */ + +unsigned short good(unsigned short a) +{ + return (a >> 8 | a << 8); +} + +/* { dg-final { scan-assembler "rol" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xchg-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xchg-2.c new file mode 100644 index 000000000..f00fb0f21 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xchg-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + +unsigned short good(unsigned short a) +{ + return (a >> 8 | a << 8); +} + +/* { dg-final { scan-assembler "xchgb" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-check.h b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-check.h new file mode 100644 index 000000000..395abe876 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-check.h @@ -0,0 +1,28 @@ +#include <stdlib.h> + +#include "cpuid.h" +#include "m256-check.h" + +static void xop_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + xop_test (); +} + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run XOP test only if host has XOP support. */ + if (ecx & bit_XOP) + do_test (); + + return 0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-haddX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-haddX.c new file mode 100644 index 000000000..7d3220baf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-haddX.c @@ -0,0 +1,206 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#include "xop-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 10 + +union +{ + __m128i x[NUM]; + signed char ssi[NUM * 16]; + short si[NUM * 8]; + int li[NUM * 4]; + long long lli[NUM * 2]; +} dst, res, src1; + +static void +init_sbyte () +{ + int i; + for (i=0; i < NUM * 16; i++) + src1.ssi[i] = i; +} + +static void +init_sword () +{ + int i; + for (i=0; i < NUM * 8; i++) + src1.si[i] = i; +} + + +static void +init_sdword () +{ + int i; + for (i=0; i < NUM * 4; i++) + src1.li[i] = i; +} + +static int +check_sbyte2word () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 8; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.si[s] = src1.ssi[t] + src1.ssi[t + 1] ; + if (res.si[s] != dst.si[s]) + check_fails++; + } + } +} + +static int +check_sbyte2dword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 4; j++) + { + t = i + (4 * j); + s = (i / 4) + j; + res.li[s] = (src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2] + + src1.ssi[t + 3]); + if (res.li[s] != dst.li[s]) + check_fails++; + } + } + return check_fails++; +} + +static int +check_sbyte2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 2; j++) + { + t = i + (8 * j); + s = (i / 8) + j; + res.lli[s] = ((src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2] + + src1.ssi[t + 3])) + ((src1.ssi[t + 4] + src1.ssi[t +5]) + + (src1.ssi[t + 6] + src1.ssi[t + 7])); + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } + return check_fails++; +} + +static int +check_sword2dword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < (NUM * 8); i = i + 8) + { + for (j = 0; j < 4; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.li[s] = src1.si[t] + src1.si[t + 1] ; + if (res.li[s] != dst.li[s]) + check_fails++; + } + } +} + +static int +check_sword2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 8; i = i + 8) + { + for (j = 0; j < 2; j++) + { + t = i + (4 * j); + s = (i / 4) + j; + res.lli[s] = (src1.si[t] + src1.si[t + 1]) + (src1.si[t + 2] + + src1.si[t + 3]); + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } + return check_fails++; +} + +static int +check_dword2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < (NUM * 4); i = i + 4) + { + for (j = 0; j < 2; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.lli[s] = src1.li[t] + src1.li[t + 1] ; + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } +} + +static void +xop_test (void) +{ + int i; + + init_sbyte (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddw_epi8 (src1.x[i]); + + if (check_sbyte2word()) + abort (); + + + for (i = 0; i < (NUM ); i++) + dst.x[i] = _mm_haddd_epi8 (src1.x[i]); + + if (check_sbyte2dword()) + abort (); + + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddq_epi8 (src1.x[i]); + + if (check_sbyte2qword()) + abort (); + + + init_sword (); + + for (i = 0; i < (NUM ); i++) + dst.x[i] = _mm_haddd_epi16 (src1.x[i]); + + if (check_sword2dword()) + abort (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddq_epi16 (src1.x[i]); + + if (check_sword2qword()) + abort (); + + + init_sdword (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddq_epi32 (src1.x[i]); + + if (check_dword2qword()) + abort (); + +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-hadduX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-hadduX.c new file mode 100644 index 000000000..9c7ea9a2a --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-hadduX.c @@ -0,0 +1,207 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#include "xop-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 10 + +union +{ + __m128i x[NUM]; + unsigned char ssi[NUM * 16]; + unsigned short si[NUM * 8]; + unsigned int li[NUM * 4]; + unsigned long long lli[NUM * 2]; +} dst, res, src1; + +static void +init_byte () +{ + int i; + for (i=0; i < NUM * 16; i++) + src1.ssi[i] = i; +} + +static void +init_word () +{ + int i; + for (i=0; i < NUM * 8; i++) + src1.si[i] = i; +} + + +static void +init_dword () +{ + int i; + for (i=0; i < NUM * 4; i++) + src1.li[i] = i; +} + +static int +check_byte2word () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 8; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.si[s] = src1.ssi[t] + src1.ssi[t + 1] ; + if (res.si[s] != dst.si[s]) + check_fails++; + } + } +} + +static int +check_byte2dword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 4; j++) + { + t = i + (4 * j); + s = (i / 4) + j; + res.li[s] = (src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2] + + src1.ssi[t + 3]); + if (res.li[s] != dst.li[s]) + check_fails++; + } + } + return check_fails++; +} + +static int +check_byte2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 2; j++) + { + t = i + (8 * j); + s = (i / 8) + j; + res.lli[s] = ((src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2] + + src1.ssi[t + 3])) + ((src1.ssi[t + 4] + src1.ssi[t +5]) + + (src1.ssi[t + 6] + src1.ssi[t + 7])); + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } + return check_fails++; +} + +static int +check_word2dword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < (NUM * 8); i = i + 8) + { + for (j = 0; j < 4; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.li[s] = src1.si[t] + src1.si[t + 1] ; + if (res.li[s] != dst.li[s]) + check_fails++; + } + } +} + +static int +check_word2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 8; i = i + 8) + { + for (j = 0; j < 2; j++) + { + t = i + (4 * j); + s = (i / 4) + j; + res.lli[s] = (src1.si[t] + src1.si[t + 1]) + (src1.si[t + 2] + + src1.si[t + 3]); + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } + return check_fails++; +} + +static int +check_dword2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < (NUM * 4); i = i + 4) + { + for (j = 0; j < 2; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.lli[s] = src1.li[t] + src1.li[t + 1] ; + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } +} + +static void +xop_test (void) +{ + int i; + + /* Check haddubw */ + init_byte (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddw_epu8 (src1.x[i]); + + if (check_byte2word()) + abort (); + + /* Check haddubd */ + for (i = 0; i < (NUM ); i++) + dst.x[i] = _mm_haddd_epu8 (src1.x[i]); + + if (check_byte2dword()) + abort (); + + /* Check haddubq */ + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddq_epu8 (src1.x[i]); + + if (check_byte2qword()) + abort (); + + /* Check hadduwd */ + init_word (); + + for (i = 0; i < (NUM ); i++) + dst.x[i] = _mm_haddd_epu16 (src1.x[i]); + + if (check_word2dword()) + abort (); + + /* Check haddbuwq */ + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddq_epu16 (src1.x[i]); + + if (check_word2qword()) + abort (); + + /* Check hadudq */ + init_dword (); + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddq_epu32 (src1.x[i]); + + if (check_dword2qword()) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-hsubX.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-hsubX.c new file mode 100644 index 000000000..f0fa9b312 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-hsubX.c @@ -0,0 +1,128 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#include "xop-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 10 + +union +{ + __m128i x[NUM]; + signed char ssi[NUM * 16]; + short si[NUM * 8]; + int li[NUM * 4]; + long long lli[NUM * 2]; +} dst, res, src1; + +static void +init_sbyte () +{ + int i; + for (i=0; i < NUM * 16; i++) + src1.ssi[i] = i; +} + +static void +init_sword () +{ + int i; + for (i=0; i < NUM * 8; i++) + src1.si[i] = i; +} + + +static void +init_sdword () +{ + int i; + for (i=0; i < NUM * 4; i++) + src1.li[i] = i; +} + +static int +check_sbyte2word () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 8; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.si[s] = src1.ssi[t] - src1.ssi[t + 1] ; + if (res.si[s] != dst.si[s]) + check_fails++; + } + } +} + +static int +check_sword2dword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < (NUM * 8); i = i + 8) + { + for (j = 0; j < 4; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.li[s] = src1.si[t] - src1.si[t + 1] ; + if (res.li[s] != dst.li[s]) + check_fails++; + } + } +} + +static int +check_dword2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < (NUM * 4); i = i + 4) + { + for (j = 0; j < 2; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.lli[s] = src1.li[t] - src1.li[t + 1] ; + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } +} + +static void +xop_test (void) +{ + int i; + + /* Check hsubbw */ + init_sbyte (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_hsubw_epi8 (src1.x[i]); + + if (check_sbyte2word()) + abort (); + + + /* Check hsubwd */ + init_sword (); + + for (i = 0; i < (NUM ); i++) + dst.x[i] = _mm_hsubd_epi16 (src1.x[i]); + + if (check_sword2dword()) + abort (); + + /* Check hsubdq */ + init_sdword (); + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_hsubq_epi32 (src1.x[i]); + + if (check_dword2qword()) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c new file mode 100644 index 000000000..0730987e1 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c @@ -0,0 +1,36 @@ +/* Test that the compiler properly optimizes floating point multiply and add + instructions vector into pmacsdd/etc. on XOP systems. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + int i32[SIZE]; + long i64[SIZE]; +} a, b, c, d; + +void +imul32_to_64 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.i64[i] = ((long)b.i32[i]) * ((long)c.i32[i]); +} + +int main () +{ + imul32_to_64 (); + exit (0); +} + +/* { dg-final { scan-assembler "vpmuldq" } } */ +/* { dg-final { scan-assembler "vpmacsdqh" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c new file mode 100644 index 000000000..382677e60 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c @@ -0,0 +1,36 @@ +/* Test that the compiler properly optimizes floating point multiply and add + instructions vector into pmacsdd/etc. on XOP systems. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + long i64[SIZE]; +} a, b, c, d; + +void +imul64 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.i64[i] = b.i64[i] * c.i64[i]; +} + +int main () +{ + imul64 (); + exit (0); +} + +/* { dg-final { scan-assembler "vpmulld" } } */ +/* { dg-final { scan-assembler "vphadddq" } } */ +/* { dg-final { scan-assembler "vpmacsdql" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-mul-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-mul-1.c new file mode 100644 index 000000000..47ef1bc02 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-mul-1.c @@ -0,0 +1,13 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O3 -mxop" } */ + +#ifndef CHECK_H +#define CHECK_H "xop-check.h" +#endif + +#ifndef TEST +#define TEST xop_test +#endif + +#include "sse2-mul-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-pcmov.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-pcmov.c new file mode 100644 index 000000000..75ed433cf --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-pcmov.c @@ -0,0 +1,22 @@ +/* Test that the compiler properly optimizes conditional floating point moves + into the pcmov instruction on XOP systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mxop" } */ + +extern void exit (int); + +double dbl_test (double a, double b, double c, double d) +{ + return (a > b) ? c : d; +} + +double dbl_a = 1, dbl_b = 2, dbl_c = 3, dbl_d = 4, dbl_e; + +int main() +{ + dbl_e = dbl_test (dbl_a, dbl_b, dbl_c, dbl_d); + exit (0); +} + +/* { dg-final { scan-assembler "vpcmov" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-pcmov2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-pcmov2.c new file mode 100644 index 000000000..6b6bd2169 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-pcmov2.c @@ -0,0 +1,22 @@ +/* Test that the compiler properly optimizes conditional floating point moves + into the pcmov instruction on XOP systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mxop" } */ + +extern void exit (int); + +float flt_test (float a, float b, float c, float d) +{ + return (a > b) ? c : d; +} + +float flt_a = 1, flt_b = 2, flt_c = 3, flt_d = 4, flt_e; + +int main() +{ + flt_e = flt_test (flt_a, flt_b, flt_c, flt_d); + exit (0); +} + +/* { dg-final { scan-assembler "vpcmov" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate1-int.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate1-int.c new file mode 100644 index 000000000..a58cd726b --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate1-int.c @@ -0,0 +1,63 @@ +/* PR target/49411 */ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#include "xop-check.h" + +#include <x86intrin.h> + +extern void abort (void); + +union +{ + __m128i v; + unsigned char c[16]; + unsigned short s[8]; + unsigned int i[4]; + unsigned long long l[2]; +} a, b, c, d; + +#define TEST1(F, N, S, SS) \ +do { \ + for (i = 0; i < sizeof (a.F) / sizeof (a.F[0]); i++) \ + a.F[i] = i * 17; \ + s = _mm_set1_epi##SS (N); \ + b.v = _mm_roti_epi##S (a.v, N); \ + c.v = _mm_rot_epi##S (a.v, s); \ + for (i = 0; i < sizeof (a.F) / sizeof (a.F[0]); i++) \ + { \ + int mask = __CHAR_BIT__ * sizeof (a.F[i]) - 1; \ + d.F[i] = a.F[i] << (N & mask); \ + if (N & mask) \ + d.F[i] |= a.F[i] >> (mask + 1 - (N & mask)); \ + if (b.F[i] != c.F[i] || b.F[i] != d.F[i]) \ + abort (); \ + } \ +} while (0) +#define TEST(N) \ + TEST1 (c, N, 8, 8); \ + TEST1 (s, N, 16, 16); \ + TEST1 (i, N, 32, 32); \ + TEST1 (l, N, 64, 64x) + +volatile int n; + +static void +xop_test (void) +{ + unsigned int i; + __m128i s; + +#ifndef NON_CONST + TEST (5); + TEST (-5); + TEST (0); + TEST (31); +#else + n = 5; TEST (n); + n = -5; TEST (n); + n = 0; TEST (n); + n = 31; TEST (n); +#endif +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c new file mode 100644 index 000000000..f2b9eb845 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c @@ -0,0 +1,34 @@ +/* Test that the compiler properly optimizes vector rotate instructions vector + into prot on XOP systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + unsigned u32[SIZE]; +} a, b, c; + +void +left_rotate32 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.u32[i] = (b.u32[i] << ((sizeof (int) * 8) - 4)) | (b.u32[i] >> 4); +} + +int +main () +{ + left_rotate32 (); + exit (0); +} + +/* { dg-final { scan-assembler "vprotd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate2-int.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate2-int.c new file mode 100644 index 000000000..634a51a84 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate2-int.c @@ -0,0 +1,7 @@ +/* PR target/49411 */ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#define NON_CONST 1 +#include "xop-rotate1-int.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c new file mode 100644 index 000000000..11d40023f --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c @@ -0,0 +1,34 @@ +/* Test that the compiler properly optimizes vector rotate instructions vector + into prot on XOP systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + unsigned u32[SIZE]; +} a, b, c; + +void +right_rotate32_b (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.u32[i] = (b.u32[i] >> ((sizeof (int) * 8) - 4)) | (b.u32[i] << 4); +} + +int +main () +{ + right_rotate (); + exit (0); +} + +/* { dg-final { scan-assembler "vprot" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c new file mode 100644 index 000000000..eb3c61431 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c @@ -0,0 +1,33 @@ +/* Test that the compiler properly optimizes vector rotate instructions vector + into prot on XOP systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + unsigned u32[SIZE]; +} a, b, c; + +void +vector_rotate32 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.u32[i] = (b.u32[i] >> ((sizeof (int) * 8) - c.u32[i])) | (b.u32[i] << c.u32[i]); +} + +int main () +{ + vector_rotate32 (); + exit (0); +} + +/* { dg-final { scan-assembler "vprotd" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c new file mode 100644 index 000000000..16b3a6b75 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c @@ -0,0 +1,34 @@ +/* Test that the compiler properly optimizes vector shift instructions into + psha/pshl on XOP systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + int i32[SIZE]; + unsigned u32[SIZE]; +} a, b, c; + +void +left_shift32 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.i32[i] = b.i32[i] << c.i32[i]; +} + +int main () +{ + left_shfit32 (); + exit (0); +} + +/* { dg-final { scan-assembler "vpshad" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c new file mode 100644 index 000000000..1f1ed630e --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c @@ -0,0 +1,34 @@ +/* Test that the compiler properly optimizes vector shift instructions into + psha/pshl on XOP systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + int i32[SIZE]; + unsigned u32[SIZE]; +} a, b, c; + +void +right_sign_shift32 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.i32[i] = b.i32[i] >> c.i32[i]; +} + +int main () +{ + right_sign_shfit32 (); + exit (0); +} + +/* { dg-final { scan-assembler "vpshad" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c new file mode 100644 index 000000000..de6417876 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c @@ -0,0 +1,34 @@ +/* Test that the compiler properly optimizes vector shift instructions into + psha/pshl on XOP systems. */ + +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + int i32[SIZE]; + unsigned u32[SIZE]; +} a, b, c; + +void +right_uns_shift32 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.u32[i] = b.u32[i] >> c.i32[i]; +} + +int main () +{ + right_uns_shfit32 (); + exit (0); +} + +/* { dg-final { scan-assembler "vpshld" } } */ diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vpermil2pd-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vpermil2pd-1.c new file mode 100644 index 000000000..83cb5163d --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vpermil2pd-1.c @@ -0,0 +1,57 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#include "xop-check.h" + +#include <x86intrin.h> + +#ifndef ZERO_MATCH +#define ZERO_MATCH 2 +#endif + +static double +select2dp(double *src1, double *src2, long long sel) +{ + double tmp = 0.0; + + if ((sel & 0x3) == 0) tmp = src1[0]; + if ((sel & 0x3) == 1) tmp = src1[1]; + if ((sel & 0x3) == 2) tmp = src2[0]; + if ((sel & 0x3) == 3) tmp = src2[1]; + + return tmp; +} + +static double +sel_and_condzerodp(double *src1, double *src2, long long sel, int imm8) +{ + double tmp; + + tmp = select2dp(src1, src2, sel & 0x3); + + if (((imm8 & 0x3) == 2) && ((sel & 0x4) == 0x4)) tmp = 0; + if (((imm8 & 0x3) == 3) && ((sel & 0x4) == 0x0)) tmp = 0; + + return tmp; +} + +void static +xop_test () +{ + union128d s1, s2, u; + union128i_q s3; + double e[2]; + + s1.x = _mm_set_pd (1, 2); + s2.x = _mm_set_pd (3, 4); + s3.x = _mm_set_epi64x (1, 2); + u.x = _mm_permute2_pd(s1.x, s2.x, s3.x, ZERO_MATCH); + + e[0] = sel_and_condzerodp (s1.a, s2.a, (s3.a[0] & 0xe)>>1, ZERO_MATCH); + e[1] = sel_and_condzerodp (s1.a, s2.a, (s3.a[1] & 0xe)>>1, ZERO_MATCH); + + if (check_union128d (u, e)) + abort (); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vpermil2pd-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vpermil2pd-256-1.c new file mode 100644 index 000000000..ab2079afa --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vpermil2pd-256-1.c @@ -0,0 +1,58 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#include "xop-check.h" + +#include <x86intrin.h> + +#ifndef ZERO_MATCH +#define ZERO_MATCH 1 +#endif + +static double +select2dp(double *src1, double *src2, long long sel) +{ + double tmp = 3.414; + + if ((sel & 0x3) == 0) tmp = src1[0]; + if ((sel & 0x3) == 1) tmp = src1[1]; + if ((sel & 0x3) == 2) tmp = src2[0]; + if ((sel & 0x3) == 3) tmp = src2[1]; + + return tmp; +} + +static double +sel_and_condzerodp(double *src1, double *src2, long long sel, int imm8) +{ + double tmp; + + tmp = select2dp(src1, src2, sel); + + if (((imm8 & 0x3) == 2) && ((sel & 0x4) == 0x4)) tmp = 0; + if (((imm8 & 0x3) == 3) && ((sel & 0x4) == 0x0)) tmp = 0; + + return tmp; +} + +void static +xop_test () +{ + union256d u, s1, s2; + double e[4] = {0.0}; + union256i_q s3; + + s1.x = _mm256_set_pd (1, 2, 3, 4); + s2.x = _mm256_set_pd (5, 6, 7, 8); + s3.x = _mm256_set_epi64x (0, 1, 2, 3); + u.x = _mm256_permute2_pd(s1.x, s2.x, s3.x, ZERO_MATCH); + + e[0] = sel_and_condzerodp (s1.a, s2.a, (s3.a[0] & 0xe)>>1, ZERO_MATCH); + e[1] = sel_and_condzerodp (s1.a, s2.a, (s3.a[1] & 0xe)>>1, ZERO_MATCH); + e[2] = sel_and_condzerodp (s1.a + 2, s2.a + 2, (s3.a[2] & 0xe)>>1, ZERO_MATCH); + e[3] = sel_and_condzerodp (s1.a + 2, s2.a + 2, (s3.a[3] & 0xe)>>1, ZERO_MATCH); + + if (check_union256d (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vpermil2ps-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vpermil2ps-1.c new file mode 100644 index 000000000..90e59ae92 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vpermil2ps-1.c @@ -0,0 +1,64 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#include "xop-check.h" + +#include <x86intrin.h> + +#ifndef ZERO_MATCH +#define ZERO_MATCH 1 +#endif + +static float +select2sp(float *src1, float *src2, int sel) +{ + float tmp; + + if ((sel & 0x7) == 0) tmp = src1[0]; + if ((sel & 0x7) == 1) tmp = src1[1]; + if ((sel & 0x7) == 2) tmp = src1[2]; + if ((sel & 0x7) == 3) tmp = src1[3]; + if ((sel & 0x7) == 4) tmp = src2[0]; + if ((sel & 0x7) == 5) tmp = src2[1]; + if ((sel & 0x7) == 6) tmp = src2[2]; + if ((sel & 0x7) == 7) tmp = src2[3]; + + return tmp; +} +static float +sel_and_condzerosp(float *src1, float *src2, int sel, int imm8) +{ + float tmp; + + tmp = select2sp(src1, src2, sel & 0x7); + + if (((imm8 & 0x3) == 2) && ((sel & 0x8) == 0x8)) tmp = 0; + if (((imm8 & 0x3) == 3) && ((sel & 0x8) == 0x0)) tmp = 0; + + return tmp; +} + +void static +xop_test () +{ + int i; + union128 source1, source2, u; + union128i_d source3; + float s1[4] = {1, 2, 3, 4}; + float s2[4] = {5, 6, 7, 8}; + int s3[4] = {0, 1, 0, 1}; + float e[4]; + + source1.x = _mm_loadu_ps(s1); + source2.x = _mm_loadu_ps(s2); + source3.x = _mm_loadu_si128((__m128i*) s3); + u.x = _mm_permute2_ps(source1.x, source2.x, source3.x, ZERO_MATCH); + + for (i = 0; i < 4; ++i) { + e[i] = sel_and_condzerosp(&s1[i & 0x4], &s2[i & 0x4], s3[i] & 0xf, ZERO_MATCH & 0x3); + } + + if (check_union128 (u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vpermil2ps-256-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vpermil2ps-256-1.c new file mode 100644 index 000000000..d458d3e49 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vpermil2ps-256-1.c @@ -0,0 +1,64 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#include "xop-check.h" + +#include <x86intrin.h> + +#ifndef ZERO_MATCH +#define ZERO_MATCH 3 +#endif + +static float +select2sp(float *src1, float *src2, int sel) +{ + float tmp; + + if ((sel & 0x7) == 0) tmp = src1[0]; + if ((sel & 0x7) == 1) tmp = src1[1]; + if ((sel & 0x7) == 2) tmp = src1[2]; + if ((sel & 0x7) == 3) tmp = src1[3]; + if ((sel & 0x7) == 4) tmp = src2[0]; + if ((sel & 0x7) == 5) tmp = src2[1]; + if ((sel & 0x7) == 6) tmp = src2[2]; + if ((sel & 0x7) == 7) tmp = src2[3]; + + return tmp; +} +static float +sel_and_condzerosp(float *src1, float *src2, int sel, int imm8) +{ + float tmp; + + tmp = select2sp(src1, src2, sel & 0x7); + + if (((imm8 & 0x3) == 2) && ((sel & 0x8) == 0x8)) tmp = 0; + if (((imm8 & 0x3) == 3) && ((sel & 0x8) == 0x0)) tmp = 0; + + return tmp; +} + +void static +xop_test () +{ + int i; + union256 source1, source2, u; + union256i_d source3; + float s1[8]={1, 2, 3, 4, 5, 6, 7, 8}; + float s2[8]={9, 10, 11, 12, 13, 14, 15, 16}; + int s3[8]={11, 2, 3, 15, 5, 12, 7, 8}; + float e[8]; + + source1.x = _mm256_loadu_ps(s1); + source2.x = _mm256_loadu_ps(s2); + source3.x = _mm256_loadu_si256((__m256i*) s3); + u.x = _mm256_permute2_ps(source1.x, source2.x, source3.x, ZERO_MATCH); + + for (i = 0; i < 8; ++i) { + e[i] = sel_and_condzerosp(&s1[i & 0x4], &s2[i & 0x4], s3[i] & 0xf, ZERO_MATCH & 0x3); + } + + if (check_union256(u, e)) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vshift-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vshift-1.c new file mode 100644 index 000000000..ee3d29903 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vshift-1.c @@ -0,0 +1,145 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mxop" } */ +/* { dg-require-effective-target xop } */ + +#ifndef CHECK_H +#define CHECK_H "xop-check.h" +#endif + +#ifndef TEST +#define TEST xop_test +#endif + +#include CHECK_H + +#define N 64 + +#ifndef TYPE1 +#define TYPE1 int +#define TYPE2 long long +#endif + +/* mingw runtime don't provide random(). */ +#ifdef __MINGW32__ +#define random rand +#endif + +signed TYPE1 a[N], b[N], g[N]; +unsigned TYPE1 c[N], h[N]; +signed TYPE2 d[N], e[N], j[N]; +unsigned TYPE2 f[N], k[N]; + +__attribute__((noinline)) void +f1 (void) +{ + int i; + for (i = 0; i < N; i++) + g[i] = a[i] << b[i]; +} + +__attribute__((noinline)) void +f2 (void) +{ + int i; + for (i = 0; i < N; i++) + g[i] = a[i] >> b[i]; +} + +__attribute__((noinline)) void +f3 (void) +{ + int i; + for (i = 0; i < N; i++) + h[i] = c[i] >> b[i]; +} + +__attribute__((noinline)) void +f4 (void) +{ + int i; + for (i = 0; i < N; i++) + j[i] = d[i] << e[i]; +} + +__attribute__((noinline)) void +f5 (void) +{ + int i; + for (i = 0; i < N; i++) + j[i] = d[i] >> e[i]; +} + +__attribute__((noinline)) void +f6 (void) +{ + int i; + for (i = 0; i < N; i++) + k[i] = f[i] >> e[i]; +} + +__attribute__((noinline)) void +f7 (void) +{ + int i; + for (i = 0; i < N; i++) + j[i] = d[i] << b[i]; +} + +__attribute__((noinline)) void +f8 (void) +{ + int i; + for (i = 0; i < N; i++) + j[i] = d[i] >> b[i]; +} + +__attribute__((noinline)) void +f9 (void) +{ + int i; + for (i = 0; i < N; i++) + k[i] = f[i] >> b[i]; +} + +static void +TEST () +{ + int i; + for (i = 0; i < N; i++) + { + asm (""); + c[i] = (random () << 1) | (random () & 1); + b[i] = (i * 85) & (sizeof (TYPE1) * __CHAR_BIT__ - 1); + a[i] = c[i]; + d[i] = (random () << 1) | (random () & 1); + d[i] |= (unsigned long long) c[i] << 32; + e[i] = (i * 85) & (sizeof (TYPE2) * __CHAR_BIT__ - 1); + f[i] = d[i]; + } + f1 (); + f3 (); + f4 (); + f6 (); + for (i = 0; i < N; i++) + if (g[i] != (signed TYPE1) (a[i] << b[i]) + || h[i] != (unsigned TYPE1) (c[i] >> b[i]) + || j[i] != (signed TYPE2) (d[i] << e[i]) + || k[i] != (unsigned TYPE2) (f[i] >> e[i])) + abort (); + f2 (); + f5 (); + f9 (); + for (i = 0; i < N; i++) + if (g[i] != (signed TYPE1) (a[i] >> b[i]) + || j[i] != (signed TYPE2) (d[i] >> e[i]) + || k[i] != (unsigned TYPE2) (f[i] >> b[i])) + abort (); + f7 (); + for (i = 0; i < N; i++) + if (j[i] != (signed TYPE2) (d[i] << b[i])) + abort (); + f8 (); + for (i = 0; i < N; i++) + if (j[i] != (signed TYPE2) (d[i] >> b[i])) + abort (); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vshift-2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vshift-2.c new file mode 100644 index 000000000..81e86d098 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xop-vshift-2.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mxop" } */ +/* { dg-require-effective-target xop } */ + +#define TYPE1 char +#define TYPE2 short + +#include "xop-vshift-1.c" diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xorps-sse.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xorps-sse.c new file mode 100644 index 000000000..e9c0a2e73 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xorps-sse.c @@ -0,0 +1,14 @@ +/* Test that we generate xorps instruction when pxor is not available. */ +/* { dg-do compile } */ +/* { dg-options "-O -msse -mno-sse2" } */ +/* { dg-final { scan-assembler "xorps\[ \t\]" } } */ + +#define vector __attribute__ ((vector_size (16))) + +vector int i(vector int f) +{ + vector int g = { 0x80000000, 0, 0x80000000, 0 }; + vector int f_int = (vector int) f; + return (f_int ^ g); +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xorps-sse2.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xorps-sse2.c new file mode 100644 index 000000000..b9576d970 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xorps-sse2.c @@ -0,0 +1,15 @@ +/* Test that we generate xorps when the result is used in FP math. */ +/* { dg-do compile } */ +/* { dg-options "-O -msse2 -mno-sse3" } */ +/* { dg-final { scan-assembler "xorps\[ \t\]" } } */ +/* { dg-final { scan-assembler-not "pxor" } } */ + +#define vector __attribute__ ((vector_size (16))) + +vector float i(vector float f, vector float h) +{ + vector int g = { 0x80000000, 0, 0x80000000, 0 }; + vector int f_int = (vector int) f; + return ((vector float) (f_int ^ g)) + h; +} + diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xorps.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xorps.c new file mode 100644 index 000000000..6803a4d89 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xorps.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -msse2" } */ + +typedef float __m128 __attribute__ ((vector_size (16))); + +static __inline __m128 +_mm_mul_ps (__m128 __A, __m128 __B) +{ + return __builtin_ia32_mulps (__A, __B); +} + +static __inline __m128 +_mm_sub_ps (__m128 __A, __m128 __B) +{ + return __builtin_ia32_subps (__A, __B); +} + +__m128 POW_FUNC (__m128 x, __m128 y) +{ + __m128 xmm0 = x, xmm1 = y, xmm2; + + xmm0 = __builtin_ia32_xorps (xmm1, xmm1); + + xmm0 = _mm_mul_ps (xmm0, xmm1); + + xmm0 = _mm_sub_ps (xmm0, xmm1); + + xmm0 = _mm_mul_ps (xmm0, xmm1); + + return xmm0; +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xrstor-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xrstor-1.c new file mode 100644 index 000000000..3e7013948 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xrstor-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx -O2" } */ +/* { dg-final { scan-assembler "xrstor\[ \\t\]" } } */ + +#include <x86intrin.h> + +void extern +xsave_test (void) +{ + char xsave_region [512] __attribute__((aligned(64))); + _xrstor (xsave_region, ((long long) 0xA0000000F)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xrstor64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xrstor64-1.c new file mode 100644 index 000000000..3cf2a66cc --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xrstor64-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mxsave -O2" } */ +/* { dg-final { scan-assembler "xrstor64\[ \\t\]" } } */ + +#include <x86intrin.h> + +void extern +xsave_test (void) +{ + char xsave_region [512] __attribute__((aligned(64))); + _xrstor64 (xsave_region, ((long long) 0xA0000000F)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xsave-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xsave-1.c new file mode 100644 index 000000000..9eee59739 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xsave-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mxsave -O2" } */ +/* { dg-final { scan-assembler "xsave\[ \\t\]" } } */ + +#include <x86intrin.h> + +void extern +xsave_test (void) +{ + char xsave_region [512] __attribute__((aligned(64))); + _xsave (xsave_region, ((long long) 0xA0000000F)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xsave64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xsave64-1.c new file mode 100644 index 000000000..661da9171 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xsave64-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mxsave -O2" } */ +/* { dg-final { scan-assembler "xsave64\[ \\t\]" } } */ + +#include <x86intrin.h> + +void extern +xsave_test (void) +{ + char xsave_region [512] __attribute__((aligned(64))); + _xsave64 (xsave_region, ((long long) 0xA0000000F)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xsaveopt-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xsaveopt-1.c new file mode 100644 index 000000000..b08a50a23 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xsaveopt-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mxsaveopt -O2" } */ +/* { dg-final { scan-assembler "xsaveopt\[ \\t\]" } } */ + +#include <x86intrin.h> + +void extern +xsave_test (void) +{ + char xsaveopt_region [512] __attribute__((aligned(64))); + _xsaveopt (xsaveopt_region, ((long long) 0xA0000000F)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xsaveopt64-1.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xsaveopt64-1.c new file mode 100644 index 000000000..f7864fe39 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/xsaveopt64-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mxsaveopt -O2" } */ +/* { dg-final { scan-assembler "xsaveopt64\[ \\t\]" } } */ + +#include <x86intrin.h> + +void extern +xsave_test (void) +{ + char xsaveopt_region [512] __attribute__((aligned(64))); + _xsaveopt64 (xsaveopt_region, ((long long) 0xA0000000F)); +} diff --git a/gcc-4.8.1/gcc/testsuite/gcc.target/i386/zee.c b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/zee.c new file mode 100644 index 000000000..1975b02b2 --- /dev/null +++ b/gcc-4.8.1/gcc/testsuite/gcc.target/i386/zee.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! { ia32 } } } } */ +/* { dg-options "-O2 -fzee" } */ +/* { dg-final { scan-assembler-not "mov\[\\t \]+\(%\[\^,\]+\),\[\\t \]*\\1" } } */ +int mask[100]; +int foo(unsigned x) +{ + if (x < 10) + x = x * 45; + else + x = x * 78; + return mask[x]; +} |