Sync down FSF r184235@google/gcc-4_6_2-mobile branch

1) Get mostly new patches from FSF gcc-4.6 branch
2) Fix PR52129
3) Insert GNU-stack note for all ARM targets

Change-Id: I2b9926981210e517e4021242908074319a91d6bd

9 files changed, 383 insertions, 23 deletions

diff --git a/gcc-4.6/libgcc/ChangeLog b/gcc-4.6/libgcc/ChangeLog
index ec575f0c1..c5b1d1cd6 100644
--- a/gcc-4.6/libgcc/ChangeLog
+++ b/gcc-4.6/libgcc/ChangeLog
@@ -1,3 +1,32 @@
+2011-12-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Backport from mainline
+	2011-12-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* generic-morestack.c (__generic_morestack_set_initial_sp): Check
+	__GLIBC__ instead of __linux__ when using __SIGRTMIN.
+
+2011-11-23  Gerald Pfeifer  <gerald@pfeifer.com>
+
+	* config.host (*-*-freebsd[12], *-*-freebsd[12].*,
+	*-*-freebsd*aout*): Remove.
+
+2011-10-26  Release Manager
+
+	* GCC 4.6.2 released.
+
+2011-08-24  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	PR target/50090
+	* config/arm/bpabi-lib.h (RENAME_LIBRARY_SET): Delete.
+	(RENAME_LIBRARY): Use a C-level alias instead of an assembly one.
+
+2011-08-23  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/64/sfp-machine.h (ASM_INVALID): New define.
+	(ASM_DIVZERO): Ditto.
+	(FP_HANLDE_EXCEPTIONS): Use ASM_INVALID and ASM_DIVZERO.
+
 2011-06-27  Release Manager
 
 	* GCC 4.6.1 released.
diff --git a/gcc-4.6/libgcc/ChangeLog.google-4_6 b/gcc-4.6/libgcc/ChangeLog.google-4_6
new file mode 100644
index 000000000..7fd222a3a
--- /dev/null
+++ b/gcc-4.6/libgcc/ChangeLog.google-4_6
@@ -0,0 +1,27 @@
+2012-01-11  Sriraman Tallam  <tmsriram@google.com>
+
+	Add support to detect AMD Family 15h(0x15) processors, version 1 and 2.
+
+	* i386-cpuinfo.c (__cpu_is_amdfam15h_bdver1): New member in __cpu_model
+	struct.
+	(__cpu_is_amdfam15h_bdver2): New member in __cpu_model struct.
+	(__cpu_model): Rename __cpu_is_amdfam10 to __cpu_is_amdfam10h.
+	Rename __cpu_is_amdfam10_barcelona to __cpu_is_amdfam10h_barcelona.
+	Rename __cpu_is_amdfam10_shanghai to __cpu_is_amdfam10h_shanghai.
+	Rename __cpu_is_amdfam10_istanbul to __cpu_is_amdfam10h_istanbul.
+	(get_amd_cpu): Check for family 15h processors.
+	(cpu_indicator_init): Adjust model and family for AMD processors.
+	Refactor code.
+
+2011-12-17  Sriraman Tallam  <tmsriram@google.com>
+
+	* config/i386/i386-cpuinfo.c (__processor_model): Add new members
+	__cpu_is_intel_corei7 and __cpu_is_amdfam10.
+	(get_amd_cpu): Set __cpu_is_amdfam10.
+	(get_intel_cpu): Set __cpu_is_intel_corei7.
+
+2011-09-01  Sriraman Tallam  <tmsriram@google.com>
+	
+	* config/i386/i386-cpuinfo.c: New file.
+	* config/i386/t-cpuinfo: New file.
+	* config.host: Add t-cpuinfo to link i386-cpuinfo.o with libgcc
diff --git a/gcc-4.6/libgcc/config.host b/gcc-4.6/libgcc/config.host
index d3f64d687..2516c0a0c 100644
--- a/gcc-4.6/libgcc/config.host
+++ b/gcc-4.6/libgcc/config.host
@@ -145,15 +145,6 @@ case ${host} in
   asm_hidden_op=.private_extern
   tmake_file="t-darwin ${cpu_type}/t-darwin t-slibgcc-darwin"
   ;;
-*-*-freebsd[12] | *-*-freebsd[12].* | *-*-freebsd*aout*)
-  # This is the place-holder for the generic a.out configuration
-  # of FreeBSD.  No actual configuration resides here since
-  # there was only ever a bare-bones ix86 configuration for
-  # a.out and it exists solely in the machine-specific section.
-  # This place-holder must exist to avoid dropping into
-  # the generic ELF configuration of FreeBSD (i.e. it must be
-  # ordered before that section).
-  ;;
 *-*-freebsd*)
   # This is the generic ELF configuration of FreeBSD.  Later
   # machine-specific sections may refine and add to this
@@ -609,7 +600,7 @@ case ${host} in
 i[34567]86-*-linux* | x86_64-*-linux* | \
   i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | \
   i[34567]86-*-gnu*)
-	tmake_file="${tmake_file} t-tls"
+	tmake_file="${tmake_file} t-tls i386/t-cpuinfo"
 	if test "$libgcc_cv_cfi" = "yes"; then
 		tmake_file="${tmake_file} t-stack i386/t-stack-i386"
 	fi
diff --git a/gcc-4.6/libgcc/config/arm/bpabi-lib.h b/gcc-4.6/libgcc/config/arm/bpabi-lib.h
index 49a28c3c2..fc0e59507 100644
--- a/gcc-4.6/libgcc/config/arm/bpabi-lib.h
+++ b/gcc-4.6/libgcc/config/arm/bpabi-lib.h
@@ -20,17 +20,10 @@
    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
    <http://www.gnu.org/licenses/>.  */
 
-#if defined (__thumb__)
-#define RENAME_LIBRARY_SET ".thumb_set"
-#else
-#define RENAME_LIBRARY_SET ".set"
-#endif
-
 /* Make __aeabi_AEABI_NAME an alias for __GCC_NAME.  */
 #define RENAME_LIBRARY(GCC_NAME, AEABI_NAME)		\
-  __asm__ (".globl\t__aeabi_" #AEABI_NAME "\n"		\
-	   RENAME_LIBRARY_SET "\t__aeabi_" #AEABI_NAME 	\
-	     ", __" #GCC_NAME "\n");
+  typeof (__##GCC_NAME) __aeabi_##AEABI_NAME \
+    __attribute__((alias ("__" #GCC_NAME)));
 
 /* Give some libgcc functions an additional __aeabi name.  */
 #ifdef L_muldi3
diff --git a/gcc-4.6/libgcc/config/i386/64/sfp-machine.h b/gcc-4.6/libgcc/config/i386/64/sfp-machine.h
index 5adf6dbba..5186c24ff 100644
--- a/gcc-4.6/libgcc/config/i386/64/sfp-machine.h
+++ b/gcc-4.6/libgcc/config/i386/64/sfp-machine.h
@@ -79,17 +79,25 @@ struct fenv
   unsigned short int __unused5;
 };
 
+#ifdef __AVX__
+ #define ASM_INVALID "vdivss %0, %0, %0"
+ #define ASM_DIVZERO "vdivss %1, %0, %0"
+#else
+ #define ASM_INVALID "divss %0, %0"
+ #define ASM_DIVZERO "divss %1, %0"
+#endif
+
 #define FP_HANDLE_EXCEPTIONS						\
   do {									\
     if (_fex & FP_EX_INVALID)						\
       {									\
 	float f = 0.0;							\
-	__asm__ __volatile__ ("divss %0, %0 " : : "x" (f));		\
+	__asm__ __volatile__ (ASM_INVALID : : "x" (f));			\
       }									\
     if (_fex & FP_EX_DIVZERO)						\
       {									\
 	float f = 1.0, g = 0.0;						\
-	__asm__ __volatile__ ("divss %1, %0" : : "x" (f), "x" (g));	\
+	__asm__ __volatile__ (ASM_DIVZERO : : "x" (f), "x" (g));	\
       }									\
     if (_fex & FP_EX_OVERFLOW)						\
       {									\
diff --git a/gcc-4.6/libgcc/config/i386/i386-cpuinfo.c b/gcc-4.6/libgcc/config/i386/i386-cpuinfo.c
new file mode 100644
index 000000000..362bfc4cb
--- /dev/null
+++ b/gcc-4.6/libgcc/config/i386/i386-cpuinfo.c
@@ -0,0 +1,307 @@
+/* Get CPU type and Features for x86 processors.
+   Copyright (C) 2011 Free Software Foundation, Inc.
+   Contributed by Sriraman Tallam (tmsriram@google.com)
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>. */
+
+#include "cpuid.h"
+#include "tsystem.h"
+
+int __cpu_indicator_init (void) __attribute__ ((constructor));
+
+enum vendor_signatures
+{
+  SIG_INTEL =	0x756e6547 /* Genu */,
+  SIG_AMD =	0x68747541 /* Auth */
+};
+
+
+/* Features supported. */
+
+struct __processor_features
+{
+  unsigned int __cpu_cmov : 1;
+  unsigned int __cpu_mmx : 1;
+  unsigned int __cpu_popcnt : 1;
+  unsigned int __cpu_sse : 1;
+  unsigned int __cpu_sse2 : 1;
+  unsigned int __cpu_sse3 : 1;
+  unsigned int __cpu_ssse3 : 1;
+  unsigned int __cpu_sse4_1 : 1;
+  unsigned int __cpu_sse4_2 : 1;
+} __cpu_features;
+
+/* Processor Model. */
+
+struct __processor_model
+{
+  /* Vendor. */
+  unsigned int __cpu_is_amd : 1;
+  unsigned int __cpu_is_intel : 1;
+  /* CPU type. */
+  unsigned int __cpu_is_intel_atom : 1;
+  unsigned int __cpu_is_intel_core2 : 1;
+  unsigned int __cpu_is_intel_corei7 : 1;
+  unsigned int __cpu_is_intel_corei7_nehalem : 1;
+  unsigned int __cpu_is_intel_corei7_westmere : 1;
+  unsigned int __cpu_is_intel_corei7_sandybridge : 1;
+  unsigned int __cpu_is_amdfam10h : 1;
+  unsigned int __cpu_is_amdfam10h_barcelona : 1;
+  unsigned int __cpu_is_amdfam10h_shanghai : 1;
+  unsigned int __cpu_is_amdfam10h_istanbul : 1;
+  unsigned int __cpu_is_amdfam15h_bdver1 : 1;
+  unsigned int __cpu_is_amdfam15h_bdver2 : 1;
+} __cpu_model;
+
+/* Get the specific type of AMD CPU.  */
+
+static void
+get_amd_cpu (unsigned int family, unsigned int model)
+{
+  switch (family)
+    {
+    /* AMD Family 10h.  */
+    case 0x10:
+      switch (model)
+	{
+	case 0x2:
+	  /* Barcelona.  */
+	  __cpu_model.__cpu_is_amdfam10h = 1;
+	  __cpu_model.__cpu_is_amdfam10h_barcelona = 1;
+	  break;
+	case 0x4:
+	  /* Shanghai.  */
+	  __cpu_model.__cpu_is_amdfam10h = 1;
+	  __cpu_model.__cpu_is_amdfam10h_shanghai = 1;
+	  break;
+	case 0x8:
+	  /* Istanbul.  */
+	  __cpu_model.__cpu_is_amdfam10h = 1;
+	  __cpu_model.__cpu_is_amdfam10h_istanbul = 1;
+	  break;
+	default:
+	  break;
+	}
+      break;
+    /* AMD Family 15h.  */
+    case 0x15:
+      /* Bulldozer version 1.  */
+      if (model >= 0 && model <= 0xf)
+        __cpu_model.__cpu_is_amdfam15h_bdver1 = 1;
+      /* Bulldozer version 2.  */
+      if (model >= 0x10 && model <= 0x1f)
+        __cpu_model.__cpu_is_amdfam15h_bdver2 = 1;
+      break;
+    default:
+      break;
+    }
+}
+
+/* Get the specific type of Intel CPU.  */
+
+static void
+get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
+{
+  /* Parse family and model only if brand ID is 0. */
+  if (brand_id == 0)
+    {
+      switch (family)
+	{
+	case 0x5:
+	  /* Pentium.  */
+	  break;
+	case 0x6:
+	  switch (model)
+	    {
+	    case 0x1c:
+	    case 0x26:
+	      /* Atom.  */
+	      __cpu_model.__cpu_is_intel_atom = 1;
+	      break;
+	    case 0x1a:
+	    case 0x1e:
+	    case 0x1f:
+	    case 0x2e:
+	      /* Nehalem.  */
+	      __cpu_model.__cpu_is_intel_corei7 = 1;
+	      __cpu_model.__cpu_is_intel_corei7_nehalem = 1;
+	      break;
+	    case 0x25:
+	    case 0x2c:
+	    case 0x2f:
+	      /* Westmere.  */
+	      __cpu_model.__cpu_is_intel_corei7 = 1;
+	      __cpu_model.__cpu_is_intel_corei7_westmere = 1;
+	      break;
+	    case 0x2a:
+	      /* Sandy Bridge.  */
+	      __cpu_model.__cpu_is_intel_corei7 = 1;
+	      __cpu_model.__cpu_is_intel_corei7_sandybridge = 1;
+	      break;
+	    case 0x17:
+	    case 0x1d:
+	      /* Penryn.  */
+	    case 0x0f:
+	      /* Merom.  */
+	      __cpu_model.__cpu_is_intel_core2 = 1;
+	      break;
+	    default:
+	      break;
+	    }
+	  break;
+	default:
+	  /* We have no idea.  */
+	  break;
+	}
+    }
+}	             	
+
+static void
+get_available_features (unsigned int ecx, unsigned int edx)
+{
+  __cpu_features.__cpu_cmov = (edx & bit_CMOV) ? 1 : 0;
+  __cpu_features.__cpu_mmx = (edx & bit_MMX) ? 1 : 0;
+  __cpu_features.__cpu_sse = (edx & bit_SSE) ? 1 : 0;
+  __cpu_features.__cpu_sse2 = (edx & bit_SSE2) ? 1 : 0;
+  __cpu_features.__cpu_popcnt = (ecx & bit_POPCNT) ? 1 : 0;
+  __cpu_features.__cpu_sse3 = (ecx & bit_SSE3) ? 1 : 0;
+  __cpu_features.__cpu_ssse3 = (ecx & bit_SSSE3) ? 1 : 0;
+  __cpu_features.__cpu_sse4_1 = (ecx & bit_SSE4_1) ? 1 : 0;
+  __cpu_features.__cpu_sse4_2 = (ecx & bit_SSE4_2) ? 1 : 0;
+}
+
+
+/* Sanity check for the vendor and cpu type flags.  */
+
+static int
+sanity_check (void)
+{
+  unsigned int one_type = 0;
+
+  /* Vendor cannot be Intel and AMD. */
+  gcc_assert((__cpu_model.__cpu_is_intel == 0)
+             || (__cpu_model.__cpu_is_amd == 0));
+ 
+  /* Only one CPU type can be set. */
+  one_type = (__cpu_model.__cpu_is_intel_atom
+	      + __cpu_model.__cpu_is_intel_core2
+	      + __cpu_model.__cpu_is_intel_corei7_nehalem
+	      + __cpu_model.__cpu_is_intel_corei7_westmere
+	      + __cpu_model.__cpu_is_intel_corei7_sandybridge
+	      + __cpu_model.__cpu_is_amdfam10h_barcelona
+	      + __cpu_model.__cpu_is_amdfam10h_shanghai
+	      + __cpu_model.__cpu_is_amdfam10h_istanbul
+	      + __cpu_model.__cpu_is_amdfam15h_bdver1
+	      + __cpu_model.__cpu_is_amdfam15h_bdver2);
+
+  gcc_assert (one_type <= 1);
+  return 0;
+}
+
+/* A noinline function calling __get_cpuid. Having many calls to
+   cpuid in one function in 32-bit mode causes GCC to complain:
+   "can’t find a register in class ‘CLOBBERED_REGS’".  This is
+   related to PR rtl-optimization 44174. */
+
+static int __attribute__ ((noinline))
+__get_cpuid_output (unsigned int __level,
+		    unsigned int *__eax, unsigned int *__ebx,
+		    unsigned int *__ecx, unsigned int *__edx)
+{
+  return __get_cpuid (__level, __eax, __ebx, __ecx, __edx);
+}
+
+
+/* A constructor function that is sets __cpu_model and __cpu_features with
+   the right values.  This needs to run only once.
+   If another constructor needs to use these values, explicitly call this
+   function from the other constructor.  Otherwise, the ordering of
+   constructors could make this constructor run later.  */
+
+int __attribute__ ((constructor))
+__cpu_indicator_init (void)
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  int max_level = 5;
+  unsigned int vendor;
+  unsigned int model, family, brand_id;
+  unsigned int extended_model, extended_family;
+  static int called = 0;
+
+  /* This function needs to run just once.  */
+  if (called)
+    return 0;
+  else
+    called = 1;
+
+  /* Assume cpuid insn present. Run in level 0 to get vendor id. */
+  if (!__get_cpuid_output (0, &eax, &ebx, &ecx, &edx))
+    return -1;
+
+  vendor = ebx;
+  max_level = eax;
+
+  if (max_level < 1)
+    return -1;
+
+  if (!__get_cpuid_output (1, &eax, &ebx, &ecx, &edx))
+    return -1;
+
+  model = (eax >> 4) & 0x0f;
+  family = (eax >> 8) & 0x0f;
+  brand_id = ebx & 0xff;
+  extended_model = (eax >> 12) & 0xf0;
+  extended_family = (eax >> 20) & 0xff;
+
+  if (vendor == SIG_INTEL)
+    {
+      /* Adjust model and family for Intel CPUS. */
+      if (family == 0x0f)
+	{
+	  family += extended_family;
+	  model += extended_model;
+	}
+      else if (family == 0x06)
+	model += extended_model;
+
+      /* Get CPU type.  */
+      __cpu_model.__cpu_is_intel = 1;
+      get_intel_cpu (family, model, brand_id);
+    }
+
+  if (vendor == SIG_AMD)
+    {
+      /* Adjust model and family for AMD CPUS. */
+      if (family == 0x0f)
+	{
+	  family += extended_family;
+	  model += (extended_model << 4);
+	}
+
+      /* Get CPU type.  */
+      __cpu_model.__cpu_is_amd = 1;
+      get_amd_cpu (family, model);
+    }
+
+  /* Find available features. */
+  get_available_features (ecx, edx);
+
+  sanity_check ();
+
+  return 0;
+}
diff --git a/gcc-4.6/libgcc/config/i386/t-cpuinfo b/gcc-4.6/libgcc/config/i386/t-cpuinfo
new file mode 100644
index 000000000..dd271f9db
--- /dev/null
+++ b/gcc-4.6/libgcc/config/i386/t-cpuinfo
@@ -0,0 +1 @@
+LIB2ADD += $(srcdir)/config/i386/i386-cpuinfo.c
diff --git a/gcc-4.6/libgcc/config/libbid/ChangeLog b/gcc-4.6/libgcc/config/libbid/ChangeLog
index c41204289..5c1f7845e 100644
--- a/gcc-4.6/libgcc/config/libbid/ChangeLog
+++ b/gcc-4.6/libgcc/config/libbid/ChangeLog
@@ -1,3 +1,7 @@
+2011-10-26  Release Manager
+
+	* GCC 4.6.2 released.
+
 2011-06-27  Release Manager
 
 	* GCC 4.6.1 released.
diff --git a/gcc-4.6/libgcc/generic-morestack.c b/gcc-4.6/libgcc/generic-morestack.c
index 7e29bbcf7..77344a925 100644
--- a/gcc-4.6/libgcc/generic-morestack.c
+++ b/gcc-4.6/libgcc/generic-morestack.c
@@ -459,8 +459,8 @@ __generic_morestack_set_initial_sp (void *sp, size_t len)
   sigemptyset (&__morestack_initial_sp.mask);
 
   sigfillset (&__morestack_fullmask);
-#ifdef __linux__
-  /* On Linux, the first two real time signals are used by the NPTL
+#ifdef __GLIBC__
+  /* In glibc, the first two real time signals are used by the NPTL
      threading library.  By taking them out of the set of signals, we
      avoiding copying the signal mask in pthread_sigmask.  More
      importantly, pthread_sigmask uses less stack space on x86_64.  */