1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
|
@ Things you can't do with 16-bit Thumb instructions, but you can
@ do with the equivalent ARM instruction. Does not include errors
@ caught by fixup processing (e.g. out-of-range immediates).
.text
.code 16
.thumb_func
l:
@ Arithmetic instruction templates
.macro ar2 opc
\opc r8,r0
\opc r0,r8
.endm
.macro ar2sh opc
ar2 \opc
\opc r0,#12
\opc r0,r1,lsl #2
\opc r0,r1,lsl r3
.endm
.macro ar2r opc
ar2 \opc
\opc r0,r1,ror #8
.endm
.macro ar3 opc
\opc r1,r2,r3
\opc r8,r0
\opc r0,r8
.endm
.macro ar3sh opc
ar3 \opc
\opc r0,#12
\opc r0,r1,lsl #2
\opc r0,r1,lsl r3
.endm
ar2sh tst
ar2sh cmn
ar2sh mvn
ar2 neg
ar2 rev
ar2 rev16
ar2 revsh
ar2r sxtb
ar2r sxth
ar2r uxtb
ar2r uxth
ar3sh adc
ar3sh and
ar3sh bic
ar3sh eor
ar3sh orr
ar3sh sbc
ar3 mul
@ Shift instruction template
.macro shift opc
\opc r8,r0,#12 @ form 1
\opc r0,r8,#12
ar2 \opc @ form 2
.endm
shift asr
shift lsl
shift lsr
shift ror
ror r0,r1,#12
@ add/sub/mov/cmp are idiosyncratic
add r0,r1,lsl #2
add r0,r1,lsl r3
add r8,r0,#1 @ form 1
add r0,r8,#1
add r8,#10 @ form 2
add r8,r1,r2 @ form 3
add r1,r8,r2
add r1,r2,r8
add r8,pc,#4 @ form 5
add r8,sp,#4 @ form 6
ar3sh sub
sub r8,r0,#1 @ form 1
sub r0,r8,#1
sub r8,#10 @ form 2
sub r8,r1,r2 @ form 3
sub r1,r8,r2
sub r1,r2,r8
cmp r0,r1,lsl #2
cmp r0,r1,lsl r3
cmp r8,#255
mov r0,r1,lsl #2
mov r0,r1,lsl r3
mov r8,#255
@ Load/store template
.macro ldst opc
\opc r8,[r0]
\opc r0,[r8]
\opc r0,[r0,r8]
\opc r0,[r1,#4]!
\opc r0,[r1],#4
\opc r0,[r1,-r2]
\opc r0,[r1],r2
.endm
ldst ldr
ldst ldrb
ldst ldrh
ldst ldrsb
ldst ldrsh
ldst str
ldst strb
ldst strh
ldr r0,[r1,r2,lsl #1]
str r0,[r1,r2,lsl #1]
@ Load/store multiple
ldmia r8!,{r1,r2}
ldmia r7!,{r8}
ldmia r7,{r1,r2}
ldmia r7!,{r1,r7}
stmia r8!,{r1,r2}
stmia r7!,{r8}
stmia r7,{r1,r2}
stmia r7!,{r1,r7}
push {r8,r9}
pop {r8,r9}
@ Miscellaneous
bkpt #257
cpsie ai,#5
cpsid ai,#5
@ Conditional suffixes
addeq r0,r1,r2
@ low register non flag setting add.
.syntax unified
add r0, r1
@ Multiply
.syntax divided
mul r0, r0, r8
mul r0, r8, r0
mul r8, r0, r0
|
