1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
|
@ Test file for ARM load/store instructions with 0 offset
.text
.syntax unified
ldr r1, [r2, #-0]
ldr r1, [r2, #-1+1]
ldr r1, [r2, #1-1]
ldr r1, [r2, #0]
ldr r1, [r2, #-0]!
ldr r1, [r2, #-1+1]!
ldr r1, [r2, #1-1]!
ldr r1, [r2, #0]!
ldr r1, [r2], #-0
ldr r1, [r2], #-1+1
ldr r1, [r2], #1-1
ldr r1, [r2], #0
ldr r1, [r2]!
ldr r1, [r2]
ldrbt r1, [r2], #0
ldrbt r1, [r2], #-0
ldrbt r1, [r2]
ldclpl p3, c5, [r6, #-0]
ldclpl p3, c5, [r6, #0]
str r1, [r2, #-0]
str r1, [r2, #-1+1]
str r1, [r2, #1-1]
str r1, [r2, #0]
str r1, [r2, #-0]!
str r1, [r2, #-1+1]!
str r1, [r2, #1-1]!
str r1, [r2, #0]!
str r1, [r2], #-0
str r1, [r2], #-1+1
str r1, [r2], #1-1
str r1, [r2], #0
str r1, [r2]!
str r1, [r2]
strbt r1, [r2], #0
strbt r1, [r2], #-0
strbt r1, [r2]
stclpl p3, c5, [r6, #-0]
stclpl p3, c5, [r6, #0]
ldr r0,1f
ldr r0,1f
ldr r0,1f
1: .word 0
|
